MT5C2568DCJ-25E/883C [MICROSS]
Standard SRAM, 32KX8, 25ns, CMOS, CDSO28, CERAMIC, SOJ-28;
| 型号： | MT5C2568DCJ-25E/883C |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Standard SRAM, 32KX8, 25ns, CMOS, CDSO28, CERAMIC, SOJ-28 CD 静态存储器 |
| 文件： | 总8页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
SRAM
32K x 8 SRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
PIN ASSIGNMENT (Top View)
28-PIN SOJ
•
•
SMD 5962-88662
MIL-STD-883
32-Pin LCC
(C-12)
28-Pin DIP
(D15/D10)
FEATURES
4
3 2 1 32 31 30
•
•
•
•
•
Ultra high speed 12, 15ns
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
A6
A5
A4
A3
A2
A1 10
A0 11
NC 12
DQ1 13
5
6
7
8
9
29 A8
28 A9
High speed: 20, 25, 35 and 45ns
Battery backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
27 A11
26 NC
25 OE
24 A10
23 CE
22 DQ8
21 DQ7
14 1516 17 18 19 20
•
•
•
Single +5V (±10%) power supply
Easy memory expansion with CE
All inputs and outputs are TTL compatible
28-Pin LCC
(C-11)
A0 10 19 DQ8
DQ1 11 18 DQ7
DQ2 12 17 DQ6
DQ3 13 16 DQ5
Vss 14 15 DQ4
OPTIONS
MARKING
3
2 1 28 27
•
Timing
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 DQ8
18 DQ7
4
5
6
7
8
A6
A5
A4
A3
A2
12ns access (Contact factory)
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-12
-15
-20
-25
-35
-45
-55*
-70*
9
A1
10
11
12
A0
DQ1
DQ2
131415 16 17
•
Packages
28-Pin Flat Pack
(F-12)
Ceramic DIP (300 mil)
Ceramic DIP (600 mil)
Ceramic LCC (28 leads)
Ceramic LCC (32 leads)
Ceramic Flat Pack
Ceramic SOJ
C
No. 108
CW No. 110
EC No. 204
ECW No. 208
Vcc
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
WE
A13
A8
A9
A11
OE
F
No. 302
A10
CE
DCJ No. 500
DQ8
DQ7
DQ6
DQ5
DQ4
A0 10
DQ1 11
DQ2 12
DQ3 13
Vss 14
•
•
2V data retention, low power standby
L
Radiation Tolerant (EPI)
E
*Electrical characteristics identical to those provided for the 45ns
access devices.
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs high-
speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon tech-
nology.
outputs in High-Z for additional flexibility in system de-
sign.
Writing to these devices is accomplished when write
enable (WE) and CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and OE go
LOW. The device offers a reduced power standby mode
when disabled. This allows system designs to achieve low
standby power requirements.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE) and output en-
able (OE) capability. These enhancements can place the
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-73
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
The “L” version provides an approximate 50 percent reduction in CMOS standby current (ISBC2) over the standard version.
All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
Vcc
GND
A
A
A
A
A
A
A
A
DQ8
262,144-BIT
MEMORY ARRAY
DQ1
CE
(LSB)
OE
WE
COLUMN DECODER
(LSB)
POWER
DOWN
A
A
A
A
A
A
A
TRUTH TABLE
MODE
OE
CE
WE
DQ
HIGH-Z
Q
POWER
STANDBY
READ
X
L
H
L
L
L
X
H
H
L
STANDBY
ACTIVE
ACTIVE
ACTIVE
READ
H
X
HIGH-Z
D
WRITE
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-74
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative to VSS .... -2V to +7V
Voltage on Vcc Supply Relative to Vss .............. -1V to +7V
Storage Temperature ................................... -65°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
Lead Temperature (soldering 10 seconds) .............. +260°C
Junction Temperature ................................................ +175°C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C ≤ T ≤ 125°C; VCC = 5V ± 10%)
C
DESCRIPTION
CONDITIONS
SYMBOL
VIH
MIN
2.2
-0.5
-5
MAX
UNITS
V
NOTES
1
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
VCC+1.0
VIL
0.8
5
V
1, 2
0V ≤ VIN ≤ VCC
ILI
µA
µA
Outputs Disabled
ILO
-5
5
0V ≤ VOUT ≤ VCC
Output High Voltage
Output Low Voltage
IOH = -4.0mA
IOL = 8.0mA
VOH
VOL
2.4
V
V
1
1
0.4
MAX
-35
DESCRIPTION
CONDITIONS
SYMBOL -12 -15
-20
-25
-45
UNITS
NOTES
Power Supply
Current: Operating
CE ≤ VIL; VCC = MAX
f = MAX = 1/ RC (MIN)
t
ICC
190 165 150 140 135 130
mA
3
Output Open
Power Supply
Current: Standby
CE ≥ VIH; VCC = MAX
f = MAX = 1/ RC (MIN)
t
ISBT1
60
25
50
25
45
25
40
25
40
25
40
25
mA
mA
Output Open
CE ≥ VIH, All Other Inputs
≤ VIL or ≥ VIH, VCC = MAX ISBT2
f = 0 Hz
CE ≥ VCC -0.2V; VCC = MAX
VIL ≤ VSS +0.2V
VIH ≥ VCC -0.2V; f = 0 Hz
ISBC2
5
4
5
4
5
4
5
4
5
4
5
4
mA
mA
“L” Version Only ISBC2
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
CI
MIN
MAX
UNITS
pF
NOTES
Input Capacitance
Output Capacitance
T
= 25°C, f = 1MHz
8
8
4
4
A
VCC = 5V
CO
pF
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-75
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55°C ≤ T ≤ 125°C; VCC = 5V ± 10%)
C
-12
-15
-20
-25
-35
-45
DESCRIPTION
SYM MIN MAX MIN MAX
MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ Cycle
READ cycle time
tRC
tAA
12
15
20
25
35
45
ns
ns
ns
ns
ns
Address access time
12
12
15
15
20
20
25
25
35
35
45
45
Chip Enable access time
Output hold from address change
Enable to output in Low-Z
disable to output in High-Z
Chip Enable to power-up time
tACE
tOH
2
2
2
2
2
2
2
2
2
2
2
2
tLZCE
tHZCE
tPU
7
7
8
9
10
14
15
ns 6, 7
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
4
4
Chip disable to power-down time tPD
Output Enable access time
tAOE
12
6
15
8
20
9
25
10
35
14
45
15
Output Enable to output in Low-Z tLZOE
Output disable to output in High-Z tHZOE
WRITE Cycle
4
6
8
10
14
15
6
WRITE cycle time
tWC
tCW
tAW
tAS
12
10
10
0
15
12
12
0
20
15
15
0
25
18
18
0
35
20
20
0
45
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width
tAH
tWP
tDS
tDH
2
2
2
2
2
2
10
6
12
7
15
10
0
17
12
0
20
15
0
25
20
0
Data setup time
Data hold time
0
0
Write disable to output in Low-Z tLZWE
2
2
2
2
2
2
7
t
Write Enable to output in High-Z HZWE
0
6
0
7
0
10
0
11
0
14
0
15
ns 6, 7
MT5C2568 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000007
1-76
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
+5V
+5V
AC TEST CONDITIONS
480
480
Input pulse levels ...................................... Vss to 3V
Input rise and fall times ....................................... 5ns
Input timing reference level ............................... 1.5V
Output reference level....................................... 1.5V
Output load ................................See figures 1 and 2
Q
Q
30 pF
5 pF
255
255
Fig. 1 OUTPUT LOAD
EQUIVALENT
Fig. 2 OUTPUT LOAD
EQUIVALENT
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns.
7. At any given temperature and voltage condition,
t
t
t
t
HZCE is less than LZCE and HZWE is less than
LZWE.
8. WE is HIGH for READ cycle.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
1
9. Device is continuously selected. Chip enable and
output enable are held in their active state.
10. Address valid prior to or coincident with latest
occurring chip enable.
unloaded, and f =
Hz.
t
RC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
11. RC = READ cycle time.
12. Chip enable (CE) and write enable (WE) can initiate
and terminate a WRITE cycle.
t
t
t
6. HZCE, HZOE and HZWE are specified with CL =
5 pF as in Fig. 2. Transition is measured ± 500mV
typical from steady state voltage, allowing for actual
tester RC time constant.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
2
MAX
UNITS
V
NOTES
VCC for Retention Data
Data Retention Current
VDR
—
CE ≥ (VCC - 0.2V) VCC = 2V
VIN ≥ (VCC - 0.2V)
ICCDR
1.0
mA
or ≤ 0.2V
VCC = 3V
1.5
0
mA
ns
t
Chip Deselect to Data
Retention Time
CDR
—
4
t
t
Operation Recovery Time
R
RC
ns
4, 11
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
4.5V
V
>2V
Vcc
DR
t
t
R
CDR
V
V
DR
IH
IL
CE
V
DON’T CARE
UNDEFINED
MT5C2568 883C
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000007
1-77
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE NO. 18, 9
t
RC
ADDR
VALID
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
Q
READ CYCLE NO. 2 7, 8, 10
t
RC
CE
OE
t
AOE
t
t
t
LZOE
HZOE
t
ACE
HZCE
t
LZCE
HIGH-Z
DATA VALID
DQ
Icc
t
t
PD
PU
DON’T CARE
UNDEFINED
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-78
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
WRITE CYCLE NO. 1 12
(Chip Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
AH
AS
CW
CE
t
WP
WE
t
t
DH
DS
D
Q
DATA VALID
HIGH-Z
WRITE CYCLE NO. 2 7, 12
(Write Enable Controlled)
t
WC
ADDR
t
AW
t
t
AH
CW
CE
t
t
AS
WP
WE
t
t
DH
DS
DATA VALID
D
Q
HIGH-Z
DON’T CARE
UNDEFINED
NOTE: Output enable (OE) is inactive (HIGH).
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-79
MT5C2568 883C
32K x 8 SRAM
AUSTIN SEMICONDUCTOR, INC.
ELECTRICAL TEST REQUIREMENTS
SUBGROUPS
MIL-STD-883 TEST REQUIREMENTS
(per Method 5005, Table I)
INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS
(Method 5004)
2, 8A, 10
FINAL ELECTRICAL TEST PARAMETERS
(Method 5004)
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
GROUP A TEST REQUIREMENTS
(Method 5005)
GROUP C AND D END-POINT ELECTRICAL PARAMETERS
(Method 5005)
*
PDA applies to subgroups 1 and 7.
** Subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input
or output capacitance.
MT5C2568 883C
REV. 11/97
DS000007
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
1-80
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