MTS1512K8C35LSJ2SE [MICROSS]
Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36;
| 型号： | MTS1512K8C35LSJ2SE |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Standard SRAM, 512KX8, 35ns, CMOS, CDSO36, CERAMIC, SOJ-36 CD 静态存储器 |
| 文件： | 总10页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
PIN DIAGRAM
4Mb, 512K x 8, Asynchronous, Low
Power SRAM Memory Array
PIN SIGNAL NAME
PIN SIGNAL NAME
1
2
3
4
5
6
36
35
34
33
32
31
A0
NC
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
2
A1
A18
A17
A16
A15
OE\
IO 7
IO 6
VSS
VCC
IO 5
IO 4
A14
A13
A12
A11
A10
NC
AVAILABILITY:
3
A2
4
A3
DSCC SMD 5962-95600
QML-Q Compliant
Mil 883 Compliant
5
A4
CE\
IO 0
IO 1
VCC
VSS
IO 2
IO 3
WE\
A5
A6
A7
A8
A9
6
7
8
9
10
11
12
13
14
15
16
17
18
7
8
9
30
29
28
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
FEATURES:
High Speed, Asynchronous operation
Fully Static, No Clocks required
Center Power & Ground for improved noise
immunity
Easy Memory Array expansion with use of Chip
Select (CS\) and Output Enable (OE\)
All Inputs/Outputs are TTL compatible
Low Power with Data Retention Functionality
Product Access Speed Options:
FUNCTIONAL BLOCK
o
15, 17, 20, 25, 35 and 45ns
Package Option:
36LD-CSOJ
o
FUNCTIONAL DESCRIPTION
INPUT BUFFER
The MTS1512K8C is a high-performance Low Power
CMOS Static Random Access Memory (SRAM),
organized as 512K words by 8-bits wide, containing a
total density of 512K bytes. Memory expansion is easily
achieved through use of the Chip-Select (CS\) and
Output Enable (OE\) control inputs along with the tri-
state output drivers. Writing to the device is
accomplished by driving CS\ and WE\ LOW. Data on
the eight IO pins (IO0-IO7) is then written into the
addressed location specified on the Address Input pins
(A0-A18).
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
512K x 8
Asynchronous
SRAM
ARRAY
2048 Rows
2048 Columns
POWER
DOWN
CE\
WE\
COLUMN DECODE
OE\
Reading from the MTS1512K8C is accomplished by
driving Chip Select (CS\) and Output Enable (OE\) LOW,
while forcing Write Enable (WE\) HIGH. Under these
stimulus conditions, the contents of the addressed
memory location (A0-A18) will be available on the
Output pins (IO0-IO7).
MAXIMUM RATINGS
PARAMETER
Operating Temperature
Storage Temperature
SYMBOL
LIMIT
UNITS
˚C
-55 to +125
-65 to 150
TA
TSTG
VS
The MTS1512K8C is placed into an inactive, High-
Impedance state when the device has been de-selected
by driving Chip-Select (CS\) HIGH. The eight Input-
Output lines (IO0-IO7) are also in a High-Impedance
state when the MTS1512K8C is placed into a WRITE
operation by driving Chip-Select (CS\) and Write Enable
(WE\) LOW. This device supports Low Voltage Data
Retention.
˚C
Supply Voltage Relative to GND
-0.5 to VCC+0.5
V
DC Voltage applied to Outputs in
High-Z
-0.5 to VCC+0.5
-0.5 to VCC+0.5
V
V
VOZG
VG
DC Input Voltage
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
CI
CONDITIONS
MAX
UNITS
V =0V, ƒ=1.0MHz
IN
8
8
pf
pf
Output Capacitance
V =0V, ƒ=1.0MHz
IN
CO
481 ohm
255 ohm
481 ohm
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Input Rise & Fall times
Input Timing Reference levels
Output Timing Reference levels
Output Test Load
LIMIT
VSS to 3.0
≤ 3
1.5
1.5
Figure 1
Figure 2
UNITS
255 ohm
30 pF
5 pF
V
ns
V
V
Figure 1
Figure 2
Output Test Load (Z testing)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input leakage current
SYMBOL
VOH
CONDITIONS
MIN
MAX
UNITS NOTE(S)
VCC=Min., IOH = -4.0 mA
VCC=Min., IOH = 8.0mA
2.4
V
V
V
V
1
1
0.4
VCC+0.5
0.8
VOL
V
IH
2.2
-0.5
-10
1
1,2
V
IL
GND < VI < VCC
10
A
µ
IIX
GND < VO < VCC
(Output disabled)
12ns
Output leakage current
-10
10
A
IOZ
µ
80
80
75
75
75
75
75
mA
mA
mA
mA
mA
mA
mA
3
3
3
3
3
3
3
Operating current
15ns
17ns
20ns
25ns
35ns
45ns
ICC1
CS\
≥ VIH, all other inputs ≤
Standby, TTL inputs
30
20
mA
mA
ICC2
VIL, VCC = MAX, ƒ = 0, Outputs
Open
CS\ V -0.2V; VCC = MAX,
≥
CC
Standby, CMOS inputs
ICC3
V
IN
V
SS +0.2V or V
V -
≥
CC
≤
IH
0.2V; = 0
ƒ
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
VDR
CONDITIONS
MIN
MAX
UNITS NOTE(S)
VCC for Data Retention
2
V
Data Retention Current
Chip Deselect to DR time
Operation Recovery
10
mA
ICCDR
tCDR
V
CC = VDR = 2.0V, CS\ V
≥
CC
0
ns
ns
4
-0.3V, V
VCC - 0.3V or V
≥
IN
IN
0.3V
≤
tRC
4,11
tR
AC SWITCHING CHARACTERISTICS
READ
15ns
17ns
20ns
MTS1512K8C15L
MTS1512K8C20L
MTS1512K8C25L
PARAMETER
VCC to First Access
SYMBOL
tPOWER
tRC
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTE(S)
100
15
-
-
-
100
20
-
-
-
100
25
-
-
-
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
READ Cycle Time
Address Access Time
15
15
-
17
17
-
20
20
-
tAC
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
-
-
-
tACS
tOH
3
3
0
-
3
3
0
-
3
3
0
-
-
-
-
4,7
tCLZ
7
7
-
8
8
-
8
4,6,7
tCHZ
tOE
10
-
0
-
0
-
0
-
4,7
tOLZ
tOHZ
tPU
7
-
8
-
8
4,6,7
0
-
0
-
0
-
-
Chip Disable to Power-Down
15
17
20
tPD
25ns
35ns
45ns
MTS1512K8C25L
MTS1512K8C35L
MTS1512K8C45L
PARAMETER
VCC to First Access
READ Cycle Time
SYMBOL
tPOWER
tRC
MIN
MAX
-
MIN
MAX
-
MIN
MAX
-
UNITS NOTE(S)
100
25
-
100
15
-
100
20
-
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
-
-
-
Address Access Time
Chip Enable Access Time
25
25
-
15
15
-
20
20
-
tAC
-
-
-
tACS
tOH
3
3
0
-
3
3
0
-
3
3
0
-
Output Hold from Address Change
-
-
-
4,7
tCLZ
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
10
12
-
12
15
-
15
22
-
4,6,7
tCHZ
tOE
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
0
-
0
-
0
-
4,7
tOLZ
tOHZ
tPU
10
-
12
-
15
-
4,6,7
0
-
0
-
0
-
Chip Disable to Power-Down
25
35
45
tPD
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
WRITE
15ns
17ns
20ns
MTS1512K8C15L
MTS1512K8C20L
MTS1512K8C25L
PARAMETER
SYMBOL
tWC
MIN
15
10
0
MAX
MIN
17
12
0
MAX
MIN
20
14
0
MAX
UNITS NOTE(S)
WRITE Cycle Time
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
-
8
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of WRITE
Address Setup Time
tCW
tAS
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
0
0
0
tAH
10
10
8
12
12
9
14
14
10
0
tAW
tWP
Data Setup Time
tDS
Data Hold Time
0
0
tDH
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
4
4
5
ns
ns
4,6,7
4,6,7
tWLZ
tWHZ
-
-
-
25ns
35ns
45ns
MTS1512K8C25L
MTS1512K8C35L
MTS1512K8C45L
PARAMETER
WRITE Cycle Time
SYMBOL
tWC
MIN
25
16
0
MAX
MIN
35
18
0
MAX
MIN
45
24
0
MAX
UNITS NOTE(S)
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of WRITE
Address Setup Time
tCW
tAS
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
0
0
0
tAH
16
16
10
0
18
18
12
0
24
24
15
0
tAW
tWP
Data Setup Time
tDS
Data Hold Time
tDH
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
5
5
5
ns
ns
4,6,7
4,6,7
tWLZ
tWHZ
10
10
12
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
NOTE 8,9
NOTE 2
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
NOTE 12
NOTE 12, 13
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
NOTE 7, 12, 14
NOTES:
All Voltages referenced to VSS (GND)
1)
2)
3)
4)
5)
6)
7)
-2.0V for Pulse
≤ 20ns
ICC is dependent on output loading, specification testing per Output Load fiqures 1&2
This parameter is guaranteed but not tested
Test conditions as specified in Output Load figure 1
tCLZ, tCHZ, tOLZ, tOHZ, tWLZ and tWHZ are specified with use of Output Load fiqure 2
At any given voltage and/or temperature condition, tCHZ is less than tCLZ and tWHZ is
less than tWLZ
WE\ is High for READ Cycles
Device is continuously selected. Chip Select and Output Enable are driven to their
Active state
8)
9)
Address Valid prior to, or coincident with latest occuring Chip Select
Full device operation requires linear VCC ramp from VDR to VCC(MIN) 50 s or statble
10)
11)
≥
µ
at VCC(MIN) 50 s Max
≥
µ
Chips Select and Write Enable can initiate and terminate a WRITE Cycle
12)
13)
14)
15)
Output Enable is Inactive when HIGH
Output Enable is Active when LOW
tPOWER gives the minimum amount of time that the power supply should be at typical
VCC values unitl the first memory access can be performed
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
MECHANICAL DIAGRAM
D
A
A1
MTCS1512K8CssLSJ2x
eA
E
LOT CODE
DAT E CODE
C
R
e
b
D2
Millimeters
Inches
MIN MAX MIN MAX
Symbol
2.920 3.680
0.630 1.140
0.380 0.510
0.150 0.300
23.39 23.85
21.46 21.71
10.54 10.92
1.270 BSC
A
A1
b
C
D
D2
E
e
0.115 0.145
0.025 0.045
0.015 0.020
0.006 0.012
0.921 0.939
0.845 0.855
0.415 0.430
0.050 BSC
eA
R
0.371 0.387
0.030 TYP
9.420 9.830
0.760 TYP
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
ORDERING INFORMATION
PART NUMBER
MTS1512K8C45LSJ2SQ
5962-9560018QMA
MTS1512K8C45LSJ2Q
5962-9560018QMC
MTS1512K8C45LSJ2SM
5962-9560018MMA
MTS1512K8C45LSJ2M
5962-9560018MMC
MTS1512K8C45LSJ2SM
MTS1512K8C45LSJ2M
MTS1512K8C45LSJ2SE
MTS1512K8C45LSJ2E
MTS1512K8C35LSJ2SQ
5962-9560019QMA
MTS1512K8C35LSJ2Q
5962-9560019QMC
MTS1512K8C35LSJ2SM
5962-9560019MMA
SPEED
45ns
45ns
45ns
45ns
45ns
45ns
45ns
45ns
45ns
45ns
45ns
45ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
35ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
25ns
PCK
LEAD
SnPb
SnPb
Au
Vinput
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Power
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
DR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TEMP / SCREENING
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
SnPb
Au
SnPb
SnPb
Au
(-55˚C to +125˚C)
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
Extended Temp
Extended Temp
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
SnPb
Au
SnPb
SnPb
Au
MTS1512K8C35LSJ2M
5962-9560019MMC
(-55˚C to +125˚C)
MTS1512K8C35LSJ2SM
MTS1512K8C35LSJ2M
MTS1512K8C35LSJ2SE
MTS1512K8C35LSJ2E
MTS1512K8C25LSJ2SQ
5962-9560020QMA
MTS1512K8C25LSJ2Q
5962-9560020QMC
MTS1512K8C25LSJ2SM
5962-9560020MMA
MTS1512K8C25LSJ2M
5962-9560020MMC
MTS1512K8C25LSJ2SM
MTS1512K8C25LSJ2M
MTS1512K8C25LSJ2SE
MTS1512K8C25LSJ2E
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
Extended Temp
Extended Temp
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
(-55˚C to +125˚C)
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
SnPb
Au
Extended Temp
Extended Temp
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
MTS1512K8C20LSJ2SQ
5962-9560021QMA
MTS1512K8C20LSJ2Q
5962-9560021QMC
MTS1512K8C20LSJ2SM
5962-9560021MMA
MTS1512K8C20LSJ2M
5962-9560021MMC
MTS1512K8C20LSJ2SM
MTS1512K8C20LSJ2M
MTS1512K8C20LSJ2SE
MTS1512K8C20LSJ2E
MTS1512K8C15LSJ2SQ
5962-9560022QMA
MTS1512K8C15LSJ2Q
5962-9560022QMC
MTS1512K8C15LSJ2SM
5962-9560022MMA
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
15ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
12ns
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
36CSOJ
SnPb
SnPb
Au
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Center
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
SnPb
Au
SnPb
SnPb
Au
(-55˚C to +125˚C)
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
Extended Temp
Extended Temp
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
SnPb
Au
SnPb
SnPb
Au
MTS1512K8C15LSJ2M
5962-9560022MMC
(-55˚C to +125˚C)
MTS1512K8C15LSJ2SM
MTS1512K8C15LSJ2M
MTS1512K8C15LSJ2SE
MTS1512K8C15LSJ2E
MTS1512K8C12LSJ2SQ
5962-9560023QMA
MTS1512K8C12LSJ2Q
5962-9560023QMC
MTS1512K8C12LSJ2SB
5962-9560023MMA
MTS1512K8C12LSJ2B
5962-9560023MMC
MTS1512K8C12LSJ2SM
MTS1512K8C12LSJ2M
MTS1512K8C12LSJ2SE
MTS1512K8C12LSJ2E
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
Extended Temp
Extended Temp
QML
QML
QML
QML
883
883
883
883
Au
SnPb
SnPb
Au
Au
SnPb
Au
(-55˚C to +125˚C)
Mil-Temp
Mil-Temp
(-55˚C to +125˚C)
(-40˚C to +105˚C)
(-40˚C to +105˚C)
SnPb
Au
Extended Temp
Extended Temp
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
相关型号：
©2020 ICPDF网 联系我们和版权申明