SMJ44C251B-10HM [MICROSS]
Memory IC;
| 型号： | SMJ44C251B-10HM |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Memory IC |
| 文件： | 总53页 (文件大小：945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
Military Operating Temperature Range
Enhanced Page-Mode Operation for Faster
Access
– 55°C to 125°C
Performance Ranges:
CAS-Before-RAS (CBR) and Hidden
Refresh Modes
ACCESS
TIME
ACCESS ACCESS ACCESS
TIME
TIME
TIME
SERIAL
ENABLE
(MAX)
All Inputs/Outputs and Clocks Are TTL
Compatible
ROW
COLUMN SERIAL
ADDRESS ENABLE DATA
(MAX) (MAX) (MAX)
Long Refresh Period
Every 8 ms (Max)
t
t
t
t
a(SE)
20 ns
a(R)
a(C)
a(SQ)
Up to 33-MHz Uninterrupted Serial-Data
Streams
’44C251B-10 100 ns
’44C251B-12 120 ns
25 ns
30 ns
30 ns
35 ns
25 ns
3-State Serial I/Os Allow Easy Multiplexing
of Video-Data Streams
Class B High-Reliability Processing
DRAM: 262144 Words × 4 Bits
SAM: 512 Words × 4 Bits
512 Selectable Serial-Register Starting
Locations
Single 5-V Power Supply (±10% Tolerance)
Packaging:
– 28-Pin J-Leaded Ceramic Chip Carrier
Package (HJ Suffix)
– 28-Pin Leadless Ceramic Chip Carrier
Package (HM Suffix)
– 28-Pin Ceramic Sidebrazed DIP
(JD Suffix)
Dual Port Accessibility–Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Bidirectional-Data-Transfer Function
Between the DRAM and the Serial-Data
Register
4 × 4 Block-Write Feature for Fast Area Fill
Operations; As Many as Four Memory
Address Locations Written per Cycle From
an On-Chip Color Register
– 28-Pin Zig-Zag In-Line (ZIP), Ceramic
Package (SV Suffix)
Split Serial-Data Register for Simplified
Real-Time Register Reload
Write-Per-Bit Feature for Selective Write to
Each RAM I/O; Two Write-Per-Bit Modes to
Simplify System Design
description
PIN NOMENCLATURE
A0–A8
CAS
DQ0–DQ3
SE
RAS
SC
SDQ0–SDQ3 Serial Data In-Out
TRG
W
DSF
QSF
Address Inputs
Column Enable
DRAM Data In-Out/Write-Mask Bit
Serial Enable
Row Enable
The SMJ44C251B multiport video RAM is a
high-speed, dual-ported memory device. It
consists of a dynamic random-access memory
(DRAM) organized as 262144 words of 4 bits
each interfaced to a serial-data register or
serial-access memory (SAM) organized as 512
words of 4 bits each. The SMJ44C251B supports
three types of operation: random access to and
from the DRAM, serial access to and from the
serial register, and bidirectional transfer of data
between any row in the DRAM and the serial
register. Except during transfer operations, the
SMJ44C251B can be accessed simultaneously
and asynchronously from the DRAM and SAM
ports.
Serial Data Clock
Transfer Register/Q Output Enable
Write-Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5-V Supply
V
V
SS
GND
CC
Ground
Ground (Important: Not connected
to internal V
)
SS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
pinouts
HJ PACKAGE
(TOP VIEW)
HM PACKAGE
(TOP VIEW)
JD PACKAGE
(TOP VIEW)
SV PACKAGE
(TOP VIEW)
V
V
1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DSF
DQ3
SDQ2
SC
SDQ0
SC
SDQ0
SS
SS
SC
SDQ0
SDQ1
TRG
DQ0
DQ1
W
V
SS
1
28
27
2
4
6
8
DQ2
SE
SDQ3
SC
SDQ1
DQ0
W
RAS
A8
A4
A7
A2
A0
3
5
7
9
2
2
SDQ3
SDQ2
SE
SDQ3
SDQ2
SE
SDQ3
SDQ2
SE
2
3
3
SDQ1
TRG
DQ0
DQ1
W
SDQ1
TRG
DQ0
DQ1
W
3
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
4
4
4
SDQ0
TRG
DQ1
GND
A8
5
5
DQ3
DQ2
DSF
CAS
DQ3
DQ2
DSF
CAS
DQ3
DQ2
DSF
CAS
QSF
A0
5
10
11
6
6
6
12
13
7
7
14
15
7
8
8
GND
RAS
A8
A6
A5
GND
RAS
A8
A6
A5
16
17
GND
RAS
A8
8
9
9
QSF
A0
A1
QSF
A0
A1
18
19
9
A5
10
11
12
13
14
10
11
12
13
14
20
21
10
11
12
13
14
V
CC
A3
22
23
A6
A1
A2
A3
A7
A2
A3
A7
24
25
A5
A2
A1
QSF
A4
A4
26
27
A4
A3
V
V
CC
CC
28
CAS
V
A7
CC
description (continued)
During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data
register. The 512 × 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents
of the 512 × 4-bit serial-data register can be written to the memory row (transfer write).
The SMJ44C251B is equipped with several features designed to provide higher system-level bandwidth and
to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates
can be achieved by the device’s 4 × 4 block-write mode. The block-write mode allows four bits of data (present
in an on-chip color-data register) to be written to any combination of four adjacent column-address locations.
As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a
writemaskorawrite-per-bitfeatureallowsmaskinganycombinationofthefourinput/outputsonanywritecycle.
The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write
cycles. The mask register eliminates having to provide mask data on every mask-write cycle.
The SMJ44C251B offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port).
This feature enables real-time register reload implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high half and a low half. While one half is being read
out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time
register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation
is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an
external device. Once the serial register within the SAM is loaded, its contents can be transferred to the
corresponding column positions in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit
position is accessed from the active half of the register and immediately transfers control to the opposite half.
A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the
split-register mode.
All inputs, outputs, and clock signals on the SMJ44C251B are compatible with Series 54 TTL devices. All
address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched
to allow greater system flexibility.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
description (continued)
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup, row-address hold, and address multiplex is
eliminated, and a memory cycle time reduction of up to 3× can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that can be accessed is determined by the maximum RAS low time
and page-mode cycle time used. The SMJ44C251B allows a full page (512 cycles) of information to be
accessed in read, write, or read-modify-write mode during a single RAS-low period using relatively conservative
page-mode cycle times.
The SMJ44C251B employs state-of-the-art technology for very high performance combined with improved
reliability. For surface mount technology, the SMJ44C251B is offered in a 28-pin J-leaded chip carrier package
(HJ suffix) or a 28-pin leadless ceramic chip carrier package (HM suffix). The SMJ44C251B is offered in a 28-pin
400-mil dual-in-line ceramic sidebrazed package (JD suffix) or a 28-pin ZIP ceramic package (SV suffix) for
through-hole insertion. The L suffix device is rated for operation from 0°C to 70°C. The M suffix device is rated
for operation from – 55°C to 125°C.
The SMJ44C251B and other multiport video RAMs are supported by a broad line of video/graphic processors
from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors.
functional block diagram
O B
u u
t
f
f
p
R
e
g
i
s
t
u e
t
r
V
V
C
o
l
o
r
CC
SS
DQ0
DQ1
DQ2
DQ3
F
u
n
c
t
S
p
e
c
i
a
l
C B
o u
L
o
g
i
Write-
Per-Bit
Control
e
r
MUX
l
f
f
B
u
f
A0
A1
A2
A3
A4
A5
A6
A7
A8
I
Column Decoder
Sense Amplifier
u
m e
n r
n
p
u
t
i
c
o
n
f
e
r
D
e
c
o
d
e
r
B
u
B
u
f
f
e
r
R
W/B
Unlatch
W/B
Latch
Address
Mask
R
o
w
I
f
o
n
p
u
t
f
e
r
w
DSF
Data Transfer
Gate
R C
e o
f
u
S O B
Serial Data
Register
r n
e
r
i
a
l
u u
A C
d o
d u
e
t
S
t
f
f
s e
h r
e
r
i
p
u e
r
n
t
Serial Data
Pointer
t
r
e
SDQ0
SDQ1
SDQ2
SDQ3
RAS
a
l
G
e
s e
s
r
CAS
TRG
W
T
n
i
e
m
r
QSF
Split Register
S
e
r
B
u
f
i
n
g
o
a
t
I
n
p
u
t
SC
i
f
r
SE
a
l
e
r
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
Function Table
CAS
RAS FALL
ADDRESS
DQ0–DQ3
FALL
DSF
X
†
FUNCTION
TYPE
§
CAS
W
‡
W
CAS TRG
DSF
X
SE
X
RAS
CAS
RAS
CBR refresh
L
X
L
X
L
X
X
X
X
X
R
T
Register-to-memory transfer
(transfer write)
Row
Addr
Tap
Point
H
X
L
X
X
X
X
X
X
Alternate transfer write
(independent of SE)
Row
Addr
Tap
Point
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
T
T
Serial-write-mode enable
(pseudo-transfer write)
Refresh
Addr
Tap
Point
Memory-to-register transfer
(transfer read)
Row
Addr
Tap
Point
L
H
H
L
L
T
Split-register-transfer read
(must reload tap)
Row
Addr
Tap
Point
L
H
L
T
Load and use write mask,
Write data to DRAM
Row
Addr
Col
Addr
DQ
Mask
Valid
Data
H
H
H
H
H
H
H
H
R
R
R
R
R
R
R
R
Load and use write mask,
Block write to DRAM
Row
Addr
Blk Addr
A2–A8
DQ
Col
L
L
H
L
Mask
Mask
Persistent write-per-bit,
Write data to DRAM
Row
Addr
Col
Addr
Valid
Data
L
H
H
L
X
X
X
X
X
X
Persistent write-per-bit,
Block write to DRAM
Row
Addr
Blk Addr
A2–A8
Col
Mask
L
H
L
Normal DRAM read/write
(nonmasked)
Row
Addr
Col
Addr
Valid
Data
H
H
H
H
Block write to DRAM
(nonmasked)
Row
Addr
Blk Addr
A2–A8
Col
Mask
L
H
L
Refresh
Addr
DQ
Mask
Load write mask
H
H
X
X
Refresh
Addr
Color
Data
Load color register
H
Legend:
H = High
L = Low
X = Don’t care
†
‡
§
R = random access operation; T = transfer operation
In persistent write-per-bit function, W must be high during the refresh cycle.
DQ0–DQ3 are latched on the later of W or CAS falling edge.
Col Mask = H: Write to address/column location enabled
DQ Mask = H: Write to I/O enabled
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
operation
Depending on the type of operation chosen, the signals of the SMJ44C251B perform different functions.
Table 1 summarizes the signal descriptions and the operational modes they control.
Table 1. Detailed Signal Description Versus Operational Mode
PIN
A0–A8
CAS
DRAM
TRANSFER
Row, tap address
SAM
Row, column address
Column enable, output enable
DRAM data I/O, write mask bits
Tap-address strobe
DQi
DSF
Block-write enable
Split-register enable
Persistent write-per-bit enable
Color-register load enable
Alternate write-transfer enable
RAS
SE
Row enable
Row enable
Serial-in mode enable
Serial enable
Serial clock
SC
SDQ
TRG
W
Serial-data I/O
Q output enable
Transfer enable
Write enable, write-per-bit select
Transfer-write enable
Split register
Active status
QSF
NC/GND
Make no external connection or tie to system V
.
SS
V
V
5-V supply (typical)
CC
Device ground
SS
The SMJ44C251B has three kinds of operations: random-access operations typical of a DRAM, transfer
operations from memory arrays to the SAM, and serial-access operations through the SAM port. The signals
used to control these operations are described here, followed by discussions of the operations themselves.
address (A0–A8)
For DRAM operation, 18 address bits are required to decode one of the 262144 storage cell locations. Nine
row-address bits are set up on A0–A8 and latched onto the chip on the falling edge of RAS. Nine
column-address bits are set up on A0–A8 and latched onto the chip on the falling edge of CAS. All addresses
must be stable on or before the falling edges of RAS and CAS.
During the transfer operation, the states of A0–A8 are latched on the falling edge of RAS to select one of the
512 rows where the transfer occurs. To select one of 512 tap points (starting positions) for the serial-data input
or output, the appropriate 9-bit column address (A0–A8) must be valid when CAS falls.
row-address strobe (RAS)
RAS is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge
of RAS. RAS is a control input that latches the states of row address, W, TRG, SE, CAS, and DSF onto the chip
to invoke DRAM and transfer functions.
column-address strobe (CAS)
CASisacontrolinputthatlatchesthestatesofcolumnaddressandDSFtocontrolDRAMandtransferfunctions.
When CAS is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output.
CAS also acts as an output enable for the DRAM outputs DQ0–DQ3.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
output enable/transfer select (TRG)
TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as
RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM outputs DQ0–DQ3. For
transfer operation, TRG must be brought low before RAS falls.
write-mask select, write enable (W)
In DRAM operation, W enables data to be written to the DRAM. W is also used to select the DRAM write-per-bit
mode. HoldingWlow on the falling edge of RAS invokes the write-per-bit operation. The SMJ44C251B supports
both the normal write-per-bit mode and the persistent write-per-bit mode.
For transfer operation, W selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation
(SAM to DRAM). During a transfer cycle, if W is high when RAS falls, a read transfer occurs; if W is low, a write
transfer occurs.
special function select (DSF)
DSF is latched on the falling edge of RAS or CAS, similar to an address. DSF determines which of the following
functions are invoked on a particular cycle:
Persistent write-per-bit
Block write
Split-register transfer read
Mask-register load for the persistent write-per-bit mode
Color-register load for the block-write mode
DRAM data I/O, write-mask data (DQ0–DQ3)
DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W is
brought low prior to CAS and the data is strobed in by CAS with data setup and hold times referenced to this
signal. In a delayed-write or read-modify-write cycle, W is brought low after CAS and the data is strobed in by
W with data setup and hold times referenced to this signal.
The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series
54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state
aslongasCASand TRG are held high. Data does not appear at the outputs until both CAS and TRG arebrought
low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going high returns
the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the
high-impedance state for the entire cycle.
The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS. This
mask selects which of the four random I/Os are written.
serial data I/O (SDQ0–SDQ3)
Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined
by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in
serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the
most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be
accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the
data register is in serial-input mode and signal data can be input to the register.
serial clock (SC)
Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B is designed
to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement
because the data registers that comprise the SAM are static. There is also no minimum SC clock operating
frequency.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
serial enable (SE)
During serial-access operations SE is used as an enable/disable for SDQ in both the input and output modes.
IfSEisheldasRASfallsduringawrite-transfercycle, apseudo-transferwriteoccurs. Thereisnoactualtransfer,
but the data register switches from the output mode to the input mode.
no connect/ground (NC/GND)
NC/GND is reserved for the manufacturer’s test operation. It is an input and should be tied to system ground
or left floating for proper device operation.
special function output (QSF)
During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF
is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high,
the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon
crossing the boundary between the two SAM halves in the split-register mode.
DuringnormaltransferoperationsQSFchangesstateuponcompletingatransfercycle. Thisstateisdetermined
by the tap point being loaded during the transfer cycle.
power up
To achieve proper device operation, an initial pause of 200 µs is required after power-up, followed by a minimum
of eight RAS cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
random-access operation
The random-access operation functions are summarized in Table 2 and described in the following sections.
Table 2. Random-Access-Operation Functions
CAS
FALL
RAS FALL
ADDRESS
DQ0–DQ3
FUNCTION
‡
CAS
W
†
CAS
L
TRG
X
W
DSF
X
SE
X
DSF
X
RAS
CAS
RAS
CBR refresh
X
L
X
X
X
X
Load and use write mask,
Write data to DRAM
Row
Addr
Col
Addr
DQ
Mask
Valid
Data
H
H
L
X
L
Load and use write mask,
Block write to DRAM
Row
Addr
Blk Addr
A2–A8
DQ
Mask
Col
Mask
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
X
X
X
X
X
X
X
H
L
Persistent write-per-bit,
Write data to DRAM
Row
Addr
Col
Addr
Valid
Data
X
X
X
X
X
X
Persistent write-per-bit,
Block write to DRAM
Row
Addr
Blk Addr
A2–A8
Col
Mask
L
H
L
Normal DRAM read/write
(nonmasked)
Row
Addr
Col
Addr
Valid
Data
H
H
H
H
Block write to DRAM
(nonmasked)
Row
Addr
Blk Addr
A2–A8
Col
Mask
L
H
L
Refresh
Addr
DQ
Mask
Load write mask
H
H
X
X
Refresh
Addr
Color
Data
Load color register
H
Legend:
H = High
L = Low
X = Don’t care
†
‡
In persistent write-per-bit function, W must be high during the refresh cycle.
DQ0–DQ3 are latched on the later of W or CAS falling edge.
Col Mask = H: Write to address/column location enabled
DQ Mask = H: Write to I/O enabled
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. This mode eliminates the time required for row address setup-and-hold and
address multiplex. The maximum RAS low time and the CAS page cycle time used determine the number of
columns that can be accessed.
Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B to operate at a
higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS
transitions low. A valid column address can be presented immediately after row-address hold time has been
satisfied, usually well in advance of the falling edge of CAS. In this case, data can be obtained after t
max
a(C)
(access time from CAS low), if t
max (access time from column address) has been satisfied.
a(CA)
refresh
There are three types of refresh available on the SMJ44C251B: RAS-only refresh, CBR refresh, and hidden
refresh.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
RAS-only refresh
A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS is
applied, the output buffers are in the high-impedance state, so the RAS-only refresh sequence avoids any
outputduringrefresh. ExternallygeneratedaddressesmustbesuppliedduringRAS-onlyrefresh. Strobingeach
of the 512 row addresses with RAS causes all bits in each row to be refreshed. CAS can remain high (inactive)
for this refresh sequence to conserve power.
CAS-before-RAS (CBR) refresh
CBR refresh is accomplished by bringing CAS low earlier than RAS. The external row address is ignored and
the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in
between CBR cycles without disturbing the internal address generation.
hidden refresh
A hidden refresh is accomplished by holding CAS low in the DRAM-read cycle andcyclingRAS. The output data
of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed
row addresses are generated internally during the hidden refresh.
write-per-bit
The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1).
The write-per-bit operation is invoked only when W is held low on the falling edge of RAS. If W is held high on
the falling edge of RAS, write-per-bit is not enabled and the write operation is performed to all four DQs. The
SMJ44C251B offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent
write-per-bit mode.
nonpersistent write-per-bit
When DSF is low on the falling edge of RAS, the write mask is reloaded. A 4-bit code (the write-per-bit mask)
is input to the device via the random DQ terminals and latched on the falling edge of RAS. The write-per-bit mask
selects which of the four random I/Os are written and which are not. After RAS has latched the on-chip
write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS or
W. When a data low is strobed into a particular I/O on the falling edge of RAS, data is not written to that I/O. When
a data high is strobed into a particular I/O on the falling edge of RAS, data is written to that I/O.
persistent write-per-bit
When DSF is high on the falling edge of RAS, the write-per-bit mask is not reloaded: it retains the value stored
during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because
the write-per-bit mask is persistent over an arbitrary number of write cycles. The write-per-bit mask reload can
be done during the nonpersistent write-per-bit cycle or by the mask-register-load cycle.
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persistent write-per-bit (continued)
Nonpersistant Write-Per-Bit
Write-Mask-Register Load
Persistent Write-Per-Bit
RAS
CAS
A0–A8
DSF
W
DQ0–
DQ3
DQ Mask
Write Data
DQ Mask
Write Data
DQ Mask = H: Write to I/O enabled
=
L: Write to I/O disabled
Figure 1. Example of Write-Per-Bit Operations
block write
The block-write mode allows data (present in an on-chip color register) to be written into four consecutive
column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-per-bit
modes can be applied in the block-write cycle. The block-write mode also offers the 4 × 4 column-mask
capability.
load color register
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high
on the falling edges of RAS and CAS. A 4-bit code is input to the color register via the random I/O terminals and
latched on the later of the falling edge of CAS or W. After the color register is loaded, it retains data until power
is lost or until another load-color-register cycle is executed.
block write cycle
After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held
high on the falling edge of CAS (see Figures 2, 3, and 4). When the block-write cycle is invoked, each data bit
in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random
I/O.
During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the falling
edge of CAS. The two least significant addresses (A0–A1) are replaced by four DQ bits (DQ0–DQ3), which
are also latched on the later of the falling edge of CAS or W. These four bits are used as a column mask, and
they indicate which of the four column-address locations addressed by A2–A8 are written with the contents of
the color register during the block-write cycle. DQ0 enables a write to column-address A1 = 0 (low), A0 = 0 (low);
DQ1 enables a write to column-address A1 = 0 (low), A0 = 1 (high); DQ2 enables a write to column-address
A1 = 1 (high), A0 = 0 (low); DQ3 enables a write to column-address A1 = 1 (high), A0 = 1 (high). A high logic
level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 × 4) can be written to
memory during each CAS cycle in the block-write mode.
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block write cycle (continued)
Load-Color-Register Cycle
†
†
†
Block-Write Cycle
(no DQ mask)
Block-Write Cycle
(load and use DQ mask)
Block-Write Cycle
(use previously
loaded DQ mask)
RAS
CAS
A0–A8
1
2
3
2
3
2
3
†
W
TRG
DSF
DQ0–DQ3
4
5
6
5
5
†
W must be low during the block-write cycle.
NOTE: DQ0–DQ3 are latched on the later of W or CAS falling edge except in block 6 (see legend).
Legend:
1. Refresh address
2. Row address
3. Block address (A2 –A8)
4. Color-register data
5. Column-mask data
6. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS.
= don’t care
Figure 2. Example Block-Write Diagram Operations
N + 1
N
N + 2
N + 3
I/O3
I/O2
Block-Write
Enable
A2–A8
A0–A1
1-of-4
I/O1
Load Write
Mask
4-of-512
Decode
I/O0
Decode
Write-Mask
Register
Write
MUX
MUX
MUX
MUX
Select
DQ0
DQ1
DQ2
DQ
Write
Enable
Write
Select
Load
Color
Register
Data
Write
Select
In
Color
MUX
Register
Write
Select
DQ3
Block-Write
Enable
Figure 3. Block-Write Circuit Block Diagram
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block write cycle (continued)
COLOR
REGISTER
DATA
COLUMN
MASK
DQ MASK
COLUMN 1 COLUMN 2
COLUMN 3 COLUMN 4
DQ0
DQ1
DQ2
DQ3
1
1
0
1
0
1
1
1
0
0
1
1
DQ0
DQ1
DQ2
DQ3
Masked
Masked
Masked
Masked
0
0
0
Block Write
0
Masked
1
0
Masked
1
0
Masked
1
Figure 4. Example of Block Write Operation With DQ Mask and Address Mask
transfer operation
Transfer operations between the memory arrays (DRAM) and the data registers (SAM) are invoked by bringing
TRG low before RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS,
determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random
and the serial interfaces.
Random-Access Port
Col
0
Col
255
Col
256
Col
511
Row
0
4
Memory Array
262 144 Bits
DQ0–DQ3
Row
511
256
256
TRG
A8
Transfer-
Pass
Gate
Transfer-
Transfer-
Control
Logic
Pass
Gate
DSF
W
256
256-Bit Data Register
256
256-Bit Data Register
SE
SC
A0–A8
A8
Serial
Counter
MUX
4
SDQ0–SDQ3
SE
TRG
W
Serial-
I/O
Control
Figure 5. Block Diagram Showing One Random and One Serial-I/O Interface
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transfer operation (continued)
As shown in Table 3, the SMJ44C251B supports five basic modes of transfer operation:
Register-to-memory transfer (normal write transfer, SAM to DRAM)
Alternate-write transfer (independent of the state of SE)
Memory-to-register transfer (pseudo-transfer write). Switches serial port from serial-out mode to serial-in
mode. No actual data transfer takes place between the DRAM and the SAM.
Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM)
Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
Table 3. Transfer-Operation Functions
CAS
FALL
RAS FALL
W
ADDRESS
DQ0–DQ3
CAS
FUNCTION
CAS
TRG
DSF
SE
DSF
RAS
CAS
RAS
W
Register-to-memory transfer
(normal write transfer)
Row
Addr
Tap
Point
H
H
H
H
H
L
L
L
L
L
L
L
X
H
L
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Alternate-write transfer
(independent of SE)
Row
Addr
Tap
Point
X
X
X
X
Serial-write-mode enable
(pseudo-transfer write)
Refresh
Addr
Tap
Point
L
Memory-to-register transfer
(normal read transfer)
Row
Addr
Tap
Point
H
H
L
Split-register-read transfer
(must reload tap)
Row
Addr
Tap
Point
H
Legend:
H = High
L = Low
X = Don’t care
write transfer
All write-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row
in the DRAM. To invoke a write-transfer cycle, W must be low when RAS falls. There are three possible
write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer.
All write-transfer cycles switch the serial port to the serial-in mode.
normal-write transfer (SAM-to-DRAM transfer)
A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array.
TRG, W, and SE are brought low and latched at the falling edge of RAS. Nine row-address bits (A0–A8) are
also latched at the falling edge of RAS to select one of the 512 rows available as the destination of the data
transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS to select one of the 512
tap points in SAM that are available for the next serial input.
During a write-transfer operation before RAS falls, the serial-input operation must be suspended after a
minimum delay of t
(see Figure 6).
but can be resumed after a minimum delay of t
after RAS goes high
d(SCRL)
d(RHSC)
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normal-write transfer (SAM-to-DRAM transfer) (continued)
RAS
CAS
Row
Tap Point
A0–A8
TRG
W
SE
t
d(SCRL)
t
d(RHSC)
SC
Figure 6. Normal-Write-Transfer-Cycle Timing
alternate-write transfer (refer to Figure 30)
When DSF is brought high and latched at the falling edge of RAS in the normal-write-transfer cycle, the
alternate-write transfer occurs.
pseudo-write transfer (write-mode control) (refer to Figure 28)
To invoke the pseudo-write transfer (write-mode control cycle), SEis brought high and latched at the falling edge
of RAS. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial
port from the serial-out (read) mode to the serial-in (write) mode.
Before serial data can be clocked into the serial port via the SDQ terminals and the SC input, the SDQ terminals
must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the
row address (A0–A8) is in the don’t care state and the column address (A0–A8), which is latched on the falling
edge of CAS, selects one of the 512 tap points in the SAM that are available for the next serial input.
read transfer (DRAM-to-SAM transfer) (refer to Figure 7)
During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two
read-transfer operations: normal-read transfer and split-register-read transfer.
normal-read transfer (refer to Figure 7)
The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG is brought low and
latched at the falling edge of RAS. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS
to select one of the 512 rows available for transfer. The nine column-address bits (A0–A8) are latched at the
falling edge of CAS to select one of the SAM’s 512 available tap points where the serial data is read out.
A normal-read transfer can be performed in three ways: early-load read transfer, real-time or midline-load read
transfer, and late-load read transfer. Each of these offers the flexibility of controlling the TRG trailing edge in
the read-transfer cycle (see Figure 7).
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normal-read transfer (continued)
Early-Load Read Transfer
RAS
Real-Time-Reload Read Transfer
Late-Load Read Transfer
CAS
A0–A8
Row
Tap Point
Row
Tap Point
Row
Tap Point
TRG
SC
Bit
512
Tap
Bit
Bit
510
Bit
511
Tap
Bit
Bit
510
Bit
511
Tap
Bit
Figure 7. Normal-Read-Transfer Timings
split-register-read transfer
In split-register-read-transfer operation, the serial-data register is split into halves. The low half contains bits
0–255, and the high half contains 256–511. While one half is being read out of the SAM port, the other half can
be loaded from the memory array.
To invoke a split-register read-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS to select
one of the 512 rows available for the transfer. The nine column-address bits (A0–A8) are latched at the falling
edge of CAS, where address bits A0 –A7 select one of the 255 tap points in the specified half of SAM and
address bit A8 selects which half is to be transferred. If A8 is a logic low, the low half is transferred. If A8 is a
logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points.
A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the
normal-read-transfer cycle, the first split-register read transfer can follow immediately without any minimum SC
requirement. However, there is a minimum requirement of a rising edge of SC between split-register
read-transfer cycles.
QSF indicates which half of the SAM is being accessed during serial-access operation. When QSF is low, the
serial-address pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the
pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a
normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF.
In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is
reached (see Figure 8 and Figure 9).
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split-register-read transfer (continued)
Read Transfer
With Tap Point N
Split-Register
Read Transfer
RAS
CAS
TRG
DSF
SC
Tap
Point N
t
d(GHQSF)
t
d(CLQSF)
QSF
Figure 8. Example of a Split-Register Read-Transfer Cycle After a Normal Read-Transfer Cycle
Split-Register
Read Transfer
With Tap Point N
Split-Register
Read Transfer
RAS
CAS
TRG
DSF
t
d(MSRL)
t
d(RHMS)
SC
255
Tap
or 511
Point N
t
a(SCQSF)
QSF
Figure 9. A Split-Register Read-Transfer Cycle After a Split-Register Read-Transfer Cycle
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serial-access operation
The serial-read and serial-write operations can be performed through the SAM port simultaneously and
asynchronously with DRAM operations except during transfer operations. The preceding transfer operation
determines the input or output state of the SAM port. If the preceding transfer operation is a read-transfer
operation, the SAM port is in the output mode. If the preceding transfer operation is a write- or
pseudo-write-transfer operation, the SAM port is in the input mode.
Serial data can be read out of or written into SAM by clocking SC starting at the tap point loaded by the preceding
transfer cycle, proceeding sequentially to the most significant bit (bit 511), then wrapping around to the least
significant bit (bit 0) (see Figure 10).
0
1
2
Tap
510
511
Figure 10. Serial Pointer Direction for Serial Read/Write
For split-register read-transfer operation, serial data can be read out from the active half of SAM by clocking
SC starting at the tap point loaded by the preceding split-register-transfer cycle, then proceeding sequentially
to the most significant bit of the half, bit 255 or bit 511. If there is a split-register-read transfer to the inactive half
during this period, the serial pointer points next to the tap-point location loaded by that split register (see
Figure 11, Case I). If there is no split-register read transfer to the inactive half during this period, the serial pointer
points next to bit 256 or bit 0, respectively (see Figure 11, Case II).
Case I
0
0
Tap
Tap
254
255
256
Tap
510
510
511
511
Case I I
254
255
256
Tap
Figure 11. Serial Pointer for Split-Register Read
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†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T : L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note Note 2)
2.9
–1
6.5
0.6
70
IL
L suffix
M suffix
L suffix
M suffix
0
T
A
Operating free-air temperature
Operating case temperature
°C
°C
– 55
125
70
T
C
125
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
High-level output voltage
TEST CONDITIONS
= –5 mA
MIN
MAX
UNIT
V
V
V
I
I
2.4
OH
OH
Low-level output voltage (see Note 3)
= 4.2 mA
= 5 V,
0.4
±10
±10
V
OL
OL
V
V = 0 V to 5.8 V,
I
CC
All others open
I
I
Input leakage current
µA
I
O
Output leakage current (see Note 4)
V
= 5.5 V,
V = 0 V to V
O CC
µA
CC
NOTES: 3. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic
Designer’s Handbook. This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ
terminalswhentheDQterminalsareswitched. ThismaycauseV
and V
toexceedthedata-booklimitforashortperiodoftime,
OL
OH
depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the
device to minimize simultaneous switching effects.
4. SE is disabled for SDQ output leakage tests.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’44C251B-10 ’44C251B-12
SAM
PORT
†
PARAMETER (SEE NOTE 5)
UNIT
TEST CONDITIONS
MIN
MAX
100
110
15
MIN
MAX
90
I
I
I
I
I
I
I
I
I
I
I
I
Operating current
t
t
and t
c(W)
= MIN
Standby
Active
CC1
c(rd)
Operating current
= MIN
100
15
CC1A
CC2
c(SC)
Standby current
All clocks = V
CC
Standby
Active
Standby current
t
t
t
t
t
t
t
t
t
= MIN
35
35
CC2A
CC3
c(SC)
RAS-only refresh current
RAS-only refresh current
Page-mode current
Page-mode current
CAS-before-RAS current
CAS-before-RAS current
Data-transfer current
Data-transfer current
and t
c(W)
= MIN
Standby
Active
100
110
65
90
c(rd)
= MIN
100
60
CC3A
CC4
c(SC)
mA
= MIN
Standby
Active
c(P)
= MIN
70
65
CC4A
CC5
c(SC)
and t
c(W)
= MIN
= MIN
Standby
Active
90
80
c(rd)
= MIN
110
100
110
100
90
CC5A
CC6
c(SC)
and t
c(W)
Standby
Active
c(rd)
= MIN
100
CC6A
c(SC)
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTE 5:
I
I
I
(standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for I
).
CC2
CC
(active) denotes that the SAM port is active and the DRAM port is active (except for I
).
CC2
CCA
is measured with no load on DQ or SDQ.
CC
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capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
Input capacitance, A0–A8
7
7
9
9
i(A)
Input capacitance, CAS and RAS
Output capacitance, SDQs and DQs
Output capacitance, QSF
pF
i(RC)
o(O)
pF
pF
o(QSF)
NOTE 6: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the terminal under test. All other terminals are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
’44C251B-10 ’44C251B-12
TEST
CONDITIONS
ALT.
SYMBOL
PARAMETER
UNIT
†
MIN
MAX
25
MIN
MAX
30
t
t
t
t
t
t
t
Access time from CAS
t
t
t
t
= MAX
= MAX
= MAX
= MAX
t
ns
ns
ns
ns
ns
ns
ns
a(C)
d(RLCL)
d(RLCL)
d(RLCL)
d(RLCL)
CAC
Access time from column address
Access time from CAS high
t
50
60
a(CA)
a(CP)
a(R)
AA
t
55
65
CPA
RAC
OEA
Access time from RAS
t
t
100
25
120
30
Access time of DQ0–DQ3 from TRG low
Access time of SDQ0–SDQ3 from SC high
Access time of SDQ0–SDQ3 from SE low
a(G)
C
C
= 30 pF
t
SCA
30
35
a(SQ)
a(SE)
L
L
= 30 pF
t
20
25
SEA
Disable time, random output from CAS high
(see Note 8)
t
t
t
C
C
C
= 100 pF
t
0
0
0
20
20
20
0
0
0
20
20
20
ns
ns
ns
dis(CH)
dis(G)
L
L
L
OFF
Disable time, random output from TRG high
(see Note 8)
= 100 pF
= 30 pF
t
OEZ
Disable time, serial output from SE high
(see Note 8)
t
dis(SE)
SEZ
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTES: 7. Switching times assume C = 100 pF unless otherwise noted (see Figure 12).
L
8.
t
, t
, and t
are specified when the output is no longer driven.
dis(CH) dis(G)
dis(SE)
20
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262144 BY 4-BIT
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature
’44C251B-10
MAX
ALT.
SYMBOL
UNIT
MIN
190
190
250
60
105
190
190
30
20
25
80
100
25
25
10
10
35
35
30
100
0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (see Note 9)
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(rd)
RC
Cycle time, write (see Note 9)
c(W)
WC
Cycle time, read-modify-write (see Note 9)
Cycle time, page-mode read or write (see Note 9)
Cycle time, page-mode read-modify-write (see Note 9)
Cycle time, read transfer (see Note 9)
Cycle time, write transfer (see Note 9)
Cycle time, serial clock (see Notes 9 and 10)
Pulse duration, CAS high
c(rdW)
c(P)
RMW
PC
c(rdWP)
c(TRD)
c(TW)
c(SC)
PRMW
RC
WC
SCC
CPN
CAS
RP
w(CH)
Pulse duration, CAS low (see Note 11)
Pulse duration, RAS high
75000
75000
w(CL)
w(RH)
Pulse duration, RAS low (see Note 12)
Pulse duration, W low
w(RL)
RAS
WP
w(WL)
w(TRG)
w(SCH)
w(SCL)
w(SEL)
w(SEH)
w(GH)
Pulse duration, TRG low
Pulse duration, SC high
t
t
t
t
t
SC
Pulse duration, SC low
SCP
SE
Pulse duration, SE low
Pulse duration, SE high
SEP
TP
Pulse duration, TRG high
Pulse duration, RAS low (page mode)
Setup time, column address
75000
w(RL)P
su(CA)
su(SFC)
su(RA)
su(WMR)
su(DQR)
su(TRG)
su(SE)
su(SESC)
su(SFR)
su(DCL)
su(DWL)
su(rd)
t
t
t
t
t
t
t
t
t
t
t
t
t
ASC
FSC
ASR
WSR
MS
Setup time, DSF before CAS low
Setup time, row address
0
0
Setup time, W before RAS low
Setup time, DQ before RAS low
Setup time, TRG before RAS low
Setup time, SE before RAS low (see Note 13)
Setup time, serial write disable
Setup time, DSF before RAS low
Setup time, data before CAS low
Setup time, data before W low
Setup time, read command
0
0
0
THS
ESR
SWIS
FSR
DSC
DSW
RCS
WCS
0
10
0
0
0
0
Setup time, early write command before CAS low
0
su(WCL)
†
Timing measurements are referenced to V max and V min.
IL IH
NOTES: 9. All cycle times assume t = 5 ns.
t
10. When the odd tap is used (tap address can be 0–511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data
out cycle needs to be 70 ns minimum.
11. In a read-modify-write cycle, t
and t
must be observed. Depending on the user’s transition times, this may require
d(CLWL)
su(WCH)
additional CAS low time [t
12. In a read-modify-write cycle, t
].
w(CL)
d(RLWL)
w(RL)
and t
must be observed. Depending on the user’s transition times, this may require
su(WRH)
additional RAS low time [t
].
13. Register-to-memory (write) transfer cycles only
21
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262144 BY 4-BIT
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (continued)
’44C251B-10
’44C251B-12
ALT.
SYMBOL
UNIT
MIN
25
25
0
MAX
MIN
30
30
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, write before CAS high
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(WCH)
su(WRH)
su(SDS)
h(CLCA)
h(SFC)
CWL
Setup time, write before RAS high with TRG = W = low
Setup time, SDQ before SC high
t
RWL
t
SDS
CAH
Hold time, column address after CAS low
Hold time, DSF after CAS low
t
20
20
15
15
15
15
15
15
45
20
45
20
0
20
20
15
15
15
15
15
15
45
25
50
25
0
t
CFH
Hold time, row address after RAS low
Hold time, TRG after RAS low
t
t
h(RA)
RAH
t
h(TRG)
h(SE)
TLH
Hold time, SE after RAS low with TRG = W = low (see Note 13)
Hold time, write mask, transfer enable after RAS low
Hold time, DQ after RAS low (write-mask operation)
Hold time, DSF after RAS low
REH
t
h(RWM)
h(RDQ)
h(SFR)
RWH
t
MH
t
RFH
Hold time, column address after RAS low (see Note 14)
Hold time, data after CAS low
t
h(RLCA)
h(CLD)
AR
t
DH
Hold time, data after RAS low (see Note 14)
Hold time, data after W low
t
DHR
h(RLD)
t
h(WLD)
h(CHrd)
h(RHrd)
h(CLW)
h(RLW)
h(WLG)
h(SDS)
DH
Hold time, read after CAS high (see Note 15)
Hold time, read after RAS high (see Note 15)
Hold time, write after CAS low
t
t
RCH
RRH
10
30
50
25
5
10
35
55
30
5
t
WCH
WCR
Hold time, write after RAS low (see Note 14)
Hold time, TRG after W low (see Note 16)
Hold time, SDQ after SC high
t
t
OEH
t
SDH
Hold time, SDQ after SC high
t
5
5
h(SHSQ)
h(RSF)
SOH
Hold time, DSF after RAS low
t
45
20
100
0
45
20
120
0
FHR
Hold time, serial-write disable
t
SWIH
h(SCSE)
d(RLCH)
d(CHRL)
d(CLRH)
d(CLWL)
d(RLCL)
d(CARH)
d(RLWL)
d(CAWL)
Delay time, RAS low to CAS high
t
t
t
CSH
CRP
RSH
Delay time, CAS high to RAS low
Delay time, CAS low to RAS high
25
55
25
50
130
85
30
65
25
60
155
100
Delay time, CAS low to W low (see Notes 17 and 18)
Delay time, RAS low to CAS low (see Note 19)
Delay time, column address to RAS high
Delay time, RAS low to W low (see Note 17)
Delay time, column address to W low (see Note 17)
t
CWD
t
75
90
RCD
t
RAL
t
RWD
t
AWD
†
Timing measurements are referenced to V max and V min.
IL IH
NOTES: 13. Register-to-memory (write) transfer cycles only
14. The minimum value is measured when t
is set to t
d(RLCL)
min as a reference.
d(RLCL)
must be satisfied for a read cycle.
15. Either t
or t
h(RHrd)
(CHrd)
16. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
17. Read-modify-write operation only
18. TRG must disable the output buffers prior to applying data to the DQ terminals.
19. The maximum value is specified only to assure RAS access time.
22
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timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (continued)
’44C251B-10 ’44C251B-12
ALT.
SYMBOL
UNIT
MIN
25
MAX
MIN
25
MAX
t
t
t
t
t
Delay time, RAS low to CAS high (see Note 20)
Delay time, CAS low to RAS low (see Note 20)
Delay time, RAS high to CAS low (see Note 20)
Delay time, CAS low to TRG high for DRAM read cycles
Delay time, TRG high before data applied at DQ
t
ns
ns
ns
ns
ns
d(RLCH)RF
d(CLRL)RF
d(RHCL)RF
d(CLGH)
CHR
t
10
10
CSR
RPC
t
10
10
25
30
t
25
30
d(GHD)
OED
Delay time, RAS low to TRG high (real-time-reload read-transfer cycle
only)
t
t
90
95
ns
d(RLTH)
RTH
t
t
t
t
Delay time, RAS low to first SC high after TRG high (see Note 21)
Delay time, CAS low to first SC high after TRG high (see Note 21)
Delay time, SC high to TRG high (see Notes 21, 22, and 23)
Delay time, TRG high to RAS high (see Notes 22 and 23)
t
t
130
40
140
45
ns
ns
ns
ns
d(RLSH)
d(CLSH)
d(SCTR)
d(THRH)
RSD
CSD
t
15
20
TSL
t
–10
–10
TRD
Delay time, SC high to RAS low with TRG = W = low
(see Notes 13, 24, and 25)
t
t
10
20
ns
d(SCRL)
SRS
t
t
t
t
t
Delay time, SC high to SE high in serial-input mode
Delay time, RAS high to SC high (see Note 13)
Delay time, TRG high to RAS low (see Note 26)
Delay time, TRG high to SC high (see Notes 22 and 23)
Delay time, SE low to SC high (see Note 27)
20
25
20
30
ns
ns
ns
ns
ns
d(SCSE)
d(RHSC)
d(THRL)
d(THSC)
d(SESC)
t
SRD
t
t
t
TRP
TSD
w(RH)
35
w(RH)
40
t
t
10
15
SWS
Delay time, RAS high to last (most significant) rising edge of SC before
boundary switch during split-register read-transfer cycles
t
15
20
ns
d(RHMS)
t
t
Delay time, CAS low to TRG high in real-time read-transfer cycles
Delaytime, columnaddresstofirstSCinearly-loadread-transfercycles
t
5
5
ns
ns
d(CLGH)
CTH
t
45
50
d(CASH)
ASD
Delay time, column address to TRG high in real-time read-transfer
cycles
t
t
10
10
ns
d(CAGH)
ATH
t
t
t
t
t
Delay time, RAS low to column address (see Note 19)
Delay time, data to CAS low
t
15
0
50
15
0
60
ns
ns
ns
ns
ns
d(RLCA)
RAD
t
d(DCL)
DZC
DZO
SDD
ROH
Delay time, data to TRG low
t
t
0
0
d(DGL)
Delay time, RAS low to serial-input data
Delay time, TRG low to RAS high
50
25
50
30
d(RLSD)
d(GLRH)
t
†
Timing measurements are referenced to V max and V min.
IL IH
NOTES: 13. Register-to-memory (write) transfer cycles only
19. The maximum value is specified only to assure RAS access time.
20. CAS-before-RAS refresh operation only
21. Early-load read-transfer cycle only
22. Real-time-reload read-transfer cycle only
23. Late-load read-transfer cycle only
24. Inaread-transfercycle, thestateofSCwhenRASfallsisadon’tcarecondition.However,toassurepropersequencingoftheinternal
clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS goes low.
25. In a memory-to-register (read) transfer cycle, t
applies only when the SAM was previously in serial-input mode.
d(SCRL)
26. Memory-to-register (read) and register-to-memory (write) transfer cycles only
27. Serial data-in cycles only
23
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (concluded)
’44C251B-10 ’44C251B-12
ALT.
SYMBOL
UNIT
MIN
MAX
MIN
MAX
Delay time, last (most significant) rising edge of SC to RAS low before
boundary switch during split-register read-transfer cycles
t
t
t
t
t
25
25
ns
ns
ns
ns
ns
d(MSRL)
Delay time, last (255 or 511) rising edge of SC to QSF switching at the
boundary during split-register read-transfer cycles (see Note 7)
t
40
35
30
75
40
35
30
75
d(SCQSF)
d(CLQSF)
d(GHQSF)
d(RLQSF)
SQD
Delay time, CAS low to QSF switching in read-transfer or write-transfer
cycles (see Note 7)
t
CQD
Delay time, TRG high to QSFswitchinginread-transferorwrite-transfer
cycles (see Note 7)
t
TQD
Delay time, RAS low to QSF switching in read-transfer or write-transfer
cycles (see Note 7)
t
RQD
t
t
Refresh time interval, memory
Transition time
t
8
8
ms
ns
rf
REF
t
T
3
50
3
50
t
†
Timing measurements are referenced to V max and V min.
IL IH
NOTE 7: Switching times assume C = 100 pF unless otherwise noted (see Figure 12).
L
PARAMETER MEASUREMENT INFORMATION
1.31 V
218 Ω
Output
Pin
C
L
V
SS
Figure 12. Load Circuit
24
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
d(RLCH)
t
RAS
CAS
t
w(RH)
t
d(CHRL)
t
d(CLRH)
t
t
t
d(RLCL)
t
w(CL)
t
t
w(CH)
h(RA)
t
d(CLGH)
t
h(RLCA)
t
t
h(CLCA)
su(RA)
t
su(CA)
Row
Column
A0–A8
DSF
Don’t Care
t
su(TRG)
t
d(GLRH)
t
h(TRG)
t
w(TRG)
TRG
t
h(RHrd)
t
su(rd)
t
h(CHrd)
W
t
t
dis(CH)
t
d(DGL)
t
a(G)
dis(G)
Data
In
DQ0–DQ3
Valid Output
t
a(C)
a(CA)
t
t
a(R)
Figure 13. Read-Cycle Timing
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
t
t
d(RLCH)
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
t
w(CL)
su(RA)
CAS
t
h(RA)
t
t
w(CH)
h(RLCA)
t
h(CLCA)
t
su(CA)
A0–A8
Row
Column
t
t
t
h(SFC)
su(SFR)
t
h(SFR)
t
su(SFC)
DSF
TRG
1
2
su(TRG)
t
h(TRG)
t
su(WMR)
t
su(WCH)
t
su(WRH)
t
h(RLW)
t
h(RWM)
t
su(WCL)
t
h(CLW)
W
3
t
t
su(DQR)
w(WL)
t
su(DCL)
t
h(CLD)
t
h(RDQ)
t
h(RLD)
DQ0–DQ3
4
5
Figure 14. Early-Write-Cycle Timing
Table 4. Write-Cycle State Table
STATE
CYCLE
1
L
2
L
L
L
L
3
H
L
4
5
Write operation
Don’t care
Write mask
Don’t care
Don’t care
Valid data
Valid data
Valid data
Write mask
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
L
H
H
L
H
26
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
CAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
d(CHRL)
t
t
d(CHRL)
d(RLCL)
t
w(CL)
t
h(RA)
t
w(CH)
t
d(RLCA)
t
d(CARH)
t
h(RLCA)
t
su(CA)
t
t
h(CLCA)
su(RA)
A0–A8
Row
Column
h(RSF)
t
t
t
h(SFC)
su(SFR)
t
su(SFC)
t
h(SFR)
DSF
1
2
t
su(TRG)
t
su(WRH)
TRG
t
h(RWM)
t
h(WLG)
t
su(WCH)
t
d(GHD)
t
h(RLW)
t
t
h(CLW)
su(WMR)
W
3
t
su(DWL)
t
t
su(DQR)
w(WL)
t
h(WLD)
t
h(RDQ)
t
h(RLD)
DQ0–DQ3
4
5
Figure 15. Delayed-Write-Cycle Timing (Output-Enable-Controlled Write)
Table 5. Write-Cycle State Table
STATE
CYCLE
1
L
2
L
L
L
L
3
H
L
4
5
Write operation
Don’t care
Write mask
Don’t care
Don’t care
Valid data
Valid data
Valid data
Write mask
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
L
H
H
L
H
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rdW)
w(RL)
d(RLCH)
t
RAS
t
t
t
t
d(CLRH)
d(CHRL)
w(RH)
t
d(RLCL)
t
d(CHRL)
t
w(CL)
CAS
t
t
h(RA)
t
w(CH)
t
su(CA)
t
h(CLCA)
su(RA)
t
d(RLCA)
t
d(CARH)
t
h(RLCA)
A0–A8
Row
Column
t
Don’t Care
Don’t Care
t
h(RSF)
t
su(SFC)
t
h(SFR)
su(SFR)
t
h(SFC)
DSF
1
2
t
t
su(WCH)
su(rd)
t
h(TRG)
t
su(WRH)
t
d(CAWL)
t
w(TRG)
TRG
t
h(WLG)
t
su(TRG)
t
h(RLW)
t
d(DCL)
t
h(CLW)
t
h(RWM)
t
d(CLWL)
t
su(WMR)
t
d(CLGH)
t
w(WL)
W
3
4
t
a(CA)
t
d(RLWL)
t
h(WLD)
t
d(DGL)
t
t
d(GHD)
a(R)
t
su(DQR)
t
t
su(DWL)
a(C)
t
h(RDQ)
Q0–
Q3
Valid
Output
5
t
dis(G)
t
a(G)
Figure 16. Read-Write/Read-Modify-Write-Cycle Timing
Table 6. Write-Cycle State Table
STATE
CYCLE
1
L
2
L
L
L
L
3
H
L
4
5
Write operation
Don’t care
Write mask
Don’t care
Don’t care
Valid data
Valid data
Valid data
Write mask
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
L
H
H
L
H
28
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SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
d(CLRH)
t
c(rdWP)
t
t
d(RLCL)
t
w(CH)
t
d(CHRL)
d(CHRL)
t
w(CL)
t
d(RLCA)
t
su(CA)
t
t
a(CP)
su(RA)
t
d(RLCH)
t
h(RA)
t
h(CLCA)
t
d(CARH)
t
h(RLCA)
A0–A8
Row
Column
Column
t
d(CLGH)
DSF
TRG
W
Don’t Care
t
h(TRG)
t
d(GLRH)
t
su(TRG)
t
t
w(TRG)
t
w(TRG)
t
h(RHrd)
t
su(WMR)
t
t
dis(G)
su(rd)
t
t
h(CHrd)
d(CLGH)
t
a(C)
a(G)
†
t
a(CA)
a(G)
t
t
d(DGL)
a(CA)
t
dis(G)
t
t
dis(CH)
‡
‡
t
t
dis(CH)
a(R)
†
t
a(CP)
Valid
Output
DQ0–
DQ3
Data In
Valid Output
t
d(DCL)
†
‡
Access time is t
or t
a(CA)
dependent.
a(CP)
Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS and CAS to select the desired write
mode (normal, block write, etc.)
Figure 17. Enhanced-Page-Mode Read-Cycle Timing
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
CAS
t
t
w(RH)
d(CLRH)
d(RLCH)
t
t
t
c(P)
d(RLCL)
t
w(CH)
t
t
t
w(CL)
d(CHRL)
d(CHRL)
t
su(CA)
t
h(RA)
t
d(RLCA)
t
h(CLCA)
t
su(RA)
t
t
d(CARH)
h(RLCA)
A0–A8
Row
t
Column
t
Column
t
t
su(SFC)
h(RSF)
t
su(SFC)
t
su(SFR)
t
h(SFR)
1
h(SFC)
h(SFC)
DSF
TRG
W
2
2
t
su(WCH)
t
h(TRG)
t
su(TRG)
See Note A
su(WCH)
t
su(WMR)
t
t
t
su(WRH)
su(RWM)
t
w(WL)
3
†
t
su(DWL)
†
t
h(CLD)
t
su(DQR)
†
t
su(DCL)
†
t
h(WLD)
t
h(RDQ)
t
h(RLD)
DQ0–DQ3
4
5
5
†
Referenced to CAS or W, whichever occurs last
NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write
feature is used. If the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period t
edge of RAS.
from the falling
h(TRG)
Figure 18. Enhanced-Page-Mode Write-Cycle Timing
Table 7. Write-Cycle State Table
STATE
CYCLE
1
L
2
L
L
L
L
3
H
L
4
5
Write operation
Don’t care
Write mask
Don’t care
Don’t care
Valid data
Valid data
Valid data
Write mask
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
L
H
H
L
H
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
t
t
d(RLCH)
d(CLRH)
t
t
w(RH)
d(CHRL)
t
c(rdWP)
t
d(CHRL)
t
t
d(RLCL)
w(CH)
t
w(CL)
CAS
t
t
d(RLCA)
d(CARH)
t
su(RA)
t
t
su(CA)
h(RA)
t
h(CLCA)
t
h(RLCA)
A0–A8
t
Row
Column
Column
t
h(SFR)
t
h(SFC)
t
h(SFC)
t
su(SFR)
t
su(SFC)
su(SFC)
DSF
1
2
2
t
su(rd)
t
t
su(WCH)
t
t
d(CLWL)
su(WRH)
h(TRG)
t
d(CAWL)
d(RLWL)
t
su(TRG)
t
t
t
t
d(DCL)
d(CLGH)
t
w(TPG)
d(CLGH)
t
TRG
t
w(WL)
t
su(WMR)
t
w(TRG)
†
t
a(C)
t
d(GHD)
h(RWM)
†
t
W
3
a(CA)
t
t
t
su(DWL)
d(DCL)
h(WLD)
t
su(DQR)
t
su(DWL)
†
t
t
h(WLD)
a(CP)
t
h(RDQ)
Valid
Out
Valid
Out
DQ0–DQ3
4
5
t
5
†
t
a(G)
d(DGL)
t
dis(G)
t
d(DGL)
t
d(GHD)
†
t
a(C)
t
a(R)
†
Output can go from the high-impedance state to an invalid data state prior to the specified access time.
NOTE A: Areadorawritecyclecanbeintermixedwithread-modify-writecyclesaslongasthereadandwritetimingspecificationsarenotviolated.
Figure 19. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
Table 8. Write-Cycle State Table
STATE
CYCLE
1
L
2
L
L
L
L
3
H
L
4
5
Write operation
Don’t care
Write mask
Don’t care
Don’t care
Valid data
Valid data
Valid data
Write mask
Write-mask load/use, write DQs to I/Os
Use previous write mask, write DQs to I/Os
Load write mask on later of W fall and CAS fall
L
H
H
L
H
31
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SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CHRL)
t
t
d(CLRH)
d(CHRL)
t
d(RLCL)
t
w(CL)
CAS
t
w(CH)
t
h(RA)
t
h(RSF)
t
su(RA)
Refresh
Row
Don’t Care
A0–A8
t
t
h(SFC)
su(SFR)
t
su(SFC)
t
h(SFR)
t
h(RSF)
h(TRG)
DSF
TRG
t
t
su(TRG)
t
su(WCH)
t
su(WRH)
t
su(WMR)
t
h(RLW)
t
h(RWM)
t
su(WCL)
t
h(CLW)
W
t
w(WL)
t
su(DCL)
t
h(CLD)
t
h(RLD)
Valid Color Data Input
DQ0–DQ3
Figure 20. Load-Color-Register-Cycle Timing (Early-Write Load)
32
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SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CHRL)
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
w(CL)
CAS
t
h(RSF)
t
w(CH)
t
su(RA)
t
h(RA)
Refresh
Row
Don’t Care
h(SFC)
A0–A8
t
t
h(SFR)
t
su(SFC)
t
su(SFR)
DSF
t
su(WCH)
t
su(TRG)
t
su(WRH)
t
TRG
d(GHD)
t
h(RWL)
t
h(CLW)
t
su(WMR)
t
h(WLG)
t
w(WL)
W
t
su(DWL)
t
h(WLD)
t
h(RLD)
DQ0–DQ3
Valid Color Data Input
Figure 21. Load-Color-Register-Cycle Timing (Delayed-Write Load)
33
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
t
t
d(RLCH)
t
d(RLCL)
d(CHRL)
t
t
d(CHRL)
t
t
d(CLRH)
w(CL)
t
t
CAS
t
w(CH)
t
h(RLCA)
t
d(RLCA)
t
h(CLCA)
t
h(RA)
su(RA)
t
d(CARH)
t
t
su(CA)
t
Row
A0–A8
t
h(RSF)
Block Address
A2–A8
t
h(SFR)
t
h(SFC)
t
su(SFC)
su(SFR)
1
DSF
t
h(TRG)
t
su(TRG)
TRG
t
su(WCH)
t
su(WRH)
t
su(WCL)
t
h(CLW)
t
h(RWM)
t
h(RLW)
t
su(WMR)
t
w(WL)
2
W
t
h(RLD)
t
su(DCL)
t
h(RDQ)
t
h(CLD)
t
su(DQR)
DQ0–DQ3
3
4
Figure 22. Block-Write-Cycle Timing (Early Write)
Table 9. Block-Write-Cycle State Table
STATE
CYCLE
1
L
2
L
3
4
Write-mask load/use, block write
Write mask
Don’t care
Don’t care
Column mask
Column mask
Column mask
Use previous write mask, block write
H
L
L
Write mask disabled, block write to all I/Os
H
Write mask data 0: I/O write disable
1: I/O write enable
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column mask data DQn =
(n = 0, 1, 2, 3)
0 column write disable
1 column write enable
34
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262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
t
w(RH)
t
d(RLCH)
t
t
t
t
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(CHRL)
t
w(CL)
CAS
t
d(RLCA)
t
w(CH)
t
h(RLCA)
t
d(CARH)
t
h(RA)
t
su(CA)
t
t
su(RA)
h(CLCA)
Row
A0–A8
t
t
h(RSF)
Block Address
su(SFR)
t
t
su(SFC)
A2–A8
t
h(SFC)
h(SFR)
1
DSF
TRG
t
su(TRG)
t
su(WRH)
t
t
su(WCH)
d(GHD)
t
h(RLW)
t
h(CLW)
t
su(WMR)
t
h(WLG)
t
h(RWM)
t
w(WL)
W
2
3
t
su(DQR)
t
su(DWL)
t
h(RDQ)
t
h(WLD)
t
h(RLD)
4
DQ0–DQ3
Figure 23. Block-Write-Cycle Timing (Delayed-Write)
Table 10. Block-Write-Cycle State Table
STATE
CYCLE
1
L
2
L
3
4
Write-mask load/use, block write
Write mask
Don’t care
Don’t care
Column mask
Column mask
Column mask
Use previous write mask, block write
H
L
L
Write mask disabled, block write to all I/Os
H
Write mask data 0: I/O write disable
1: I/O write enable
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RL)P
RAS
CAS
t
t
t
d(RLCH)
d(RLCL)
d(CHRL)
c(P)
w(RH)
t
t
d(CLRH)
t
w(CH)
t
t
t
d(CHRL)
w(CL)
t
d(RLCA)
t
su(CA)
t
h(CLCA)
t
h(RA)
t
h(RLCA)
t
d(CARH)
t
su(RA)
Block Address
A2–A8
Block Address
A2–A8
Row
A0–A8
t
h(SFR)
t
t
h(SFC)
h(SFC)
t
su(SFC)
t
t
su(SFC)
su(SFR)
1
DSF
TRG
t
h(TRG)
su(TRG)
t
See Note A
t
t
su(WMR)
su(WCH)
t
su(WCH)
t
w(WL)
t
t
su(WRH)
h(RWM)
2
W
†
t
su(DWL)
†
t
h(CLD)
†
t
su(DQR)
t
h(WLD)
†
t
t
h(RDQ)
su(DCL)
t
h(RLD)
3
4
4
DQ0–DQ3
†
Referenced to CAS or W, whichever occurs last
NOTE A: TRG must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If
the early-write-cycle timing is used, the state of TRG is a don’t care after the minimum period t from the falling edge of RAS.
h(TRG)
Figure 24. Enhanced-Page-Mode Block-Write-Cycle Timing
Table 11. Enhanced-Page-Mode Block-Write-Cycle Table
STATE
CYCLE
1
L
2
L
3
4
Write-mask load/use, block write
Write mask
Don’t care
Don’t care
Column mask
Column mask
Column mask
Use previous write mask, block write
H
L
L
Write mask disabled, block write to all I/Os
H
Write mask data 0: I/O write disable
1: I/O write enable
DQ0 — column 0 (address A1 = 0, A0 = 0)
DQ1 — column 1 (address A1 = 0, A0 = 1)
DQ2 — column 2 (address A1 = 1, A0 = 0)
DQ3 — column 3 (address A1 = 1, A0 = 1)
Column mask data DQn =
0 column write disable
(n = 0, 1, 2, 3) 1 column write enable
36
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SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
RAS
t
w(RH)
t
t
t
d(CHRL)
t
d(RHCL)
t
t
t
d(CHRL)
CAS
A0–A8
DSF
Don’t Care
Don’t Care
Don’t Care
Don’t Care
t
t
t
h(RA)
t
su(RA)
Row
Row
h(SFR)
h(TRG)
t
su(SFR)
t
su(TRG)
TRG
W
Don’t Care
Don’t Care
DQ0–DQ3
NOTE A: In persistent write-per-bit function, W must be high at the falling edge of RAS during the refresh cycle.
Figure 25. RAS-Only Refresh-Cycle Timing
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RH)
t
w(RL)
RAS
t
d(RHCL)RF
t
d(CLRL)RF
t
d(RLCH)RF
CAS
t
d(CHRL)
A0–A8
Don’t Care
Don’t Care
Don’t Care
Don’t Care
DSF
TRG
W
t
dis(CH)
DQ0–DQ3 Valid Out
Hi-Z
NOTE A: In persistent write-per-bit operation, W must be high at the falling edge of RAS during the refresh cycle.
Figure 26. CBR-Refresh-Cycle Timing
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Read Cycle
t
c(rd)
t
c(rd)
t
w(RH)
t
t
c(rd)
w(RH)
t
t
w(RL)
w(RL)
RAS
CAS
t
d(CARH)
t
d(RLCH)
t
d(CHRL)
t
w(CL)
t
d(RLCA)
t
h(CLCA)
t
su(CA)
t
h(RA)
t
su(RA)
Row
Col
Don’t Care
A0–A8
DSF
t
h(RHrd)
Don’t Care
t
d(GLRH)
t
su(TRG)
t
a(G)
t
dis(G)
t
h(TRG)
TRG
t
su(RD)
W
Don’t Care
t
a(C)
t
dis(CH)
t
a(R)
DQ0–DQ3
Valid Data
Figure 27. Hidden-Refresh-Cycle Timing
39
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SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TW)
t
w(RL)
t
d(RLCL)
RAS
t
d(RLCH)
t
d(CARH)
t
d(CHRL)
t
w(RH)
t
w(CL)
CAS
t
su(CA)
d(RLCA)
t
w(CH)
t
t
h(CLCA)
t
h(RA)
t
h(RLCA)
t
su(RA)
Tap Point
A0–A8
Row
Don’t Care
A0–A8
DSF
t
h(SFR)
t
su(SFR)
t
h(TRG)
t
su(TRG)
Don’t Care
TRG
t
t
d(RHSC)
su(WMR)
t
h(RWM)
W
DQ0–DQ3
Hi-Z
t
w(SCH)
t
w(SCH)
t
d(SCRL)
SC
t
t
w(SCL)
d(RLSD)
t
h(SDS)
t
t
su(SDS)
Don’t Care
h(RLSQ)
Valid Data
Input
SDQ0–SDQ3
Valid Data Output
dis(SE)
t
t
t
h(SE)
d(SESC)
t
su(SE)
Don’t Care
SE
t
d(CLQSF)
Tap Point
Bit A7
QSF
t
d(GHQSF)
d(RLQSF)
t
NOTE: The write-mode-control cycle is used to change the SDQs from the output mode to the input mode. This allows serial data to be written
into the data register. This figure assumes that the device was originally in the serial-read mode.
Figure 28. Write-Mode-Control Pseudo-Transfer Timing
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TW)
t
w(RL)
t
d(RLCL)
RAS
t
d(RLCH)
t
d(CARH)
t
d(CHRL)
t
w(RH)
t
w(CL)
t
CAS
su(CA)
t
w(CH)
t
d(RLCA)
t
h(CLCA)
t
h(RA)
t
d(CARH)
t
h(RLCA)
t
su(RA)
Tap Point
A0–A8
Row
Don’t Care
A0–A8
DSF
Don’t Care
t
h(TRG)
t
su(TRG)
Don’t Care
TRG
t
t
su(WMR)
t
d(RHSC)
h(RWM)
W
Don’t Care
DQ0–DQ3
Hi-Z
t
w(SCH)
t
w(SCH)
t
d(SCRL)
SC
t
w(SCL)
t
su(SDS)
t
h(SDS)
t
h(SDS)
t
su(SDS)
SDQ0–SDQ3
Data In
Data In
t
h(SE)
t
su(SE)
t
d(SESC)
SE
t
d(CLQSF)
Tap Point
Bit A7
QSF
t
d(GHQSF)
d(RLQSF)
t
Figure 29. Data-Register-to-Memory Transfer Timing, Serial Input Enabled
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C251B
262144 BY 4-BIT
MULTIPORT VIDEO RAM
SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TW)
t
w(RL)
t
d(RLCL)
RAS
t
t
d(RLCH)
t
d(CARH)
t
d(CHRL)
w(RH)
t
w(CL)
CAS
t
su(CA)
d(RLCA)
t
w(CH)
t
t
h(CLCA)
t
h(RA)
t
h(RLCA)
t
su(RA)
Tap Point
A0–A8
Don’t Care
A0–A8
DSF
Row
t
h(SFR)
t
su(SRF)
Don’t Care
t
h(TRG)
t
su(TRG)
TRG
t
su(WMR)
t
d(RHSC)
t
h(RWM)
W
Don’t Care
DQ0–DQ3
Hi-Z
t
w(SCH)
t
w(SCH)
t
d(SCRL)
SC
t
t
w(SCL)
su(SDS)
t
h(SDS)
t
h(SDS)
t
su(SDS)
SDQ0–SDQ3
Data In
Don’t Care
Data In
t
d(SCSE)
t
d(SESC)
Don’t Care
SE
t
d(CLQSF)
Tap Point
Bit A7
QSF
t
d(GHQSF)
d(RLQSF)
t
Figure 30. Alternate Data-Register-to-Memory Transfer-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
d(RLCL)
RAS
CAS
t
w(RH)
t
d(RLCH)
t
t
d(CHRL)
w(CL)
t
d(CARH)
t
d(RLCA)
t
h(RA)
t
h(CLCA)
t
su(CA)
t
su(RA)
t
h(RLCA)
Tap Point
A0–A8
Don’t Care
A0–A8
DSF
Row
t
su(SFR)
t
h(SFR)
t
su(TRG)
t
h(TRG)
TRG
t
t
w(GH)
h(RWM)
t
t
su(WMR)
d(CASH)
Don’t Care
W
Hi-Z
DQ0–DQ3
t
d(SCTR)
t
d(CLSH)
t
d(RLSH)
t
w(SCL)
t
w(SCH)
SC
t
w(SCH)
t
c(SC)
t
a(SQ)
t
a(SQ)
t
t
h(SHSQ)
h(SHSQ)
Old Data
Old Data
New Data
SDQ0–SDQ3
t
d(GHQSF)
Tap Point bit A7
QSF
SE
t
d(CLQSF)
H
L
t
d(RLQSF)
NOTES: A. Early-load operation is defined as t
min < t
< t min.
h(TRG) d(RLTH)
h(TRG)
B. DQoutputsremaininthehigh-impedancestatefortheentirememory-to-data-registertransfercycle. Thememory-to-data-register
transfercycle is used to load the data registersinparallelfromthememoryarray. The512locationsineachdataregisterarewritten
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 31. Memory-to-Data-Register Transfer-Cycle Timing, Early-Load Operation
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
d(RLCL)
RAS
CAS
t
w(RH)
t
d(CHRL)
t
d(RLCH)
t
w(CL)
t
d(RLCA)
t
h(RLCA)
t
su(RA)
t
su(CA)
t
t
h(RA)
h(CLCA)
Don’t Care
A0–A8
DSF
TRG
W
Row
Tap Point
A0–A8
t
t
su(SFR)
h(SFR)
Don’t Care
t
t
d(THRL)
d(THRH)
d(CLGH)
t
su(TRG)
t
t
d(CAGH)
t
d(RLTH)
t
t
w(GH)
h(RWM)
t
su(WMR)
Don’t Care
t
d(SCTR)
t
d(THSC)
DQ0–DQ3
SC
Hi-Z
t
w(SCH)
t
a(SQ)
t
t
a(SQ)
c(SC)
t
w(SCL)
t
t
h(SHSQ)
h(SHSQ)
Old Data
SDQ0–SDQ3
Old Data
Old Data
New Data
t
d(GHQSF)
QSF
SE
Tap Point Bit A7
t
H
L
d(CLQSF)
t
d(RLQSF)
NOTES: A. Late-load operation is defined as t
d(THRH)
< 0 ns.
B. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 32. Memory-to-Data-Register Transfer-Cycle Timing,
Real-Time-Reload Operation/Late-Load Operation
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
d(RLCL)
RAS
CAS
t
w(RH)
t
d(RLCH)
t
d(CHRL)
t
d(CARH)
t
w(CL)
t
d(RLCA)
t
h(RLCA)
t
su(RA)
t
h(CLCA)
t
t
h(RA)
su(CA)
Tap Point
A0–A8
Row
Don’t Care
A0–A8
DSF
t
t
d(CAGH)
h(SFR)
t
Don’t Care
su(SFR)
t
d(THRH)
t
su(TR
t
t
d(CLGH)
t
d(THRL)
t
h(TRG)
Don’t Care
TRG
t
w(GH)
t
h(RWM)
d(RLTH)
t
su(WMR)
Don’t Care
W
Hi-Z
DQ0–DQ3
t
d(THSC)
t
d(SCRL)
t
d(CLSH)
t
d(RLSH)
SC
t
t
t
c(SC)
d(SDRL)
su(SDS)
t
t
h(SDS)
a(SQ)
Valid In
Invalid Out
Valid Out
SDQ0–SDQ3
t
d(GHQSF)
Tap Point bit A7
QSF
SE
t
d(CLQSF)
H
L
t
d(RLQSF)
NOTES: A. Late-load operation is defined as t
d(THRH)
< 0 ns.
B. DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register
transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written
from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted
out or transferred back into another row.
C. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted
out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a positive
transition of SC.
Figure 33. Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode
45
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(TRD)
t
w(RL)
t
w(RH)
t
d(RLCL)
RAS
CAS
t
t
d(CHRL)
t
t
w(CH)
d(RLCH)
t
d(RLCA)
t
w(CL)
t
su(CA)
t
h(RA)
t
d(CARH)
su(RA)
t
h(CLCA)
A0–A8
Row
Tap Point A0–A8
Don’t Care
t
t
su(TRG)
d(THRH)
t
t
h(TRG)
w(GH)
TRG
DSF
t
h(SFR)
t
su(SFR)
Don’t Care
Don’t Care
t
h(RWM)
t
su(WMR)
W
Hi-Z
DQ0–DQ3
t
d(MSRL)
t
d(RHMS)
t
c(SC)
t
t
c(SC)
w(SCH)
t
w(SCL)
Bit 255
or 511
Bit 255
or 511
Tap
Point M
Tap
Point N
SC
t
a(SQ)
t
t
a(SQ)
t
a(SQ)
w(SCL)
t
h(SHSQ)
Bit 254 or
Bit 510
Bit 255 or
Bit 511
Bit 255 or
Bit 511
Tap
Point N
Tap Point M
SDQ0–SDQ3
t
t
a(SQ)
d(SCQSF)
t
d(SCQSF)
QSF
SE
Old MSB
New MSB
H
L
Figure 34. Split-Register-Mode Read-Transfer-Cycle Timing
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A8
Row Tap1
(low)
Row Tap1
(high)
Row Tap2
(low)
Row Tap2
(high)
TRG
DSF
CASE I
SC
Tap1
(low)
Bit Tap1
255 (high)
Bit
511
Tap2
(low)
Bit
255
QSF
CASE II
SC
Tap1
(high)
Tap1
(low)
Bit
255
Bit
511
Tap2
(low)
Bit
255
QSF
CASE III
SC
Tap1
(low)
Bit Tap1
255 (high)
Bit
511
Tap2
(low)
Bit
255
QSF
Split Register to the
High Half of the
Data Register
Split Register to the
Split Register to the
High Half of the
Data Register
Normal Read Transfer
Low Half of the
Data Register
NOTES: A. In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer
cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the
normal read-transfer cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle
(CASE III). There is no minimum requirement of SC clock between the normal read-transfer cycle and the first split-register cycle.
B. Asplitregistertransferintotheinactivehalfisnotalloweduntilt
ismet.t
istheminimumdelaytimebetweentherising
d(MSRL)
d(MSRL)
edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS of the split-register transfer cycle into the inactive
half.Aftert ismet,thesplit-registertransferintotheinactivehalfmustalsosatisfythet requirement.t isthe
d(MSRL)
d(RHMS)
d(RHMS)
minimum delay time between the rising edge of RAS of the split-register transfer cycle into the inactive half and the rising edge of
theserialclockofthelastbit(bit255or511).ThereisaminimumrequirementofonerisingedgeofSCclockbetweentwosplit-register
transfer cycles.
Figure 35. Split-Register-Transfer Operating Sequence
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
c(SC)
t
t
w(SCH)
w(SCH)
t
w(SCH)
t
t
w(SCL)
w(SCL)
SC
t
su(SDS)
t
t
su(SDS)
su(SDS)
t
h(SDS)
t
t
h(SDS)
h(SDS)
SDQ0–SDQ3
Valid In
Valid In
Valid In
NOTES: A. The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the
SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other
write-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the
read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous
transfer cycle.
B. While accessing data in the serial-data registers, the state of TRG is a don’t care as long as TRG is held high when RAS goes low
to prevent data transfers between memory and data registers.
Figure 36. Serial-Write-Cycle Timing (SE = V )
IL
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
c(SC)
t
t
w(SCH)
w(SCH)
t
w(SCH)
t
t
w(SCL)
w(SCL)
SC
t
su(SDS)
t
su(SDS)
t
h(SDS)
t
h(SDS)
SDQ0–SDQ3
t
Valid In
Valid In
t
h(SCSE)
d(SESC)
t
su(SESC)
t
w(SEH)
t
d(SCSE)
t
d(SESC)
t
w(SEL)
SE
NOTES: A. The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the
SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other
write-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the
read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous
transfer cycle.
B. While accessing data in the serial-data registers, the state of TRG is a don’t care as long as TRG is held high when RAS goes low
to prevent data transfers between memory and data registers.
Figure 37. Serial-Write-Cycle Timing (SE-Controlled Write)
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
c(SC)
t
t
w(SCH)
w(SCH)
t
w(SCH)
t
t
w(SCL)
w(SCL)
SC
t
t
t
a(SQ)
a(SQ)
a(SQ)
t
t
t
h(SHSQ)
h(SHSQ)
h(SHSQ)
SDQ0–SDQ3
Valid Out
Valid Out
Valid Out
Valid Out
NOTES: A. While reading data through the serial-data register, the state of TRG is a don’t care as long as TRG is held high when RAS goes
low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put
into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the
subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.
Figure 38. Serial-Read-Cycle Timing (SE = V )
IL
50
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262144 BY 4-BIT
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
RAS
TRG
t
su(TRG)
t
h(TRG)
t
c(SC)
t
c(SC)
t
t
w(SCH)
w(SCH)
t
w(SCH)
t
t
w(SCL)
w(SCL)
SC
t
t
t
a(SQ)
a(SQ)
a(SQ)
t
t
h(SHSQ)
h(SHSQ)
t
a(SE)
Data
In
SDQ0–SDQ3
Valid Out
Valid Out
Valid Out
Valid Out
t
dis(SE)
t
d(SDSE)
SE
NOTES: A. While reading data through the serial-data register, the state of TRG is a don’t care as long as TRG is held high when RAS goes
low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put
into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the
subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.
Figure 39. Serial-Read-Cycle Timing (SE-Controlled Read)
device symbolization
TI
-SS
Speed (-10, -12)
SMJ44C251B
JD
Package Code
JD = ZIP
F
R
A
XXX LLL
Lot Traceability Code
Date Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
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SGMS058A – MARCH 1995 – REVISED JUNE 1995
52
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