SMJ626162-15HKD [MICROSS]
Synchronous DRAM, 1MX16, 9ns, CMOS, CDFP50, 0.650 INCH, CERAMIC, DFP-50;
| 型号： | SMJ626162-15HKD |
| 厂家： | 
MICROSS COMPONENTS |
| 描述： | Synchronous DRAM, 1MX16, 9ns, CMOS, CDFP50, 0.650 INCH, CERAMIC, DFP-50 时钟 动态存储器 CD 内存集成电路 |
| 文件： | 总42页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
HKD PACKAGE
(TOP VIEW)
Organization
512K × 16 Bits × 2 Banks
3.3-V Power Supply (±5% Tolerance)
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
V
SS
DQ15
DQ14
CC
Two Banks for On-Chip Interleaving
(Gapless Accesses)
2
DQ0
DQ1
3
High Bandwidth – Up to 83-MHz Data Rates
4
V
V
SSQ
DQ13
DQ12
SSQ
DQ2
Read Latency Programmable to
2 or 3 Cycles From Column-Address Entry
5
6
DQ3
7
Burst Sequence Programmable to Serial or
Interleave
V
V
CCQ
DQ11
DQ10
CCQ
DQ4
8
9
DQ5
Burst Length Programmable to 1, 2, 4, 8, or
256 (Full Page)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
SSQ
DQ9
DQ8
SSQ
DQ6
Chip Select and Clock Enable for Enhanced
System Interfacing
DQ7
V
V
CCQ
CCQ
DQML
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control
NC
DQMU
CLK
CKE
NC
A9
W
CAS
RAS
CS
Autorefresh Capability
4K Refresh (Total for Both Banks)
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
A11
A10
A0
Power-Down Mode
A8
Pipeline Architecture
A7
Temperature Ranges:
A1
A6
Operating, – 55°C to 125°C
Storage, – 65°C to 150°C
A2
A5
A3
A4
Performance Ranges:
V
V
SS
CC
SYNCHRONOUS ACCESS TIME REFRESH
CLOCK CYCLE
TIME
CLOCK TO
OUTPUT
TIME
INTERVAL
PIN NOMENCLATURE
t
t
t
REF
CK
AC
(MIN)
(MIN)
8ns
9ns
10ns
(MAX)
32ms
32ms
32ms
A[0:10]
Address Inputs
’626162-12
’626162-15
12 ns
15 ns
20 ns
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
’626162-20
Read latency = 3
†
A11
CAS
CKE
Column-Address Strobe
Clock Enable
description
CLK
System Clock
CS
Chip Select
The SMJ626162 series of devices are
16777216-bit synchronous dynamic random-
access memory (SDRAM) devices organized as
two banks of 524288 words with 16 bits per word.
DQ[0:15]
DQML, DQMU
NC
SDRAM Data Input/Data Output
Data-Input/Data-Output Mask Enable
No Connect
Row-Address Strobe
Power Supply (3.3-V Typical)
Power Supply for Output Drivers
(3.3-V Typical)
RAS
V
V
CC
CCQ
All inputs and outputs of the SMJ626162 series
are compatible with the LVTTL interface.
V
V
W
Ground
Ground for Output Drivers
Write Enable
SS
SSQ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power requirements.
All inputs and outputs are synchronized with the CLK input to simplify system design and enhance use with
high-speed microprocessors and caches.
The SMJ626162 SDRAM is available in a 50-lead, 650-mil-wide ceramic dual flatpack (HKD suffix).
functional block diagram
CLK
CKE
AND
Array Bank T
CS
DQMx
RAS
CAS
W
DQ
Buffer
Control
DQ0–DQ15
16
Array Bank B
A0–A11
12
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ15, are also referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently; however, a bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
Bank-activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank-deactivate
Autorefresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1, Table 2, and Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
†
Table 1. Basic Command Truth Table
STATE OF
BANK(S)
COMMAND
CS
RAS
CAS
W
A11
A10
A9–A0
MNEMONIC
A9=V
A8 –A7 = 0
A6–A0 = V
T = deac
B = deac
Mode register set
L
L
L
L
X
X
MRS
Bank deactivate (precharge)
Deactivate all banks
X
L
L
L
L
L
L
H
H
H
L
L
L
BS
X
L
H
V
L
X
X
V
V
DEAC
DCAB
ACTV
WRT
X
Bank activate/row-address entry
Column-address entry/write operation
SB = deac
SB = actv
L
H
L
BS
BS
H
Column-address entry/write operation
with auto-deactivate
SB = actv
SB = actv
SB = actv
L
L
L
H
H
H
L
L
L
L
H
H
BS
BS
BS
H
L
V
V
V
WRT-P
READ
Column-address entry/read operation
Column-address entry/read operation
with auto-deactivate
H
READ-P
No operation
X
X
L
H
X
H
X
H
X
X
X
X
X
X
X
NOOP
DESL
Control-input inhibit/no operation
H
T = deac
B = deac
‡
Autorefresh
L
L
L
H
X
X
X
REFR
†
For execution of these commands on cycle n, one of the following must be true:
– CKE (n–1) must be high
– t
– t
must be satisfied for power-down exit
CESP
and n
must be satisfied for clock-suspend exit. DQMx (n) is irrelevant.
CLE
CES
‡
Autorefresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.
Legend:
n
L
H
X
V
T
B
actv
deac
BS
SB
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Bank T
Bank B
Activated
Deactivated
Logic high to select bank T; logic low to select bank B
Bank selected by A11 at cycle n
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
†
Table 2. Clock-Enable (CKE) Command Truth Table
CKE
(n–1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
COMMAND
STATE OF BANK(S)
MNEMONIC
§
§
T = no access operation
B = no access operation
‡
Power-down entry on cycle (n + 1)
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
PDE
—
T = power down
B = power down
¶
Power-down exit
X
X
X
§
§
T = access operation
B = access operation
CLK suspend on cycle (n + 1)
H
L
HOLD
—
§
§
T = access operation
B = access operation
CLK suspend exit on cycle (n + 1)
H
†
‡
§
For execution of these commands, A0–A11 (n) and DQMx (n) are don’t care entries.
On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
¶
If setup time from CKE high to the next CLK high satisfies t
, the device executes the respective command (listed in Table 1). Otherwise,
CESP
either a DESL or a NOOP command must be applied before any other command.
Legend:
n
L
H
X
T
B
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Bank T
Bank B
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
†
Table 3. Data Mask (DQM) Command Truth Table
DQML
DQMU
(n)
STATE OF
BANK(S)
DATA IN
(n)
DATA OUT
(n + 2)
‡
COMMAND
MNEMONIC
T = deac
and
B = deac
—
X
X
N/A
N/A
Hi-Z
Hi-Z
—
T = actv
and
B = actv
—
—
§
(no access operation)
T = write
or
B = write
Data-in enable
Data-in mask
L
H
L
V
N/A
N/A
V
ENBL
MASK
ENBL
MASK
T = write
or
B = write
M
T = read
or
B = read
Data-out enable
Data-out mask
N/A
N/A
T = read
or
H
Hi-Z
B = read
†
For execution of these commands on cycle n, one of the following must be true:
– CKE (n) must be high
– t
– t
must be satisfied for power-down exit
CESP
and n
must be satisfied for clock-suspend exit.
CES
CLE
CS(n), RAS(n), CAS(n), W(n), and A0–A11 are irrelevant.
DQML controls DQ0 –DQ7.
‡
§
DQMU controls DQ8 –DQ15.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
=
=
=
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Masked input data
Not applicable
Bank T
L
H
X
V
M
N/A
T
B
Bank B
Activated
Deactivated
actv
deac
write
read
Hi-Z
Activated and accepting data in on cycle n
Activated and delivering data out on cycle (n + 2)
High-impedance state
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
burst sequence
All data for the ’626162 is written or read in a burst fashion—that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first access can be at preceding, as well as succeeding, column
addresses, depending on the starting address entered. This sequence can be programmed to follow either a
serialburstoraninterleaveburst(seeTable 4, Table 5, and Table 6). The length of the burst can be programmed
to be either 1, 2, 4, 8, or full-page (256) accesses (see the section on setting the mode register). After a read
burstiscompleted(asdeterminedbytheprogrammedburstlength), theoutputsareinthehigh-impedancestate
until the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL BINARY
START
2ND
3RD
2
4TH
3
START
00
2ND
3RD
10
11
4TH
11
0
1
2
3
0
1
2
3
1
2
3
0
1
0
3
2
01
10
11
00
01
00
11
10
3
0
01
00
01
10
11
Serial
0
1
10
00
01
10
11
1
2
11
2
3
00
3
2
01
10
01
00
Interleave
0
1
10
00
01
1
0
11
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
BINARY
START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
001
010
011
100
101
110
111
000
001
000
011
010
101
100
111
110
010 011 100 101 110 111
011 100 101 110 111 000
100 101 110 111 000 001
101 110 111 000 001 010
Serial
110
111
111 000 001 010 011
000 001 010 011 100
000 001 010 011 100 101
001 010 011 100 101 110
010 011 100 101 110 111
011 010 101 100 111 110
000 001 110 111 100 101
001 000 111 110 101 100
Interleave
110
111
111 000 001 010 011
110 001 000 011 010
100 101 010 011 000 001
101 100 011 010 001 000
latency
The beginning data-out cycle of a read burst can be programmed to occur 2 or 3 CLK cycles after the read
command (see the section on setting the mode register). This feature allows the adjustment of the ’626162 to
operate in accordance with the system’s capability to latch the data output from the ’626162. The delay between
the READ command and the beginning of the output burst is known as read latency (also known as CAS
latency). After the initial output cycle begins, the data burst occurs at the CLK frequency without any intervening
gaps. Use of minimum read latencies is restricted, based on the particular maximum frequency rating of the
’626162.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the contents of the mode register.
two-bank operation
The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion.
Each bank must be activated with a row address before it can be accessed. Then, each bank must be
deactivated before it can be activated again with a new row address. The bank-activate/row-address-entry
command (ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK.
A bank can be deactivated either automatically during a READ-P or a WRT-P command or by use of the
deactivate-bank command (DEAC). Both banks can be deactivated at once by use of the DCAB command (see
Table 1 and the section on bank deactivation).
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM. This is accomplished by activating one bank with a row address and, while the data
stream is being accessed to/from that bank, activating the second bank with another row address. When the
data stream to/from the first bank is complete, the data stream to/from the second bank can begin without
interruption. After the second bank is activated, the first bank can be deactivated to allow the entry of a new row
address for the next round of accesses. In this manner, operation can continue in an interleaved fashion.
Figure 25 is an example of two-bank, row-interleaving, read bursts with automatic deactivate for a read latency
of 3 and a burst length of 8.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
read or write commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 26 is an example of two-bank, column-interleaving, read bursts
for a read latency of 3 and a burst length of 2.
bank deactivation (precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 is used to select the bank to be precharged as shown in Table 1.
A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is held high
during the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically
upon completion of the access burst. If A10 is held low during the entry of a read or write command, that bank
remains active following the burst. The read and write commands with automatic deactivation are denoted as
READ-P and WRT-P.
chip select (CS)
CS can be used to select or deselect the ’626162 for command entry, which might be required for
multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again. Device select is accomplished by holding
CS low on the rising edge of CLK. Any other valid command can be entered simultaneously on the same rising
CLKedge of the select operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1
and Table 2). The use of CS does not affect an access burst that is in progress; the DESL command can restrict
only RAS, CAS, and W input to the ’626162.
data mask
The mask command, or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any individual data cycle within a read burst or a write burst. DQML controls
DQ0–DQ7, and DQMU controls DQ8–DQ15. The application of DQMx to a write burst has no latency
(n
= 0 cycle), but the application of DQMx to a read burst has a latency of n
= 2 cycles. During a write
DID
DOD
burst, if DQMx is held high on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst,
if DQMx is held high on the rising edge of CLK, then n cycles after the rising edge of CLK, the data-output
DOD
will be in the high-impedance state. Figure 16, Figure 29, Figure 30, Figure 31, and Figure 32 show examples
of data-mask operations.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
setting the mode register
The ’626162 contains a mode register that must be programmed with the read latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on address lines A0–A9. A logic 0 must be entered on A7 and A8. A10 and A11 are don’t care entries
for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined
by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word
valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.
A11
A10
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
Reserved
0 = Serial
1 = Interleave
(burst type)
REGISTER
BITS
REGISTER
BITS
WRITE-
BURST
LENGTH
†
†
REGISTER
BIT A9
READ
LATENCY
BURST LENGTH
‡
A6
A5
A4
A2
A1
A0
0
0
0
1
1
1
0
1
0
1
1
1
2
4
8
256
0
1
A2–A0
1
0
0
0
1
0
0
1
1
0
1
2
3
†
‡
All other combinations are reserved.
See the timing requirements for minimum valid read latencies based on maximum frequency rating.
Figure 1. Mode-Register Programming
refresh
The ’626162 must be refreshed at intervals not exceeding t
(see timing requirements) or data cannot be
REF
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, or by
performing 4096 autorefresh (REFR) commands. Regardless of the method used, refresh must be
accomplished before t
has expired.
REF
autorefresh (REFR)
Before performing a REFR operation, both banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, both banks of the ’626162 have
been refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command
automaticallydeactivatesbothbanksuponcompletionoftheinternalautorefreshcycle. Thisallowsconsecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before t
expires.
REF
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
CLK-suspend/power-down mode
For normal device operation, CKE must be held high to enable CLK. If CKE goes low during the execution of
a read or write operation, the DQ bus occurring at the immediate next rising edge of CLK is frozen at its current
state. No further inputs are accepted until CKE returns high; this is known as a CLK-suspend operation, and
its execution is denoted as a HOLD command. The device resumes operation from the point at which it was
placed in suspension, beginning with the second rising edge of CLK after CKE returns high.
If CKE is brought low when no read or write command is in progress, the device enters the power-down mode.
If both banks are deactivated when the power-down mode is entered, power consumption is reduced to the
minimum. Power-down mode can be used during row-active or autorefresh periods to reduce input-buffer
power. After power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that
data in the device remains valid, the power-down mode must be exited periodically to meet the requirements
described earlier for device refresh. When exiting power-down mode, new commands can be entered on the
first CLK edge after CKE returns high, provided that the setup time (t
) is satisfied. Table 2 shows the
CESP
command configuration for a CLK-suspend/power-down operation; Figure 17, Figure 18, and Figure 35 show
examples of the procedure.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of a READ-P or a
WRT-P operation is not supported.
Table 7. Read-Burst Interruption
INTERRUPTING
EFFECT OR NOTE ON USE DURING READ BURST
COMMAND
Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met
and new output cycles begin (see Figure 2).
READ, READ-P
TheWRT (WRT-P)commandimmediatelysupersedesthereadburstinprogress. Toavoiddatacontention, DQMxmust
WRT, WRT-P
DEAC, DCAB
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (n
CCD
–1), n , and
CCD
(n
CCD
+1), assuming that there is any output on these cycles (see Figure 3).
TheDQbusisinthehigh-impedancestatewhenn
occurs first (see Figure 4).
cyclesaresatisfiedorwhenthereadburstcompletes, whichever
HZP
n
CCD
= 1 Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
C0
C1
C1 + 1
C1 + 2
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
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interrupted bursts (continued)
n
CCD
= 5 Cycles
CLK
Interrupting
READ Command
WRT Command
DQ
Q
D
D
See Note B
DQMx
NOTES: A. For this example, assume read latency = 3 and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (n
– 1), n
CCD
, and (n + 1).
CDD
CCD
Figure 3. Read Burst Interrupted by Write Command
n
CCD
= 2 Cycles
n
HZP
CLK
Interrupting
DEAC/DCAB
Command
READ Command
DQ
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).
The new WRT (WRT-P) command and data inputs immediately supersede the write burst in progress
(see Figure 6).
WRT, WRT-P
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
DEAC, DCAB
mask the DQ bus such that the write recovery specification (t ) is not violated by the
RWL
interrupt (see Figure 7).
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interrupted bursts (continued)
n
CCD
= 1 Cycle
CLK
WRT
READ
Command
Command
DQ
D
Q
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 5. Write Burst Interrupted by Read Command
n
CCD
= 2 Cycles
CLK
DQ
WRT Command
at Column
Address C0
Interrupting
WRT Command
at Column Address C1
C0
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
n
CCD
= 3 Cycles
CLK
WRT Command
Interrupting
DEAC or DCAB
Command
Ignored
DQ
D
D
Ignored
t
RWL
DQMx
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
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power up
Device initialization should be performed after a power up to the full V
level; however, after power is
CC
established, a 200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the
device must be deactivated. Eight REFR commands must be performed and the mode register must be set to
complete the device initialization.
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†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range for output drivers, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CCQ
Voltage range on any input pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V + 0.5 V
CC
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
3.135
3.135
NOM
3.3
3.3
0
MAX
3.465
3.465
UNIT
V
V
V
V
V
V
V
Supply voltage
CC
CCQ
SS
‡
Supply voltage for output drivers
V
Supply voltage
V
Supply voltage for output drivers
High-level input voltage
Low-level input voltage
Ambient temperature
0
V
SSQ
IH
2
– 0.3
–55
V
CC
+ 0.3
0.8
V
V
IL
T
A
125
°C
‡
V
CCQ
V
+ 0.3 V
CC
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electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (see Note 2)
’626162-12
’626162-15
’626162-20
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= –2 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 2 mA
0.4
±10
±10
0.4
±10
±10
0.4
±10
±10
OL
OL
Input current
(leakage)
0 V ≤ V ≤ V
All other pins = 0 V to V
,
I
CC
I
I
µA
µA
I
CC
Output current
(leakage)
0 V ≤ V ≤ V
, Output disabled
O
O
CCQ
Burst length = 1,
Read latency = 2
85
75
95
70
85
t
≥ t MIN,
RC RC
Average read or
write current
I
/I = 0 mA,
I
mA
OH OL
CC1
One bank activated
(see Note 3)
Read latency = 3
100
I
I
CKE ≤ V MAX,
t
= MIN (see Note 4)
2
2
2
2
2
2
CC2P
Precharge standby
current in
power-down mode
IL
CK
mA
mA
CKE and CLK
V
MAX,
IL
CC2PS
t
= ∞ (see Note 5)
CK
Precharge standby
current in
nonpower-down
mode
I
CKE ≥ V MIN,
t
= MIN (see Note 4)
40
2
35
2
30
2
CC2N
IH
CK
CKE ≥ V MIN,
CLK ≤ V MAX,
IH
IL
I
CC2NS
t
= ∞ (see Note 5)
CK
CKE ≤ V MAX,
t
= MIN
IL
One bank activated (see Note 4)
CK
I
I
I
I
10
10
55
15
10
10
45
15
10
10
40
15
CC3P
Active standby
current in
power-down mode
mA
mA
CKE and CLK ≤ V MAX,
IL
One bank activated (see Note 5)
t
= ∞
CK
CC3PS
CC3N
CKE ≥ V MIN, = MIN
t
IH
CK
Active standby
current in
nonpower-down
mode
One bank activated (see Note 4)
CKE ≥ V MIN,
CLK ≤ V MAX,
IH IL
CC3NS
t
= ∞, One bank activated (see Note 5)
CK
Continuous burst,
/I = 0 mA,
Read latency = 2
Read latency = 3
165
210
130
175
110
150
I
OH OL
All banks activated,
= one cycle
I
Burst current
Autorefresh
mA
mA
CC4
n
CCD
(see Note 6)
Read latency = 2
Read latency = 3
120
120
100
100
80
80
I
t ≥ t MIN
RC RC
CC5
NOTES: 2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Control and address inputs change state twice during t
4. Control and address inputs change state once every 2 × t
5. Control and address inputs do not change state (stable).
.
RC
.
CK
6. Control and address inputs change state once every cycle.
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capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 7)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
Input capacitance, CLK input
8
i(S)
i(AC)
i(E)
o
Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W
Input capacitance, CKE input
8
8
pF
pF
Output capacitance
10
pF
NOTE 7: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
†‡
ac timing requirements
’626162-12
’626162-15
’626162-20
UNIT
MIN
15
12
4
MAX
MIN
20
15
4
MAX
MIN
30
20
4
MAX
Read latency = 2
Read latency = 3
t
Cycle time, CLK (system clock)
ns
CK
t
t
Pulse duration, CLK (system clock) high
Pulse duration, CLK (system clock) low
ns
ns
CKH
4
4
4
CKL
Read latency = 2
Read latency = 3
9
8
15
9
20
10
Access time, CLK ↑ to data out
(see Note 8)
t
t
t
ns
ns
ns
AC
Delay time, CLK to DQ in the low-impedance state (see Note 9)
0
0
0
LZ
Read latency = 2
Read latency = 3
8
8
14
11
15
12
Delay time, CLK to DQ in the
high-impedance state (see Note 10)
HZ
t
t
t
t
t
t
t
t
t
t
Setup time, data input
Setup time, address
3
3
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS
AS
Setup time, control input (CS, RAS, CAS, W, DQMx)
Setup time, CKE (suspend entry/exit, power-down entry)
Setup time, CKE (power-down/self-refresh exit) (see Note 11)
Hold time, CLK ↑ to data out
3
4
4
CS
3
4
4
CES
CESP
OH
10
1.5
2
10
2
10
2
Hold time, data input
2
2
DH
Hold time, address
2
2
2
AH
Hold time, control input (CS, RAS, CAS, W, DQMx)
Hold time, CKE
2
2
2
CH
2
2
2
CEH
REFR command to ACTV, MRS, or REFR command;
ACTV command to ACTV, MRS, or REFR command
t
96
120
160
ns
RC
t
t
t
ACTV command to DEAC or DCAB command
60 100 000
75 100 000
100 100 000
ns
ns
ns
RAS
RCD
RP
ACTV command to READ or WRT command (see Note 12)
DEAC or DCAB command to ACTV, MRS, or REFR command
24
36
30
45
40
60
†
‡
See Parameter Measurement Information for load circuits.
All references are made to the rising transition of CLK unless otherwise noted.
NOTES: 8. t
is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out t
is referenced
AC
AC
from the rising transition of CLK that is one cycle before read latency for the READ command. Access time is measured at output
reference level 1.4 V.
9.
10.
t
t
is measured from the rising transition of CLK that is one cycle before read latency for the READ command.
(MAX) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
HZ
11. See Figure 18.
12. For read or write operations with automatic deactivate, t
must be set to satisfy minimum t .
RAS
RCD
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†‡
ac timing requirements (continued)
’626162-12
’626162-15
’626162-20
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Final data out of READ-P operation to ACTV, MRS, or REFR
command
t
t
+ (n
× t
EP CK
)
ns
APR
RP
t
t
t
t
t
Final data in of WRT-P operation to ACTV, MRS, or REFR command
Final data in to DEAC or DCAB command
ACTV command for one bank to ACTV command for the other bank
Transition time, all inputs (see Note 13)
Refresh interval
t
+ t
ns
ns
ns
ns
ms
APW
RWL
RRD
T
RP CK
24
24
1
30
30
1
40
40
1
5
5
5
32
32
32
REF
†
‡
See Parameter Measurement Information for load circuits.
All references are made to the rising transition of CLK unless otherwise noted.
NOTE 13: Transition time (rise and fall) should be a minimum of 1 ns and a maximum of 5 ns measured between V MIN and V MAX. This is
IH
IL
ensured by design but not tested.
‡§
clock timing requirements
’626162-12
’626162-15
’626162-20
§
UNIT
MIN
–1
MAX
MIN
–1
MAX
MIN
–1
MAX
Read latency = 2
Final data out to DEAC or
DCAB command
n
cycles
EP
Read latency = 3
Read latency = 2
–2
–2
–2
DEAC or DCAB interrupt of
data-out burst to DQ in the
high-impedance state
2
3
2
3
2
3
n
cycles
cycles
HZP
CCD
Read latency = 3
READ or WRT command to interrupting READ, WRT, DEAC, or DCAB
command
n
1
1
1
n
n
n
n
Final data in to READ or WRT command in either bank
WRT command to first data in
1
0
0
2
1
0
0
2
1
0
0
2
cycles
cycles
cycles
cycles
CWL
WCD
DID
0
0
2
0
0
0
2
ENBL or MASK command to data in
ENBL or MASK command to data out
0
2
DOD
HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command
n
CLE
1
1
1
1
1
1
cycles
n
n
MRS command to ACTV, REFR, or MRS command
DESL command to control input inhibit
2
0
2
0
2
0
cycles
cycles
RSA
0
0
0
CDD
‡
§
All references are made to the rising transition of CLK unless otherwise noted.
A CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE
(those CLK cycles occurring during the time when CKE is asserted low).
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PARAMETER MEASUREMENT INFORMATION
The ac timing measurements are based on signal rise and fall times equal to 1 ns (t = 1 ns) and a midpoint
T
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level is changed
to V MIN and V MAX instead of the midpoint level. All specifications referring to READ commands are also
IH
IL
valid for READ-P commands unless otherwise noted. All specifications referring to WRT commands are also
valid for WRT-P commands unless otherwise noted. All specifications referring to consecutive commands are
specified as consecutive commands for the same bank unless otherwise noted.
I
OL
Tester Pin
Electronics
(see Note A)
Output
Under
Test
50 Ω
1.4 V
C
= 50 pF
L
I
OH
NOTE A: Series termination resistors may be used on test
hardwarefor output impedance matching purposes.
Figure 8. LVTTL-Load Circuit
t
CK
t
CKH
CLK
t
T
t
CKL
t
, t , t , t
DS AS CS CES
t
T
t
, t , t , t
DH AH CH CEH
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
t
T
t
, t , t , t
DH AH CH CEH
t
, t , t , t
, t
DS AS CS CES CESP
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
t
T
Figure 9. Input-Attribute Parameters
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PARAMETER MEASUREMENT INFORMATION
Read Latency
CLK
t
ACTV
READ
AC
Command
Command
t
HZ
t
LZ
t
OH
DQ
Figure 10. Output Parameters
READ, WRT
DESL
READ, READ-P, WRT, WRT-P, DEAC, DCAB
Command Disable
n
CCD
n
t
CDD
ACTV
DEAC, DCAB
RAS
ACTV, REFR
ACTV
ACTV, MRS, REFR
t
RC
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR
t
t
RCD
DEAC, DCAB
ACTV
t
RP
ACTV (different bank)
ACTV, MRS
RRD
MRS
n
RSA
Figure 11. Command-to-Command Parameters
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PARAMETER MEASUREMENT INFORMATION
n
HZP
n
EP
CLK
DQ
DEAC or
DCAB
Command
READ
Command
t
HZ
Q
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 12. Read Followed by Deactivate
t
APR
CLK
DQ
ACTV, MRS, or
REFR Command
READ-P
Command
Final Data Out
Q
NOTE A: For this example, assume read latency = 3 and burst length = 1.
Figure 13. Read With Auto-Deactivate
n
CWL
t
RWL
CLK
DQ
DEAC or DCAB
Command
WRT
Command
WRT
Command
D
D
NOTE A: For this example, assume burst length = 1.
Figure 14. Write Followed By Deactivate
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PARAMETER MEASUREMENT INFORMATION
n
CWL
t
APW
CLK
DQ
ACTV, MRS, or
REFR Command
WRT
Command
WRT-P
Command
D
D
Figure 15. Write With Auto-Deactivate
n
DOD
t
RWL
n
DOD
CLK
DEAC or
DCAB
Command
WRT
Command
READ
Command
DQ
Q
D
Ignored
MASK
Ignored
Ignored
ENBL
MASK
MASK
MASK
ENBL
MASK
Command
Command
Command
Command
Command
Command Command
DQMx
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 16. DQ Masking
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PARAMETER MEASUREMENT INFORMATION
n
CLE
n
CLE
CLK
DQ
DQ
DQ
DQ
DQ
t
CES
t
CES
t
CEH
t
CEH
CKE
Figure 17. CLK-Suspend Operation
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PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Exit
power-down
modeift
is
CESP
satisfied (new
command)
CLK is don’t
care, but
must be
stable
before CKE
high
Last
Data-Out
READ
(READ-P)
Operation
Enter
power-down
mode
CKE
CLK
t
t
CESP
CEH
t
CES
DESL or
NOOP
Last Data-In
WRT
command
(WRT-P)
Operation
only if t
CESP
is not
CLK is don’t
care, but
must be
stable
before CKE
high
satisfied
Last
Data-Out
READ
(READ-P)
Operation
Exit power-down
mode (new
command)
Enter
power-down
mode
CKE
t
CEH
t
CESP
t
CES
Figure 18. Power-Down Operation
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ACTV T
READ T
DEAC T
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum t and n for the ’626162-15 at 66 MHz.
RCD
EP
Figure 19. Read Burst (read latency = 3, burst length = 4)
ACTV T
WRT T
DEAC T
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
A0–A9
CS
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum t and t for the ’626162-15 at 66 MHz.
RCD
RWL
Figure 20. Write Burst (burst length = 8)
ACTV B
WRT B
READ B
DEAC B
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
D
Q
B
B
R0
R0
C0
C0 + 1
C1
C1 + 1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum t and n for the ’626162-15 at 66 MHz.
RCD
EP
Figure 21. Write-Read Burst (read latency = 3, burst length = 2)
ACTV T
READ T
WRT-P T
i
CLK
DQ
a
b
c
d
e
f
g
h
j
k
l
m
n
o
p
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Q
D
T
T
R0
R0
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-15 at 66 MHz.
RCD
Figure 22. Read-Write Burst With Automatic Deactivate (read latency = 3, burst length = 8)
ACTV T
READ T
WRT-P T
i
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
f
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
e
g
h
i
Q
D
T
T
R0
R0
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-15 at 66 MHz.
RCD
Figure 23. Read Burst – Single Write With Automatic Deactivate (read latency = 3, burst length = 8)
ACTV B
READ-P B
CLK
DQ0
DQMx
RAS
CAS
W
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10 n+11 n+12 n+13 n+14
n+253 n+254 n+255
R0
R0
A10
A11
C0
A0–A9
CS
CKE
BURST
†
BURST CYCLE
BANK ROW
TYPE
(D/Q)
Q
(B/T) ADDR
R0
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
B
C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
255
†
Column-address sequence depends on programmed burst type and starting column address C0.
NOTE A: This example illustrates minimum t for the ’626162-15 at 66 MHz.
RCD
Figure 24. Read Burst – Full Page (read latency = 3, burst length = 256)
ACTV T READ-P T
ACTV T
ACTV B READ-P B
ACTV B READ-P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
R0
R1
R1
R2
R2
R3
R3
A10
A11
R0
C0
C1
C2
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK ROW
(B/T) ADDR
(D/Q)
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
Q
Q
Q
B
T
B
R0
R1
R2
C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
C2 C2+1 C2+2
.
.
†
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-15 at 66 MHz.
RCD
Figure 25. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8)
ACTV T
READ T
READ T
ACTV B
READ B
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQMx
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
C2
C3
C4
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
C0 + 1
c
d
e
f
. . .
. . .
Q
Q
Q
.
B
T
B
R0
R1
R0
. . .
C0
C1
C1 + 1
C2
C2 + 1
. . .
. . .
. . .
†
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).
Figure 26. Two-Bank Column-Interleaving Read Bursts (read latency = 3, burst length = 2)
ACTV T
WRT T
DEAC T
ACTV B
READ B
DEAC B
CLK
DQ
DQMx
RAS
CAS
W
a
b
c
d
e
f
g
h
A10
R0
R0
R1
R1
A11
A0–A9
C0
C1
CS
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
B
T
R0
R1
C0
C0 +1
C0 + 2
C0 + 3
C1
C1 + 1
C1 +2
C1+ 3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5.)
NOTE A: This example illustrates minimum t , n , and t for the ’626162-15 at 66 MHz.
RCD EP
RWL
Figure 27. Read-Burst Bank B, Write-Burst Bank T (read latency = 3, burst length = 4)
ACTV T
WRT-P T
ACTV B
READ-P B
CLK
DQ
a
b
c
d
e
f
g
DQMx
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
C0 +1
c
d
e
f
C1 + 1
g
h
D
Q
T
B
R0
R1
C0
C0 + 2
C0 + 3
C1
C1 + 2
C1 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum n for the ’626162-15 at 66 MHz.
CWL
Figure 28. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (read latency = 3, burst length = 4)
ACTV T
READ T
WRT T
e
DCAB
CLK
DQ
g
b
a
c
d
f
h
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
C0+1
c
d
e
f
g
h
Q
D
T
T
R0
R1
C0
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t for the ’626162-15 at 66 MHz.
RCD
Figure 29. Data Mask (read latency = 3, burst length = 4)
ACTV B
ACTV T
READ B
READ T
READ B
READ T
READ B
CLK
DQ0–DQ7
a
b
c
d
e
f
DQML
Hi-Z
DQ8–DQ15
DQMU
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0–A9
CS
C0
C1
C2
C3
C4
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
Q
Q
Q
T
B
T
B
R0
R1
R0
R1
C0
C0+1
C1
C1+1
C2
C1+1
C3
C3+1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
Figure 30. Data Mask With Byte Control (read latency = 3, burst length = 2)
ACTV T
ACTV B
READ B
DEAC B
WRT T
DEAC T
CLK
DQ0–DQ7
DQML
e
f
g
h
a
b
c
d
DQ8–DQ15
DQMU
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
B
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t and n read burst, and a minimum t write burst for the ’626162-15 at 66 MHz.
RCD
EP RWL
Figure 31. Data Mask With Byte Control (read latency = 3, burst length = 4)
ACTV T
READ T
ACTV B
c
WRT B
DCAB
CLK
DQ0–DQ7
DQML
b
b
a
a
d
d
f
f
h
h
c
e
g
DQ8–DQ15
DQMU
RAS
CAS
W
R0
R0
R1
R1
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
B
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t and t for the ’626162-15 at 66 MHz.
RCD
RWL
Figure 32. Data Mask With Cycle-by-Cycle Byte Control (read latency = 3, burst length = 4)
REFR
ACTV T
READ T
DEAC T
REFR
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
R0
R0
A10
A11
A0–A9
C0
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim t , t , and n for the ’626162-15 at 66 MHz.
RC RCD EP
Figure 33. Refresh Cycles (read latency = 3, burst length = 4)
DCAB
MRS
ACTV B
WRT-P B
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
R0
R0
A10
See Note B
See Note B
See Note B
A11
A0–A9
C0
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
D
B
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum t , n , and t for the ’626162-15 at 66 MHz.
RP RSA
RCD
B. See Figure 1.
Figure 34. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(read latency = 3, burst length = 4)
ACTV T
READ T
WRT-P T
HOLD
PDE
HOLD
b
CLK
DQ
a
d
e
f
g
h
c
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 35. CLK Suspend (HOLD) During Read Burst and Write Burst (read latency = 3, burst length = 4)
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
MECHANICAL DATA
HKD (R-CDFP-F50)
CERAMIC DUAL FLATPACK
0.665 (16,90)
0.634 (16,10)
1
50
0.031 (0,80)
0.843 (21,40)
0.811 (20,60)
0.766 (19,45)
0.746 (18,95)
0.020 (0,50)
0.012 (0,30)
25
26
0.370 (9,40)
0.250 (6,35)
0.015 (0,38) MIN
(4 Places)
Lid
0.140 (3,55)
0.110 (2,80)
0.587 (14,90)
0.026 (0,66) MIN
0.555 (14,10)
0.009 (0,23)
0.004 (0,10)
0.030 (0,76) MIN
4081537/B 10/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The leads will be gold plated.
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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