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数据手册MT8880CS-1 概述
ISO2-CMOS Integrated DTMFTransceiver ISO2 -CMOS集成DTMFTransceiver
MT8880CS-1 数据手册
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MT8880C/MT8880C-1
Integrated DTMF Transceiver
ISSUE 2
May 1995
Features
Ordering Information
•
•
•
•
•
•
•
Complete DTMF transmitter/receiver
MT8880CE/CE-1
20 Pin Plastic DIP
20 Pin Ceramic DIP
20 Pin SOIC
24 Pin SSOP
28 Pin Plastic LCC
MT8880CC/CC-1
MT8880CS/CS-1
MT8880CN/CN-1
MT8880CP/CP-1
Central office quality
Low power consumption
Microprocessor port
Adjustable guard time
Automatic tone burst mode
Call progress mode
-40°C to +85°C
based upon the industry standard MT8870
monolithic DTMF receiver; the transmitter utilizes a
switched capacitor D/A converter for low distortion,
high accuracy DTMF signalling. Internal counters
provide a burst mode such that tone bursts can be
transmitted with precise timing. A call progress filter
can be selected allowing a microprocessor to
Applications
•
•
•
•
•
Credit card systems
Paging systems
analyze
call
progress
tones.
A
standard
Repeater systems/mobile radio
Interconnect dialers
Personal computers
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors. The
MT8880C-1 is functionally identical to the MT8880C
except for the performance of the receiver section,
which is enhanced to accept and reject lower signal
levels.
Description
The MT8880C/C-1 is a monolithic DTMF transceiver
with call progress filter. It is fabricated in Mitel’s
2
ISO -CMOS technology, which provides low power
dissipation and high reliability. The DTMF receiver is
D0
Data
Bus
Buffer
Row and
D/A
Transmit Data
D1
D2
D3
∑
Column
TONE
Converters
Register
Counters
Status
Register
Interrupt
Logic
Tone Burst
Gating Cct.
Control
Logic
IRQ/CP
Control
Register
A
IN+
IN-
GS
+
-
Dial
Tone
Filter
High Group
Filter
Digital
Φ2
Algorithm
and Code
Converter
Control
Register
B
I/O
Control
CS
Low Group
Filter
OSC1
OSC2
Oscillator
R/W
RS0
Circuit
Control
Logic
Receive Data
Register
Steering
Logic
Bias
Circuit
VDD VRef VSS
ESt
St/GT
Figure 1 - Functional Block Diagram
4-33
MT8880C/MT8880C-1 ISO2-CMOS
20
19
18
17
16
15
14
13
12
11
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
2
3
4
5
6
7
8
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
Φ2
RS0
•
NC
NC
NC
D3
D2
D1
D0
NC
VRef
VSS
OSC1
OSC2
NC
5
25
24
23
22
21
20
19
6
7
8
9
10
NC 11
9
10
9
10
11
12
RS0
20 PIN CERDIP/PLASTIC DIP/SOIC
28 PIN PLCC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20 24 28
1
2
3
1
2
3
1
2
4
IN+ Non-inverting op-amp input.
IN- Inverting op-amp input.
GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
4
5
6
7
4
5
6
7
6
7
V
Reference Voltage output, nominally V /2 is used to bias inputs at mid-rail (see Fig. 13).
Ref
DD
V
Ground input (0V).
SS
8 OSC1 DTMF clock/oscillator input.
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
8
9
10 12 TONE Tone output (DTMF or single tone).
11 13 R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
10 12 14 CS Chip Select, TTL input (CS=0 to select the chip).
11 13 15 RS0 Register Select input. See register decode table. TTL compatible.
12 14 17 Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the
device is not being accessed.
13 15 18 IRQ/ Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has
CP been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.
14- 18- 19- D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
17 21 22
18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
19 23 27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than V
detected at St
TSt
causes the device to register the detected tone pair and update the output latch. A voltage
less than V frees the device to accept a new tone pair. The GT output acts to reset the
TSt
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28
V
DD
Positive power supply input (+5V typical).
8,9
16,
17
3,5,
10,
11,
16,
23-
25
NC No Connection.
4-34
ISO2-CMOS MT8880C/MT8880C-1
Functional Description
The MT8880C/C-1 Integrated DTMF Transceiver
architecture consists of a high performance DTMF
receiver with internal gain setting amplifier and a
DTMF generator which employs a burst counter such
that precise tone bursts and pauses can be
synthesized. A call progress mode can be selected
such that frequencies within the specified passband
R1
R4
IN+
IN-
C1
C2
R5
can be detected.
A
standard microprocessor
interface allows access to an internal status register,
two control registers and two data registers.
GS
R2
R3
Input Configuration
VRef
MT8880C/C-1
The input arrangement of the MT8880C/C-1 provides
a differential-input operational amplifier as well as a
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
bias source (V ) which is used to bias the inputs at
Ref
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)
V
/2. Provision is made for connection of a
DD
feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 3.
VOLTAGE GAIN
(AV diff) = R5/R1
INPUT IMPEDANCE
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 4 shows the necessary connections for a
differential input configuration.
Figure 4 - Differential Input Configuration
which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.
IN+
IN-
RIN
C
Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state.
GS
RF
VRef
MT8880C/C-1
VOLTAGE GAIN
(AV) = RF / RIN
Figure 3 - Single-Ended Input Configuration
Receiver Section
Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Fig. 7). These filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators
4-35
MT8880C/MT8880C-1 ISO2-CMOS
Steering Circuit
Guard Time Adjustment
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
ESt. A logic high on ESt causes v (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
c
t
= t +t
DP GTP
REC
t =t +t
ID DA GTA
the validation period (t
), v reaches the threshold
GTP
c
The value of t
Electrical Characteristics) and t
is a device parameter (see AC
(V ) of the steering logic to register the tone pair,
DP
TSt
is the minimum
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives v to V . GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
REC
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
c
DD
present (t
) and tone absent (t
). This may be
GTP
GTA
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
selected, the IRQ/CP pin will pull low when
delayed steering flag is active.
the
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt
)
R
P = (R1R2) / (R1 + R2)
VDD
C1
R2
St/GT
R1
ESt
a) decreasing tGTP; (tGTP < tGTA)
VDD
tGTP = (R1C1) In [VDD / (VDD-VTSt
tGTA = (RpC1) In (VDD/VTSt
RP = (R1R2) / (R1 + R2)
)
)
C1
VDD
VDD
Vc
St/GT
ESt
C1
R1
St/GT
tGTA = (R1C1) In (VDD / VTSt
)
R1
R2
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
ESt
MT8880C/C-1
b) decreasing tGTA; (tGTP > tGTA)
Figure 5 - Basic Steering Circuit
Figure 6 - Guard Time Adjustment
4-36
ISO2-CMOS MT8880C/MT8880C-1
Increasing t
improves talk-off performance since
REC
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
DIGIT
1
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t
with a long t
would be appropriate for
REC
DO
2
extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 9 with a description of the events in Figure 11.
3
4
5
6
Call Progress Filter
7
A call progress mode, using the MT8880C/C-1, can
be selected allowing the detection of various tones
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
DTMF signals cannot be detected if CP mode has
been selected (see Table 5). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard-
limited by a high gain comparator with the IRQ/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
8
9
0
*
#
A
B
C
D
a
microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ/CP
pin will remain low.
0= LOGIC LOW, 1= LOGIC HIGH
Figure 7 - Functional Encode/Decode Table
LEVEL
(dBm)
DTMF Generator
The DTMF transmitter employed in the MT8880C/C-
1 is capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Figure 7 must be written to
the transmit Data Register. Note that this is the same
as the receiver output code. The individual tones
-25
0
250
500
750
FREQUENCY (Hz)
= Reject
= May Accept
= Accept
Figure 8 - Call Progress Response
The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number
which are generated (f
and f
) are referred to
LOW
HIGH
as Low Group and High Group tones. As seen from
the table, the low group frequencies are 697, 770,
852 and 941 Hz. The high group frequencies are
1209, 1336, 1477 and 1633 Hz. Typically, the high
group to low group amplitude ratio (pre-emphasis) is
2dB to compensate for high group attenuation on
long loops.
4-37
MT8880C/MT8880C-1 ISO2-CMOS
EVENTS
A
B
C
D
E
F
tREC
tID
tDO
tREC
TONE
#n + 1
TONE
#n + 1
TONE #n
Vin
tDA
tDP
ESt
tGTP
tGTA
VTSt
St/GT
tPStRX
RX0-RX3
b3
DECODED TONE # (n-1)
# (n + 1)
# n
tPStb3
b2
Read
Status
Register
IRQ/CP
Figure 9 - Receiver Timing Diagram
column tones which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
of time segments is fixed at 32, however, by varying
the segment length as described above the tone
output signal frequency will be varied. The divider
output clocks another counter which addresses the
sinewave lookup ROM.
burst accuracy.
A
bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 10
that the distortion products are very low in amplitude.
The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and
Scaling Information
10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz
Figure 10 - Spectrum Plot
4-38
ISO2-CMOS MT8880C/MT8880C-1
and the transmitter gated on and off by an external
hardware or software timer.
Burst Mode
In certain telephony applications it is required that
DTMF signals being generated are of a specific
duration determined either by the particular
application or by any one of the exchange transmitter
specifications currently existing. Standard DTMF
signal timing can be accomplished by making use of
the Burst Mode. The transmitter is capable of issuing
symmetric bursts/pauses of predetermined duration.
This burst/pause duration is 51 ms±1 ms which is a
standard interval for autodialer and central office
applications. After the burst/pause has been issued,
the appropriate bit is set in the Status Register
indicating that the transmitter is ready for more data.
The timing described above is available when DTMF
mode has been selected. However, when CP mode
(Call Progress mode) is selected, a second burst/
Single Tone Generation
A single tone mode is available whereby individual
tones from the low group or high group can be
generated. This mode can be used for DTMF test
equipment applications, acknowledgment tone
generation and distortion measurements. Refer to
Control Register B description for details.
Distortion Calculations
The MT8880C/C-1 is capable of producing precise
tone bursts with minimal error in frequency (see
Table 1). The internal summing amplifier is followed
by a first-order lowpass switched capacitor filter to
minimize harmonic components and intermodulation
products. The total harmonic distortion for a single
tone can be calculated using Equation 1, which is the
ratio of the total power of all the extraneous
frequencies to the power of the fundamental
frequency expressed as a percentage. The Fourier
pause
time of 102 ms ±2 ms is available. This
extended interval is useful when precise tone bursts
of longer than 51 ms duration and 51 ms pause are
desired. Note that when CP mode and Burst mode
have been selected, DTMF tones may be transmitted
only and not received.
components of the tone output correspond to V ....
In applications where a non-standard burst/pause
duration is required, burst mode must be disabled
2f
V
as measured on the output waveform. The total
nf
harmonic distortion for a dual tone can be calculated
EXPLANATION OF EVENTS
A)
B)
C)
TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED.
TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
D)
E)
F)
TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.
ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.
END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLS
Vin
DTMF COMPOSITE INPUT SIGNAL.
ESt
EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
St/GT
RX0-RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER
b3
DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A
VALID DTMF SIGNAL.
b2
INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS
REGISTER IS READ.
IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS
CLEARED AFTER THE STATUS REGISTER IS READ.
tREC
tREC
tID
MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.
MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.
MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.
MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.
TIME TO DETECT VALID FREQUENCIES PRESENT.
TIME TO DETECT VALID FREQUENCIES ABSENT.
GUARD TIME, TONE PRESENT.
tDO
tDP
tDA
tGTP
tGTA
GUARD TIME, TONE ABSENT.
Figure 11 - Description of Timing Events
4-39
MT8880C/MT8880C-1 ISO2-CMOS
Maximum Series Resistance:150 ohms
Maximum Drive Level: 2mW
V22f + V23f + V24f + .... V2
nf
e.g. CTS Knights MP036S
THD(%) = 100
Toyocom TQC-203-A-9S
Vfundamental
A
number of MT8880C/C-1 devices can be
Equation 1. THD (%) For a Single Tone
connected as shown in Figure 12 such that only one
crystal is required. Alternatively, the OSC1 inputs on
all devices can be driven from a TTL buffer with the
OSC2 outputs left unconnected.
V22L + V23L + .... V2nL + V2
+
2H
V23H + .. V2nH + V2
IMD
MT8880C/C-1
MT8880C/C-1
MT8880C/C-1
THD (%) = 100
OSC1 OSC2
OSC1 OSC2
OSC1 OSC2
V2L + V2
H
Equation 2. THD (%) For a Dual Tone
OUTPUT FREQUENCY
3.579545 MHz
(Hz)
ACTIVE
INPUT
%ERROR
Figure 12 - Common Crystal Connection
SPECIFIED
697
ACTUAL
699.1
L1
L2
L3
L4
H1
H2
H3
H4
+0.30
-0.49
-0.54
+0.74
+0.57
-0.32
-0.35
+0.73
Microprocessor Interface
770
766.2
The MT8880C/C-1 employs
a
microprocessor
852
847.4
interface which allows precise control of transmitter
and receiver functions. There are five internal
registers associated with the microprocessor
interface which can be subdivided into three
categories, i.e., data transfer, transceiver control and
transceiver status. There are two registers
associated with data transfer operations.
941
948.0
1209
1336
1477
1633
1215.9
1331.7
1471.9
1645.0
Table 1. Actual Frequencies Versus Standard
Requirements
The Receive Data Register contains the output code
of the last valid DTMF tone pair to be decoded and is
a read only register. The data entered in the Transmit
Data Register will determine which tone pair is to be
generated (see Figure 7 for coding details). Data can
only be written to the transmit register. Transceiver
control is accomplished with two Control Registers
(CRA and CRB) which occupy the same address
space. A write operation to CRB can be executed by
setting the appropriate bit in CRA. The following
write operation to the same address will then be
directed to CRB and subsequent write cycles will
then be directed back to CRA. A software reset must
be included at the beginning of all programs to
initialize the control and status registers after power
up or power reset (see Figure 16). Refer to Tables 3,
4, 5 and 6 for details concerning the Control
Registers. The IRQ/CP pin can be programmed such
that it will provide an interrupt request signal upon
validation of DTMF signals or when the transmitter is
ready for more data (Burst mode only). The IRQ/CP
pin is configured as an open drain output device and
as such requires a pull-up resistor (see Figure 13).
using Equation 2. V and V correspond to the low
L
H
group amplitude and high group amplitude,
2
respectively, and V
is the sum of all the
IMD
intermodulation components. The internal switched-
capacitor filter following the D/A converter keeps
distortion products down to a very low level as
shown in Figure 10.
DTMF Clock Circuit
The internal clock circuit is completed with the
addition of a standard television colour burst crystal.
The crystal specification is as follows:
Frequency:
3.579545 MHz
±0.1%
Frequency Tolerance:
Resonance Mode:
Load Capacitance:
Parallel
18pF
4-40
ISO2-CMOS MT8880C/MT8880C-1
RS0
R/W
FUNCTION
b3
b2
b1
b0
0
0
Write to Transmit
Data Register
RSEL
IRQ
CP/DTMF
TOUT
Table 3. CRA Bit Positions
0
1
1
1
0
1
Read from Receive
Data Register
Write to Control
Register
b3
b2
b1
b0
Read from Status
Register
C/R
S/D
TEST
BURST
Table 2. Internal Register Functions
Table 4. CRB Bit Positions
BIT
NAME
FUNCTION
DESCRIPTION
b0
b1
TOUT
TONE OUTPUT
A logic ‘1’ enables the tone output. This function can be
implemented in either the burst mode or non-burst mode.
CP/DTMF
MODE CONTROL
In DTMF mode (logic ‘0’) the device is capable of generating
and receiving Dual Tone Multi-Frequency signals. When the
CP (Call Progress) mode is selected (logic ‘1’) a 6th order
bandpass filter is enabled to allow call progress tones to be
detected. Call progress tones which are within the specified
bandwidth will be presented at the IRQ/CP pin in
rectangular wave format if the IRQ bit has been enabled
(b2=1). Also, when the CP mode and BURST mode have both
been selected, the transmitter will issue DTMF signals with a
burst and pause of 102 ms (typ) duration. This signal duration
is twice that obtained from the DTMF transmitter if DTMF
mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode of operation has been selected.
b2
b3
IRQ
INTERRUPT ENABLE
REGISTER SELECT
A logic ‘1’ enables the INTERRUPT mode. When this mode is
active and the DTMF mode has been selected (b1=0) the IRQ/
CP pin will pull to a logic ‘0’ condition when either 1) a valid
DTMF signal has been received and has been present for the
guard time duration or 2) the transmitter is ready for more data
(BURST mode only).
RSEL
A logic ‘1’ selects Control Register B on the next Write cycle to
the Control Register address. Subsequent Write cycles to the
Control Register are directed back to Control Register A.
Table 5. Control Register A Description
4-41
MT8880C/MT8880C-1 ISO2-CMOS
BIT
NAME
FUNCTION
DESCRIPTION
b0
BURST
BURST MODE
A logic ‘0’ enables the burst mode. When this mode is
selected, data corresponding to the desired DTMF tone pair
can be written to the Transmit Register resulting in a tone
burst of a specific duration (see AC Characteristics).
Subsequently, a pause of the same duration is induced.
Immediately following the pause, the Status Register is
updated indicating that the Transmit Register is ready for
further instructions and an interrupt will be generated if the
interrupt mode has been enabled. Additionally, if call
progress (CP) mode has been enabled, the burst and pause
duration is increased by a factor of two. When the burst
mode is not selected (logic ‘1’) tone bursts of any desired
duration may be generated.
b1
b2
b3
TEST
S/D
TEST MODE
By enabling the test mode (logic’1’), the IRQ/CP pin will
present the delayed steering (inverted) signal from the DTMF
receiver. Refer to Figure 9 (b3 waveform) for details
concerning the output waveform. DTMF mode must be
selected (CRA b1=0) before test mode can be implemented.
SINGLE /DUAL TONE
GENERATION
A logic ‘0’ will allow Dual Tone Multi-Frequency signals to be
produced. If single tone generation is enabled (logic ‘1’),
either row or column tones (low group or high group) can be
generated depending on the state of b3 in Control Register
B.
C/R
COLUMN/ROW TONES
When used in conjunction with b2 (above) the transmitter
can be made to generate single row or single column
frequencies. A logic ‘0’ will select row frequencies and a logic
‘1’ will select column frequencies.
Table 6. Control Register B Description
BIT
NAME
STATUS FLAG SET
STATUS FLAG CLEARED
b0
IRQ
Interrupt has occurred. Bit one (b1) Interrupt is inactive. Cleared after
or bit two (b2) is set.
Status Register is read.
b1
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
Pause duration has terminated
and transmitter is ready for new
data.
Cleared after Status Register is
read or when in non-burst mode.
b2
b3
RECEIVE DATA
REGISTER FULL
Valid data is in the Receive Data
Register.
Cleared after Status Register is
read.
DELAYED STEERING
Set upon the valid detection of the Cleared upon the detection of a
absence of a DTMF signal. valid DTMF signal.
Table 7. Status Register Description
4-42
ISO2-CMOS MT8880C/MT8880C-1
VDD
MT8880C/C-1
C3
VDD
St/GT
ESt
IN+
C1
R1
C2
DTMF/CP
INPUT
IN-
R4
GS
R3
R2
D3
VRef
VSS
OSC1
OSC2
TONE
R/W
CS
D2
X-tal
D1
D0
To µP
or µC
IRQ/CP
Φ2
DTMF
OUTPUT
C4
RL
RS0
Notes:
R1, R2 = 100 kΩ 1%
R3 = 374 Ω 1%
R4 = 3.3 kΩ 10%
RL = 10 k Ω (min.)
C1 = 100 nF 5%
C2 = 100 nF 5%
C3 = 100 nF 10%*
C4 = 10 nF 10%
X-tal = 3.579545 MHz
* Microprocessor based systems can inject undesirable noise into
the supply rails. The performance of the MT8880 can be optimized
by keeping noise on the supply rails to a minimum. The decoupling
capacitor (C3) should be connected close to the device and ground
loops should be avoided.
Figure 13 - Application Circuit (Single-Ended Input)
5.0 VDC
5.0 VDC
MMD6150
(or equivalent)
2.4 kΩ
3 kΩ
TEST POINT
TEST POINT
130 pF
24 kΩ
70 pF
MMD7000
(or equivalent)
Test load for D0-D3 pins
Test load for IRQ/CP pin
Figure 14 - Test Circuit
4-43
MT8880C/MT8880C-1 ISO2-CMOS
+5V
3.3k
MT8880C/C-1
6802
IRQ
RS0
IRQ
Address
CS
Peripheral decode
VMA
R/W
Φ2
R/W
E
Data
Data
Figure 15 - MT8880C/C-1 to 6802 Interface
EXAMPLE 1: A software reset must be included at the beginning of all programs to initialize the control
registers after power up. The initialization procedure should be implemented 100ms after power up.
Description
Control
Data
b2
CS
RS0 R/W
b3
b1
b0
1) Read Status Register
2) Write to Control Register
3) Write to Control Register
4) Write to Control Register
5) Write to Control Register
6) Read Status Register
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
X
0
0
1
0
X
X
0
0
0
0
X
X
0
0
0
0
X
X
0
0
0
0
X
EXAMPLE 2: Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones
Description
CS
RS0 R/W
b3
b2
b1
b0
1) Write to Control Register A
0
1
1
0
0
0
0
1
1
0
1
(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B
(burst mode)
3) Write to Transmit Data Register
(send a digit 7)
0
0
0
0
1
0
1
0
1
0
--------------------------------------wait for an interrupt or poll Status Register ----------------------------------------------
4) Read the Status Register
0
1
1
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case...
Write to Transmit Register
(send a digit 5)
0
0
0
0
1
0
1
-if bit 2 is set, a DTMF tone has been received, in which case....
Read the Receive Data Register
0
0
1
X
X
X
X
-if both bits are set...
Read the Receive Data Register
Write to Transmit Data Register
0
0
0
0
1
0
X
0
X
1
X
0
X
1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms).
Figure 16 - Application Hints
4-44
ISO2-CMOS MT8880C/MT8880C-1
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
Power supply voltage V -V
V
6
V
V
DD SS
DD
Voltage on any pin
V
V
-0.3
V
+0.3
DD
I
SS
Current at any pin (Except V
Storage temperature
V
)
10
mA
°C
DD and SS
T
-65
+150
1000
ST
Package power dissipation
P
mW
D
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated.
SS
‡
Parameter
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Positive power supply
Operating temperature
Crystal clock frequency
V
4.75
-40
5.00
5.25
+85
V
DD
T
°C
O
f
3.575965 3.579545
3.583124
MHz
CLK
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - V =0 V.
SS
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
4
Operating supply voltage
Operating supply current
Power consumption
V
4.75
5.0
7.0
5.25
11
V
mA
mW
V
DD
S
U
P
I
DD
P
57.8
C
High level input voltage
(OSC1)
V
3.5
2.2
IHO
I
N
P
U
T
S
5
Low level input voltage
(OSC1)
V
1.5
2.5
0.1
V
V
V
V
ILO
TSt
6
7
Steering threshold voltage
V
2.3
V
=5V
DD
Low level output voltage
(OSC2)
No load
V
OLO
OHO
O
U
T
P
U
T
8
9
High level output voltage
(OSC2)
No load
V
4.9
2.4
V
V
=5 V
DD
Output leakage current
(IRQ)
I
1
10
µA
V
=2.4 V
OZ
OH
S
10
11
12
13
14
V
V
output voltage
V
2.5
1.3
2.6
No load, V =5V
DD
Ref
Ref
Ref
output resistance
R
kΩ
V
OR
D
i
g
i
Low level input voltage
High level input voltage
Input leakage current
V
0.8
10
IL
IH
IZ
V
2.0
V
I
µA
V =V to V
IN
SS
DD
t
a
l
15
16
17
18
Source current
Sink current
I
I
-1.4
2.0
-0.5
2
-6.6
4.0
-3.0
4
mA
mA
mA
mA
V
V
V
V
=2.4V
OH
OH
Data
Bus
I
=0.4V
OL
OL
ESt
and
St/Gt
Source current
Sink current
=4.6V
OH
OH
I
=0.4V
OL
OL
OL
OL
IRQ/
CP
19
Sink current
I
4
16
mA
V
=0.4V
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.
4-45
MT8880C/MT8880C-1 ISO2-CMOS
Electrical Characteristics
Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0 V, VDD=5V, TO=25°C.
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
3
4
5
6
7
8
9
Input leakage current
Input resistance
I
±100
10
nA
MΩ
mV
dB
V
≤ V ≤ V
IN
SS
IN
DD
R
IN
Input offset voltage
V
25
OS
Power supply rejection
Common mode rejection
DC open loop voltage gain
Unity gain bandwidth
Output voltage swing
Allowable capacitive load (GS)
PSRR
CMRR
60
1 kHz
60
dB
0.75V ≤ V ≤ 4.25V
IN
A
65
dB
VOL
BW
1.5
4.5
100
50
MHz
V
V
R ≥ 100 kΩ to V
O
pp
L
SS
C
R
pF
L
L
10 Allowable resistive load (GS)
11 Common mode range
kΩ
V
3.0
V
No Load
CM
pp
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
MT8880C-1 AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1,2,3,5,6,9
Valid input signal levels
(each tone of composite
signal)
-31
dBm
21.8
mV
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
RMS
1
2
+1
dBm
R
X
869
mV
RMS
Input Signal Level Reject
-37
dBm
10.9
mV
RMS
† Characteristics are over recommended temperature and at VDD=5V, using the test circuit shown in Figure 13.
MT8880C AC Electrical Characteristics†- Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1,2,3,5,6,9
-29
dBm
Valid Input signal levels
(each tone of composite
signal)
27.5
mV
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
R
X
RMS
1
+1
dBm
mV
869
RMS
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
2
3
4
5
6
7
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
8
8
dB
dB
2,3,6,9
2,3,6,9
2,3,5,9
2,3,5
±1.5%±2Hz
±3.5%
R
X
-16
-12
22
dB
dB
dB
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9,11
Dial tone tolerance
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing.
* See “Notes” following AC Electrical Characteristics Tables.
4-46
ISO2-CMOS MT8880C/MT8880C-1
AC Electrical Characteristics† - Call Progress - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
@ -25 dBm
1
2
3
4
5
Lower freq. (ACCEPT)
Upper freq. (ACCEPT)
Lower freq. (REJECT)
Upper freq. (REJECT)
f
320
510
290
540
Hz
Hz
LA
f
@ -25 dBm
@ -25 dBm
@ -25 dBm
HA
f
Hz
LR
f
Hz
HR
Call progress tone detect level
(total power)
-30
dBm
† Characteristics are over recommended operating conditions unless otherwise stated
‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing
* See “Notes” AC Electrical Characteristics Tables
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max Units
Conditions
ms Note 12
ms Note 12
1
2
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Delay St to b3
t
3
11
4
14
8.5
40
DP
t
0.5
DA
#
#
#
#
3
t
t
ms User adjustable
ms User adjustable
ms User adjustable
ms User adjustable
µs
REC
REC
4
20
20
R
X
5
t
40
ID
6
t
DO
7
t
13
8
PStb3
PStRX
8
Delay St to RX -RX
t
µs
0
3
9
Tone burst duration
t
50
50
52
52
ms DTMF mode
ms DTMF mode
BST
10
11
12
13
14
15
16
Tone pause duration
t
PS
T
X
Tone burst duration (extended)
Tone pause duration (extended)
High group output level
Low group output level
Pre-emphasis
t
100
100
-6.1
-8.1
104
104
-2.1
-4.1
3
ms Call Progress mode
ms Call Progress mode
BSTE
t
PSE
V
dBm R =10kΩ
L
HOUT
T
O
N
E
V
dBm R =10kΩ
L
LOUT
dB
2
dB
dB
R =10kΩ
P
L
Output distortion (Single Tone)
THD
-35
25 kHz Bandwidth
O
U
T
R =10kΩ
L
17
18
19
20
21
22
23
24
25
26
27
Frequency deviation
f
±0.7 ±1.5
%
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
f =3.579545 MHz
D
C
Output load resistance
Φ2 cycle period
R
10
50
250
LT
t
CYC
M
P
U
Φ2 high pulse width
t
115
CH
Φ2 low pulse width
t
110
CL
I
Φ2 rise and fall time
t
t
25
R, F
N
T
E
R
F
A
C
E
Address, R/W hold time
Address, R/W setup time (before Φ2)
Data hold time (read)
Φ2 to valid data delay (read)
Data setup time (write)
t
t
26
23
22
AH, RWH
t
t
AS, RWS
t
t
*
DHR
DDR
DSW
100
200 pF load
t
45
4-47
MT8880C/MT8880C-1 ISO2-CMOS
AC Electrical Characteristics† (Cont‘d) - Voltages are with respect to ground (VSS) unless otherwise stated.
‡
Characteristics
Sym
Min
Typ
Max
Units
Notes*
28
29
30
31
32
33
34
35
Data hold time (write)
t
10
ns
pF
pF
MHz
ns
DHW
Input Capacitance (data bus)
Output Capacitance (IRQ/CP)
Crystal/clock frequency
Clock input rise time
C
5
5
IN
C
OUT
f
3.5759 3.5795 3.5831
D
T
M
F
C
t
t
110
110
Ext. clock
LHCL
HLCL
Clock input duty cycle
Clock input duty cycle
Capacitive load (OSC2)
ns
Ext. clock
Ext. clock
C
L
K
DC
40
50
60
%
CL
C
30
pF
LO
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
* The data bus output buffers are no longer sourcing or sinking current by tDHR
See Figure 6 regarding guard time adjustment.
.
#
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.
2) Digit sequence consists of all 16 DTMF tones.
3) Tone duration=40 ms. Tone pause=40 ms.
4) Nominal DTMF frequencies are used.
5) Both tones in the composite signal have an equal amplitude.
6) The tone pair is deviated by ±1.5%±2 Hz.
7) Bandwidth limited (3 kHz) Gaussian noise.
8) The precise dial tone frequencies are 350 and 440 Hz (±2%).
9) For an error rate of less than 1 in 10,000.
10) Referenced to the lowest amplitude tone in the DTMF signal.
11) Referenced to the minimum valid accept level.
12) For guard time calculation purposes.
4-48
ISO2-CMOS MT8880C/MT8880C-1
tCYC
tF
tR
Φ2
tCH
tCL
Figure 17 - Φ2 Pulse
Φ2
tDDR
tAH
tAS
CS
tRWS
tRWH
RS0
R/W
tDHR
Valid
Data
DATA BUS
Figure 18 - MPU Read Cycle
Φ2
tAH
tAS
CS
RS0
R/W
tRWS
tRWH
tDSW
tDHW
Valid
Data
DATA BUS
Figure 19 - MPU Write Cycle
4-49
MT8880C/MT8880C-1 ISO2-CMOS
NOTES:
4-50
MT8880CS-1 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| MT8880CS/CS-1 | MITEL | Integrated DTMFTransceiver | 获取价格 |
|
| MT8880CSR1 | MICROSEMI | DTMF Signaling Circuit, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20 | 获取价格 |
|
| MT8880CSR1 | ZARLINK | DTMF Signaling Circuit, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20 | 获取价格 |
|
| MT8885 | MITEL | Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface | 获取价格 |
|
| MT8885AE | MITEL | Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface | 获取价格 |
|
| MT8885AE1 | MICROSEMI | DTMF Signaling Circuit, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24 | 获取价格 |
|
| MT8885AE1 | ZARLINK | DTMF Signaling Circuit, CMOS, PDIP24, LEAD FREE, PLASTIC, MS-011AA, DIP-24 | 获取价格 |
|
| MT8885AN | MITEL | Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface | 获取价格 |
|
| MT8885AN1 | MICROSEMI | DTMF Signaling Circuit, CMOS, PDSO24, 5.30 MM, LEAD FREE, MO-150AG, SSOP-24 | 获取价格 |
|
| MT8885ANR | MICROSEMI | DTMF Signaling Circuit, CMOS, PDSO24, | 获取价格 |
|
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