MT93L16AQ_技术文档

CMOS MT93L16

Low-Voltage Acoustic Echo Canceller

Preliminary Information

DS5068

ISSUE3

July 1999

Features

Ordering Information

•

Contains two echo cancellers: 112ms acoustic

echo canceller + 16ms line echo canceller

MT93L16AQ

-40 °C to + 85 °C

AGC on speaker path

36 Pin QSOP

Works with low cost voice codec. ITU-T G.711

or signed mag µ/A-Law, or linear 2’s comp

•

Each port may operate in different format

•

Advanced NLP design - full duplex speech with

no switched loss on audio paths

Handles up to 0 dB acoustic echo return loss

and 0dB line ERL

•

Fast re-convergence time: tracks changing

echo environment quickly

•

Transparent data transfer and mute options

20 MHz master clock operation

Adaptation algorithm converges even during

Double-Talk

Low power mode during PCM Bypass

Designed for exceptional performance in high

background noise environments

Bootloadable for future factory software

upgrades

Provides protection against narrow-band signal

divergence

•

2.7V to 3.6V supply voltage; 5V-tolerant inputs

Howling prevention stops uncontrolled

oscillation in high loop gain conditions

Applications

•

Offset nulling of all PCM channels

Serial micro-controller interface

•

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferencing

Handsfree in automobile environment

Full duplex speaker-phone for PC

ST-BUS, GCI, or variable-rate SSI PCM

interfaces

•

User gain control provided for speaker path

(-24dB to +21dB in 3dB steps)

Limiter

+

µ/A-Law/

Linear

ADV

NLP

Linear/

Offset

Null

+

Sin

Sout

µ/A-Law

-

S₂

Program

RAM

DATA1

DATA2

MD1

Micro

Interface

S₃

S₁

Program

ROM

NBSD

CONTROL

UNIT

Howling

Adaptive

Filter

Adaptive

Filter

Double

Talk

Controller

Detector

NBSD

R₃

R₁

SCLK

CS

R₂

MD2

Rout

-24 -> +21dB

-

Offset

Null

User

Gain

µ/A-Law/

Linear

ADV

NLP

Linear/

µ/A-Law

Rin

AGC

+

Limiter

VSS

VDD

BCLK/C4i

FORMAT

ENA1

MCLK

RESET

ENA2

LAW

F0i

Figure 1 - Functional Block Diagram

1

MT93L16

Preliminary Information

IC

35 IC

ENA1

MD1

1

2

3

4

5

36

34

IC

ENA2

33 MCLK2

NC

32

MD2

Rin

VSS

Sin

31

6

30

VDD2

IC

7

29 VSS2

28 IC

8

MCLK

IC

9

QSOP

27

IC

10

11

12

13

14

15

IC

26 BCLK/C4i

IC

25 F0i

LAW

FORMAT

RESET

NC

24

23

Rout

Sout

22 VDD

NC

21

NC

SCLK

CS 18

16

17

20 DATA1

19 DATA2

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

1

ENA1

SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions

depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present

for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits

wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125

microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the

proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description).

2

3

MD1

ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in

conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS

and GCI Operation description). Connect this pin to Vss in SSI mode.

ENA2

SSI Enable Strobe / ST-BUS & GCI Mode for Sin/Rout (Input).This pin has dual functions

depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel

enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins.

Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2

pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description).

4

5

MD2

Rin

ST-BUS & GCI Mode for Sin/Rout (Input).When in ST-BUS or GCI operation, this pin in

conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and

GCI Operation description). Connect this pin to Vss in SSI mode.

Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data

may be in either companded or 2’s complement linear format. This is the Receive Input

channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-

BUS timing requirements.

6

Sin

IC

Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may

be in either companded or 2’s complement linear format. This is the Send Input channel

(from the microphone). Data bits are clocked in following SSI,GCI or ST-BUS timing

requirements.

7

8

Internal Connection (Input): Must be tied to Vss.

MCLK Master Clock (Input): Nominal 20 MHz Master Clock input (may be asynchronous relative

to 8KHz frame signal.) Tie together with MCLK2 (pin 33).

9,10,11

12

IC

Internal Connection (Input): Must be tied to Vss.

LAW

A/µ Law Select (Input). When low, selects µ−Law companded PCM. When high, selects A-

Law companded PCM. This control is for both serial pcm ports.

13

FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects

ITU-T (G.711) PCM code. This control is for both serial pcm ports.

2

Preliminary Information

MT93L16

Pin Description (continued)

Pin #

Name

Description

14

RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a

low-power stand-by mode.

15, 16

17

NC

SCLK

CS

No Connect (Output). These pins should be left un-connected.

Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.

Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low.

18

19

DATA2 Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin

is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and

must be tied to Vss or Vdd.

20

DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1

pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for

transmitting and receiving data.

21

22

23

NC

No Connect (Output). This pin should be left un-connected.

Positive Power Supply (Input). Nominally 3.3 volts.

VDD

Sout

Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. This is the Send

Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked

out following SSI, ST-BUS, or GCI timing requirements.

24

Rout

Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. This is the Receive

out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits

are clocked out following SSI, ST-BUS, or GCI timing requirements.

25

26

F0i

Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high)

frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.

BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.

In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27, 28

29

IC

Internal Connection (Input). Tie to Vss.

Digital Ground (Input): Nominally 0 volts.

VSS2

30

VDD2 Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22).

31

VSS

Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29).

No Connect (Output). This pin should be left un-connected.

32

NC

33

MCLK2 Master Clock (Input): Nominal 20MHz master clock (tie together with MCLK, pin 8).

34,35,36

IC Internal Connection (Input). Tie to Vss.

Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.

2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers

on a shared bus).

Glossary

Double-Talk

Near-end Single-Talk

Far-end Single-Talk

ADV NLP

Simultaneous signals present on Rin and Sin.

Signals only present at Sin input.

Signals only present at Rin input.

Advanced Non-Linear-Processor

Howling

Oscillation caused by feedback from acoustic and line echo paths

Any mono or dual sinusoidal signals

Narrow Band Signal Detector

Narrowband

NBSD

Noise-Gating

Offset Nulling

Reverberation time

ERL

Audible switching of background noise

Removal of DC component

The time duration before an echo level decays to -60dBm

Echo Return Loss

ERLE

AGC

Echo Return Loss Enhancement

Automatic Gain Control

3

MT93L16

Preliminary Information

•

PCM encoder/decoder compatible with µ/A-

Law ITU-T G.711, µ/A-Law Sign-Mag or linear

2’s complement coding.

Functional Description

The MT93L16 device contains two echo cancellers,

as well as the many control functions necessary to

operate the echo cancellers. One canceller is for

acoustic speaker to microphone echo, and one for

line echo cancellation. The MT93L16 provides clear

signal transmission in both audio path directions to

ensure reliable voice communication, even with low

level signals. The MT93L16 does not use variable

attenuators during double-talk or single-talk periods

of speech, as do many other acoustic echo

cancellers for speaker-phones. Instead, the

MT93L16 provides high performance full-duplex

operation similar to network echo cancellers, so that

users experience clear speech and un-interrupted

background signals during the conversation. This

prevents subjective sound quality problems

associated with “noise gating” or “noise contrasting”.

Automatic gain control on the receive speaker

path.

Adaptation Speed Control

The adaptation speed of the acoustic echo canceller

is designed to optimize the convergence speed

versus divergence caused by interfering near-end

signals. Adaptation speed algorithm takes into

account many different factors such as relative

double-talk condition, far end signal power, echo

path change, and noise levels to achieve fast

convergence.

2

Advanced Non-Linear Processor (ADV-NLP)

(2. Patent Pending)

The MT93L16 uses an advanced adaptive ﬁlter

algorithm that is double-talk stable, which means

that convergence takes place even while both parties

After echo cancellation, there is likely to be residual

echo which needs to be removed so that it will not be

audible. The MT93L16 uses an NLP to remove low

level residual echo signals which are not comprised

of background noise. The operation of the NLP

depends upon a dynamic activation threshold, as

well as a double-talk detector which disables the

NLP during double-talk periods.

1

are talking . This algorithm allows continual tracking

of changes in the echo path, regardless of double-

talk, as long as a reference signal is available for the

echo canceller.

(1. Patent Pending)

The echo tail cancellation capability of the acoustic

echo canceller has been sized appropriately (112ms)

to cancel echo in an average sized ofﬁce with a

reverberation time of less than 112ms. The 16ms line

echo canceller is sufﬁcient to ensure a high ERLE for

most line circuits.

The MT93L16 keeps the perceived noise level

constant, without the need for any variable

attenuators or gain switching that causes audible

“noise gating”. The noise level is constant and

identical to the original background noise even when

the NLP is activated.

In addition to the echo cancellers, the following

functions are supported:

For each audio path, the NLP can be disabled by

setting the NLP- bit to 1 in the LEC or AEC control

registers.

•

Control of adaptive ﬁlter convergence speed

during periods of double-talk, far end single-

talk, and near-end echo path changes.

3

Narrow Band Signal Detector (NBSD)

•

Control of Non-Linear Processor thresholds for

suppression of residual non-linear echo.

(3. Patent Pending)

Howling detector to identify when instability is

starting to occur, and to take action to prevent

oscillation.

Single or multi-frequency tones (e.g. DTMF, or

signalling tones) present in the reference input of an

echo canceller for a prolonged period of time may

cause the adaptive ﬁlter to diverge. The Narrow

Band Signal Detector (NBSD) is designed to prevent

this divergence by detecting single or multi-tones of

arbitrary frequency, phase, and amplitude. When

narrow band signals are detected, the ﬁlter

adaptation process is stopped but the echo canceller

continues to cancel echo.

•

Narrow-Band Detector for preventing adaptive

ﬁlter divergence caused by narrow-band signals

Offset Nulling ﬁlters for removal of DC

components in PCM channels.

Limiters that introduce controlled saturation

levels.

Serial controller interface compatible with

Motorola, National and Intel microcontrollers.

The NBSD can be disabled by setting the NB- bit to 1

in the MC control registers.

4

Preliminary Information

MT93L16

4

Howling Detector (HWLD)

(4. Patent Pending)

The AGC can be disabled by setting the AGC- bit to

1 in MC control register.

The Howling detector is part of an Anti-Howling

control, designed to prevent oscillation as a result of

positive feedback in the audio paths.

Mute Function

A pcm mute function is provided for independent

control of the Receive and Send audio paths. Setting

the MUTE_R or MUTE_S bit in the MC register,

causes quiet code to be transmitted on the Rout or

Sout paths respectively.

The HWLD can be disabled by setting the AH- bit to

1 in the (MC) control register.

Offset Null Filter

Quiet code is deﬁned according to the following

table.

To ensure robust performance of the adaptive ﬁlters

at all times, any DC offset that may be present on

either the Rin signal or the Sin signal, is removed by

LINEAR

16 bits

SIGN/

MAGNITUDE

µ-Law

CCITT (G.711)

2’s

µ-Law

FFh

A-Law

highpass ﬁlters. These ﬁlters have

frequency placed at 40Hz.

a

corner

complement

A-Law

+Zero

0000h

80h

D5h

(quiet code)

The offset null ﬁlters can be disabled by setting the

HPF- bit to 1 in the LEC or AEC control registers.

Table 1 - Quiet PCM Code Assignment

Bypass Control

Limiters

A PCM bypass function is provided to allow

transparent transmission of pcm data through the

MT93L16. When the bypass function is active, pcm

data passes transparently from Rin to Rout and from

Sin to Sout, with bit-wise integrity preserved.

To prevent clipping in the echo paths, two limiters

with variable thresholds are provided at the outputs.

The Rout limiter threshold is in Rout Limiter Register

1 and 2. The Sout limiter threshold is in Sout Limiter

Register. Both output limiters are always enabled.

When the Bypass function is selected, most internal

functions are powered down to provide low power

consumption.

User Gain

The user gain function provides the ability for users

to adjust the audio gain in the receive path (speaker

path). This gain is adjustable from -24dB to +21dB in

3dB steps. It is important to use ONLY this user gain

function to adjust the speaker volume. The user gain

function in the MT93L16 is optimally placed between

the two echo cancellers such that no reconvergence

is necessary after gain changes.

The BYPASS control bit is located in the main control

MC register.

Adaptation Enable/Disable

Adaptation control bits are located in the AEC and

LEC control registers. When the ADAPT- bit is set to

1, the adaptive ﬁlter is frozen at the current state. In

this state, the device continues to cancel echo with

the current echo model.

The gain can be accessed through Receive Gain

Control Register.

When the ADAPT- bit is set to 0, the adaptive ﬁlter is

continually updated. This allows the echo canceller

to adapt and track changes in the echo path. This is

the normal operating state.

AGC

The AGC function is provided to limit the volume in

the speaker path. The gain of the speaker path is

automatically

conditions:

reduced

during

the

following

MT93L16 Throughput Delay

•

When clipping of the receive signal occurs.

In all modes, voice channels always have 2 frames of

delay. In ST-BUS/GCI operation, the D and C

channels have a delay of one frame.

When initial convergence of the acoustic echo

canceller detects unusually large echo return.

•

When howling is detected.

5

MT93L16

Preliminary Information

Power Down / Reset

high) frame pulse is applied to the F0i pin, the device

will assume GCI operation. If F0i is tied continuously

to Vss, the device will assume SSI operation.

Figures 11 to 13 show timing diagrams of these 3

PCM-interface operation conventions.

Holding the RESET pin at logic low will keep the

MT93L16 device in a power-down state. In this state

all internal clocks are halted, and the DATA1, Sout

and Rout pins are tristated.

ST-BUS and GCI Operation

The user should hold the RESET pin low for at least

200 msec following power-up. This will insure that

the device powers up in a proper state. Following

any return of RESET to logic high, the user must wait

for 8 complete 8 KHz frames prior to writing to the

device registers. During this time, the initialization

routines will execute and set the MT93L16 to default

operation (program execution from ROM using

default register values).

The ST-BUS PCM interface conforms to Mitel’s ST-

BUS standard, with an active-low frame pulse. Input

data is clocked in by the rising edge of the bit clock

(C4i) three-quarters of the way into the bitcell, and

output data bit boundaries (Rout, Sout) occur every

second falling edge of the bit clock (see Figure 11.)

The GCI PCM interface corresponds to the GCI

standard commonly used in Europe, with an active-

high frame pulse. Input data is clocked in by the

falling edge of the bit clock (C4i) three-quarters of

the way into the bitcell, and output data bit

boundaries (Rout, Sout) occur every second rising

edge of the bit clock (see Figure 12.)

PCM Data I/O

The PCM data transfer for the MT93L16 is provided

through two PCM ports. One port consists of Rin and

Sout pins while the second port consists of Sin and

Rout pins. The data are transferred through these

ports according to either ST-BUS, GCI, or SSI

conventions, and the device automatically detects

the correct convention. The device determines the

convention by monitoring the signal applied to the

F0i pin. When a valid ST-BUS (active low) frame

pulse is applied to the F0i pin, the MT93L16 will

assume ST-BUS operation. When a valid GCI (active

Either of these interfaces (STBUS or GCI) can be

used to transport 8 bit companded PCM data (using

one timeslot) or 16 bit 2’s complement linear PCM

data (using two timeslots). The MD1/ENA1 pins

select the timeslot on the Rin/Sout port while the

MD2/ENA2 pin selects the timeslot on the Sin/Rout

port, as in Table 2. Figures 3 to 6 illustrate the

timeslot allocation for each of these four modes.

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

0

1

2

3

4

B

F0i (GCI)

PORT1

Rin

7 6 5 4 3 2 1 0

EC

Sout

7 6 5 4 3 2 1 0

PORT2

Sin

7 6 5 4 3 2 1 0

EC

7 6 5 4 3 2 1 0

Rout

outputs = High impedance

inputs = don’t care

In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can conﬁgure PORT1

and PORT2 into different modes.

Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)

6

Preliminary Information

MT93L16

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

F0i (GCI)

0

1

2

3

4

B

PORT1

Rin

7 6 5 4 3 2 1 0

EC

Sout

7 6 5 4 3 2 1 0

PORT2

Sin

7 6 5 4 3 2 1 0

EC

7 6 5 4 3 2 1 0

Rout

outputs = High impedance

inputs = don’t care

In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can conﬁgure PORT1

and PORT2 into different modes.

Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

0

1

2

3

4

B

C

D

F0i (GCI)

PORT1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Rin

EC

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Sout

PORT2

Sin

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

EC

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Rout

outputs = High impedance

inputs = don’t care

indicates that an input channel is bypassed to an output channel

ST-BUS/GCI Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller

(EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be conﬁgured in Mode 3.

Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)

7

MT93L16

Preliminary Information

C4i

start of frame (stbus & GCI)

F0i (stbus)

F0i (GCI)

Rin

S 141312 1110 9 8 7 6 5 4 3 2 1 0

PORT1

EC

S 141312 1110 9 8 7 6 5 4 3 2 1 0

Sout

Sin

S 141312 1110 9 8 7 6 5 4 3 2 1 0

PORT2

EC

S 141312 1110 9 8 7 6 5 4 3 2 1 0

Rout

outputs = High impedance

inputs = don’t care

ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and

PORT2 need not necessarily both be in mode 4.

Figure 6 - ST-BUS and GCI 16-Bit 2’s complement linear PCM I/O (Mode 4)

In SSI operation, the frame boundary is determined

by the rising edge of the ENA1 enable strobe (see

Figure 7). The other enable strobe (ENA2) is used

for parsing input/output data and it must pulse within

125 microseconds of the rising edge of ENA1.

PORT1

ST-BUS/GCI Mode

Selection

PORT2

Rin/Sout

Sin/Rout

Enable Pins

MD1 ENA1

Enable Pins

MD2 ENA2

0

1

0

1

0

Mode 1. 8 bit companded PCM I/O on

timeslot 0

0

1

0

1

0

In SSI operation, the enable strobes may be a mixed

combination of 8 or 16 BCLK cycles allowing the

ﬂexibility to mix 2’s complement linear data on one

port (e.g., Rin/Sout) with companded data on the

other port (e.g., Sin/Rout).

Mode 2. 8 bit companded PCM I/O on

timeslot 2.

Mode 3. 8 bit companded PCM I/O on

timeslot 2. Includes D & C channel

bypass in timeslots 0 & 1.

Enable Strobe Pin

Designated PCM I/O Port

1

Mode 4. 16 bit 2’s complement linear

PCM I/O on timeslots 0 & 1.

1

ENA1

ENA2

Line Side Echo Path (PORT 1)

Acoustic Side Echo Path (PORT 2)

Table 2 - ST-BUS & GCI Mode Select

SSI Operation

Table 3 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The SSI PCM interface consists of data input pins

(Rin, Sin), data output pins (Sout, Rout), a variable

rate bit clock (BCLK), and two enable pins (ENA1,

ENA2) to provide strobes for data transfers. The

active high enable may be either 8 or 16 BCLK

cycles in duration. Automatic detection of the data

type (8 bit companded or 16 bit 2’s complement

linear) is accomplished internally. The data type

cannot change dynamically from one frame to the

next.

The PCM companding/coding law used by the

MT93L16 is controlled through the LAW and

FORMAT pins. ITU-T G.711 companding curves for

µ-Law and A-Law are selected by the LAW pin. PCM

coding ITU-T G.711 and Sign-Magnitude are

selected by the FORMAT pin. See Table 4.

8

Preliminary Information

MT93L16

BCLK

start of frame (SSI)

PORT1

ENA1

8 or 16 bits

Rin

EC

Sout

8 or 16 bits

PORT2

ENA2

8 or 16 bits

Sin

EC

8 or 16 bits

Rout

outputs = High impedance

inputs = don’t care

Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate

with 16-bit enable strobes.

Figure 7 - SSI Operation

Bit Clock (BCLK/C4i )

Sign-Magnitude

FORMAT=0

ITU-T (G.711)

FORMAT=1

The BCLK/C4i pin is used to clock the PCM data for

GCI and ST-BUS (C4i) interfaces, as well as for the

SSI (BCLK) interface.

PCM Code

µ/A-LAW

µ-LAW

A-LAW

LAW = 0 or 1

LAW = 0

LAW =1

In SSI operation, the bit rate is determined by the

BCLK frequency. This input must contain either eight

or sixteen clock cycles within the valid enable strobe

window. BCLK may be any rate between 128 KHz to

4.096 MHz and can be discontinuous outside of the

enable strobe windows deﬁned by ENA1, ENA2 pins.

Incoming PCM data (Rin, Sin) are sampled on the

falling edge of BCLK while outgoing PCM data (Sout,

Rout) are clocked out on the rising edge of BCLK.

See Figure 13.

+ Full Scale

+ Zero

1111 1111

1000 0000

0000 0000

0111 1111

1000 0000

1111 1111

0111 1111

0000 0000

1010 1010

1101 0101

0101 0101

0010 1010

- Zero

- Full Scale

Table 4 - Companded PCM

Linear PCM

The 16-bit 2’s complement PCM linear coding

permits a dynamic range beyond that which is

speciﬁed in ITU-T G.711 for companded PCM. The

echo-cancellation algorithm will accept 16 bits 2’s

complement linear code which gives a maximum

signal level of +15dBm0.

In ST-BUS and GCI operation, connect the system

C4 (4.096MHz) clock to the C4i pin.

Master Clock (MCLK)

A nominal 20MHz, continuously-running master

clock (MCLK) is required. MCLK may be

asynchronous with the 8KHz frame.

9

MT93L16

Preliminary Information

The

MT93L16

microport

automatically

Microport

accommodates these two schemes for normal data

bytes. However, to ensure timely decoding of the

R/W and address information, the Command/

Address byte is deﬁned differently for Intel and

Motorola/National operations. Refer to the relative

timing diagrams of Figure 8 and Figure 9. Receive

data bits are sampled on the rising edge of SCLK

while transmit data is clocked out on the falling edge

of SCLK. Detailed microport timing is shown in

Figure 14 and Figure 15.

The serial microport provides access to all MT93L16

internal read and write registers, plus write-only

access to the bootloadable program RAM (see next

section for bootload description.) This microport is

compatible with Intel MCS-51 (mode 0), Motorola

SPI

(CPOL=0,

CPHA=0),

Microwire speciﬁcations.

and

National

The

Semiconductor

microport consists of a transmit/receive data pin

(DATA1), a receive data pin (DATA2), a chip select

pin (CS) and a synchronous data clock pin (SCLK).

Bootload Process and Execution from RAM

The MT93L16 automatically adjusts its internal

timing and pin conﬁguration to conform to Intel or

Motorola/National requirements. The microport

dynamically senses the state of the SCLK pin each

time CS pin becomes active (i.e. high to low

transition). If SCLK pin is high during CS activation,

then Intel mode 0 timing is assumed. In this case

DATA1 pin is deﬁned as a bi-directional (transmit/

receive) serial port and DATA2 is internally

disconnected. If SCLK is low during CS activation,

then Motorola/National timing is assumed and

DATA1 is deﬁned as the data transmit pin while

DATA2 becomes the data receive pin. The MT93L16

supports Motorola half-duplex processor mode

(CPOL=0 and CPHA=0). This means that during a

write to the MT93L16, by the Motorola processor,

output data from the DATA1 pin must be ignored.

This also means that input data on the DATA2 pin is

ignored by the MT93L16 during a valid read by the

Motorola processor.

A bootloadable program RAM (BRAM) is available on

the MT93L16 to support factory-issued software

upgrades to the built-in algorithm. To make use of

this bootload feature, users must include 4096 X

8bits of memory in their microcontroller system (i.e.

external to the MT93L16), from which the MT93L16

can be bootloaded. Registers and program data are

loaded into the MT93L16 in the same fashion via the

serial microport. Both employ the same command /

address / data byte speciﬁcation described in the

previous section on serial microport. Either intel or

motorola mode may be transparently used for

bootloading. There are also two registers relevant to

bootloading (BRC=control and SIG=signature, see

Register Summary). The effect of these register

values on device operation is summarized in Table 5.

Bootload mode is entered and exited by writing to the

bootload bit in the Bootload RAM Control (BRC)

register at address 3fh (see Register Summary).

During bootload mode, any serial microport "write"

(R/W command bit =0) to an address other than that

All data transfers through the microport are two bytes

long. This requires the transmission of a Command/

Address byte followed by the data byte to be written

to or read from the addressed register. CS must

remain low for the duration of this two-byte transfer.

As shown in Figures 8 and 9, the falling edge of CS

indicates to the MT93L16 that a microport transfer is

about to begin. The ﬁrst 8 clock cycles of SCLK after

the falling edge of CS are always used to receive the

Command/Address byte from the microcontroller.

The Command/Address byte contains information

detailing whether the second byte transfer will be a

read or a write operation and at what address. The

next 8 clock cycles are used to transfer the data byte

between the MT93L16 and the microcontroller. At the

end of the two-byte transfer, CS is brought high again

to terminate the session. The rising edge of CS will

tri-state the DATA1 pin. The DATA1 pin will remain tri-

stated as long as CS is high.

of the BRC register

will contribute to ﬁlling the

program BRAM. Call these transactions "BRAM-ﬁll"

writes. Although a command/address byte must still

precede each data byte (as described for the serial

microport), the values of the address ﬁelds for these

"BRAM-ﬁll" writes are ignored (except for the value

3fh, which designates the BRC register.) Instead,

addresses are internally generated by the MT93L16

for each "BRAM-ﬁll" write. Address generation for

"BRAM-ﬁll" writes resumes where it left off following

any read transaction while bootload mode is

enabled. The ﬁrst 4096 such "BRAM-ﬁll" writes while

bootload is enabled will load the memory, but further

ones after that are ignored.

Following the write of

the ﬁrst 4096 bytes, the program BRAM will be ﬁlled.

Before bootload mode is disabled, it is

recommended that users then read back the value

from the signature register (SIG) and compare it to

the one supplied by the factory along with the code.

Equality veriﬁes that the correct data has been

loaded. The signature calculation uses an 8-bit MISR

which only incorporates input from "BRAM-ﬁll"

Intel processors utilize Least Signiﬁcant Bit (LSB)

ﬁrst transmission while Motorola/National processors

use Most Signiﬁcant Bit (MSB) ﬁrst transmission.

10

Preliminary Information

MT93L16

FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM

BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)

R/W

Data

Address

W

3fh

Writes "data" to BRC reg.

- Bootload frozen; BRAM contents are NOT affected.

BRC Register

Bits

(= 1 1 1 1 1 1 b)

C₃C₂C₁C₀

W

R

other than 3fh

1 x x x x x b

Writes "data" to next byte in BRAM (bootloading.)

X 1 0 0

Reads back "data" = BRC reg value.

- Bootload frozen; BRAM contents are NOT affected.

R

0 x x x x x b

Reads back "data" = SIG reg value.

- Bootload frozen; BRAM contents are NOT affected.

NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)

BRC Register

Bits

R/W

Data

Address

C₃C₂C₁C₀

W

any

Writes "data" to corresponding DREG.

(= a₅a₄a₃a₂a₁a₀b)

X 0 0 0

R

any

Reads back "data" = corresponding DREG value.

(= a₅a₄a₃a₂a₁a₀b)

PROGRAM EXECUTION MODES

Execute program in ROM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

C₃C₂C₁C₀

0

0 0 0

C₃C₂C₁C₀

Execute program in ROM, while bootloading the RAM.

- BRAM address counter increments on microport writes (except to 3fh)

- SIG reg recalculates signature on microport writes (except to 3fh)

0

1 0 0

C₃C₂C₁C₀

Execute program in RAM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

1

0 0 0

C₃C₂C₁C₀

- NOT RECOMMENDED -

(Execute program in RAM, while bootloading the RAM)

1

0

Table 5 - Bootload RAM Control (BRC) Register States

Note: bits C C are reserved, and must be set to zero.

1

0

writes. Resetting the bootload bit (C ) in the BRC

Following program loading and enabling of execution

from RAM, it is recommended that users set the

software reset bit in the Main Control (MC) register,

to ensure that the device updates the default register

values to those of the new program in RAM. Note: it

is important to use a software reset rather than a

hardware (RESET=0) reset, as the latter will return

the device to its default settings (which includes

execution from program ROM instead of RAM.)

2

register to 0 (see Register Summary) exits bootload

mode, resetting the signature (SIG) register and

internal address generator for the next bootload. A

hardware reset (RESET=0) similarly returns the

MT93L16 to the ready state for the start of a

bootload.

Once the program has been loaded, to begin

execution from RAM, bootload mode must be

disabled (BOOT bit, C =0) and execution from RAM

To verify which code revision is currently running,

users can access the Firmware Revision Code

(FRC) register (see Register Summary). This

register reﬂects the identity code (revision number)

of the last program to run register initialization (which

follows a software or hardware reset.)

2

enabled (RAM_ROMb bit, C =1) by setting the

3

appropriate bits in the BRC register. During the

bootload process, however, ROM program execution

(RAM_ROMb bit, C =0) should be selected. See

3

Table 5 for the effect of the BRC register settings on

Microport accesses and on program execution.

11

MT93L16

Preliminary Information

COMMAND/ADDRESS ➄

DATA INPUT/OUTPUT

A

X

D

R/W

DATA 1

0

1

2

3

4

5

0

1

2

3

4

5

6

7

➀

➁

SCLK

CS

➃

➂

➀

➁

This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.

The MT93L16: latches receive data on the rising edge of SCLK

outputs transmit data on the falling edge of SCLK

➂

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent

byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➃

➄

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

6 bits - Addressing Data

1 bit - Unused

Figure 8 - Serial Microport Timing for Intel Mode 0

COMMAND/ADDRESS ➄

DATA INPUT

DATA 2

Receive

R/W A

A

X

D

5

4

3

2

1

0

7

6

5

4

3

2

1 0

DATA OUTPUT

DATA 1

Transmit

D

High Impedance

7

6

5

4

3

2

1 0

➀

➁

SCLK

CS

➃

➂

➀

➁

This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.

The MT93L16: latches receive data on the rising edge of SCLK

outputs transmit data on the falling edge of SCLK

➂

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent

byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➃

➄

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

6 bits - Addressing Data

1 bit - Unused

Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire

12

Preliminary Information

MT93L16

Absolute Maximum Ratings*

Parameter

Symbol

-V

Min

Max

Units

1

2

3

4

5

6

Supply Voltage

V

-0.5

5.0

5.5

±20

150

V

DD SS

Input Voltage

V

-0.3

i

SS

Output Voltage Swing

Continuous Current on any digital pin

Storage Temperature

Package Power Dissipation

V

-0.3

V

o

I

mA

°C

i/o

T

-65

ST

P

90 (typ)

mW

D

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

.

Recommended Operating Conditions - Voltages are with respect to ground (V ) unless otherwise stated

SS

Characteristics

Supply Voltage

Sym

Min

Typ

Max Units

Test Conditions

1

2

3

4

V

2.7

1.4

3.3

3.6

V

DD

Input High Voltage

Input Low Voltage

V

DD

V

0.4

V

SS

Operating Temperature

T

-40

+85

°C

A

Echo Return Limits

Characteristics

Acoustic Echo Return

Line Echo Return

Min

Typ

Max Units

Test Conditions

1

2

0

dB

Measured from Rout -> Sin

Measured from Sout -> Rin

DC Electrical Characteristics*- Voltages are with respect to ground (V ) unless otherwise stated.

SS

‡

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Notes

RESET = 0

RESET = 1, clocks active

Standby Supply Current:

Operating Supply Current:

Input HIGH voltage

I

3

70

µA

mA

V

CC

1

20

DD

2

3

4

5

6

7

8

9

V

0.7V

DD

IH

Input LOW voltage

V

0.3V

V

IL

DD

Input leakage current

High level output voltage

Low level output voltage

High impedance leakage

Output capacitance

I /I

0.1

10

µA

V

V =V to V

IH IL

IN

SS

DD

V

0.8V_DD

I

=2.5mA

OH

V

0.4V

V

=5.0mA

OL

OZ

DD

I

1

10

8

10

µA

pF

V =V to V

IN SS

C

o

Input capacitance

C

i

‡ Typical ﬁgures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

*DC Electrical Characteristics are over recommended temperature and supply voltage.

13

MT93L16

Preliminary Information

AC Electrical Characteristics^†- Serial Data Interfaces - Voltages are with respect to ground (V ) unless

SS

otherwise stated

Characteristics

MCLK Frequency

Sym

Min

Typ

Max

Units

Test Notes

1

2

f

19.15

90

20.5

MHz

ns

CLK

BCLK/C4i Clock High

BCLK/C4i Clock Low

BCLK/C4i Period

t

BCH,

t

C4H

3

t

90

ns

BLL,

t

C4L

4

5

t

240

80

7900

ns

BCP

SSI Enable Strobe to Data Delay

(ﬁrst bit)

t

C =150pF

L

SD

6

7

8

9

SSI Data Output Delay (excluding

ﬁrst bit)

t

80

10

15

ns

C =150pF

L

DD

SSI Output Active to High

Impedance

t

C =150pF

L

AHZ

SSI Enable Strobe Signal Setup

t

BCP

-15

SSS

SSH

SSI Enable Strobe Signal Hold

t

BCP

-10

10 SSI Data Input Setup

11 SSI Data Input Hold

t

10

15

20

80

ns

DIS

t

DIH

12 ST-BUS/GCI F0i Setup

13 ST-BUS/GCI F0i Hold

14 ST-BUS/GCI Data Output delay

t

150

F0iS

F0iH

DSD

t

C =150pF

L

15 ST-BUS/GCI Output Active to High

Impedance

t

C =150pF

L

ASHZ

16 ST-BUS/GCI Data Input Hold time

17 ST-BUS/GCI Data Input Setup time

t

20

ns

DSH

t

DSS

† Timing is over recommended temperature and power supply voltages.

14

Preliminary Information

MT93L16

AC Electrical Characteristics^†- Microport Timing

Characteristics

Input Data Setup

Sym

Min

Typ

Max

Units

Test Notes

1

2

3

4

5

6

7

8

9

t_IDS

t_IDH

30

ns

Input Data Hold

30

Output Data Delay

Serial Clock Period

SCLK Pulse Width High

SCLK Pulse Width Low

CS Setup-Intel

t_ODD

t_SCP

t_SCH

t_SCL

t_CSSI

t_CSSM

t_CSH

t_OHZ

100

500

250

200

100

C =150pF

L

CS Setup-Motorola

CS Hold

10 CS to Output High Impedance

C =150pF

L

† Timing is over recommended temperature range and recommended power supply voltages.

Characteristic

CMOS reference level

Symbol

CMOS Level

Units

V

0.5*V

0.9*V

0.1*V

0.7*V

0.3*V

V

CT

DD

Input HIGH level

V

H

Input LOW level

V

L

Rise/Fall HIGH measurement point

Rise/Fall LOW measurement point

V

HM

V

LM

Table 8 - Reference Level Deﬁnition for Timing Measurements

T=1/f_CLK

V_H

(I)

MCLK

V

CT

V_L

Notes: O. CMOS output

I. CMOS input (5V tolerant)

(see Table 8 for symbol deﬁnitions)

Figure 10 - Master Clock - MCLK

15

MT93L16

Preliminary Information

Bit 7

Bit 6

(O)

Sout/Rout

V

CT

t_ASHZ

t_DSD

t_C4H

V_H

V_L

(I)

C4i

V

CT

t_F0iSt_F0iH

t_C4L

V_H

V_L

(I)

F0i

V

CT

t_DSSt_DSH

start of frame

V_H

V_L

(I)

Rin/Sin

V

CT

Bit 6

Bit 7

Figure 11 -GCI Data Port Timing

)

Bit 7

Bit 6

(O)

Sout/Rout

V

CT

t_DSD

t_C4H

t_ASHZ

V_H

V_L

(I)

C4i

V

CT

t_F0iSt_F0iH

t_C4L

V_H

V_L

(I)

F0i

V

CT

start of frame

t_DSSt_DSH

V_H

V_L

(I)

Rin/Sin

V

CT

Bit 6

Bit 7

Figure 12 - ST-BUS Data Port Timing

Bit 7

Bit 6

Bit 5

(O)

V

Sout/Rout

CT

t_AHZ

t_SD

t_DD

t_BCH

V_H

V_L

(I)

V

BCLK

CT

t_SSS

t_BCP

t_BCL

t_SSH

V_H

V_L

(I)

ENA1

V

CT

or

(I)

ENA2

t_DIS

t_DIH

start of frame

V_H

V_L

(1)

V

CT

Rin/Sin

Bit 7

Bit 6

Bit 5

Notes: O. CMOS output

I. CMOS input (5V tolerant)

(see Table 8 for symbol deﬁnitions)

Figure 13 - SSI Data Port Timing

16

Preliminary Information

MT93L16

DATA OUTPUT

DATA INPUT

(I,O)

DATA1

V

CT

t_IDSt_IDH

t_SCH

t_ODD

t_OHZ

V_H

(I)

SCLK

V

CT

V_L

t_CSSI

t_SCL

t_SCP

t_CSH

V_H

(

I)

CS

V

CT

V_L

Notes: O. CMOS output

I. CMOS input (5V tolerant)

(see Table 8 for symbol deﬁnitions)

Figure 14 - INTEL Serial Microport Timing

V_H

V_L

(I)

DATA2

(Input)

V

CT

t_IDSt_IDH

t_SCH

t_SCP

V_H

V_L

(I)

SCLK

V

CT

t_CSSM

t_SCL

t_CSH

V_H

V_L

(I)

CS

V

CT

t_ODD

t_OHZ

(O)

DATA1

V

CT

(Output)

Notes: O. CMOS output

I. CMOS input (5V tolerant)

(see Table 8 for symbol deﬁnitions)

Figure 15 - Motorola Serial Microport Timing

17

MT93L16

Preliminary Information

Register Summary

Address:

00h R/W

Main Control Register (MC)

Power Up

Reset 00h

7

6

5

4

3

2

1

0

RESET

MUTE_S

LIMIT

BYPASS

AGC-

AH-

MUTE_R

NB-

MSB

LSB

RESET

When high, the power initialization routine is executed presetting all registers to default values.

This bit automatically clears itself to’0’ when reset is complete.

AH-

AGC-

When high, the Howling detector is disabled and when low the Howling detector is enabled.

When high, AGC is disabled and when low AGC is enabled.

NB-

When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled

BYPASS

When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and

Receive paths are not bypassed

MUTE_S

MUTE_R

LIMIT

When high, the Sin path is muted to quite code (after the NLP) and when low the Sin path is not muted

When high, the Rin path is muted to quite code (after the NLP) and when low the Rin path is not muted

When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC register and when low 2-bit shift mode is

disabled

Address:

21h R/W

Acoustic Echo Canceller Control Register (AEC)

7

6

5

4

3

2

1

0

ECBY

Power Up

Reset 00h

P-

HPF-

NLP-

INJ-

HCLR

ASC-

ADAPT-

MSB

LSB

ECBY

ADAPT-

HCLR

HPF-

INJ-

When high, the Echo estimate from the ﬁlter is not subtracted from the input (Sin), when low the estimate is subtracted

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

When high, Adaptive ﬁlter coefﬁcients are cleared and when low the ﬁlter coefﬁcients are not cleared

When high, Offset nulling ﬁlter is bypassed in the Sin/Sout path and when low the Offset nulling ﬁlter in not bypassed

When high, the Noise ﬁltering process is disabled in the NLP and when low the Noise ﬁltering process is enabled

When high, the Non Linear Processor is disabled in the Sin/Sout path and when low the NLP is enabled

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

NLP-

ASC-

P-

When high, the Exponential weighting function for the adaptive ﬁlter is disabled and when low the weighting function is

enabled

Address:

01h R/W

Line Echo Canceller Control Register (LEC)

7

6

5

4

3

2

1

0

ECBY

Power Up

Reset 00h

HPF-

SHFT

NLP-

INJ-

HCLR

ASC-

ADAPT-

MSB

LSB

ECBY

ADAPT-

HCLR

HPF-

When high, the Echo estimate from the ﬁlter is not substracted from the input (Rin), when low the estimate is substracted

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

When high, Adaptive ﬁlter coefﬁcients are cleared and when low the ﬁlter coefﬁcients are not cleared

When high, Offset nulling ﬁlter is bypassed in the Rin/Rout path and when low the Offset nulling ﬁlter in not bypassed

When high, the Noise ﬁltering process is disabled in the NLP and when low the Noise ﬁltering process is enabled

When high, the Non Linear Processor is disabled in the Rin/Rout path and when low the NLP is enabled

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

INJ-

NLP-

ASC-

SHFT

when high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and outputs Sout, Rout are shift left by 2. This bit is

ignored when 16-bit linear mode is not selected in both ports. This bit is also ignored if bit 7 of MC register is set to zero

18

Preliminary Information

MT93L16

Address:

22h Read

Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

-

ACMUND

NBS

HWLNG

-

DT

NLPDC

NB

MSB

LSB

NBS

When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not

been detected in the Sin/Sout path

NB

LOGICAL OR of the status bit NBS + NBR from LSR Register

When high the Double Talk is detected and when low, the Double talk is not detected

When high, the NLP is activated and when low the NLP is not activated

RESERVED.

DT

NLPDC

-

HWLNG

ACMUND

-

When high, Howling is occurring in the loop and when low, no Howling is detected

When high, No active signal in the Rin/Rout path

RESERVED.

Address:

02h Read

Line Echo Canceller Status Register (LSR) (* Do not write to this register)

Power Up

Reset 00h

6

5

4

3

2

1

0

-

NLPC

DT

-

NB

NBR

LSB

NBR

When high, a narrowband signal has been detected in the Receive (Rin) path. When low no narrowband signal is not

detected in the Rin path

NB

This bit indicates a LOGICAL-OR of Status bits NBR + NBS (from ASR Register)

When high, double-talk is detected and when low double-talk is not detected

When high, NLP is activated and when low NLP is not activated

DT

NLPC

-

RESERVED.

.

-

--

Address:

20h R/W

Receive Gain Control Register (RGC)

7

6

5

4

3

2

1

0

Power Up

Reset 6Dh

GO

-

G3

G2

-

G1

MSB

LSB

G0

G1

G2

G3

-

User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB).

The hexadecimal number represents G3 to G0 value in the table below.

-

RESERVED

-

Gain Values for Receive Gain Control Register Bit G3 to G0 (RGC)

0h

1h

2h

3h

-24dB

-21dB

-18dB

-15dB

4h

5h

6h

7h

-12dB

-9 dB

-6 dB

-3 dB

8h

9h

Ah

Bh

0 dB

Ch

Dh

Eh

Fh

+12 dB

+ 3 dB

+ 6 dB

+9 dB

+ 15 dB

+ 18 dB

+ 21 dB

19

MT93L16

Preliminary Information

Address:

16h Read

Receive (Rin) Peak Detect Register 1 (RIPD1)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

RIPD

3

RIPD

0

RIPD

5

RIPD

1

4

6

2

7

MSB

LSB

RIPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

17h Read

Receive (Rin) Peak Detect Register 2 (RIPD2)

Power Up

Reset 00h

7

6

5

4

3

2

1

0

RIPD

11

RIPD

8

RIPD

13

RIPD

9

12

14

10

15

MSB

LSB

7

RIPD

8

MSB

9

RIPD

10

11

12

13

14

15

See Above Description

Address:

18h Read

Receive (Rin) ERROR Peak Detect Register 1 (REPD1)

7

6

5

4

3

2

1

0

REPD

Power Up

Reset 00h

REPD

2

REPD

1

4

3

6

5

0

7

MSB

LSB

REPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure #1).

The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte is in Register

2 and the low byte is in Register 1.

Address:

19h Read

Receive (Rin) ERROR Peak Detect Register 2 (REPD2)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

REPD

8

REPD

10

REPD

9

12

15

14

13

11

MSB

LSB

REPD8

REPD9

See above description

REPD10

REPD11

REPD12

REPD13

REPD14

REPD15

20

Preliminary Information

MT93L16

Address:

3Ah Read

Receive (Rout) Peak Detect Register 1 (ROPD1)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

ROPD

1

0

4

6

5

7

3

2

MSB

LSB

ROPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

3Bh Read

Receive (Rout) Peak Detect Register 2 (ROPD2)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

ROPD

8

ROPD

10

11

9

12

15

14

13

MSB

LSB

ROPD

8

9

ROPD

10

11

12

13

14

15

See Above description

Address:

36h Read

Send (Sin) Peak Detect Register 1 (SIPD1)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

SIPD

3

SIPD

0

SIPD

5

SIPD

1

4

6

2

7

MSB

LSB

SIPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

37h Read

Send (Sin) Peak Detect Register 2 (SIPD2)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

SIPD

11

SIPD

8

SIPD

13

SIPD

9

12

14

10

15

MSB

LSB

SIPD

8

9

SIPD

10

11

12

13

14

15

See above description

21

MT93L16

Preliminary Information

Address:

38h Read

Send ERROR Peak Detect Register 1 (SEPD1)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

SEPD

3

SEPD

0

SEPD

5

SEPD

1

4

6

2

7

MSB

LSB

SEPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2

(see Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high

byte is in Register 2 and the low byte is in Register 1.

Address:

39h Read

Send ERROR Peak Detect Register 2 (SEPD2)

Power Up

Reset 00h

7

6

5

4

3

2

1

0

SEPD

8

SEPD

10

SEPD

9

12

15

14

13

11

MSB

LSB

SEPD8

SEPD9

SEPD10

SEPD11

SEPD12

SEPD13

SEPD14

SEPD15

See Above description

Address:

1Ah Read

Send (Sout) Peak Detect Register 1 (SOPD1)

7

6

5

4

3

2

1

0

SOPD

Power Up

Reset 00h

SOPD

5

SOPD

6

SOPD

2

7

4

3

0

1

MSB

LSB

SOPD

0

1

2

3

4

5

6

7

These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see

Figure #1). The information is in 16-bit 2’s complement linear coded format presented in two 8 bit registers. The high byte

is in Register 2 and the low byte is in Register 1.

Address:

1Bh Read

Send (Sout) Peak Detect Register 2 (SOPD2)

Power Up

Reset 00h

7

6

5

4

3

2

1

0

SOPD

8

SOPD

10

SOPD

9

12

15

14

13

11

MSB

LSB

SOPD

8

9

SOPD

10

11

12

13

14

15

See Above description

22

Preliminary Information

MT93L16

Address:

3Ch R/W

Acoustic Echo Canceller Adaptation Speed Register 1 (A_AS1)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

A_AS

5

A_AS

6

A_AS

2

7

4

0

3

1

MSB

LSB

A_AS

0

1

2

3

4

5

6

7

This register allows the user to program control the adaptation speed of the Acoustic Echo Canceller. This register value

changes dynamically when the ’ASC-’ bit in the Acoustic Echo Canceller Control Register is low. The ’ASC-’ bit must be 1

when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low

byte is in Register 1. Smaller values correspond to slower adaptation speed.

Address:

3Dh R/W

Acoustic Echo Canceller Adaptation Speed Register 2 (A_AS2)

Power Up

Reset 10h

7

6

5

4

3

2

1

0

A_AS

10

A_AS

9

8

12

15

14

13

11

MSB

LSB

A_AS

8

9

A_AS

10

11

12

13

14

15

See Above description

Address:

1Ch R/W

Line Echo Canceller Adaptation Speed Register 1 (L_AS1)

7

6

5

4

3

2

1

0

L_AS

Power Up

Reset 00h

L_AS

5

L_AS

6

L_AS

2

7

4

3

0

1

MSB

LSB

L_AS

0

1

2

3

4

5

6

7

This register allows the user to program control the adaptation speed of the Line Echo Canceller. This register value

changes dynamically when the ’ASC-’ bit in the Acoustic Echo Canceller Control Register is low. The ’ASC-’ bit must be 1

when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low

byte is in Register 1. Smaller values correspond to slower adaptation speed.

Address:

1Dh Read

Line Echo Canceller Adaptation Speed Register 2 (L_AS2)

7

6

5

4

3

2

1

0

Power Up

Reset 08h

L_AS

8

L_AS

10

L_AS

9

12

15

14

13

11

MSB

LSB

L_AS

8

9

L_AS

10

11

12

13

14

15

See Above description

23

MT93L16

Preliminary Information

Address:

24h R/W

Rout Limiter Register 1 (RL1)

7

6

5

4

3

2

1

0

Power Up

Reset 80h

-

L

-

0

MSB

LSB

-

RESERVED

L

This bit is used in conjunction with Rout Limiter Register 2. (See description below.)

0

Address:

25h R/W

Rout Limiter Register 2 (RL2)

7

6

5

4

3

2

1

0

Power Up

Reset 3Eh

L

2

L

7

L

3

5

6

L

8

4

1

MSB

LSB

L

1

2

3

4

5

6

7

8

In conjunction with bit 7 (L ) of the above (RL1) register, this register (RL2) allows the user to program the output Limiter

threshold value in the Rout path.

0

Default value is (1f40)h which is equal to 3.14dBmo

Maximum value is (7FC0 )h = 15 dBmo

Minimum value is (0040)h = -38 dBmo

Address:

26h R/W

Sout Limiter Register (SL)

7

6

5

4

3

2

1

0

Power Up

Reset 3Dh

-

L

-

L

1

4

2

0

3

MSB

LSB

-

RESERVED

L

0

1

2

3

4

This register allows the user to program the output Limiter threshold value in the Rout path

Default value is (1f40)h which is equal to 3.14dBmo

Maximum value is (7F40 )h

24

Preliminary Information

MT93L16

Address:

03h Read

Firmware Revision Code Register (FRC)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

-

FRC

-

FRC

-

2

-

0

1

MSB

LSB

-

RESERVED

FRC

0

1

2

Revision code of the ﬁrmware program currently being run (default=rom=00).

Address:

3fh R / W

Bootload RAM Control Register (BRC)

7

6

5

4

3

2

1

0

Power Up

Reset 00h

-

BOOT

RAM_ROMb

-

MSB

LSB

C

RESERVED. Must be set to zero.

0

1

2

3

BOOT bit. When high, puts device in bootload mode. When low, bootload is disabled.

RAM_ROMb bit. When high, device executes from RAM. When low, device executes from ROM.

-

RESERVED

Address:

07h Read

Bootload RAM Signature Register (SIG)

7

6

5

4

3

2

1

0

Power Up

Reset FFh

SIG

2

SIG

1

0

4

7

6

5

3

MSB

LSB

SIG

7

6

5

4

3

2

1

0

This register provides the signature of the bootloaded data to verify error-free delivery into the device.

Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While

bootload is disabled, the register value is held constant at its reset seed value of FFh.

25


型号：	MT93L16AQ
厂家：	MITEL NETWORKS CORPORATION
描述：	CMOS Low-Voltage Acoustic Echo Canceller CMOS低压声学回声消除器光电二极管
文件：	总27页 (文件大小：120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT93L16AQ [MITEL]

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