MV182CG/DPAS [MITEL]
Video Programme Delivery Control Interface Circuit; 视频节目传送控制接口电路
| 型号： | MV182CG/DPAS |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | Video Programme Delivery Control Interface Circuit |
| 文件： | 总9页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MV1820
Purchase of Mitel Semiconductor I2C components conveys a licence under the Philips
I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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© Mitel Corporation 1998 Publication No. DS3106 Issue No. 3.0 May 1996
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any
guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and
to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
MV1820
5
MV1820
CRYSTAL SPECIFICATION
Parallel resonant fundamental frequency 27.750000MHz. AT cut.
Tolerance at -10°C to 60°C 50ppm.
Tolerance overall 100ppm.
Nominal load capacitance 20pF.
Equivalent series resistance <20Ω.
FUNCTIONAL DESCRIPTION
The video signal is sliced to produce data and
synchronising signals. Timing circuits monitor the sync signal
to enable the MV1820 to lock onto the broadcast signal. A
timing window, for the Vertical Blanking Interval (VBI) lines 6
- 22 and 318 - 335, is established to enable the acquisition
circuit to monitor the sliced data signal for valid teletext data.
The framing code is checked for valid World System
Teletext(WST)data. Magazine, packetanddesignationcode
bytes are checked and valid Broadcast Service Data Packets
(BSDP) format two type only are accepted. These are known
aspacket8/30. Formattwoissignalledbybytesix, databittwo
beingsethighandbits3and4setlow. Bytes13to25inclusive
are Hamming decoded (8,4) and stored in seven registers
each of eight bits. If the complete message is correctly
received with no uncorrectable Hamming errors, an interrupt
to the microprocessor is signalled by the DAV (bar) pin going
low. At the same time the data is transferred to a second bank
of registers, reorganised with original numbered bytes 14, 15,
24, 25 and 13 placed after byte 23, to be read out on the I2C
bus when so requested. Subsequent valid messages will
continue to be transferred to the output registers overwriting
any existing data. In this way the output registers always
contain the latest PDC message.
significant bit (MSB) first. It will then monitor the SDA line for
an acknowledge from the microprocessor. If the
microprocessor does NOT send an acknowledge, the
MV1820 will release the data line to allow the microprocessor
to send a stop condition. If the microprocessor does send an
acknowledge, the following bytes of the message will be
outputprovidedeachbyteisacknowledged. Thefinaldatawill
be byte 13 followed by the four ‘1’s.
When readout is complete, the DAV (bar) pin is reset high
and the output registers are all set high. If the microprocessor
continues to send clocks on the SCL line, the MV1820 will
output FF bytes on the SDA line. Also, if the MV1820 is re-
addressed before another PDC message is received, the
MV1820 will output FF bytes on the SDA line. The
microprocessor can prematurely stop the message by NOT
sending an Acknowledge followed by a STOP condition after
any byte has been sent by the MV1820. The registers will then
be reset to FF bytes and the DAV pin will be reset high.
To prevent any corruption of the data in the output
registers during I2C bus activity, valid PDC messages are held
in the incoming registers until I2C bus activity ceases. Here
they may be overwritten by new PDC messages until the I2C
bus activity ceases and they can then be transferred to the
output registers.
The MV1820 is configured as an I2C bus slave transmitter
with a selectable address. The I2C bus address is 0010 0001
(20 + 1 hex) with the address select (AS) pin set high, or 0010
0011 (22 + 1 hex) with the AS pin set low. The read bit (LSB)
must always be set, it is not possible to write to the MV1820.
System clock is provided by an on - chip 27.75MHz
oscillator together with an external parallel resonant
fundamental frequency AT cut crystal.
Following a reset, RESET pulled low, the output I2C bus
registerswillcontainFFbytesandtheDAVpinwillbesethigh.
When the power supply is removed, the I2C bus will not be
clamped to ground, leaving it free for other I2C bus traffic.
On recognising its address, the MV1820 will send an
acknowledge and then transmit on the SDA line the first byte
from the output registers (decoded byte 16 and 17) most
Fig.3 Typical application diagram
4
MV1820
ELECTRICAL CHARACTERISTICS (continued)
These characteristics are guaranteed over the following conditions (unless otherwise stated)
Tamb = 0 to 70˚C, VDD = 5V 10%
Value
Units
Pin
Characteristic
I2C bus
Conditions
Min
Typ
Max
11, 13
SCL, SDA Schmitt inputs
Input voltage Low
Input voltage High
Output voltage Low
SCL clock frequency
DAV data available
Output voltage low
RESET Schmitt input
Input voltage Low
Input voltage High
Input current Low
Not clamped when VDD = 0V
0
1.5
VDD
0.4
V
V
3.5
0.1
V
IOL = 3.0mA
11
1
100
1000
kHz
100k (nom) pull-up resistor
IOH = 2.4mA
0.2
-50
0.4
V
100k (nom) pull-up resistor
0
VDD-1.0
-22
0.8
VDD
-220
+10
V
V
µA
µA
VIN = VSS
VIN = VDD
-10
Input current High
NOTE
Input voltage low and input voltage high for EXT/INT, AS and XTI are as specified for DATA I/O.
PIN DESCRIPTION
Pin Name and Description
Symbol
RESET
EXT/INT
Pin
1
Active Low Reset. Includes a 100kΩ pull - up resistor
Control Pin for SYNC I/O and DATA I/O. Includes a 100kΩ pull - down resistor.
When low or not connected, internal SYNC and DATA are used, pins 9 and 10 are
outputs. When high, supply SYNC and DATA from an external source, pins 9 and
10 are inputs.
2
BLC
3
4
5
6
7
Black level capacitor.
WLC
VIDEO
GND
TCR
White level capacitor.
Input for composite video signal with negative going syncs
Ground 0 volts.
Time constant resistor. Controlling discharge rate of black and white level
capacitor voltages.
Address select for I2C bus. [0010 0001] with AS set high, or [0010 0011] with AS
set low. Includes 100kΩ pull - down resistor.
AS
8
Data input/output.
DATA I/O
SYNC I/O
SCL
9
Sync input/output.
I2C bus serial clock.
10
11
12
13
14
Positive supply voltage +5V 10%
I2C bus bi-directional data port.
VDD
SDA
Active low open drain output data available signal to microprocessor.
DAV
Includes 100kΩ pull - up resistor
XTO
XTI
15
16
Crystal out, 27.75MHz fundamental crystal with on-chip 1MΩ resistor to XTI.
Crystal input.
3
MV1820
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated)
T
amb = 0 to 70˚C, VDD = 5V 10%
Value
Typ
5.0
Units
Pin
Characteristic
Conditions
Min
Max
12
12
5
4.5
5.5
V
Supply voltage
20
25
mA
Supply current
Video input
0.8
4.7
1.8
3.0
Vpp
Video amplitude
Source impedance
TCR input
Bottom of sync to white (pk to pk)
250
Ω
7
4.7
10
200
kΩ
nF
Ω
External resistance
BLC and WLC
Connected to VDD
Connected to GND
1MHz
3 & 4
Capacitor value
Capacitor tolerance
Effective series resistance
DATA I/O and SYNC I/O
Output voltage High
Output voltage Low
Input voltage Low
Input voltage High
Input current
-10%
VDD-1.0
+10%
5
9 & 10
4.5
0.2
V
V
IOH = -1.2mA
IOL = 2.4mA
0.4
0.8
0
V
VDD-1.0
-30
VDD
+30
V
µA
VIN = VSS or VDD
2
8
EXT/INT
100k (nom) pull-down resistor
0
VDD-1.0
-10
0.8
VDD
+10
220
V
V
Input voltage Low
Input voltage High
Input current Low
Input current High
AS
µA
µA
VIN = VSS
22
50
50
VIN = VDD
100k (nom) pull-down resistor
0
VDD-1.0
-10
1.0
VDD
+10
220
V
V
Input voltage Low
Input voltage High
Input current Low
Input current High
XTI Input
µA
µA
VIN = VSS
VIN = VDD
22
16
15
-0.5
0.5
-5.0
5.0
-20
20
µA
µA
Input current Low
Input current High
XTO Output
-0.3<VIN<VIL max
VIHmin<VIN<(VDD + 0.3)
VDD-1.0
4.5
0.2
V
V
Output voltage High
Output voltage Low
Frequency
IOH = -1.0mA
IOL = 2.0mA
100ppm
0.4
27.750
MHz
2
MV1820
Video Programme Delivery Control Interface Circuit
Supersedes version in October 1995 Media IC Handbook, HB3120 - 3.0
DS3106 - 3.0 May 1996
The MV1820 is a high speed CMOS receiver for
Programme Delivery Control (PDC) messages broadcast in
World System Teletext (WST) Format Two Broadcast
Service Data Packets (BSDP). The PDC message can be
read on an I2C bus with data format similar to standard Video
Programming Service (VPS) decoders. Additional data is
appended to include new PDC features.
It is intended for use in Video Cassette Recorders to
provide automatic recording of suitably labelled Television
programmes requested by the user.
8
7
6
5
4
3
2
1
DP16
9
8
10 11 12 13 14 15 16
7
6
5
4
3
2
1
FEATURES
I On chip data slicing
I Low external component count
I I2C bus for low cost interfacing
I Advanced CMOS technology gives low power
dissipation and high reliability
MP16
9
10 11 12 13 14 15 16
PIN
DESCRIPTION
DESCRIPTION
PIN
ABSOLUTE MAXIMUM RATINGS
1
2
3
4
5
6
7
8
Supply voltage
0.3V to 7V
-0.3 to VDD +0.3V
0 to +70°C
RESET
EXT/INT
BLC
WLC
VIDEO
GND
XTI
XTO
DAV
SDA
VDD
SCL
SYNC I/O
DATA I/O
16
15
14
13
12
11
10
9
All inputs
Operating temperature
Storage temperature
-55 to 125°C
TCR
AS
ORDERING INFORMATION
MV1820F/CG/DPAS
Fig.1 Pin connections - top view
MV1820F/CG/MPES
Fig.2 MV1820 block diagram
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This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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