M2L64S40DWG-6 [MITSUBISHI]
Synchronous DRAM, 4MX16, 7ns, CMOS, PBGA54, BGA-54;
| 型号： | M2L64S40DWG-6 |
| 厂家： | 
Mitsubishi Group |
| 描述： | Synchronous DRAM, 4MX16, 7ns, CMOS, PBGA54, BGA-54 时钟 动态存储器 内存集成电路 |
| 文件： | 总47页 (文件大小：587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
M2L64S40DWG is a 4-bank x 1,048,576-word x 16-bit, low power synchronous DRAM, with1.8V
/2.5V interface. All inputs and outputs are referenced to the rising edge of CLK. They achieves low
power consumption with the lower VDD(=2.5V) and VDDQ(=1.8V/2.5V), compared to the normal
synchronous DRAM, and has the additional functions standarized in JEDEC for reducing self-refresh
current. It is suitable for main memory in mobile system, such as PDA and 3G phone terminal.
FEATURES
M2L64S40DWG
ITEM
-6
-7
CL3
CL2
8ns
9.5ns
9.5ns
19 ns
Clock Cycle Time
(Min.)
(Max.)
tCLK
tAC
9.5ns
19 ns
CL1
CL3
CL2
CL1
7ns
7ns
8ns
8ns
Access Time from CLK
17ns
18ns
Icc1
Icc6
Icc7
Operation Current(Max.) (Single Bank)
55mA
0.3mA
10 uA
50mA
0.3mA
10uA
Self Refresh Current
(Max.)
(Max.)
Deep Power Down Current
- 2.5V±0.2V power supply and 1.8V±0.15V/ 2.5V±0.2V I/O power supply for output
- Operating temperature range is -20'C ~ 85'C for -6L/-7L version. (for -6/-7 : 0'C~70'C)
- Max. Clock frequency -6:125MHz(CL3), -7:105MHz(CL3)
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 1, 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQML and DQMU
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Low power function: Deep power down,
Temperature compensated self-refresh, and
Partial array self-refresh
- 4096 refresh cycles every 64ms
-1.8V/ 2.5V Interface
- 54 ball BGA ( M2L64S40DWG )
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
M2L64S40DWG PIN Configration & Package Dimension
8.0 mm
6.4 mm
0.8 mm
0.8 mm
6.4 mm
9.0 mm
A
B
C
D
E
F
9 8
3 2 1
7
G
H
J
<Bottom View>
54ea -
0.45 mm
Max. 1.2 mm
7
8
9
Vdd
1
Vss
2
3
CLK
CKE
/CS
: Master Clock
DQ15 VssQ A VddQ DQ0
: Clock Enable
: Chip Select
B
C
D
E
DQ14 DQ13 VddQ
DQ12 DQ11 VssQ
DQ10 DQ9 VddQ
VssQ
VddQ
VssQ
Vdd
DQ2
DQ4
DQ6
DQ1
DQ3
DQ5
/RAS
/CAS
/WE
: Row Address Strobe
: Column Address Strobe
: Write Enable
DQ0-15 : Data I/O
DQ8
NC
Vss
CKE
A9
LDQM DQ7
DQM
: Output Disable/ Write Mask
: Address Input
UDQM CLK
F /CAS
/RAS
BA1
A1
/WE
/CS
A0-11
BA0,1 : Bank Address
G
H
J
NC
A8
A11
A7
BA0
A0
Vdd
: Power Supply
A6
A10
Vdd
VddQ
Vss
: Power Supply for Output
: Ground
Vss
A5
A4
A3
A2
VssQ
: Ground for Output
<Top View>
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
BLOCK DIAGRAM
DQ0-7 and DQ8-15
I/O Buffer
Memory Array
4096 x256 x16
Cell Array
Bank #0
Memory Array
4096 x256 x16
Cell Array
Memory Array
4096 x256 x16
Cell Array
Memory Array
4096 x256 x16
Cell Array
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
/RAS
/WE
A0-11
CLK
CKE
/CS
/CAS
DQL,U
BA0,1
Type Designation Code
M2 L 64 S 4 0
These rules are only applied to the Synchronous DRAM family.
D
WG -7
Access Item
-6 : 125MHz (CL3)
-7 : 105MHz (CL3)
Package Type
Process Generation
Function
WG: 54 ball BGA
D : 5th gen.
Reserved for Future Use
4 : x16
Organization
Synchronous DRAM
Density
64 : 64Mbit
Interface
L : Vdd=2.5V, VddQ=1.8V/2.5V
Mitsubishi DRAM
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
PIN FUNCTION
Master Clock:
CLK
Input
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select auto / self refresh. After self
refresh mode is started, CKE becomes asynchronous input. Self refresh is
maintained as long as CKE is low.
CKE
Input
Chip Select:
/CS
Input
Input
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is specified by
A0-7 (x16).
A0-11
Input
A10 is also used to indicate precharge option. When A10 is high at a read /
write command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied. BA0,1 must
be set with ACT, PRE, READ, WRITE commands.
BA0,1
Input
Data In and Data out are referenced to the rising edge of CLK.
DQ0-15
Input / Output
Din Mask and Output Disable:
When DQMU, L is high in burst write, Din for the current cycle is masked.
When DQMU, L is high in burst read, Dout is disabled at the next but one
cycle.
DQM(U, L)
Input
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
Vdd, Vss
Power Supply
Power Supply
VddQ, VssQ
MITSUBISHI ELECTRIC
4
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
BASIC FUNCTIONS
The M2L64S40DWG provides basic functions, bank (row) activate, burst read and write, bank (row)
precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
CKE
A10
Command
Command
define basic commands
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge, READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
COMMAND TRUTH TABLE
CKE CKE
A0-9
COMMAND
MNEMONIC
/CS /RAS /CAS /WE BA1 BA0 A10
n-1
n
A11
Deselect
DESEL
NOP
H
X
H
L
L
X
H
L
X
H
H
X
H
H
X
X
V
X
X
V
X
X
V
X
X
V
No Operation
H
H
X
X
Row Address Entry &
Bank Activate
ACT
PRE
Single Bank Precharge
H
H
X
X
L
L
L
L
H
H
L
L
V
X
V
X
L
X
X
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
H
Precharge All Banks
Column Address Entry
H
X
L
H
L
L
V
V
L
V
& Write
Column Address Entry &
H
H
X
X
L
L
H
H
L
L
L
V
V
V
V
H
L
V
V
Write with Auto-Precharge
Column Address Entry
& Read
H
Column Address Entry &
Read with Auto-Precharge
H
H
X
H
L
L
H
L
L
L
H
H
V
X
V
X
H
X
V
X
Auto-Refresh
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
L
L
H
H
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
Self-Refresh Exit
REFSX
TBST
Deep Power Down Exit
Burst Terminate
H
X
L
H
H
L
X
X
X
X
H
H
H
L
X
X
L
L
L
L
X
L
L
L
L
L
L
L
X
L
H
X
X
L
L
L
L
X
X
V*1
V*2
X
Mode Register Set
Extended Mode Register Set
Deep Power Down
MRS
EMRS
DPD
H
X
H
X
X
X
H
X
Deep Power Down Exit
DPDX
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9,11 =0, A0-A6 =Mode Address
2. A5-A11 =0, A0-A4 =Extended Mode Address
MITSUBISHI ELECTRIC
6
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
DEEP
DPDX
POWER
EXTENDED
MODE
DOWN
REGISTER
SET
DPD
EMRS
MODE
REGISTER
SET
MRS
REFA
AUTO
IDLE
REFRESH
REFS
CKEL
REFSX
CKEH
SELF
REFRESH
ACT
POWER
DOWN
CKEL
CKEH
CLK
SUSPEND
ROW
ACTIVE
TERM
TERM
READ
WRITE
WRITEA READA
CKEL
CKEH
CKEL
CKEH
READ
WRITE
READ
WRITE
READ
WRITE
SUSPEND
SUSPEND
READA
WRITEA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
READA
WRITEA
WRITEA
PRE
READA
SUSPEND
SUSPEND
PRE
POWER
APPLIED
PRE
CHARGE
POWER
ON
PRE
Automatic Sequence
Command Sequence
MITSUBISHI ELECTRIC
7
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the
inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.
5. Issue a normal mode register set command to initialize the normal mode register.
6. Issue a extended mode register set command to initialize the extended mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
CLK
NORMAL MODE REGISTER
/CS
Burst Length, Burst Type, /CAS Latency and Write Mode can be
programmed by setting the normal mode register (MRS) with BA0-BA1
=0. The normal mode register stores these data until the next MRS
command, which may be issued when both banks are in idle state. After
tRSC from a MRS command, the SDRAM is ready for the extended
mode resister set (EMRS). Unused bit A7-A8, A10-A11have to be
programmed to "0".
/RAS
/CAS
/WE
BA0,1
A11-A0
V
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
WM
0
0
LTMODE
BT
BL
Write
0
1
Burst Write
Mode
Single Write
BL
BT=0
BT=1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
2
2
CL
/CAS LATENCY
4
4
BURST
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
1
8
8
LENGTH
R
R
R
R
R
R
R
2
LATENCY
MODE
3
Full Page
R
R
R
R
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
R: Reserved for Future Use
MITSUBISHI ELECTRIC
8
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
CLK
Read
Write
Y
Command
Y
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
/CAS Latency
CL= 3
BL= 4
Burst Length
Burst Length
Burst Type
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
MITSUBISHI ELECTRIC
9
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
EXTENDED MODE REGISTER
Low power functions such as Partial Array Self-Refresh (PASR) and
Temperature Compensated Self-Refresh (TCSR) can be programmed by
setting the extended mode register (EMRS) with BA1=1 and BA0=0.
The main difference between EMRS and MRS is the input of BA0-1.
The mode register stores these data until the next EMRS command,
which may be issued when both banks are in idle state. After tRSC from
a EMRS command, the SDRAM is ready for new command.
CLK
/CS
/RAS
/CAS
/WE
BA0
Unused bit A5-A11 have to be programmed to "0".
BA1
V
A11-A0
PARTIAL ARRAY SELF-REFRESH (PASR) reduces the self-refresh
current by reducing the memory array size to be refreshed during the self-
refresh operation. Two banks (BA1=0) and one bank ( BA1=BA0=0) can be
selected in case of 32Mb and 16Mb partial array self-refresh, respectively.
Temperature Compensated Self-Refresh (TCSR) is used for
programming the refresh rate for self-refresh mode to allow the system to
control power as a function of the temperature.
Three kinds of TCSR select the self-refresh rate for the maximum
temperature of 15'C, 45'C and 85'C *1).
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0* 0* 0* 0* 0*
0
1
0* 0*
TCSR
PASR
A logic 0 should be programmed to unused bits
to ensure future compatibility (indicated by 0*).
Self-Refresh Coverage
All banks
0 0 0
Banks 0 and 1 (BA1=0)
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bank 0 (BA1=BA0=0)
R
PASR
Temperature (max)
R
0 0
0 1
1 0
1 1
85 'C *1)
45 'C
15 'C
R
TCSR
R
R
R
R: Reserved for Future Use
Note) *1 Only for -6L/-7L. (For -6/-7 : Ta max.= 70'C)
MITSUBISHI ELECTRIC
10
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CLK
Command
A0-9,11
A10
ACT
Xa
ACT
Xb
READ
Yb
PRE
ACT
Xa
tRRD
tRCD
tRP
Xa
Xb
0
1
Xa
BA0-1
DQ
00
01
01
00
Qb0
Qb1
Qb2
Qb3
Precharge All
READ
A READ command can be issued to any active bank. The start address is specified by A0-7 (x16). 1st
output data is available after the /CAS Latency from the READ. The consecutive data length is defined by
the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay
of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.
=
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Multi Bank Interleaving Read (CL=2, BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
READ
Ya
ACT
Xb
READ PRE
Yb
ACT
Xa
tRCD
tRCD
tRP
Xa
0
Xb
0
01
0
Xa
BA0-1
DQ
00
00
01
00
00
Qa0
Qa1
Qa2
Qa3 Qb0
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK
Command
ACT
Xa
READ
Ya
ACT
tRCD
BL
tRP
A0-9,11
A10
Xa
Xa
00
Xa
1
BA0-1
DQ
00
00
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK
Command
ACT
READ
ACT
tRCD
BL
DQ
DQ
CL=2
Qa0
Qa1
Qa0
Qa2
Qa1
Qa3
CL=3
Qa2 Qa3
internal precharge starts
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank.The start address is specified by A0-7 (x16). 1st
input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by
the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay of a
WRITE command after an ACT command to the same bank is tRCD. From the last input data to the
PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command,
auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the
same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after
the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
=
Write (BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
Write
Ya
PRE
ACT
Xa
tRCD
BL
tRP
Xa
0
0
Xa
BA0-1
DQ
00
00
00
00
tWR
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK
Command
ACT
Xa
Write
ACT
Xa
tRCD
BL
tRP
A0-9,11
A10
Ya
1
Xa
Xa
BA0-1
DQ
00
00
00
tWR
Da0
Da1
Da2
Da3
internal precharge starts
MITSUBISHI ELECTRIC
13
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any active bank. Random column access is
allowed. READ to READ interval is minimum 1 CLK.
Read interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11
A10
READ
Ya
READ READ
Yb
Yc
0
0
0
00
BA0-1
DQ
00
10
Qa0 Qa1
Qa2
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access is allowed.
In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention.
The output is disabled automatically 1 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
READ
Ya
Write
Ya
0
Xa
0
BA0-1
00
00
00
DQM
DQ
Qa0
Da0
Da1
Da2
Da3
Output disable by DQM by WRITE
MITSUBISHI ELECTRIC
14
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is
minimum 1 CLK.
A PRE command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
Q1
DQ
Q0
Q2
Command
READ
PRE
CL=2
DQ
Q0
Q1
Command
READ PRE
DQ
Q0
Command
READ
PRE
Q0
DQ
Q1
Q1
Q2
Command
READ
PRE
CL=3
DQ
Q0
Q0
Command
READ PRE
DQ
MITSUBISHI ELECTRIC
15
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and
disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1
CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
Read interrupted by Terminate (BL=4)
CLK
Command
READ
TBST
Q1
DQ
Q0
Q2
Command
READ
TBST
CL=2
DQ
Q0
Q1
Command
READ TBST
DQ
Q0
Command
READ
TBST
Q0
DQ
Q1
Q1
Q2
Command
READ
TBST
CL=3
DQ
Q0
Q0
Command
READ TBST
DQ
MITSUBISHI ELECTRIC
16
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
A0-9,11
A10
Write
Ya
Write Write
Yb
0
Yc
0
0
BA0-1
DQ
00
00
10
Da0
Da1
Da2
Db0 Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
Write
Ya
READ
Yb
Xa
0
0
BA0-1
DQ
00
00
00
Da0
Da1
Qb0
Qb1
Qb2 Qb3
don't care
MITSUBISHI ELECTRIC
17
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by
DQM.
Write interrupted by Precharge (BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
0
Write
Ya
0
PRE
ACT
Xa
0
tRP
0
BA0-1
DQM
00
00
00
00
tWR
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is
not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
0
Write
Ya
TBST
Write
Yb
0
0
BA0-1
DQ
00
00
00
Da0
Da1
Db0
Db1 Db2
Db3
MITSUBISHI ELECTRIC
18
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write or Read to another Bank ]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT
comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a
command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK
ACT
Xa
Command
A0-9,11
A10
Write
Ya
Write
BL
tRP
Yb
tWR
Xa
1
0
00
BA0-1
DQ
00
10
Da0
Da1
Db0 Db1
Db2
Db3
auto-precharge interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
Write
Ya
Read
BL
ACT
Xa
tRP
A0-9,11
A10
Yb
tWR
Xa
1
0
00
BA0-1
DQ
00
10
Da0
Da1
Qb0
Qb1
Qb2 Qb3
auto-precharge interrupted
activate
MITSUBISHI ELECTRIC
19
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ]
Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can
be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same
bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK
Command
A0-9,11-12
A10
Read
Ya
1
Read
BL
ACT
Xa
tRP
Yb
0
Xa
BA0-1
00
10
00
DQ
Qa0 Qa1
Qb0
Qb1
Qb2
activate
Qb3
auto-precharge interrupted
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst read or write
is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page
burst, a read or write with auto-precharge command is illegal.
Single Write
When sigle write mode is set, burst length for write is always one, independently of Burst Length
defined by (A2-0).
MITSUBISHI ELECTRIC
20
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit
memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-
refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any
command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0-1
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
21
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and
ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After
tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be
issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
new command
X
A0-11
BA0-1
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
MITSUBISHI ELECTRIC
22
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
DEEP POWER DOWN
During the deep power down mode all input except CKE is disabled and the power of the whole memory
array is cut, so that the maximum power reduction is achieved. Once the device enters deep power down
mode, data will not be retained.
[Deep Power Down Entry]
Deep power down mode is entered by issuing a DPD command (/CS= /WE= L, / RAS=/CAS= H, CKE=
L). All banks is needed to be idle state in advance before issuing DPD command. If precharge all command
is needed, a DPD command can be issued after tRP. Once the deep power down is initiated, it is
maintained as long as CKE is kept low. During the deep power down mode, CKE is asynchronous and the
only enabled input.
Deep Power Down Entry
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-9,11
A10
BA0-1
tRP
Precharge All
( If necessary )
Deep Power Down
Entry
MITSUBISHI ELECTRIC
23
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
[Deep Power Down Exit]
To exit the deep power down, supplying stable CLK inputs, asserting NOP command and then asserting
CKE=H. The power on sequence is required before issuing a new command.
Deep Power DownExit
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-9,11
A10
Key
Key
BA0
BA1
200us
tRP
tRFC
tRFC
tRSC
tRSC
Deep Power
Down Exit
Precharge Auto-Refresh Auto-Refresh
All
Normal
MRS
Extended
MRS
New Command
MITSUBISHI ELECTRIC
24
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By
negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output
suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK
suspend can be performed either when the banks are active or idle. A command at the suspended cycle is
ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CLK
CKE
Standby Power Down
Active Power Down
Command
PRE NOP NOP NOP
CKE
Command
ACT NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
Write
Read
D0
D1
D2
D3
DQ
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
25
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
DQM CONTROL
DQM(U, L) is a dual functional signal defined as the data mask for writes and the output disable for
reads. During writes, DQM(U, L) masks input data word by word. DQM(U, L) to Data In latency is
0. During reads, DQM(U, L) forces output to Hi-Z word by word. DQM(U, L) to output Hi-Z
latency is 2.
DQM Function
CLK
Write
Read
Command
DQM(U, L)
D0
D2
D3
Q0
Q1
Q3
DQ
masked by DQM(U, L)=H
disabled by DQM(U, L)=H
MITSUBISHI ELECTRIC
26
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
Parameter
Conditions
Ratings
-0.5 ~ 3.7
Unit
V
Supply Voltage
with respect to Vss
Supply Voltage for Output with respect to VssQ
-0.5 ~ 3.7
V
Input Voltage
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
with respect to VssQ -0.5 ~ VddQ+0.5
50
V
IO
Output Current
mA
mW
'C
Pd
Power Dissipation
Operating Temperature
Storage Temperature
Ta = 25'C
1000
Topr
Tstg
-20 ~ 85 *1)
-65 ~ 150
'C
Note 1) Only for -6L/-7L parts. -6/-7 parts has the spec. of Topr : 0 ~ 70 'C.
RECOMMENDED OPERATING CONDITIONS
(Ta=-20 ~ 85'C *1), unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2.3
0
Typ.
2.5
0
Max.
2.7
0
Vdd
Vss
Supply Voltage
Supply Voltage
V
V
VddQ(2.5V)
VddQ(1.8V)
Supply Voltage
for Output
2.3
2.5
1.8
2.7
V
VddQ
1.65
1.95
VssQ
VIH
VIL
Supply Voltage for Output
0
0
0
V
V
V
High-Level Input Voltage all inputs VddQ x 0.8
Low-Level Input Voltage all inputs -0.3
VddQ+0.3
0.3
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
CAPACITANCE
(Ta=-20 ~ 85'C *1) , Vdd = 2.5 ± 0.2V, VddQ = 1.8 ± 0.15V / 2.5V± 0.2V, Vss = VssQ = 0V,
unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
Min.
2.5
2.5
2.5
4.0
Max.
3.8
3.8
3.5
6.5
CI(A) Input Capacitance, address pin
CI(C) Input Capacitance, control pin
CI(K) Input Capacitance, CLK pin
CI/O Input Capacitance, I/O pin
pF
pF
pF
pF
VI=0.9v
f=1MHz
VI=200mVrms
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
MITSUBISHI ELECTRIC
27
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=-20 ~ 85'C *1), Vdd = 2.5 ± 0.2V, VddQ = 1.8 ± 0.15V / 2.5V± 0.2V, Vss = VssQ = 0V,
Output Open, unless otherwise noted)
Limits (max.)
Unit
Symbol
Parameter
Test condition
-6
-7
tRC=min, tCLK =min
BL=1, CL=3
tCLK = 15ns, CKE = H
VIH > Vcc - 0.2V,
Operating current
55
50
mA
mA
mA
Icc1
( Single bank operation )
Icc2N
Icc2NS
15
15
Precharge standby current in
VIL < 0.2V
Non Power down mode
CLK = L & CKE = H
VIH > Vcc - 0.2V, VIL < 0.2V
all input signals are fixed.
7
1
7
1
/CS > Vcc -0.2V
Precharge standby current
Icc2P
Icc2PS
Icc3N
Icc3NS
Icc4
tCLK = 15ns, CKE = L
CLK = L, CKE = L
mA
mA
in Power down mode
0.5
25
20
0.5
25
20
/CS > Vcc -0.2V
CKE = H, tCLK=15ns
Active standby current
mA
mA
CKE = H, CLK=L
All Bank Active
tCLK = min, BL=4, CL=3
Burst current
60
55
110
0.3
Icc5
tRC=min, tCLK=min
100
0.3
mA
mA
Auto-refresh current
4 Banks
2 Banks
1 Bank
8 5'C
0.25
0.2
0.3
0.2
0.1
0.4
0.25
0.2
0.3
0.2
0.1
0.4
mA
mA
Self-refresh current
-6 L,
-7L
CKE < 0.2V
Icc6
mA
mA
mA
mA
uA
45'C
15'C
4
-6 , -7 *
-6 L, -7L
-6 , -7
10
30
10
30
Deep power down current
Icc7
CKE < 0.2V
uA
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
2) In the case of TCSR=85'C
3) In the case of PASR=4 Banks
4) Only specified the Icc6 with PASR=4-banks, TCSR=70'C(85'C)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=-20 ~ 85'C *1), Vdd = 2.5 ± 0.2V, VddQ = 1.8 ± 0.15V / 2.5V± 0.2V, Vss = VssQ = 0V,
unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
0.2
VOH(DC) High-Level Output Voltage (DC) IOH=-0.1mA
VOL(DC) Low-Level Output Voltage (DC) IOL= 0.1mA
VddQ-0.2
V
V
IOZ
II
Off-state Output Current
Input Current
Q floating Vo=0 ~ VddQ
VIH=0 ~ VddQ+0.3V
µA
µA
-5
-5
5
5
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
MITSUBISHI ELECTRIC
28
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=-20 ~ 85'C *1), Vdd = 2.5 ± 0.2V, VddQ = 1.8 ± 0.15V / 2.5V± 0.2V, Vss = VssQ = 0V,
unless otherwise noted) Input Pulse Levels : 0.2V to 1.6V
Input Timing Measurement Level : 0.9V
Limits
-6
-7
Unit
Parameter
Symbol
tCLK
Max.
Max.
Min.
8
Min.
9.5
9.5
19
CL=3
ns
ns
ns
CLK cycle time
CL=2
CL=1
9.5
19
2.5
2.5
1.0
2.5
tCH
tCL
CLK High pulse width
CLK Low pulse width
3
3
ns
ns
10
10
tT
Transition time of CLK
Input Setup time
1.5
3
ns
ns
tIS
(all inputs)
(all inputs)
tIH
tRC
Input Hold time
1.0
67.5
72
1.5
70
ns
ns
ns
ns
ns
Row Cycle time
76
tRFC
tRCD
tRAS
Refresh Cycle time
Row to Column Delay
Row Active time
19
45
19
100K
100K
47.5
tRP
Row Precharge time
Write Recovery time
19
16
19
19
ns
ns
tWR
Act to Act delay
19
tRRD
tRSC
tREF
16
ns
ns
Mode Register Set Cycle time
Refresh Interval time
9.5
9.5
64
64
ms
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
CLK
0.9V
0.9V
AC timing is referenced to the
input signal crossing through
0.9V.
Signal
MITSUBISHI ELECTRIC
29
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=-20 ~ 85'C *1), Vdd = 2.5 ± 0.2V, VddQ = 1.8 ± 0.15V/ 2.5V± 0.2V, Vss = VssQ = 0V,
unless otherwise noted)
SWITCHING CHARACTERISTICS
Limits
Symbol
tAC
Parameter
-6
-7
Unit Note
ns
Max.
Min.
Max.
7
Min.
CL=3
CL=2
8
8
Access time from CLK
7
ns
ns
CL=1
17
20
ns
CL=3
CL=2
3
3
3
3
3
Output Hold time
from CLK
tOH
*1
ns
CL=1
3
0
ns
ns
Delay, output low-
tOLZ
tOHZ
0
3
impedance from CLK
Delay, output high-
3
ns
8
7
impedance from CLK
Note 1) Only for -6L/-7L parts. For -6/-7 parts : Ta= 0 ~ 70 'C.
Output Load Condition
CLK
0.9V
0.9V
V
OUT
30pF
DQ
Output Timing Measurement
Reference Point
CLK
DQ
0.9V
0.9V
tOLZ
tAC
tOHZ
tOH
MITSUBISHI ELECTRIC
30
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Burst Write (Single Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
tWR
tWR
X
X
X
0
Y
X
Y
X
X
0
A9,11
BA0,1
DQ
0
0
0
0
D0 D0 D0 D0
D0 D0 D0 D0
ACT#0 WRITE#0
PRE#0 ACT #0 WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
31
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Burst Write (Multi Bank) [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRAS
tRP
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
tRCD
tWR
tWR
X
X
X
0
Y
X
X
X
1
Y
X
X
X
0
Y
X
X
X
1
A9,11
BA0,1
DQ
0
1
0
0
0
D0 D0 D0 D0 D1 D1 D1 D1
D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
PRE#0 ACT #0 WRITE#0
PRE#0
WRITEA#1
ACT#1
(Auto-Precharge)
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
32
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Burst Read (Single Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRAS
tRP
tRAS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
X
X
X
0
Y
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
0
0
Q0 Q0 Q0 Q0
Q0 Q0 Q0 Q0
ACT#0 READ#0
PRE#0 ACT #0 READ#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
33
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Burst Read (Multi Bank) [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRC
tRRD
tRAS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
tRCD
X
X
X
0
Y
X
X
X
1
Y
X
X
X
0
Y
X
X
X
1
A9,11
BA0,1
DQ
0
1
0
0
Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READA #0
ACT#1
ACT #0 READ#0
PRE#0
ACT #1
READA #1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Write Interrupted by Write [BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tWR
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A9,11
BA0,1
DQ
0
0
1
0
0
D0 D0 D0 D0 D0 D1 D1 D1 D0 D0 D0 D0
ACT#0 WRITE#0
ACT#1
WRITE#0 WRITEA#1
WRITE#0
interrupt
other
PRE#0
interrupt
same
interrupt
other
ACT #1
bank
bank
bank
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
35
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Read Interrupted by Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
X
X
X
0
Y
X
X
X
1
Y
Y
Y
X
X
X
1
A9,11
BA0,1
DQ
0
1
1
0
Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q1 Q0 Q0 Q0 Q0
ACT#0 READ#0
ACT#1
READ#1 READA #1
READ#0
interrupt
interrupt
other
interrupt
ACT #1
same bank other
bank
bank
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
tWR
X
X
X
0
X
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
1
1
1
D0 D0
Q1 Q1
D1 D1 D1 D1
ACT#0
WRITE#0 READ#1
ACT#1
WRITE#1
PRE#1
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
37
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Write / Read Terminated by Precharge [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRC
tRP
tRAS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tRCD
tWR
X
X
X
0
Y
X
X
X
0
Y
X
X
X
0
A9,11
BA0,1
DQ
0
0
0
0
D0 D0
Q0 Q0
ACT#0 WRITE#0
PRE#0 ACT#0
Terminate
READ#0 PRE#0
Terminate
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
tWR
X
X
X
0
Y
Y
Y
A9,11
BA0,1
DQ
0
0
0
0
D0 D0
Q0 Q0
D0 D0 D0 D0
ACT#0 WRITE#0 TERM READ#0 TERM
WRITE#0
PRE#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
39
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Single Write Burst Read [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
X
X
X
0
Y
Y
A9,11
BA0,1
DQ
0
0
D0
Q0 Q0 Q0 Q0
ACT#0 WRITE#0 READ#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Power-On Sequence and Intialize
CLK
/CS
200µs
tRP
tRFC
tRFC
tRSC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
A9,11
BA0
BA1
DQ
MA
EA
X
X
X
0
0
0
0
0
0
0
0
1
0
NOP
Power On
PRE ALL REFA
REFA
REFA
MRS
EMRS
ACT #0
Minimum 8 REFA cycles
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8
A10
tRCD
X
Y
X
X
0
A9,11
BA0,1
DQ
0
D0 D0 D0 D0
PRE ALL
REFA
ACT#0 WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
42
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Self Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CLK
/CS
tRFC
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8,
A10
X
X
X
0
A9,11
BA0,1
DQ
PRE ALL Self Refresh Entry
All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
43
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
CLK Suspension [CL=2, BL=4]
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
CLK
/CS
/RAS
/CAS
/ W E
CKE
DQM
A0-8
A10
t R C D
X
X
X
0
Y
Y
A9,11
BA0,1
DQ
0
0
D 0
D 0
D 0
D 0
Q 0
Q 0
Q 0
Q 0
A C T # 0 W R I T E # 0 i n t e r n a l
C L K
R E A D # 0
i n t e r n a l
C L K
s u s p e n d e d
s u s p e n d e d
Italic paramater s h o w s m i n i m u m c a s e
MITSUBISHI ELECTRIC
44
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576 -WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov . ' 0 1
64 M Low Power Synchronous DRAM
P o w e r D o w n
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
CLK
/CS
/RAS
/CAS
/ W E
CKE
DQM
A0-8
A10
S t a n d b y P o w e r D o w n
A c t i v e P o w e r D o w n
X
X
X
0
A9,11
BA0,1
DQ
P R E A L L
A C T # 0
Italic paramater s h o w s m i n i m u m c a s e
MITSUBISHI ELECTRIC
45
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576 -WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov . ' 0 1
64 M Low Power Synchronous DRAM
Revison History
Date
May '01
Description
Rev.
- 1st edition (Preliminaly Version)
0.1
0.2
- Package dimension of BGA was changed.
(from 9x10.5mm2 to 9.25x10.85mm2)
- Command truth table of DPD was revised.
May '01
- Package dimension of BGA was changed again.
(from 9.25x10.85mm2 to 10.05x10.85mm2)
0.3
1.0
Jul. '01
- Remove sTSOP(64-pin) package
- Change operation temperature range.
-6L/-7L : Ta= -20'C ~ 85'C
Aug. '01
-6/-7 : Ta= 0'C ~ 70'C
- Change the package size
1.1
Sep . '01
From 10.05x10.85mm2 to 9.25x10.85mm2. (P2)
- Add the Icc6 spec. for TCSR. (P28)
- Change the Access and Frequency. (P1, P3, P29, P30)
2.0
Sep . '01
Oct . '01
- Change the package size
3.0
From 9.25x10.85mm2 to 9.0x8.0mm2. (P2)
- Removed 'Preliminary'
3.1
Nov. '01
MITSUBISHI ELECTRIC
46
MITSUBISHI LSIs
SDRAM (Rev.3.1)
(4-BANK x 1,048,576-WORD x 16-BIT)
M2L64S40DWG -6, -6L,-7,-7L
Nov.'01
64M Low Power Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi
semiconductor product best suited to the customer's application; they do not convey any license under
any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third
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2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit
application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts, programs and
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subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other
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The information described here may contain technical inaccuracies or typographical errors. Mitsubishi
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Please also pay attention to information published by Mitsubishi Electric Corporation by various means,
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5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or
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Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country
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8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
47
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