M30600E8-XXXFP [MITSUBISHI]
Microcontroller, 16-Bit, MROM, M16C CPU, 10MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100;
| 型号： | M30600E8-XXXFP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 16-Bit, MROM, M16C CPU, 10MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 微控制器 |
| 文件： | 总139页 (文件大小：1782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/60 group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of in-
struction efficiency. With 1M bytes of address space, they are capable of executing instructions at high
speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communi-
cations, industrial equipment, and other high-speed processing applications.
The M16C/60 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity............................................ ROM (See Figure 1.4. ROM Expansion)
RAM 10K bytes
• Shortest instruction execution time................ 100ns (f(XIN)=10MHz)
• Supply voltage ............................................... 4.0 to 5.5V (f(XIN)=10MHz)
2.7 to 5.5V (f(XIN)=7MHz with software one-wait)
• Low power consumption ................................ 18mW ( f(XIN)=7MHz, with software one-wait, Vcc = 3V)
• Interrupts........................................................ 17 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer................................ 5 timers + 3 timers
• Serial I/O (UART or clock synchronous)........ 2 channels
• DMAC ............................................................ 2 channels (trigger: 15 sources)
• A-D converter................................................. 10 bits X 8 channels
(Expandable up to 10 channels)
• D-A converter................................................. 8 bits X 2 channels
• CRC calculation circuit................................... 1 circuit
• Watchdog timer.............................................. 15 bits
• Programmable I/O ......................................... 87 lines
_______
• Input port........................................................ 1 line (P85 shared with NMI pin)
• Memory expansion ........................................ Available (to a maximum of 1M bytes)
• Chip select output .......................................... 4 lines
• Clock generating circuit ................................. 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... 13
Reset.............................................................16
Processor Mode ............................................ 20
Clock Generating Circuit ............................... 30
Protection ......................................................37
Interrupts ....................................................... 38
Watchdog Timer............................................ 46
DMAC ...........................................................48
Timer .............................................................55
Serial I/O ....................................................... 72
A-D Converter ...............................................86
D-A Converter ...............................................96
CRC Calculation Circuit ................................ 97
Programmable I/O Ports ...............................98
Electrical Characteristics.............................106
1
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figures 1.1 and 1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P0
P0
P0
P0
P0
P0
P0
P0
7
6
5
4
3
2
1
0
/D
/D
/D
/D
/D
/D
/D
/D
7
6
5
4
3
2
1
0
P4
P4
P4
P4
P5
P5
4
5
6
7
/CS0
/CS1
/CS2
/CS3
81
82
83
84
85
86
87
88
89
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
0/WRL/WR
1
/WRH/BHE
P52/RD
P5
3
/BCLK
/HLDA
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
6
5
/KI3
/KI
/KI
P5
4
2
90
91
92
P55/HOLD
P5
M30600M8-XXXFP
1
0
6
/ALE
P104/AN4/KI
P5
7
/RDY/CLKOUT
P10
P10
P10
3
2
1
/AN
/AN
/AN
3
2
1
93
94
95
96
97
98
99
100
P6
P6
P6
P63/TXD0
P64/CTS
P6
P6
P67/TXD1
0/CTS
0
0
0
/RTS
0
1
/CLK
/RxD
2
AVSS
P10
0/AN0
1
/RTS
1/CTS0/CLKS1
V
REF
5
/CLK
/RxD
1
1
AVcc
7/ADTRG
6
P9
Package: 100P6S-A
Figure 1.1. Pin configuration (top view)
2
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (top view)
P1
P1
P1
P0
P0
P0
2
/D10
/D
/D
/D
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4
P4
P4
P4
P4
P4
P5
P5
2
3
4
5
6
7
0
1
/A18
/A19
1
9
0
8
/CS0
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
7
7
6
/D
6
5
/D
5
P0
P0
4
3
/D
/D
4
3
P0
P0
2
1
/D
/D
2
1
P5
2
P53
P54
P55
P56
/BCLK
P0
0
/D
/KI
/KI
/KI
/AN4/KI
0
/HLDA
/HOLD
/ALE
P10
P10
P10
7
/AN
7
3
6
/AN
/AN
6
2
M30600M8-XXXGP
5
5
1
P57/RDY/CLKOUT
P6
P6
P6
P6
0
/CTS
/CLK
/RxD
0
0
0
/RTS0
P10
4
0
1
2
3
P10
3
/AN
3
2
1
P10
2
/AN
/AN
/TXD0
P10
1
P64/CTS1/RTS1/CTS0/CLKS1
AVSS
/AN
P6
P6
P6
P7
P7
P7
5
6
7
/CLK
/RxD
/TXD1
/TA0OUT
/TA0IN
/TA1OUT
1
P10
0
0
1
V
REF
AVcc
/ADTRG
/ANEX1
/ANEX0
0
1
2
P9
P9
P9
7
6
5
Package: 100P6D-A
100P6Q-A
Figure 1.2. Pin configuration (top view)
3
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.3 is a block diagram of the M16C/60 group.
Block diagram of the M16C/60 group
8
8
Port P2
8
8
8
8
8
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer
System clock generator
IN-XOUT
A-D converter
(10 bits
X 8 channels
X
Expandable up to 10 channels)
X
CIN-XCOUT
Timer TA0 (16 bit)
Timer TA1 (16 bit)
Timer TA2 (16 bit)
Timer TA3 (16 bit)
Timer TA4 (16 bit)
Timer TB0 (16 bit)
Timer TB1 (16 bit)
Timer TB2 (16 bits)
UART/clock synchronous SO
(8 bits X 2 channels )
CRC arithmetic circuit (CCIT)
(Polynomial : X16+X12+X5+1)
M16C/60 series16-bit CPU core
Memory
ROM
Registers
Stack pointer
Watchdog timer
(15 bits)
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
ISP
USP
Vector table
INTB
DMAC
(2 channels)
RAM
10K bytes
D-A converter
Multiplier
(8 bits X 2 channels)
SB
Figure 1.3. Block diagram of M16C/60 group
4
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1 is a performance outline of M16C/60 group.
Table 1.1. Outline performance of M16C/60 group
Item
Performance
Number of basic instructions
91 instructions
100ns(f(XIN)=10MHz)
Shortest instruction execution time
Memory
ROM
(See Figure 1.4. ROM expansion)
10K bytes
capacity
RAM
I/O port
P0 to P10 (except P85)
P85
8 bits X 10, 7 bits X 1
1 bit X 1
Input port
Multifunction
timer
TA0,TA1,TA2,TA3,TA4
TB0,TB1,TB2
UART0,UART1
16 bits X 5
16 bits X 3
Serial I/O
A-D converter
D-A converter
DMAC
(UART or clock synchronous) X 2
10 bits X 8 channels (expandable up to 10 channels)
8 bits X 2
2 channels (trigger: 15 factors)
16
12
5
CRC calculation circuit
Watchdog timer
1 circuit (Generator polynomial: X + X + X + 1)
15 bits X 1 (with prescaler)
Interrupt
17 internal and 5 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
4.0 to 5.5V (f(XIN ) = 10MHz)
Clock generating circuit
Supply voltage
2.7 to 5.5V(f(XIN) = 7MHz with software one-wait)
18mW (f(XIN) = 7MHz with software one-wait,Vcc=3V)
5V
Power consumption
I/O
I/O withstand voltage
Output current
characteristics
Memory expansion
5mA
Available (to a maximum of 1M bytes)
o
Operating ambient temperature
Device configuration
Package
– 40 to 85 C
CMOS silicon gate
100-pin plastic mold QFP
5
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M16C/60 group:
(1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version
(2) ROM capacity
(3) Package
100P6S-A
: Plastic molded QFP (mask ROM version and one-time PROM version)
100P6D-A/100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version)
100D0
: Ceramic LCC (EPROM version)
ROM
Size(Byte)
External
ROM
M30600SFP / GP
M30600M8-XXXFP / GP M30600E8-XXXFP / GP
M30600E8FS
64K
32K
Mask ROM version
One-time PROM version
EPROM version
External ROM version
Figure 1.4. ROM expansion
The M16C/60 group products currently supported are listed in Table 1.2.
Table 1.2. M16C/60 group
Feb. 1997
RAM Capacity
10K bytes
10K bytes
10K bytes
10K bytes
10K bytes
10K bytes
10K bytes
10K bytes
10K bytes
ROM Capacity
64K bytes
64K bytes
64K bytes
64K bytes
64K bytes
64K bytes
64K bytes
Package Type
100P6S-A
Remarks
M30600M8-XXXFP
M30600M8-XXXGP
M30600E8-XXXFP
M30600E8-XXXGP
M30600E8FP
Mask ROM version
100P6D-A/100P6Q-A
100P6S-A
Mask ROM version
One-time PROM version
One-time PROM version
One-time PROM version (blank)
One-time PROM version (blank)
EPROM version
100P6D-A/100P6Q-A
100P6S-A
M30600E8GP
100P6D-A/100P6Q-A
100D0
M30600E8FS
M30600SFP
100P6S-A
External ROM version
External ROM version
M30600SGP
100P6D-A/100P6Q-A
6
Mitsubishi microcomputers
M16C / 60 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Type No. M30600 M 8 - XXX FP
Package type:
FP : Package 100P6S-A
GP :
FS :
100P6D-A/100P6Q-A
100D0
ROM No.
Omitted for blank one-time PROM version
and EPROM version
ROM capacity:
1 : 8K bytes
2 : 16K bytes
3 : 24K bytes
4 : 32K bytes
5 : 40K bytes
6 : 48K bytes
7 : 56K bytes
8 : 64K bytes
Memory type:
M : Mask ROM version
E : EPROM or one-time PROM version
S : External ROM version
F : Flash ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/60 Group
M16C Family
Figure 1.5. Type No., memory size, and package
7
Mitsubishi microcomputers
M16C / 60 Group
Pin Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin name
Signal name
I/O type
Function
Power supply
input
VCC, VSS
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
CNVSS
RESET
CNVSS
Input
This pin switches between processor modes. Connect it to the VSS pin
when operating in single-chip or memory expansion mode. Connect it
to the VCC pin when in microprocessor mode.
Reset input
Input
A “L” on this input resets the microcomputer.
X
IN
OUT
Clock input
Input
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
X
Clock output
Output
XOUT pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
BYTE
External data Input
bus width
select input
operating in single-chip mode, connect this pin to VSS
.
AVCC
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS
.
V
REF
Input
Reference
voltage input
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
P00
to P0
7
I/O port P0
Input/output
D
0
to D
7
Input/output When set as a separate bus, these pins input and output data (D
Input/output This is an 8-bit I/O port equivalent to P0.
0–D7).
P1
0
to P1
7
I/O port P1
I/O port P2
D
8
to D15
to P2
Input/output When set as a separate bus, these pins input and output data (D
8–D15).
P2
0
7
Input/output This is an 8-bit I/O port equivalent to P0.
A
0
to A7
Output
These pins output 8 low-order address bits (A0–A7).
Input/output If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D –D ) and output 8 low-order address bits
(A –A ) separated in time by multiplexing.
A
0
/D
0
to
0
7
A7
/D
7
6
0
7
A
0
,
/D
Output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D –D ) and output address (A –A ) separated
in time by multiplexing. They also output address (A ).
A
1
0
to
0
6
1
7
Input/output
A7
/D
0
P3
0
to P3
to A15
/D
7
I/O port P3
I/O port P4
Input/output This is an 8-bit I/O port equivalent to P0.
A
8
Output
These pins output 8 middle-order address bits (A8–A15).
Input/output If the external bus is set as a 16-bit wide multiplexed bus, these pins
A
8
7,
Output
input and output data (D
7) and output address (A
8) separated in time
–A15).
A9 to A15
by multiplexing. They also output address (A
9
P40
to P4
7
Input/output This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A16–A19 are 4 high-
order address bits.
CS
A
0
to CS
3,
16 to A19
8
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
P5 to P5
Signal name
I/O type
Function
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
0
7
I/O port P5
Input/output
Output
Output
Output
Output
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
HOLD,
ALE,
RDY
Output
Input
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state. BCLK outputs
a clock with the same cycle as the internal clock
.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
P6
0
to P6
7
I/O port P6
I/O port P7
I/O port P8
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as timer A0–A3 I/O pins as selected by software.
P70
to P7
7
P8
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8 and P8 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
pin) and P8 (XCIN pin). P8 is an input-only port that also functions
0 to P84, P86, and P87 are I/O ports with the same functions as P0.
P8
P8
0
6
to P8
4
,
Input/output
Input/output
,
,
6
7
P87
Input/output
Input
6
(XCOUT
P85
I/O port P85
7
5
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
P9
0
to P9
7
I/O port P9
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as Timer B0–B2 input pins, D-A converter output pins, A-D converter’s
extended input pins, or A-D trigger input pins as selected by software.
P10
0
to P10
7
I/O port P10
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P10
input pins for the key input interrupt function.
4–P107 also function as
9
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/60 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.6 is a memory map of the M16C/60 group. The address space extends the 1M bytes from address
0000016 to FFFFF16. From FFFFF16 down is ROM. (In the M30600M8-XXXFP, there is 64K bytes of
_______
internal ROM from F000016 to FFFFF16.) The vector table for fixed interrupts such as the reset and NMI are
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
10K bytes of internal RAM is mapped to the space from 0040016 to 02BFF16. In addition to storing data, the
RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode, the spaces between 02C0016 and 03FFF16, and between D000016 and
EFFFF16 are reserved and cannot be used. Likewise, the space between 02C0016 and 03FFF16 is re-
served when in microprocessor mode.
0000016
SFR area
For details, see
Figures 1.7 and 1.8
FFE0016
0040016
Internal RAM area
10K bytes
Special page
vector table
02C0016
0400016
Internal reserved
area (Note1)
FFFDC16
Undefined instruction
External area
Overflow
BRK instruction
Address match
Single step
Internal reserved
area (Note 2)
D000016
Address XXXXX16
F000016
Type No.
Watchdog timer
XXXXX16
DBC
NMI
Reset
Internal ROM area
M30600M8/E8
FFFFF16
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: During memory expansion mode, can not be used.
Figure 1.6. Memory map
10
Mitsubishi microcomputers
M16C / 60 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
002016
002116 DMA0 source pointer (SAR0)
002216
002316
002416
DMA0 destination pointer (DAR0)
002516
002616
002716
002816
DMA0 transfer counter (TCR0)
002916
002A16
002B16
002C16
DMA0 control register (DM0CON)
002D16
002E16
002F16
003016
DMA1 source pointer (SAR1)
003116
003216
003316
003416
DMA1 destination pointer (DAR1)
003516
003616
003716
003816
DMA1 transfer counter (TCR1)
003916
003A16
003B16
003C16
DMA1 control register (DM1CON)
003D16
003E16
003F16
Figure 1.7. Location of peripheral unit control registers
11
Mitsubishi microcomputers
M16C / 60 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Count start flag (TABSR)
A-D register 0 (AD0)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer A3 (TA3)
Timer A4 (TA4)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
D-A register 1 (DA1)
D-A control register (DACON)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
CRC data register (CRCD)
CRC input register (CRCIN)
Figure 1.8. Location of peripheral unit control registers
12
Mitsubishi microcomputers
M16C / 60 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0 (Note)
R1 (Note)
R2 (Note)
R3 (Note)
A0 (Note)
A1 (Note)
FB (Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I
O B
S
Z
D
C
Note: These registers consist of two register banks.
Figure 1.9. Configuration of central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can be
used as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
13
Mitsubishi microcomputers
M16C / 60 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows a configu-
ration of the flag register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
14
Mitsubishi microcomputers
M16C / 60 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag Register (FLG)
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.10. Configuration of flag register (FLG)
15
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2 VCC max.) for at least 2µs. When the reset pin level is then returned to the “H” level
while main clock is stable, the reset status is cancelled and program execution resumes from the address
in the reset vector table.
Figure 1.11 shows an example reset circuit. Figure 1.12 shows the reset sequence.
5V
4.0V
VCC
0V
VCC
5V
RESET
RESET
0.8V
0V
Example when f(XIN) = 10MHz and VCC = 5V.
Figure 1.11. Example reset circuit
X
IN
More than 20 cycles are needed
BCLK 24 cycles
Microprocessor
mode BYTE = “H”
RESET
BCLK
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
Address
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
CS0
Single-chip
mode
Content of reset vector
FFFFC16
FFFFE16
Address
Figure 1.12. Reset sequence
18
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.3 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.13 shows the
internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.3. Pin status when RESET pin level is “L”
Status
CNVSS = VCC
Pin Name
CNVSS = VSS
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
P1
Data input (floating)
Input port (floating)
P2, P3, P4
0
to P4
3
Address output (undefined)
Address output (undefined)
P44
CS0 output (“H” level is output) CS0 output (“H” level is output)
Input port (floating) Input port (floating)
WR output (“H” level is output) WR output (“H” level is output)
BHE output (undefined) BHE output (undefined)
RD output (“H” level is output) RD output (“H” level is output)
BCLK output
BCLK output
P4
5
0
to P47
P5
P5
P5
P5
1
2
3
HLDA output (The output value HLDA output (The output value
P5
4
Input port (floating)
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P5
P5
P5
5
6
7
Input port (floating)
Input port (floating)
Input port (floating)
HOLD input (floating)
HOLD input (floating)
ALE output (“L” level is output) ALE output (“L” level is output)
RDY input (floating)
Input port (floating)
RDY input (floating)
Input port (floating)
P6, P7, P8
0 to P84,
Input port (floating)
P8 , P8 , P9, P10
6
7
19
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(42)Timer B0 mode register
(039B16)···
(039C16)···
(039D16)···
(03A016)···
(1) Processor mode register 0 (Note) (000416)···
0016
0
0
0
0
0
0
?
?
?
0
0
0
0
0
0
0
0
0
0
0
(43)Timer B1 mode register
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
(000516)···
(000616)···
(000716)···
(000816)···
(000916)···
(000A16)···
(000F16)···
0
0
0
0
(44)Timer B2 mode register
0
1
0
0
1
0
0
(45)UART0 transmit/receive mode register
0016
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
?
0
1
0
0
?
(46)UART0 transmit/receive control register 0 (03A416)···
(47)UART0 transmit/receive control register 1 (03A516)···
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
(6) Address match interrupt enable
register
(7) Protect register
0016
(48)UART1 transmit/receive mode register
(03A816)···
0
?
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
(49)UART1 transmit/receive control register 0 (03AC16)···
(50)UART1 transmit/receive control register 1 (03AD16)···
(51)UART transmit/receive control register 2 (03B016)···
(8) Watchdog timer control register
0
0
0
?
?
0016
0016
0
(9) Address match interrupt register 0 (001016)···
(001116)···
0016
0016
(001216)···
(10)Address match interrupt register 1 (001416)···
(001516)···
0
0
0
(52)DMA0 cause select register
(53)DMA1 cause select register
(54)A-D control register2
(03B816)···
(03BA16)···
(03D416)···
(03D616)···
(03D716)···
(03DC16)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03F216)···
(03F316)···
(03F616)···
(03FC16)···
(03FD16)···
(03FE16)···
···
0016
0016
0
0
?
0
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(001616)···
0
0
0
0
0
?
?
(55)A-D control register 0
0016
0016
(11)DMA0 control register
(002C16)···
(003C16)···
(004B16)···
(004C16)···
(004D16)···
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
(56)A-D control register 1
(12)DMA1 control register
(57)D-A control register
(13)DMA0 interrupt control register
(14)DMA1 interrupt control register
(15)Key input interrupt control register
0016
0016
0016
(58)Port P0 direction register
(59)Port P1 direction register
(60)Port P2 direction register
(61)Port P3 direction register
(62)Port P4 direction register
(63)Port P5 direction register
(64)Port P6 direction register
(65)Port P7 direction register
(66)Port P8 direction register
(67)Port P9 direction register
(68)Port P10 direction register
(69)Pull-up control register 0
(70)Pull-up control register 1
(71)Pull-up control register 2
(72)Data registers (R0/R1/R2/R3)
(73)Address registers (A0/A1)
(74)Frame base register (FB)
(75)Interrupt table register (INTB)
(76)User stack pointer (USP)
(77)Interrupt stack pointer (ISP)
(78)Static base register (SB)
(79)Flag register (FLG)
(16)A-D conversion interrupt control register (004E16)···
(17)UART0 transmit interrupt control register (005116)···
(18)UART0 receive interrupt control register (005216)···
(19)UART1 transmit interrupt control register (005316)···
(20)UART1 receive interrupt control register (005416)···
(21)Timer A0 interrupt control register (005516)···
(22)Timer A1 interrupt control register (005616)···
(23)Timer A2 interrupt control register (005716)···
(24)Timer A3 interrupt control register (005816)···
(25)Timer A4 interrupt control register (005916)···
(26)Timer B0 interrupt control register (005A16)···
(27)Timer B1 interrupt control register (005B16)···
(28)Timer B2 interrupt control register (005C16)···
0016
0016
0016
0016
0016
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0016
0016
0016
0016
0016
000016
000016
000016
···
(29)INT0 interrupt control register
(30)INT1 interrupt control register
(31)INT2 interrupt control register
(32)Count start flag
(005D16)···
(005E16)···
(005F16)···
(038016)···
(038116)···
(038216)···
(038316)···
(038416)···
(039616)···
(039716)···
(039816)···
(039916)···
(039A16)···
···
0
0
0
0
0
0
···
0000016
000016
000016
000016
000016
···
?
0
0
0
0016
···
0
0
(33)Clock prescaler reset flag
(34)One-shot start flag
···
0
0 0
0
0
0
···
(35)Trigger select flag
0016
0016
0016
(36)Up-down flag
The content of other registers and RAM is undefined when the microcomputer is
reset. The initial values must therefore be set.
x : Nothing is mapped to this bit
(37)Timer A0 mode register
(38)Timer A1 mode register
(39)Timer A2 mode register
(40)Timer A3 mode register
(41)Timer A4 mode register
? : Undefined
0016
0016
0016
Note : When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
0016
Figure 1.13. Device's internal status after a reset is cleared
20
Mitsubishi microcomputers
M16C / 60 Group
Software Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved. Figure 1.14 shows a configuration of processor mode register 0 and 1.
Processor mode register 0 (Note 1)
Symbol
PM0
Address
000416
When reset
0016 (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
PM00
R W
Bit name
Function
b1 b0
Processor mode bit
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
PM01
PM02
1 1: Microprocessor mode
R/W mode select bit
Software reset bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM03
PM04
b5 b4
Multiplexed bus space
select bit
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note 4)
PM05
PM06
0 : Address output
1 : Port function
Port P40 to P43 function
select bit (Note 3)
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
BCLK output disable bit
PM07
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to
this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is
0316. (PM00 and PM01 are both set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected,
address bus range is 256 bytes in each chip select.
Processor mode register 1 (Note)
Symbol
PM1
Address
000516
When reset
0XXXXXX0
b7 b6 b5 b4 b3 b2 b1 b0
2
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
0 : No wait state
1 : Wait state inserted
PM17
Wait bit
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to
this register.
Figure 1.14. Configuration of processor mode register 0 and 1
19
Mitsubishi microcomputers
M16C / 60 Group
Processor Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.15 shows the memory maps applicable for each of the modes.
20
Mitsubishi microcomputers
M16C / 60 Group
Processor Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Single-chip mode
SFR area
Memory expansion mode
SFR area
Microprocessor mode
SFR area
0000016
0040016
Internal RAM
area
Internal RAM
area
Internal RAM
area
02C0016
0400016
Internally reserved
area
Internally reserved
area
Inhibited
External area
External area
D000016
F000016
Internally reserved
area
Internal ROM
area
Internal ROM
area
FFFFF16
External area : Accessing this area allows the user to access a device connected
externally to the microcomputer.
Figure 1.15. Memory maps in each processor mode
21
Mitsubishi microcomputers
M16C / 60 Group
Bus Settings
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 1.4 shows the factors used to change the bus settings.
Table 1.4. Factors for switching bus settings
Bus setting
Switching factor
Bit 6 of processor mode register 0
BYTE pin
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.)
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external de-
vices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before accessing the multiplex bus, always set the CSi wait bit of the chip select control register to “0”.
22
Mitsubishi microcomputers
M16C / 60 Group
Bus Settings
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.5. Pin functions for each processor mode
Single-chip
Memory
expansion mode
Processor mode
Memory expansion mode/microprocessor modes
mode
Multiplexed bus and
separate bus
Multiplexed
bus (Note 1)
separate bus
“00”
External bus type
Multiplexed bus
space select bit
“01”, “10”
“11” (Note 2)
8 bits
= “H”
16 bits
= “L”
Data bus width
BYTE pin level
8 bits
= “H”
16 bits
= “L”
8 bits
= “H”
P0
0
to P0
7
I/O port
Data bus
I/O port
Data bus
Data bus
Data bus
I/O port
I/O port
P1
P2
0
0
to P1
7
I/O port
I/O port
Data bus
I/O port
Data bus
Address bus
/data bus (Note 3)
Address bus
Address bus
Address bus
Address bus
/data bus
P2
1
0
to P2
7
I/O port
I/O port
Address bus
/data bus (Note 3) /data bus (Note 3)
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
/data bus
P3
Address bus
Address bus
I/O port
/data bus (Note 3)
P3
1
0
to P3
to P4
7
I/O port
I/O port
Address bus
I/O port
Address bus
I/O port
Address bus
I/O port
Address bus
I/O port
I/O port
I/O port
P4
3
Port P4
0
to P43
function select bit = 1
P40
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Port P4
0
to P43
function select bit = 0
P4
4
to P4
7
I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
P50
to P5
3
P5
P5
P5
P5
4
5
6
7
I/O port
I/O port
I/O port
I/O port
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
RDY
RDY
RDY
RDY
RDY
Note 1: In memory expansion mode, do not select a 16-bit multiplex bus.
Note 2: In microprocessor mode, muitiplexed bus for the entire space cannot be selected.
In memory expansion mode, when muitiplexed bus for the entire space is selected, address bus range is 256 bytes
in each chip select.
Note 3: Address bus when in separate bus mode.
23
Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed.
Also, when a change is made from single-chip mode to memory expansion mode, the value of the
address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______
_______
_______
_______
celled. CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resis-
tors are required. Figure 1.16 shows the configuration of the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.6
shows the external memory areas specified using the chip select signal.
Table 1.6. External areas specified by the chip select signals
Chip select
Specified address range
Memory expansion mode
Microprocessor mode
9000016 to FFFFF16 (448K)
1000016 to 8FFFF16 (512K)
_______
CS0
9000016 to CFFFF16(256K)
1000016 to 8FFFF16(512K)
0800016 to 0FFFF16 (32K)
0400016 to 07FFF16 (16K)
_______
CS1
_______
CS2
0800016 to 0FFFF16
0400016 to 07FFF16
(32K)
(16K)
_______
CS3
Chip select control register
Symbol
CSR
Address
000816
When reset
0116
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
Bit symbol
R W
CS0
CS1
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
CS2
CS3
CS0W
CS1W
0 : Wait state inserted
1 : No wait state
CS1 wait bit
CS2 wait bit
CS3 wait bit
CS2W
CS3W
Figure 1.16. Configuration of chip select control register
24
Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________
______
_____ ________
_________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____ ______
_______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 7 and 8 show the operation of these signals.
_____ ______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________
_________
Table 1.7. Operation of RD, WRL, and WRH signals
Data bus width
Status of external data bus
RD
L
WRL
WRH
H
L
H
H
L
Read data
H
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
16-bit
(BYTE = “L”)
H
H
L
H
L
_____ ______
________
Table 1.8. Operation of RD, WR, and BHE signals
Data bus width
Status of external data bus
RD
WR
BHE
A0
H
L
L
H
L
L
H
H
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
L
H
L
H
L
16-bit
(BYTE = “L”)
H
L
H
L
H
L
L
L
H
L
L
L
H
L
Not used
Not used
H/L
H/L
8-bit
(BYTE = “H”)
H
Read 1 byte of data
25
Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H”
ALE
/A
When BYTE pin = “L”
ALE
Address
Data (Note 1)
D0
0 to D7/A7
A0
Address
Address
Data (Note 1)
D0/A1 to D7/A8
A8 to A19
Address (Note 2)
A9 to A19
Address
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.17. ALE signal and address/data bus
(5) Ready signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
________
Figure 1.18, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter
________
the ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table 1.9
_____
shows the microcomputer status in the ready state. Figure 1.18 shows an example of the RD signal being
________
extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is applied.
Table 1.9. Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
___
_____
R/W signal, address bus, data bus, CS
Maintain status when ready signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
Note: The ready signal cannot be received immediately prior to a software wait.
BCLK
RD
:
Wait using ready function
Wait using software
CSi
(i = 0 to 3)
:
RDY
tsu(RDY — BCLK)
_____
________
Figure 1.18. Example of RD signal extended by RDY signal
26
Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.10
shows the microcomputer status in the hold state.
Table 1.10. Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____ _______
R/W signal, address bus, data bus, CS, BHE
Floating
Floating
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Maintains status when hold signal is received
Undefined
ALE signal
__________
HLDA
Output “L”
Internal peripheral circuits
ON (but watchdog timer stops)
(7) BCLK output
The output of the internal clock can be selected using bit 7 of the processor mode register 0 (address
000416) (Note). The output is floating when bit 7 is set to “1”.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(8) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, bits 4 to 7 of the chip select control register are invalid and a
wait is applied to all external memory areas (two or three BCLK cycles). When VCC is in the range 2.7V to
4.0V, set the wait bit to “1”. However, this is not necessary if the oscillation frequency is less than 3MHz.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to
access the external memory area.
Table 1.11 shows the software wait and bus cycles. Figure 1.19 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.11. Software waits and bus cycles
Bits 4 to 7 of chip select
Bus cycle
2 BCLK cycles
Area
SFR
Bus status
Wait bit
control register
Invalid
0
Invalid
Invalid
1 BCLK cycle
Internal
ROM/RAM
1
0
0
Invalid
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Separate bus
Separate bus
Separate bus
1
0
External
memory
area
1
0
1
0 (Note)
0 (Note)
0 (Note)
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
Multiplex bus
Multiplex bus
Note: Always set to “0”.
28
Mitsubishi microcomputers
M16C / 60 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
< Separate bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Data bus
Input
Output
Address bus
Chip select
Address
Address
< Separate bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Output
Input
Data bus
Address bus
Address
Address
Chip select
< Multiplexed bus >
Bus cycle
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Address
Address
Input
Address
Address
Data output
Data bus
Chip select
Figure 1.19. Typical bus timings using software wait
29
Mitsubishi microcomputers
M16C / 60 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.12. Main clock and sub clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub clock generating circuit
• CPU’s operating clock source
• Timer A/B’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.20 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 1.21 shows some examples of sub
clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived
clock for input. Circuit constants in Figures 1.20 and 1.21 vary with each oscillator used. Use the values
recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 1.20. Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
C
CIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Figure 1.21. Examples of sub clock
30
Mitsubishi microcomputers
M16C / 60 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Control
Figure 1.22 shows a block diagram of the clock generating circuit.
X
CI
N
XCOUT
fC32
1/32
f
1
CM04
fAD
fC
f
8
Sub clock
CM10 “1”
Write signal
f
32
S
R
Q
X
I
XOUT
b
c
CM07=0
a
d
Divider
RESET
Software reset
NMI
Internal
clock
f
C
Main clock
CM02
CM07=1
CM0
5
Interrupt request
level judgment
output
S Q
R
WAIT instruction
c
b
1/
2
1/
2
1/
2
1/
2
1/
2
a
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
CM06=0
CM17,CM16=00
Details of divider
Figure 1.22. Clock generating circuit
31
Mitsubishi microcomputers
M16C / 60 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describe the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the internal clock . The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
Stopping the clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit defaults to “1” when shifting to stop mode
and after a reset.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be
selected as the internal clock
by using the system clock select bit (bit 7 at address 000616). However,
be sure that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) Internal clock
The internal clock
is the clock that drives the CPU, and is either the main clock or fc or is derived by
dividing the main clock by 2, 4, 8, or 16. The internal clock is derived by dividing the main clock by 8
after a reset.
When shiffing to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”.
(4) Peripheral function clock
• f1, f8, f32
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
• fAD
This clock has the same frequency as the main clock and is used for A-D conversion.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It is used for internal clock and for the watchdog
timer.
32
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.23 shows the configuration of system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
0 0 : I/O port P5
7
0 1 : f
1 0 : f
C
output
output
8
CM01
CM02
CM03
1 1 : f32 output
0 : Do not stop f
1 : Stop f , f , f32 in wait mode
WAIT peripheral function
clock stop bit
1, f8, f32 in wait mode
1
8
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3) (Note 4)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 2)
1 : Division by 8 mode
System clock select bit
(Note 5)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode.
Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop
mode and operating with XIN, set this bit to “0”. When main clock oscillation is operating by
itself, set system clock select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input
is acceptable.
Note 5: Set port Xc select bit (CM04) to “1” before writing to this bit. The both bits can not be
written at the same time.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0 0 0
Bit symbol
CM10
Bit name
All clock stop control bit
Function
R W
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Always set to “0”
Always set to “0”
Always set to “0”
Always set to “0”
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
CM15
select bit (Note 2)
b7 b6
Main clock division
select bit1 (Note 3)
0 0 : No division mode
CM16
CM17
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shiffing to stop mode.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”,
division mode is fixed at 8.
Figure 1.23. Configuration of system clock control registers 0 and 1
33
Mitsubishi microcomputers
M16C / 60 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation of internal clock , f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions
such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate
provided that the event counter mode is set to an external pulse, and UART0 and UART1 functions pro-
vided an external clock is selected. Table 1.13 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled.
When shifting to stop mode, the main clock division select bit 0 (bit 6 at 000616) is set to “1”.
Table 1.13. Port status during stop mode
Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3
Retains status before stop mode
_____ ______ ________ ________ _________
RD, WR, BHE, WRL, WRH
“H”
“H”
“H”
__________
HLDA, BCLK
ALE
Port
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode “H”
CLKOUT
When fc selected
When f8, f32 selected
Valid only in single-chip mode Retains status before stop mode
34
Mitsubishi microcomputers
M16C / 60 Group
Wait Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
When a WAIT instruction is executed, the internal clock
stops and the microcomputer enters the wait
and watchdog timer stop. Writing “1” to
mode. In this mode, oscillation continues but the internal clock
the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied
to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.14 shows the status
of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as internal clock
tion was executed.
the clock that had been selected when the WAIT instruc-
Table 1.14. Port status during wait mode
Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
Address bus, data bus,CS0 to CS3
Retains status before wait mode
_____ ______ ________ ________ _________
RD,WR,BHE,WRL,WRH
“H”
__________
HLDA,BCLK
ALE
“H”
“H”
Port
Retains status before wait mode
Retains status before wait mode
CLKOUT
When fC selected
Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is main
tained.
35
Mitsubishi microcomputers
M16C / 60 Group
Status Transition Of Internal Clock
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition Of Internal Clock
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
internal clock . Table 1.15 shows the operating modes corresponding to the settings of system clock
control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division select
bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal clock
:
(1) Division by 2 mode
The main clock is divided by 2 to obtain the internal clock
.
.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the internal clock
(3) Division by 8 mode
The main clock is divided by 8 to obtain the internal clock . Note that oscillation of the main clock must
have stabilized before transferring from this mode to another mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the internal clock
.
(5) No-division mode
The main clock is used as internal clock
.
(6) Low-speed mode
fC is used as internal clock . Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the
sub clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the internal clock and the main clock is stopped.
Table 1.15. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of internal clock
Division by 2 mode
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
Division by 4 mode
Invalid
1
Invalid
1
1
0
Division by 8 mode
Division by 16 mode
No-division mode
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-speed mode
1
Low power dissipation mode
36
Mitsubishi microcomputers
M16C / 60 Group
Protection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.24 shows the configuration of the protect register. The values
in the processor mode register 0 (addresss 000416), processor mode register 1 (address 000516), system
clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P9
direction register (address 03F316) can only be changed when the respective bit in the protect register is set
to “1”. Therefore, important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
2
Bit symbol
PRC0
Bit name
Function
R W
Enables writing to system clock
control registers 0 and 1 (addresses
0 : Write-inhibited
1 : Write-enabled
000616 and 000716
)
Enables writing to processor mode
registers 0 and 1 (addresses 000416
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
and 000516
)
Enables writing to port P9 direction 0 : Write-inhibited
1 : Write-enabled
register (address 03F316) (Note
)
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.24. Configuration of protect register
37
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Tables 1.16 and 1.17 show the interrupt sources and vector addresses. When an interrupt is received, the
program is executed from the address shown by the respective interrupt vector.
The vector addresses for the interrupts in Table 1.16 are fixed (interrupt vector addresses). These inter-
rupts are not affected by the interrupt enable flag (I flag) (non-maskable interrupts).
The vector table addresses for the interrupt in Table 1.17 are variable, being determined as relative to the
fixed address in the interrupt table register (INTB) (variable interrupt addresses). These interrupts can be
enabled or disabled using the interrupt enable flag (I flag) (maskable interrupts). 64 vectors can be set in
the interrupt table register (INTB). Any software interrupt Nos. 0 to 63 can be assigned to each vector. By
using the INT instruction to specify a software interrupt No., the program can be executed starting at the
address indicated by the respective vector. The BRK instruction interrupt has interrupt vectors in both the
fixed vector addresses and variable vector addresses. When the contents of FFFE416 to FFFE716 are all
“FF16”, the program is executed from the address shown in the BRK instruction interrupt vector in the
variable vector addresses.
Specify the starting address of the interrupt program in the interrupt vector. Figure 1.25 shows the format
for specifying the address.
Table 1.16. Interrupt factors (fixed interrupt vector addresses)
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Undefined instruction
Overflow
Interrupt on UND instruction
Interrupt on INTO instruction
BRK instruction
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Single step (Note)
Watchdog timer
________
DBC (Note)
Do not use
_______
_______
NMI
External interrupt by input to NMI pin
Reset
Note: Interrupts used for debugging purposes only.
MSB
LSB
Low address
Vector address + 0
Vector address + 1
Vector address + 2
Mid address
0 0 0 0
0 0 0 0
High address
0 0 0 0
V
ector address + 3
Figure 1.25. Format for specifying interrupt vector addresses
38
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.17. Interrupt causes (variable interrupt vector addresses)
Vector table address
Software interrupt number
Software interrupt number 0
Interrupt source
Remarks
Address (L) to address (H)
+0 to +3 (Note)
BRK instruction
Cannot be masked by I flag
Software interrupt number 11
+44 to +47 (Note)
DMA0
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
+48 to +51 (Note)
+52 to +55 (Note)
+56 to +59 (Note)
DMA1
Key input interrupt
A-D
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
+68 to +71 (Note)
+72 to +75 (Note)
+76 to +79 (Note)
+80 to +83 (Note)
+84 to +87 (Note)
+88 to +91 (Note)
+92 to +95 (Note)
+96 to +99 (Note)
+100 to +103 (Note)
+104 to +107 (Note)
+108 to +111 (Note)
+112 to +115 (Note)
+116 to +119 (Note)
+120 to +123 (Note)
+124 to +127 (Note)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
Software interrupt number 32
to
+128 to +131 (Note)
to
Software interrupt
Cannot be masked by I flag
Software interrupt number 63
+252 to +255 (Note)
Note: Address relative to address in interrupt table register (INTB).
39
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Interrupt control registers
Peripheral I/O interrupts have their own interrupt control registers. Table 1.18 shows the addresses of the
interrupt control registers. Figure 1.26 shows the configuration of the interrupt control registers.
The interrupt request bit is set by hardware to “0” when an interrupt request is received. The interrupt
request bit can also be set by software to “0”. (Do not set to “1”.)
________ _______
________
INT0, INT1, and INT2 are triggered by the edges of external inputs. The edge polarity is selected using the
polarity select bit. (Other interrupts are described elsewhere.)
An interrupt must first be enabled before it can be used to cancel stop mode.
Table 1.18. Addresses in interrupt control register
Interrupt control register
Symbol name Address
Interrupt control register
Symbol name Address
DMA0 interrupt control register
DM0IC
004B16 DMA1 interrupt control register
004D16 A-D interrupt control register
DM1IC
ADIC
004C16
004E16
005216
005416
005616
005816
005A16
005C16
005E16
Key input interrupt control register KUPIC
UART0 transmit interrupt control register
UART1 transmit interrupt control register
S0TIC
S1TIC
005116 UART0 receive interrupt control registe
r
S0RIC
S1RIC
005316 UART1 receive interrupt control register
Timer A0 interrupt control register TA0IC
Timer A2 interrupt control register TA2IC
Timer A4 interrupt control register TA4IC
005516 Timer A1 interrupt control register TA1IC
005716 Timer A3 interrupt control register TA3IC
005916 Timer B0 interrupt control register TB0IC
Timer B1 interrupt control register TB1IC
005B16 Timer B2 interrupt control register TB2IC
________
________
INT0 interrupt control register INT0IC
005D16 INT1 interrupt control register INT1IC
005F16
________
INT2 interrupt control register INT2IC
(2) Interrupt priority
The order of priority when two or more interrupts are generated simultaneously is determined by both
hardware and software.
_______
________
The interrupt priority levels determined by hardware are reset > NMI > DBC > wacthdog timer > peripheral
I/O interrupts > single-step > address matching interrupt.
The interrupt priority levels determined by software are as the interrupt priority levels are set in the inter-
rupt control registers.
Figure 1.27 shows the circuit that judges the interrupt priority level. When two or more interrupts are
generated simultaneously, this circuit selects the interrupt with the highest priority level. However, if the
interrupts have the same priority level, the interrupt is selected according to the priority set in the circuit.
The selected interrupt is accepted only when the priority level is higher than the processor interrupt
priority level (IPL) in the flag register (FLG) and the interrupt enable flag (I flag) is “1”. Note that the reset,
_______ ________
NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined in-
struction interrupts are generated regardless of the interrupt enable flag (I flag).
40
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt control register
Symbol
Address
When reset
DMiIC(i=0,1)
KUPIC
ADIC
SiTIC(i=0,1)
SiRIC(i=0,1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
004B16, 004C16
XXXXX000
2
2
2
2
2
2
2
004D16 XXXXX000
004E16 XXXXX000
005116,005316 XXXXX000
005216,005416 XXXXX000
005516 to 005916 XXXXX000
005A16 to 005C16 XXXXX000
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
(Note)
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: This bit can only be accessed for reset (= 0), but cannot be accesd
for set (= 1).
Symbol
Address
When reset
XX00X000
b7 b6 b5 b4 b3 b2 b1 b0
INTiIC(i=0 to 2) 005D16 to 005F16
2
0
R
W
Bit symbol
Bit name
Function
ILVL0
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
ILVL2
1 1 1 : Level 7
IR
0: Interrupt not requested
1: Interrupt requested
Interrupt request bit
Polarity select bit
(Note)
POL
0 : Selects falling ede
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: This bit can only be accessed for reset (= 0), but cannot be accesd
for set (= 1).
Figure 1.26. Configuration of interrupt control register
41
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
INT2
INT0
Timer B1
Timer A4
Timer A2
Priority of peripheral I/O interrupts
(if priority levels are same)
UART1 reception
UART0 reception
A-D conversion
DMA1
Timer A0
UART1 transmission
UART0 transmission
Key input interrupt
DMA0
Low
Processor interrupt priority level (IPL)
Interrupt
request
Interrupt enable flag (I flag)
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 1.27. Interrupt resolution circuit
42
Mitsubishi microcomputers
M16C / 60 Group
Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Flag changes
When an interrupt request is received, the stack pointer select flag (U flag) changes to “0” and the flag
register (FLG) and program counter (PC) are saved to the stack area indicated by the interrupt stack
pointer (ISP). Thereafter, the interrupt enable flag (I flag) and debug flag (D flag) change to “0” and the
processor interrupt priority level (IPL) at the flag register (FLG) is replaced by the priority level of the
received interrupt. However, when interrupt requests are received for software interrupt Nos. 32 to 63, the
flag register (FLG) and program counter (PC) are saved to the stack shown by the stack pointer select
flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change.
The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of
_______ ________
reset, NMI, DBC, watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined
instruction interrupts. Table 1.19 shows how the IPL changes when interrupt requests are received.
Table 1.19. Change of IPL state when interrupt requests are accepted
Interrupt
Change of IPL
Reset
Level 0 (“0002”) is set
Level 7 (“1112”) is set
_______
NMI
________
DBC
Does not change
Level 7 (“1112”) is set
Does not change
Does not change
Does not change
Watchdog timer
Single step
Address match
Software interrupt
43
Mitsubishi microcomputers
M16C / 60 Group
______
NMI Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Notes:
______
______
______
(1) When not intending to use the NMI function, be sure to connect the NMI pin to VCC. Because the NMI
interrupt is non-maskable, it cannot be disabled.
______
______
(2) When the NMI pin input is “L”, do not set the microcomputer in stop mode or wait mode. The NMI
interrupt is triggered by the falling edge, so the “L” level does not need to be maintained longer than
necessary.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.28 shows a block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Port P104-P107 pull-up
select bit
Pull-up
Key input interrupt control register
(address 004D16
)
transistor
Port P107 direction
register
Port P10
7
direction register
P10
7
/KI
3
2
Port P106 direction
register
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
P10
6
/KI
Pull-up
transistor
Port P10
register
5
direction
direction
P105/KI1
Port P10
4
Pull-up
transistor
register
P104/KI0
Figure 1.28. Block diagram of key input interrupt
44
Mitsubishi microcomputers
M16C / 60 Group
Address Match Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.29 shows a configuration of address match interrupt-related registers.
Address match interrupt enable register
Symbol
AIER
Address
000916
When reset
XXXXXX00
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
AIER0
Bit name
Function
R W
Address match interrup 0
enable bit
0: Interrupt disabled
1: Interrupt enabled
Address match interrupt 1 0: Interrupt disabled
enable bit
1: Interrupt enabled
AIER1
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
(b23)
b7
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
Nothing is assigned.
0000016 to FFFFF16
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Figure 1.29. Configuration of address match interrupt-related registers
45
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the internal clock using the prescaler.
A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is
selected for the internal clock , bit 7 of the watchdog timer control register (address 000F16) selects the
prescaler division ratio (by 16 or by 128). When XCIN is selected as the internal clock , the prescaler is set
for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Table 1.20
shows a periodic table for the watchdog timer.
Table 1.20. Watchdog timer periodic table (XIN = 10MHz, XCIN = 32kHz)
CM07
0
CM06
0
CM17
0
CM16
0
Internal clock
10MHz
WDC7
Period
0
Approx. 52.4ms (Note)
Approx. 419.2ms (Note)
Approx. 104.9ms (Note)
Approx. 838.8ms (Note)
Approx. 209.7ms (Note)
Approx. 1.68s (Note)
Approx. 838.8ms (Note)
Approx. 6.71s (Note)
Approx. 419.2ms (Note)
Approx. 3.35s (Note)
Approx. 2s (Note)
1
0
0
0
0
1
0
0
1
1
1
0
1
5MHz
2.5MHz
0.625MHz
1.25MHz
32kHz
0
1
0
0
1
0
1
0
1
Invalid Invalid
0
1
Invalid
Invalid Invalid
Invalid
Note: Error is generated by the prescaler.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.30 shows a block diagram of the watchdog timer. Figure 1.31 shows the configuration of the
watchdog timer-related registers.
Prescaler
"CM07=0"
"WDC7=0"
1/16
"CM07=0"
"WDC7=1"
Internal clock
HOLD
Watchdog timer
interrupt request
1/128
1/2
Watchdog timer
"CM07=1"
Write to the watchdog
timer start register
Set to
"7FFF16
(address 000E16
)
"
RESET
Figure 1.30. Block diagram of watchdog timer
46
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
00XXXXXX
0
0
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Must always be set to “0”
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of the value written.
”
Figure 1. 31. Configuration of watchdog timer control and start registers
47
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. Table 1.21 shows the DMAC specifications. Figure 1.33 shows a block
diagram of the DMAC. Figures 1.34 and 1.35 show the configuration of the registers used by the DMAC.
Table 1.21. DMAC specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
________ ________
________
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1)
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
8 bits or 16 bits
Transfer unit
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer
The DMA enable bit is cleared and transfer ends when an underflow
occurs in the transfer counter
• Repeat transfer
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is reloaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation timing When an underflow occurs in the transfer counter
DMA startup
• Single transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
• Repeat transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Transfer starts when the DMA is requested after an underflow occurs in the transfer counter
• When “0” is written to the DMA enable bit
DMA shutdown
• When, in simple transfer mode, an underflow occurs in the transfer counter
When DMA transfer starts, the value of whichever of the source or destination pointer
that is set up as the forward pointer is reloaded into the forward address pointer. The
value in the transfer counter reload register is reloaded into the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Forward address pointer and
reload timing for transfer
counter
Writing to register
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt.
48
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416
)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 002916, 002816
)
)
DMA0 transfer counter TCR0 (16)
(addresses 003616 to 003416
)
DMA1 forward address pointer (20) (Note)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.33. Block diagram of DMAC
49
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiSL(i=0,1)
Address
03B816,03BA16
When reset
0016
Bit symbol
DSEL0
Bit name
Function
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT0 / INT1
pin (Note)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
DSEL1
DSEL2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART1 transmit
1 1 0 1 : UART1 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Inhibited
DSEL3
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Software DMA request bit
DSR
Note: Address 03B816 is for INT0; address 03BA16 is for INT1.
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X00
2
Bit symbol
DMBIT
Bit name
Function
R
W
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMASL
DMAS
DMAE
0 : DMA not requested
1 : DMA requested
DMA request bit (Note 1)
DMA enable bit
(Note 2)
0 : Disabled
1 : Enabled
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 1.34. Configuration of DMAC register (1)
50
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Addre
When reset
002216 to 002016 Indeterminate
003216 to 003016 Indeterminate
Transfer count
R W
Function
specification
• Source pointer
Stores the source address
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
DMAi destination pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Addresse
002616 to 002416 Indeterminate
003616 to 003416 Indeterminate
When reset
Transfer count
R W
Function
specification
• Destination pointer
Stores the destination address
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Transfer counter
Set a value one less than the transfer count
000016 to FFFF16
Figure 1.35. Configuration of DMAC register (2)
51
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.36 shows an example of the transfer cycles for a source read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
1.36, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
52
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1 Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.36. Example of the transfer cycles for a source read
53
Mitsubishi microcomputers
M16C / 60 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.22 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.22. No. of DMAC transfer cycles
Single-chip mode
Memory expansion mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
(BYTE= “L”)
8-bit
Even
Odd
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
8-bit transfers
(DMBIT= “1”)
Even
Odd
—
—
1
—
—
1
(BYTE = “H”)
16-bit
Even
Odd
16-bit transfers
(DMBIT= “0”)
(BYTE = “L”)
8-bit
2
2
Even
Odd
—
—
—
—
(BYTE = “H”)
Coefficient j, k
Internal memory
External memory
Internal ROM/RAM Internal ROM/RAM SFR area Separate bus Separate bus
Multiplex
No wait
1
With wait
2
No wait
1
With wait
2
bus
3
2
54
Mitsubishi microcomputers
M16C / 60 Group
Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figure 1.37 shows a block diagram of timers.
Clock prescaler
1/32
Reset
X
IN
f
1
8
fC32
X
CIN
f
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
1/4
f
32
f1 f8 f32 fc32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A3
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A4
Noise
filter
TA4IN
TB0IN
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B0 interrupt
Timer B1 interrupt
Noise
filter
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB1IN
TB2IN
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B2 interrupt
Noise
filter
Timer B2
• Event counter mode
Figure 1.37. Block diagram of timer
55
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.38 shows a block diagram of timer A. Figures 1.39 to 1.41 show configuration of timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4)'s bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
•
Event counter mode: The timer counts pulses from an external source or a timer's over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
Data bus low-order bits
selection
• Timer
• One shot
• PWM
f
f
1
8
Low-order
8 bits
High-order
8 bits
f
32
• Timer
(gate function)
Reload register (16)
f
C32
• Event counter
Clock selection
Counter (16)
Polarity
selection
Up count/down count
TAiIN
Always down count except
in event counter mode
(i = 0 to 4)
Count start flag
(Address 038016
)
TAi
Addresses
TAj
TAk
Down count
Timer A0 038716 038616
Timer A1 038916 038816
Timer A4 Timer A1
Timer A0 Timer A2
TB2 overflow
External
trigger
Up/down flag
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
TAj overflow
(j = i - 1. Note, however, that j = 4 when i = 0)
(Address 038416
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Figure 1.38. Block diagram of timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit
Bit name
Function
l
TMOD0
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.39. Configuration of timer A-related registers (1)
56
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note)
Symbol
TA0
TA1
TA2
TA3
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
TA4
Values that can be set
Function
R W
• Timer mode
000016 to FFFF
Counts an internal count source
• Event counter mode
Counts pulses from an external source or timer overflow 000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
000016 to FFFE16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
Note: Read and write data is in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
0016
R W
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
038416
When reset
0016
Bit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
Bit name
Function
R W
Timer A0 up/down flag
0 : Down count
1 : Up count
Timer A1 up/down flag
Timer A2 up/down flag
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Timer A3 up/down flag
Timer A4 up/down flag
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA3P
TA4P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Timer A4 two-phase pulse
signal processing select bit
Figure 1.40. Configuration of timer A-related registers (2)
57
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
038216
When reset
00X00000
2
R W
Bit symbol
Bit name
Function
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
1: Timer start
When read, the value is “0”
Nothing is assigned.
This bit can neither be set nor reset. When read, the content is indeterminate.
b7 b6
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
038316
When reset
0016
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
R W
Bit symbol
Bit name
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.41. Configuration of timer A-related registers (3)
58
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.23.) Figure 1.42 shows
the configuration of the timer Ai mode register in timer mode.
Table 1.23. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Down count
•
When the timer underflows, reload register’s content is reloaded and the timer starts over again
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 4) 039616 to 039A16
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
Operation mode
select bit
0 0 : Timer mode
TMOD1
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR3
0 (Must always be fixed to “0” in timer mode)
b7 b6
0 0 : f
Count source select bit
TCK0
1
8
0 1 : f
1 0 : f32
1 1 : fC32
TCK1
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.42. Configuration of timer Ai mode register in timer mode
59
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.24 lists timer specifications when counting a single-phase external signal. Fig-
ure 1.43 shows the configuration of the timer Ai mode register in event counter mode.
Table 1.25 lists timer specifications when counting a two-phase external signal. Figure 1.44 shows the
configuration of the timer Ai mode register in event counter mode.
Table 1.24. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
Divide ratio
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, reload register content is reloaded
and the timer starts over again (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register’s content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TAiMR(i = 0, 1)
Address
039616, 039716
When reset
0016
0
0 1
Bit symbol
Bit name
Function
R W
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
Pulse output function
select bit
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be fixed to “0” in event counter mode)
Count operation type
0 : Reload type
TCK0
select bit
1 : Free-run type
TCK1
Invalid in event counter mode
Can be “0” or “1”
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Figure 1.43. Configuration of timer Ai mode register in event counter mode
60
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.25. Timer specifications in event counter mode (when processing two-phase pulse signal
with timers A2, A3, and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register’s content is
reloaded and the timer starts over again(Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
the reload register (Transferred to counter at next reload time)
• Normal processing operation
Select function
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count down all edges
Count down all edges
Count up all edges
TAiIN
(i=3,4)
Count up all edges
Note: This does not apply when the free-run function is selected.
61
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 2 to 4) 039816 to 039A16
0
0 1
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
Pulse output function
select bit
0 : Pulse is not output
MR0
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
MR1
MR2
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
Up/down switching
cause select bit
0 (Must always be “0” in event counter mode)
MR3
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
Two-phase pulse signal
processing operation
select bit (Note 4)(Note 5)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: The settings of the corresponding port register and port direction register are invalid
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
0
1 0 0 0 1
TAiMR(i = 2 to 4) 039816 to 039A16
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
0 (Must always be “0” when using two-phase pulse
signal processing)
MR0
MR1
0 (Must always be “0” when using two-phase pulse
signal processing)
1 (Must always be “1” when using two-phase pulse
signal processing)
MR2
0 (Must always be “0” when using two-phase pulse
signal processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”.
Figure 1.44. Configuration of timer Ai mode register in event counter mode
62
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.26.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.45 shows the configuration of the timer Ai mode
register in one-shot timer mode.
Table 1.26. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 4) 039616 to 039A16
0
1 0
Bit symbol
Bit name
Function
R W
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
MR2
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
External trigger select
bit (Note 2)
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure45. Configuration of timer Ai mode register in one-shot timer mode
63
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.27.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.46 shows the configu-
ration of the timer Ai mode register in pulse width modulation mode. Figure 1.47 shows an example of how a 16-bit
pulse width modulator operates. Figure 1.48 shows an example of how an 8-bit pulse width modulator operates.
Table 1.27. Timer specifications in pulse width modulation mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
•
• The timer is not affected by a trigger that occurs when counting
• High level width n / fi n : Set value
• Cycle time
(216-1) / fi fixed
16-bit PWM
8-bit PWM
•
•
High level width n X (m+1) / fi
Cycle time
n : values set to timer Ai register’s high-order address
m : values set to timer Ai register’s low-order address
(28-1) X (m+1) / fi
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
1
1 1
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode
select bit
1 1 : PWM mode
1 (Must always be fixed to “1” in PWM mode)
External trigger select
MR1
0: Falling edge of TAiIN pin's input signal (Note 2)
bit (Note 1)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
MR3
b7 b6
TCK0
TCK1
Count source select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0
Note 2: Set the corresponding port direction register to “0”.
Figure 1.46. Configuration of timer Ai mode register in pulse width modulation mode
64
Mitsubishi microcomputers
M16C / 60 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition : Reload register = 000316, when external trigger
(falling edge of TAiIN pin's input signal) is selected.
1 / fi X
(216 –1)
Count source
“H”
“L”
TAiIN pin's
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f
1
8, f32, fC32)
Cleared to “0” by software, or when interrupt request is accepted.
Note: n = 000016 to FFFE16
.
Figure 1.47. Example of how a 16-bit pulse width modulator operates
Condition : Reload register's high-order 8 bits = 0216
Reload register's low-order bits 8 = 0216
When external trigger (falling edge of TAiIN pin's input signal) is selected.
1 / fi X (m + 1) X
(28 – 1)
Count sourc
(Note 1)
“H”
“L”
TAiIN pin's input
signal
1 / fi X (m + 1)
“H”
“L”
Underflow signal of 8-
bit prescaler (Note 2)
1 / fi X (m + 1) X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” by software, or when interrupt request is accepted.
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16
.
Figure 1.48. Example of how an 8-bit pulse width modulator operates
65
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Figure 1.49 shows a block diagram of timer B. Figures 1.50 and 1.51 show configuration of timer B-related
registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f
1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f
8
f
32
fc32
Counter (16)
• Event counter
Count start flag
(address 038016
TBiIN
(i = 0 to 2)
Polarity switching
and edge pulse
)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
Timer B0 039116 039016 Timer B2
Timer B1 039316 039216 Timer B0
Timer B2 039516 039416 Timer B1
TBj overflow
(j = i - 1. Note, however,
j = 2 when i = 0)
Figure 1.49. Block diagram of timer B
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 2) 039B16 to 039D16
00XX0000
2
R
W
Bit symbol
TMOD0
Function
Bit name
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
TMOD1
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 1.50. Configuration of timer B-related registers (1)
66
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
Symbol
TB0
TB1
Address
When reset
(b15)
b7
(b8)
b0 b7
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
b0
TB2
Values that can be set
000016 to FFFF16
R W
Function
• Timer mode
Counts the timer's period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
0016
R W
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
R W
Bit name
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
0 : No effect
CPSR
Clock prescaler reset flag
1 : Prescaler is reset
(When read, the value is “0”)
Figure 1.51. Configuration of timer B-related registers (2)
67
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.28.) Figure 1.52 shows
the configuration of the timer Bi mode register in timer mode.
Table 1.28. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
0
0
TBiMR(i=0 to 2) 039B16 to 039D16
2
Bit symbol
R
W
Bit name
Function
0 0 : Timer mode
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
MR1
MR2
MR3
0 (Fixed to “0” in timer mode ; i = 0)
(Note 1)
(Note 2)
Nothing is assigned (i = 1,2).
This bit can neither be set nor reset. When read, its content is indeterminate.
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
b7 b6
TCK0
TCK1
Count source select bit
0 0 : f
0 1 : f
1 0 : f32
1
8
1 1 : fC32
Note 1: Timer B0.
Note 2: Timer B1, timer B2.
Figure 1.52. Configuration of timer Bi mode register in timer mode
68
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.29.) Figure
1.53 shows the configuration of the timer Bi mode register in event counter mode.
Table 1.29. Timer specifications in event counter mode
Item
Specification
• External signals input to TBiIN pin
Count source
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
• Counts down
Count operation
•
When the timer underflows, the reload register's content is reloaded and the timer starts over again
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
TBiMR(i=0 to 2) 039B16 to 039D16
2
0
1
R
W
Bit symbol
Bit name
Function
TMOD0
TMOD1
MR0
b1 b0
Operation mode
select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's falling edges
0 1 : Counts external signal's rising edges
1 0 : Counts external signal's falling and
rising edges
MR1
MR2
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2).
This bit can neither be set nor reset. When read, its content is
indeterminate.
Invalid in event counter mode.
This bit can neither be set nor reset. When read in event counter
mode, its content is indeterminate.
MR3
Invalid in event counter mode.
Can be “0” or “1”.
TCK0
TCK1
0: Input from TBiIN pin (Note 4)
1: TBj overflow
Event clock select
(j = i-1; however, j = 2 when i = 0)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Note 4: Set the corresponding port direction register to “0”.
Figure 1.53. Configuration of timer Bi mode register in event counter mode
69
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.30.)
Figure 1.54 shows the configuration of timer Bi mode register in pulse period/pulse width measurement
mode. Figure 1.55 shows the operation timing when measuring a pulse period. Figure 1.56 shows the
operation timing when measuring a pulse width.
Table 1.30. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input(Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from time
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result)(Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
1
0
TBiMR (i=0 to 2) 039B16 to 039D16
2
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
MR2
MR3
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2).
This bit can neither be set nor reset. When read, its content is indeterminate.
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
Count source
select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0.
Note 3: Timer B1, timer B2.
Figure 1.54. Configuration of timer Bi mode register in pulse period/pulse width measurement mode
70
Mitsubishi microcomputers
M16C / 60 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Measurement of puls time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing when counter
reaches “000016
”
“1”
“0”
Count start
flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” by software, or when interrupt request is accepted.
“1”
“0”
Timer Bi overflow
flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.55. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer (indeterminate value) Transfer (measured value)
Reload register
transfer timing
counter
(Note 2)
(Note 1)
(Note 1)
(Note 1) (Note 1)
Timing when counter
reaches “000016
”
“1”
“0”
Count start
flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” by software, or when interrupt request is accepted.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.56. Operation timing when measuring a pulse width
71
Mitsubishi microcomputers
M16C / 60 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive
timer to generate a transfer clock, so they operate independently of each other.
Figure 1.57 shows a block diagram of UART0 and UART1. Figure 1.58 shows a block diagram of the
transmit/receive unit.
UARTi (i = 0, 1) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016 and 03A816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART.
Although a few functions are different, UART0 and UART1 have almost the same functions. Figure 1.59
through 61 show configuration of UARTi-related registers.
(UART0)
TxD
0
RxD
0
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
Clock source selection
control circuit
Clock synchronous type
Bit rate generator
f
f
1
8
Internal
(address 03A116
)
UART transmission
1/16
Transmit
clock
1 / (m+1)
f32
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is
selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
Polarity
reversing
circuit
CLK
0
CTS/RTS disabled
CTS/RTS selected
RTS0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS0
CTS/RTS separated
CTS0 from UART1
(UART1)
RxD
1
TxD
1
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
f
f
1
Internal
(address 03A916
)
8
UART transmission
1/16
Transmit
clock
1 / (n+1)
f
32
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is
selected)
1/2
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
Polarity
reversing
circuit
CLK
1
CTS/RTS disabled
CTS/RTS separated
Clock output pin
select switch
RTS
1
1
CTS
CTS
1
0
/ RTS
/ CLKS
1
1
VCC
CTS/RTS disabled
CTS
CTS
0
CTS
0
to UART0
m: Values set to UART0 bit rate generator (BRG0)
n : Values set to UART1 bit rate generator (BRG1)
Figure 1.57. Block diagram of UARTi (i = 0, 1)
72
Mitsubishi microcomputers
M16C / 60 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
RxDi
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
D7
D6
D5
D4
D3
D
2
D1
D0
0
0
0
0
0
0
0
D8
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D7
D6
D5
D
4
D3
D2
D
1
D0
D
8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock
synchronouss
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
SP: Stop bit
UART (7 bits)
UART (8 bits)
"0"
Clock synchronous
type
PAR: Parity bit
Figure 1.58. Block diagram of transmit/receive unit
73
Mitsubishi microcomputers
M16C / 60 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
b0
Function
R W
Transmission data
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
b0
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Reception data
Reception data
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is indeterminate.
OER
Overrun error flag (Note) 0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
PER
Framing error flag (Note) Invalid
0 : No framing error
1 : Framing error found
Parity error flag (Note)
Invalid
Invalid
0 : No parity error
1 : Parity error found
SUM Error sum flag (Note)
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A016 and 03A816) are set to “000 ” or the receive enable bit is set to “0”.
2
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A616 and 03AE16) is read out.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U1BRG
Address
03A116
03A916
When reset
Indeterminate
Indeterminate
R
W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count
source by (n + 1)
Figure 1.59. Configuration of serial I/O-related registers (1)
74
Mitsubishi microcomputers
M16C / 60 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR (i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
SMD0
Must be fixed to 001
b2 b1 b0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
SMD1
SMD2
1 1 1 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be “0”
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0 (i=0,1)
Address
03A416, 03AC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
R W
Bit name
symbol
CLK0
b1 b0
b1 b0
BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
CRS
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
CRD
NCH
CTS/RTS disable bit
Data output select bit
(P60
and P6
4
function as
programmable I/O port)
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Figure 1.60. Configuration of serial I/O-related registers (2)
75
Mitsubishi microcomputers
M16C / 60 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516, 03AD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X00000002
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Invalid
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Invalid
CLKMD CLK/CLKS select bit 0
0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD CLK/CLKS select
0 : Normal mode
Must always be “0”
1
bit 1 (Note)
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
Figure 1.61. Configuration of serial I/O-related registers (3)
76
Mitsubishi microcomputers
M16C / 60 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.31 lists the specifications
of the clock synchronous serial I/O mode. Figure 1.62 shows a configuration of the UARTi transmit/receive mode register.
Table 1.31. Specifications of clock synchronous serial I/O mode
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
•
•
When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/ 2(n+1)(Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 03A016, 03A816 = “1”) : Input from CLKi pin(Note 2)
Transmission/reception control • CTS function/_R__T__S__ function/C___T__S__, _R__T__S__ function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_______
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_______
_ When CTS function selected, CTS input level = “L”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”: CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
•
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “0”: CLKi input level = “H”
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16) = “1”: CLKi input level = “L”
• When transmitting
Interrupt request
generation timing
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
Select function
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (Note 4)
UART1 transfer clock can be chosen by software to be output from one of the two pins set
_______ _______
• Separate CTS/RTS pins(Note 4)
_______
_______
UART0's CTS and RTS pins each can be assigned to separate pins
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
_______ _______
Note 4: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
77
Mitsubishi microcomputers
M16C / 60 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be "0" in clock synchronous serial I/O mode)
Figure 1.62. Configuration of UARTi transmit/receive mode register in clock synchronous serial I/O mode
Table 1.32 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
_______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.32. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
Serial data output
(P63, P67)
RxDi
(Outputs dummy data when performing reception only)
Serial data input
Port P62 and P66 direction register (bits 2 and 6 at address 03EE16) = “0”
(P62, P66)
CLKi
(Can be used as an input port when performing transmission only)
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
Transfer clock output
Transfer clock input
(P61, P65)
Port P61 and P65 direction register (bits 1 and 5 at address 03EE16) = “0”
_______ _______
________ ________
_______
CTSi/RTSi
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
_______ _______
(P60, P64)
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = “0”
_______ _______
_______
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
_______ _______
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
_______ _______
Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
_______ _______
(When transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
78
Mitsubishi microcomputers
M16C / 60 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
“0”
“1”
“0”
“H”
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
D0
D
1
D
2
D3
D4
D5
D
6
D7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” by software, or when an interrupt request is accepted.
Tc = TCLK = 2(n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
fi: frequency of BRGi's count source (f
n: value set to BRGi
1, f8, f32)
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
“H”
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D2
D3
D
4
D5
D6
D0
D1
D
2
D4
D5
D7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” by software, or when an interrupt request is accepted.
fEXT: frequency of external clock
Shown in ( ) are bit symbols.
The above timing applies to the following settings.
• External clock is selected.
Meet the following conditions when the CLK input bef
data reception = “H”
• Transmit enable bit
• Receive enable bit
“1”
“1”
• RTS function is selected.
• CLK polarity select bit = “0”.
• Dummy data write to UARTi transmit buffer registe
Figure 1.63. Typical transmit/receive timings in clock synchronous serial I/O mode
79
Mitsubishi microcomputers
M16C / 60 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Polarity select function
As shown in Figure 1.64, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16) allows selec-
tion of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK
i
Note 1: The CLK pin level when not
transferring data is “H”.
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
• When CLK polarity select bit = “1”
CLK
i
Note 2: The CLK pin level when not
transferring data is “L”.
D
0
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
1
D
2
D
3
D
D
5
D
6
D7
D
RXDi
Figure 1. 64. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.65, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16) = “0”,
the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK
i
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
LSB first
D
1
D
2
D
D4
D
D
D
D0
RXDi
• When transfer format select bit = “1”
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies when the CLK polarity select bit = “0”.
Figure 1. 65. Transfer format
80
Mitsubishi microcomputers
M16C / 60 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.66.) The
multiple pins function is valid only when the internal clock is selected for UART1. Note that when this
_______ _______
function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS
1
1
(P6
4
)
CLK
(P65
)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission is
performed only in clock synchronous serial I/O mode.
Figure 1. 66. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in the continuous receive mode. In this mode, when the receive buffer register is read out, the
unit simultaneously goes to a receive enable state without having to set dummy data to the transmit
buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
81
Mitsubishi microcomputers
M16C / 60 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Table 1.33 lists the specifications of the UART mode. Figure 1.67 shows the configuration
of the UARTi transmit/receive mode register.
Table 1.33. Specifications of UART Mode
Item
Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16 (n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816=“1”) :
fEXT/16 (n+1) (Note 1) (Note 2)
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
_______
_______
- When CTS function selected, CTS input level = “L”
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
Reception start condition
Interrupt request
generation timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
-
Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”: Interrupts
requested when data transmission from UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
Error detection
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
_______ _______
Select function
• Separate CTS/RTS pins
_______
_______
UART0’s CTS and RTS pins can each be assigned to separate pins
• Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
82
Mitsubishi microcomputers
M16C / 60 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR (i=0,1)
Address
03A016, 03A816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd/even parity select bit Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Figure 1.67. Configuration of UARTi transmit/receive mode register in UART mode
Table 1.34 lists the functions of the input/output pins during UART mode. This table shows the pin
_______ _______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
________ _______
Table 1.34. Input/output pin functions in UART mode (when separate CTS/RTS pins function is
not selected)
Pin name
TxDi
Function
Method of selection
Serial data output
(P63, P67)
RxDi
Serial data input
Internal/external clock select bit (bit 2, bit 6 at address 03EE16) = “0”
(P62, P66)
CLKi
(Can be used as an input port when performing transmission only)
Programmable I/O port
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “0”
(P61, P65)
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
________ ________
_______
_______ _______
CTSi/RTSi
(P60, P64)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
_______ _______
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “0”
Port P60 and P64 direction register (bits 0 and 4 at address 03EE16) = “0”
_______ _______
_______
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “0”
_______ _______
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16) = “1”
_______ _______
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16) = “1”
83
Mitsubishi microcomputers
M16C / 60 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
“1”
Transmit enablee
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transmit enable bit = “0”
Start
bit
Parity Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D
3
D
4
D
5
D
7
P
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
SP
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” by software, or when an interrupt request is accepted.
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi's count source (f
The above timing applies to the following settings :
• Parity is enabled.
1, f8, f32)
fEXT : frequency of BRGi's count source (external clock)
• One stop bit.
n : value set to BRGi
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D
0
D1
D2
D3
D
4
D5
D
7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SPSP
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” by software, or when an interrupt request is accepted.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
fi : frequency of BRGi's count source (f
EXT : frequency of BRGi's count source (external clock)
n : value set to BRGi
1, f8, f32)
f
• CTS function is disabled.
• Transmit interrupt causes select bit = “0”.
Figure 1.68. Typical transmit timings in UART mode
84
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi's count
source
“1”
“0”
Receive
enable bit
Stop bit
Start bit
Sampled “L”
D1
D7
RxDi
D0
Receive data taken in
Transfer clock
Reception triggered when
transfer clock is genelated
by falling edge of start bit
Transferred from UARTi receive register to
UARTi receive buffer register
“1”
Receive
complete flag
“0”
“H”
“L”
RTSi
Receive interrupt “1”
request bit
“0”
Cleared to “0” by software, or when an interrupt request is accepted.
The above timing applies to the following settings :
• Parity is disabled.
• One stop bit.
• RTS function is selected.
Figure 1.69. Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function
_______ _______
_______
With the separate CTS/RTS bit (bit 6 at address 03B016) is set to “1”, the unit outputs/inputs the CTS
_______
and RTS signals on different pins. (See Figure 1.70.) This function is valid only for UART0. Note that
_______ _______
if this function is selected, the CTS/RTS function for UART1 cannot be used.
Microcomputer
IC
TX
D
0
(P63)
IN
R
X
D0
(P62)
OUT
RTS0 (P6
0
4
)
)
CTS
RTS
CTS0 (P6
_______ _______
Figure 1.70. Example for the separate CTS/RTS pins function usage
(b) Sleep mode
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
85
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.35 shows the performance of the A-D converter. Figure 1.71 shows a block diagram of the A-D
converter, and Figures 1.72 and 1.73 show configurations of the A-D converter-related registers.
Table 1.35. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock AD (Note 2) VCC = 5V
VCC = 3V
fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±3LSB
ANEX0 and ANEX1 input (including mode in which exter
nal operation amp is connected) : ±7LSB
• Without sample and hold function (8-bit resolution)
±2LSB
VCC = 3V
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
A-D conversion
start condition
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
• Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles
• With sample and hold function
8-bit resolution: 28 AD cycles
,
10-bit resolution: 59 AD cycles
,
10-bit resolution: 33 AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the AD frequency to 250kHz min.
With the sample and hold function, set the AD frequency to 1MHz min.
86
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
CKS0=1
CKS0=0
AD
f
AD
1/2
1/2
A-D conversion
rate selection
CKS1=0
VCUT=0
VCUT=1
AVSS
Resistor ladder
V
REF
Successive conversion register
A-D control register 1 (address 03D716
)
)
A-D control register 0 (address 03D616
Addresses
(03C116, 03C016
)
A-D register 0(16)
(03C316, 03C216
)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03C516, 03C416
)
Vref
(03C716, 03C616
(03C916, 03C816
(03CB16, 03CA16
(03CD16, 03CC16
(03CF16, 03CE16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
V
IN
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
CH2,CH1,CH0=000
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=1,1
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1,OPA0=0,1
Figure 1.71. Block diagram of A-D converter
87
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
Analog input pin select bit
CH0
CH1
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
b4 b3
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
CH2
MD0
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
MD1
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
A-D sweep pin select bit
mode 0 are selected
b1 b0
SCAN0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
When repeat sweep mode 1 is selected
b1 b0
SCAN1
MD2
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN
1
(2 pins)
to AN
2
3
(3 pins)
(4 pins)
to AN
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
Frequency select bit 1
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Vref connect bit
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.72. Configuration of A-D converter-related registers (1)
88
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
Symbol
ADCON2
Address
03D416
When reset
XXXXXXX02
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
SMP
Bit name
Function
R W
0
1
Without sample and hold
With sample and hold
A-D conversion method
select bit
Nothing is assigned.
These bits can neither be set nor reset. When read, their content is “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi (i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
These bits can neither be set nor reset. When read, their
content is “0”.
Figure 1.73. Configuration of A-D converter-related registers (2)
89
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.36
shows the specifications of one-shot mode. Figure 1.74 shows the configuration of the A-D control register in one-shot
mode.
Table 1.36. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
0
0
Bit symbol
Bit name
Function
R W
b2 b1 b0
Analog input pin
select bit
CH0
CH1
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
0: fAD/4 is selected
1: fAD/2 is selected
CKS0
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in one-shot mode
SCAN0
SCAN1
MD2
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Frequency select bit1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.74. Configuration of A-D conversion register in one-shot mode
90
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.37
shows the specifications of repeat mode. Figure 1.75 shows the configuration of the A-D control register in repeat
mode.
Table 1.37. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
0
1
Bit symbol
Bit name
Function
0 is selected
R W
b2 b1 b0
Analog input pin
select bit
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 1 : Repeat mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversin
result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in repeat mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
CKS1
VCUT
0 : fAD/2 or fAD/4 is selected
Frequency select bit 1
Vref connect bit
1 : fAD is selected
1 : Vref connected
b7 b6
External op-amp
connection mode bit
OPA0
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversn
result is indeterminate.
Figure 1.75. Configuration of A-D conversion register in repeat mode
91
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
I
n single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.38 shows the specifications of single sweep mode. Figure 1.76 shows the configura-
tion of the A-D control register in single sweep mode.
Table 1.38. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
Start condition
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
0
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in single sweep mode
CH0
CH1
CH2
b4 b3
A-D operation mode
select bit 0
MD0
MD1
1 0 : Single sweep mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
SCAN1
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.76. Configuration of A-D conversion register in single sweep mode
92
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.39 shows the specifications of repeat sweep mode 0. Figure 1.77 shows the
configuration of the A-D control register in repeat sweep mode 0.
Table 1.39. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit When single sweep and repeat sweep mode 0
SCAN0
SCAN1
are selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit.
Figure 1.77. Configuration of A-D conversion register in repeat sweep mode 0
93
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.40 shows the specifications of repeat sweep mode 1. Figure
1.78 shows the configuration of the A-D control register in repeat sweep mode 1
.
Table 1.40. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D register corresponding to selected pin (at any time)
Reading of result of A-D converter
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
1
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
1
SCAN1
to AN
to AN
2
3
(3 pins)
(4 pins)
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Figure 1.78. Configuration of A-D conversion register in repeat sweep mode 1
94
Mitsubishi microcomputers
M16C / 60 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”.
When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 f AD
cycle is achieved with 8-bit resolution and 33 f AD with 10-bit resolution. Sample and hold can be
selected in all modes. However, in all modes, be sure to specify before starting A-D conversion
whether sample and hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins, ANEX0 and ANEX1,
can also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1,
can be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in
the corresponding A-D register. The speed of A-D conversion depends on the response of the exter-
nal operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.79 is an example of
how to connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
Analog
input
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.79. Example of external op-amp connection mode
95
Mitsubishi microcomputers
M16C / 60 Group
D-A Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.41 lists the performance of the D-A converter. Figure 1.80 shows a block diagram of the D-A
converter. Figure 1.81 shows the configuration of the D-A control register.
Table 1.41. Performance of D-A converter
Item
Conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 channels
Data bus low-order bits
(Address 03D816, 03DA16
)
D-A register i (8) (i = 0, 1)
R-2R resistor ladder
D-Ai output enable bit (i = 0, 1)
P9
P9
3
4
/ DA
0
1
/ DA
Figure 1.80. Block diagram of D-A converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DC16
When reset
0016
Bit symbol
DA0E
Bit name
Function
R W
0 : Output disabled
1 : Output enabled
D-A0 output enable bit
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is “0”.
D-A register
b7
Symbol
DAi (i = 0,1)
Address
03D816 03DA16
When reset
Indeterminate
b0
,
Function
R W
Output value of D-A conversion
Figure 1.81. Configuration of D-A control register
96
Mitsubishi microcomputers
M16C / 60 Group
CRC Calculation Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.82 shows a block diagram of the CRC circuit. Figure 1.83 shows the configuration of CRC-related
registers.
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16
)
CRC code generating circt
x
16 + x12 + x5 + 1
CRC input register (8) (Address 03BE16
)
Figure 1.82. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
b0
Values that
can be set
Function
R W
CRC calculation result output register
000016 to FFFF16
CRC input register
b7
b0
Symbo
CRCIN
Address
03BE16
When reset
Indeterminate
Values that
can be set
Function
R W
Data input register
0016 to FF16
Figure 1.83. Configuration of CRC-related registers
97
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.84 and 1.85 show the configuration of the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.86 shows a configuration of direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.87 shows a configuration of port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.88 shows a configuration of pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, P0 to P5 operate as the bus and the
pull-up control register setting is invalid.
98
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P0
P2
P4
0
0
0
to P0
to P2
to P4
7
7
3
, P1
0
0
to P1
7
7
,
,
Pull-up selection
Direction register
, P3
to P3
Data bus
Port latch
Pull-up selection
Direction register
P5
P7
P9
5
5
0
, P6
2
, P6
6
1
, P7
1
, P7
3
,
, P77, P8
to P8
4
, P8
7,
to P92, P97
Port latch
Data bus
Input to respective peripheral functions
Pull-up selection
P4
P5
4
to P4
7
, P5
0
to P54,
6, P6 , P6
3
7
, P8
6
Direction register
“1”
output
Data bus
Port latch
Pull-up selection
P5
P6
P7
7
5
6
, P6
, P7
, P8
0
0
0
, P6
1
2
, P6
4
,
,
Direction register
“1”
, P7
, P7
4
output
Data bus
Port latch
Input to respective peripheral functions
Figure 1.84. Configuration of programmable I/O ports (1)
99
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P85
Data bus
NMI interrupt input
Pull-up selection
P9
(inside dotted-line not included)
P10 to P10
(inside dotted-line included)
5, P96, P100 to P103
Direction register
4
7
Data bus
Port latch
Analog input
Pull-up selection
Direction register
P93, P94
Data bus
Port latch
Analog output
D-A output enabled
Figure 1.85. Configuration of programmable I/O ports (2)
100
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
PDi (i = 0 to 10, except 8) 03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
Bit symbol
PDi_0
Bit name
direction register
Function
R W
Port Pi
0
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
PDi_2
Port Pi
Port Pi
1
2
direction register
direction register
(Functions as an output port)
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
3
4
5
6
7
direction register
direction register
direction register
direction register
direction register
(i = 0 to 10 except 8)
Note: Set bit 2 of protect register (address 000A16) to “1” before rewritting
to the port P9 direction register.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
0: Input mode
(Functions as an input port)
1: Output mode
R W
Port P8
Port P8
Port P8
Port P8
Port P8
0
1
2
3
4
direction register
direction register
direction register
direction register
direction register
PD8_1
PD8_2
(Functions as an output port)
PD8_3
PD8_4
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
7
direction register
direction register
(Functions as an output port)
Figure 1.86. Configuration of direction register
101
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi register
Symbol
Pi (i = 0 to 10, except
Addres
When reset
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F116, 03F416
Bit symbol
PDi_0
Bit name
register
Function
R W
Port Pi
0
1
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit
0 : “L” level data
PDi_1
Port Pi
register
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
2
3
4
5
6
7
register
register
register
register
register
register
1 : “H” level data
(i = 0 to 10 except 8)
Port P8 register
Symbol
P8
Address
03F016
When reset
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
PD8_0
Bit name
register
register
register
register
register
register
register
register
Function
R W
Port P8
0
1
2
3
4
5
6
7
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
PD8_1
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
PD8_2
PD8_3
PD8_4
PD8_5
PD8_6
PD8_7
Figure 1.87. Configuration of port register
102
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When rese
0016
t
Bit
symbo
PU00
Bit
name
pull-up
Function
R W
R W
R W
P0
0
to P0
3
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
P0
4
0
to P0
7
3
pull-up
pull-up
P1
to P1
1 : Pulled high
PU03
PU04
PU05
P1
P2
P2
4
0
4
to P1
to P2
to P2
7
3
7
pull-up
pull-up
pull-up
PU06
PU07
P3
0
4
to P3
3
7
pull-up
pull-up
P3
to P3
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When rese
0016
t
Function
Bit name
Bit symbol
PU10
P4
P4
P5
P5
P6
P6
P7
0
to P4
to P4
to P5
to P5
to P6
to P6
to P7
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
PU12
PU13
PU14
PU15
PU16
4
7
0
4
0
4
0
3
7
3
7
3
1 : Pulled high
PU17
P7
4
to P7
7
pull-up
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
Function
P8
0
4
to P8
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU21
P8
to P8
7
pull-up
(Except P85)
1 : Pulled high
PU22
PU23
PU24
P9
P9
0
4
to P9
3
7
pull-up
pull-up
to P9
P10
P10
0
4
to P10
3
pull-up
pull-up
PU25
to P10
7
Nothing is assigned.
Theses bits can neither be set nor reset. When read, their contents are "0".
Figure 1.88. Configuration of pull-up control register
103
Mitsubishi microcomputers
M16C / 60 Group
Programmable I/O Ports
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.42. Example of connection of unused pins in single-chip mode
Pin name
Connection
Specify output mode, and leave these pins open;
Ports P0 to P10 (excluding P85)
or specify input mode, and connect to VSS via resistor (pull-down)
Open
XOUT (Note)
Connect to VCC
Connect to VSS
AVCC, NMI
AVSS, VREF, BYTE
Note: With external clock input to XIN pin.
Table 1.43. Example of connection of unused pins in memory expansion and microprocessor mode
Pin name
Connection
Specify output mode, and leave these pins open;
Ports P6 to P10 (excluding P85)
or specify input mode, and connect to VSS via resistor (pull-down)
Open
BHE, ALE, HLDA,
X
OUT (Note), BCLK
Connect via resistor to VCC (pull-up)
Connect to VCC
HOLD, RDY
AVCC, NMI
AVSS, VREF
Connect to VSS
Note: With external clock input to XIN pin.
Microcomputer
Microcomputer
Port P0 to P10 (except for P8
5
)
Port P6 to P10 (except for P85)
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
Open
Open
NMI
BHE
HLDA
ALE
NMI
XOUT
VCC
XOUT
VCC
BCLK
AVCC
HOLD
BYTE
AVSS
RDY
AVCC
VREF
AVSS
VSS
VSS
VREF
In memory expansion mode or
in microprocessor mode
In single-chip mode
Figure 1.89. Example of connection of unused pins
104
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Items to be submitted when ordering masked ROM version
Please submit the following when ordering masked ROM products:
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data : EPROM (3 sets)
Items to be submitted when ordering data to be written to ROM
Please submit the following when ordering data to be written to one-time PROM products at the factory:
(1) ROM writing order form
(2) Mark specification sheet
(3) ROM data : EPROM (3 sets)
105
Mitsubishi microcomputers
M16C / 60 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.44. Absolute maximum ratings
Symbol
Vcc
Parameter
Condition
Rated value
–0.3 to 7
Unit
V
Supply voltage
AVcc
–0.3 to 7
V
Analog supply voltage
V
I
Input voltage
RESET, CNVss, BYTE
P0
P3
0
to P0
7
, P1
0
to P17, P2
to P47, P5
0
0
to P2
7
,
,
0
to P3
7
, P4
0
to P5
7
–0.3 to Vcc + 0.3
(Note 1)
V
P6
P9
0
0
to P6
to P9
7
, P7
, P10
0 to P77, P80 to P87,
7
0
to P107,
VREF, XIN
Output voltage
P0
P3
0
0
to P0
7
, P1
0
0
0
to P17, P2
to P47, P5
0
to P2
to P57,
to P84,
7,
to P3
7
, P4
, P7
0
V
O
d
V
P60
to P6
7
to P77, P8
0
–0.3 to Vcc + 0.3
P8
6
,P8 , P9
7
0
to P97, P10
0
to P107,
X
OUT
300
mW
C
P
Power dissipation
Ta=25 C
Topr
Operating ambient temperature
Storage temperature
–40 to 85
–65 to 150
T
stg
C
Note 1: When writting to EPROM, only CNVss is –0.3 to 13 (V).
Table 1.45. Recommended operating conditions (referenced to VCC = 2.7V to 5V at Ta = –40 to
o
85 C unless otherwise specified)
Standard
Symbol
Parameter
Unit
Min
Typ.
5.0
Vcc
0
Max.
Supply voltage
Vcc
2.7
5.5
V
V
V
V
Analog supply voltage
Supply voltage
AVcc
Vss
AVss
0
Analog supply voltage
P3
P7
1
0
to P3
to P7
7
, P4
, P8
0
0
to P4
to P8
7
, P5
, P9
0
0
to P57, P6
0
to P6
0
7,
HIGH input
voltage
7
7
to P9
7
, P10 to P107,
V
IH
IH
0.8Vcc
Vcc
V
X
IN, RESET, CNVSS, BYTE
V
HIGH input
voltage
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
, P3
0
0.8Vcc
0.5Vcc
Vcc
Vcc
V
V
(during single-chip mode)
HIGH input
voltage
P0 to P0 , P1 to P1 , P2
(during memory expansion and microprocessor modes)
0
7
0
7
0
to P2
7
, P3
0
V
IH
P3 to P3 , P4 to P4 , P5 to P5 , P6 to P6
1
7
0
7
0
7
0
7,
LOW input
voltage
V
V
0
0.2Vcc
V
P7 to P7 , P8 to P8 , P9 to P9 , P10 to P10
0
7
0
7
0
7
0
7,
IL
IL
XIN, RESET, CNVSS, BYTE
P0 to P0 , P1 to P1 , P20 to P27, P30
(during single-chip mode)
0
7
0
7
LOW input
voltage
0
0
0.2Vcc
V
V
LOW input
voltage
P0
0 to P07, P10 to P17, P20 to P27, P30
V
0.16Vcc
IL
(during memory expansion and microprocessor modes)
P0
P4
P8
0
0
to P0
to P4
to P84,P86,P87,P9
7
7
, P1
, P5
0
0
to P1
7
, P2
0
0
to P2
to P6
7
7
,P3
,P7
0
0
to P3
to P7
7
7
,
,
HIGH peak
output current
to P5
7
, P6
0
–10.0
–5.0
mA
mA
I OH (peak)
0
to P97,P10
0
to P10
7
P0
P4
P8
0
0
to P0
to P4
to P84,P86,P87,P9
7
7
, P1
, P5
0
0
to P1
7
, P2
0
0
to P2
to P6
7
7
,P3
,P7
0
0
to P3
to P7
7
7
,
,
HIGH average
output current
to P5
7
, P6
0
I OH (avg)
0
to P97,P10
0
to P10
7
P0
P4
0
0
to P0
to P4
7
7
, P1
, P5
0
0
to P1
7
, P2
0
0
to P2
to P6
7
7
,P3
,P7
0
0
to P3
to P7
7
7
,
,
LOW peak
output current
I OL (peak)
to P5
7
, P6
10.0
5.0
mA
mA
P8
0
to P84,P86,P87,P9
0
to P97,P10
0
to P10
7
P00
0
to P0
7
, P1
0
0
to P1
7
7
, P2
, P6
0
0
to P2
to P6
7
7
,P3
,P7
0
0
to P3
to P7
7
,
,
LOW average
output current
I OL (avg)
P4
to P47, P5
to P5
7
P80 to P84,P86,P87,P90 to P97,P100 to P107
Vcc =4.0V to 5.5V
10
7
MHz
MHz
kHz
Main clock input oscillation frequency
Subclock oscillation frequency
f (XIN
)
Vcc = 2.7V to 5.5V
(with wait)
f (XcIN
)
32.768
50
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max.
106
Mitsubishi microcomputers
M16C / 60 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Table 1.46. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, f(XIN) = 10MHz
unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
HIGH output
voltage
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P57,
P60 to P67,P70 to P77,P80 to P84,
P86,P87,P90 to P97,P100 to P107
VOH
IOH = –5mA
3.0
V
HIGH output
voltage
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P57
VOH
VOH
IOH = –200µA
4.7
V
V
IOH = –1mA
HIGHPOWER
3.0
3.0
HIGH output
voltage
XOUT
LOWPOWER
IOH = –0.5mA
LOW output
voltage
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P57,
P60 to P67,P70 to P77,P80 to P84,
P86,P87,P90 to P97,P100 to P107
VOL
IOL = 5mA
2.0
V
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P53
LOW output
voltage
VOL
VOL
IOL = 200µA
0.45
V
V
IOL = 1mA
HIGHPOWER
2.0
2.0
LOW output
voltage
XOUT
IOL = 0.5mA
LOWPOWER
Hysteresis
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB2IN, INT0 to INT2,
ADTRG, CTS0, CTS1, CLK0,
CLK1
VT+-VT-
0.2
0.8
V
VT+-VT-
VT+-VT-
0.2
0.2
1.8
0.8
V
V
RESET
XIN
Hysteresis
Hysteresis
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P57,
P60 to P67,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
HIGH input
current
IIH
VI = 5V
5.0
µA
XIN, RESET, CNVss, BYTE
P00 to P07,P10 to P17,P20 to P27,
P30 to P37,P40 to P47,P50 to P57,
P60 to P67,P70 to P77,P80 to P87,
P90 to P97,P100 to P107,
LOW input
current
IIL
VI = 0V
–5.0
µA
XIN, RESET, CNVss, BYTE
VRAM
2.0
V
RAM retention voltage
When clock is stopped
f(XIN) = 10MHz
Square wave,
no division
19.0 38.0
4.2
mA
When reset
in single-chip
mode, the
output-only
pins are open
and other
f(XIN) = 10MHz
Square wave,
division by 8
mA
µA
Icc
Power supply current
f(XCIN) = 32kHz
When a WAIT
instruction is
executed
4.0
pins are VSS
Ta = 25 C when
clock is stopped
1.0
µA
Ta = 85 C when
clock is stopped
20.0
107
Mitsubishi microcomputers
M16C / 60 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.47. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V
o
at Ta = 25 C, f(XIN) = 10MHz unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
–
–
V
REF
REF = VCC = 5V
AN
=
V
CC
10
Bits
LSB
LSB
Resolution
Absolute
accuracy
Sample & hold function not available
±3
V
±3
0
to AN7 input
V
REF =VCC
Sample & hold function available(10bit)
ANEX0, ANEX1 input,
External op-amp connection mode
±7
±2
LSB
= 5V
Sample & hold function available(8bit)
VREF = VCC = 5V
LSB
kΩ
R
LADDER
VREF =VCC
10
3.3
2.8
0.3
2
40
Ladder resistance
Conversion time(10bit)
Conversion time(8bit)
Sampling time
t
t
t
CONV
µs
µs
µs
V
CONV
SAMP
V
REF
IA
V
CC
Reference voltage
Analog input voltage
V
0
VREF
V
Table 1.48. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V at
o
Ta = 25 C, f(XIN) = 10MHz unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition
Unit
Min. Typ. Max.
Bits
%
–
–
Resolution
Absolute accuracy
8
1.0
tsu
µs
Setup time
3
kΩ
RO
Output resistance
4
10
20
I
VREF
Reference power supply input current
mA
(
Note)
1.5
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
108
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.50. External clock input
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
40
t
r
15
15
t
f
External clock fall time
Table 1.51. Memory expansion and microprocessor modes
Standard
Symbol
Parameter
Unit
Min.
Max.
t
ac1(RD-DB)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (no wait)
(Note)
t
ac2(RD-DB)
ac3(RD-DB)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
(Note)
(Note)
t
t
su(DB-RD)
40
30
40
0
Data input setup time
t
t
t
su(RDY-BCLK )
su(HOLD-BCLK )
h(RD-DB)
RDY input setup time
HOLD input setup time
Data input hold time
t
t
t
h(BCLK -RDY)
h(BCLK-HOLD )
d(BCLK-HLDA )
0
RDY input hold time
HOLD input hold time
HLDA output delay time
0
40
Note: Calculated according to the BCLK frequency as follows:
109
f(BCLK) X 2
3 X 109
f(BCLK) X 2
[ns]
t
ac1(RD – DB) =
– 45
– 45
[ns]
[ns]
t
t
ac2(RD – DB) =
ac3(RD – DB) =
3 X 109
f(BCLK) X 2
– 45
109
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.52. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
40
Table 1.53. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
w(TAL)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.54. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.55. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.56. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
TAiOUT input HIGH pulse width
t
w(UPL)
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
110
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 C unless otherwise specified)
Table 1.57. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 1.58. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
ns
Min.
400
Max.
t
c(TB)
TBiIN input cycle time
t
w(TBH)
w(TBL)
ns
ns
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
t
Table 1.59. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.60. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 1.61. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
h(C-D)
RxDi input setup time
RxDi input hold time
t
_______
Table 1.62. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
111
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.63. Memory expansion mode and microprocessor mode (no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
ns
ns
ns
ns
ns
ns
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
4
0
0
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
25
t
Chip select output hold time (BCLK standard)
4
t
t
d(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
25
25
25
ns
ns
ns
ns
ns
ns
h(BCLK-ALE)
– 4
0
Figure 1.90
t
t
d(BCLK-RD)
h(BCLK-RD)
t
t
d(BCLK-WR)
h(BCLK-WR)
0
t
d(BCLK-DB)
h(BCLK-DB)
40
ns
ns
ns
ns
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard) (Note 2)
t
4
(Note 1)
t
d(DB-WR)
h(WR-DB)
t
0
Note 1: Calculated according to the BCLK frequency as follows:
10 9
– 40
td(DB – WR) =
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC, C = 30pF, R = 1kW, hold time
of output “L” level is
t = – 30pF X 1kW X ln (1 – 0.2VCC / VCC
= 6.7ns.
)
112
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.64. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
25
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
t
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
0
ns
ns
h(RD-AD)
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
0
ns
ns
ns
td(BCLK-CS)
25
25
25
25
40
t
h(BCLK-CS)
4
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
ns
ns
– 4
0
Figure 1.90
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
ns
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
0
ns
ns
ns
t
t
d(BCLK-DB)
h(BCLK-DB)
4
(Note 1)
0
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
ns
t
Data output hold time (WR standard) (Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
109
td(DB – WR) =
[ns]
– 40
f(BCLK)
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC, C = 30pF, R = 1kW, hold time
of output “L” level is
t = – 30pF X 1kW X ln (1 – 0.2VCC / VCC
= 6.7ns.
)
113
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 C, CM15 =“1” unless
otherwise specified)
Table 1.65. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
25
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
4
(Note)
t
h(RD-AD)
(Note)
t
h(WR-AD)
t
d(BCLK-CS)
h(BCLK-CS)
25
25
t
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
4
(Note)
t
h(RD-CS)
(Note)
t
h(WR-CS)
t
d(BCLK-RD)
h(BCLK-RD)
t
t
t
t
t
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
0
0
ns
ns
ns
ns
ns
d(BCLK-WR)
25
40
Figure 1.90
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
4
(Note)
t
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
(Note)
Data output hold time (WR standard)
ns
ns
ns
ns
ns
t
t
d(BCLK-ALE)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
ALE signal output hold time (Adderss standard)
25
h(BCLK-ALE)
– 4
(Note)
t
t
d(AD-ALE)
h(ALE-AD)
50
0
0
t
t
t
d(AD-RD)
d(AD-WR)
dZ(RD-AD)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output floating start time
ns
ns
ns
8
Note: Calculated according to the BCLK frequency as follows:
109
th(RD – AD) =
[ns]
f(BCLK) X 2
109
th(WR – AD) =
[ns]
f(BCLK) X 2
109
th(RD – CS) =
th(WR – CS) =
td(DB – WR) =
[ns]
[ns]
[ns]
f(BCLK) X 2
109
f(BCLK) X 2
109 X 3
– 40
– 25
f(BCLK) X 2
109
th(WR – DB) =
td(AD – ALE) =
[ns]
[ns]
f(BCLK) X 2
109
f(BCLK) X 2
114
Mitsubishi microcomputers
M16C / 60 Group
Timing
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
30pF
Figure 1.90. Port P0 to P10 measurement circuit
115
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
t
c(CK)
tw(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
d(C–Q)
t
su(D–C)
t
h(C–D)
t
w(INL)
INTi input
t
w(INH)
116
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
RDY input
t
su(RDY-BCLK)
t
h(BCLK-RDY)
(Valid with or without wait)
BCLK
t
h(BCLK-HOLD)
t
su(HOLD-BCLK)
HOLD input
HLDA output
t
d(BCLK-HLDA)
t
d(BCLK-HLDA)
P0, P1, P2,
P3, P4,
Hi-Z
P50
to P5
2
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
•VCC = 5V
• Input timing voltage : Determined with VIL = 1.0V, VIH = 4.0V
• Output timing voltage : Determined with VOL =2.5V, VOH = 2.5V
117
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Modes
(With no wait)
Read timing
BCLK
t
d(BCLK–CS)
25ns.max
th(BCLK–CS)
4ns.min
CSi
tcyc
t
h(RD–CS)
0ns.min
t
d(BCLK–AD)
t
h(BCLK–AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
t
h(RD–AD)
0ns.min
25ns.max
–4ns.min
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
25ns.max
t
ac1(RD–DB)
Hi–Z
th(RD–DB)
tSU(DB–RD)
0ns.min
40ns.min
Write timing
BCLK
t
h(BCLK–CS)
td(BCLK–CS)
4ns.min
25ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
25ns.max
ADi
BHE
t
d(BCLK–ALE)
t
h(WR–AD)
25ns.max
t
h(BCLK–ALE)
0ns.min
ALE
–4ns.min
t
d(BCLK–WR)
25ns.max
t
h(BCLK–WR)
0ns.min
WR,WRL,
WRH
t
d(BCLK–DB)
t
h(BCLK–DB)
40ns.max
4ns.min
DB
Hi–Z
t
h(WR–DB)
t
d(DB–WR)
(tcyc/2–40)ns.min
0ns.min
118
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Modes
(When accessing external memory area with wait)
Read timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
25ns.max
CSi
t
h(RD–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
25ns.max
ADi
BHE
t
h(RD–AD)
t
d(BCLK–ALE)
t
h(BCLK–ALE)
25ns.max
0ns.min
–4ns.min
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
25ns.max
tac2(RD–DB)
Hi–Z
t
h(RD–DB)
t
SU(DB–RD)
40ns.min
0ns.min
Write timing
BCLK
t
h(BCLK–CS)
t
d(BCLK–CS)
25ns.max
4ns.min
CSi
tcyc
t
h(WR–CS)
0ns.min
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
25ns.max
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
t
h(WR–AD)
25ns.max
–4ns.min
0ns.min
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
WR,WRL,
WRH
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
40ns.max
DBi
t
h(WR–DB)
0ns.min
td(DB–WR)
(tcyc–40)ns.min
Measuring conditions :
• VCC = 5V
• Input timing voltage : Determined with VIL = 0.8V, VIH = 2.5V
• Output timing voltage : Determined with VOL = 0.8V, VOH = 2.0V
119
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
t
d(BCLK–CS)
t
h(BCLK–CS)
4ns.min
tcyc
t
h(RD–CS)
25ns.max
(tcyc/2)ns.min
CSi
t
d(AD–ALE)
(tcyc/2–25)ns.min
th(ALE–AD)
50ns.min
ADi
/DBi
Data input
Address
Address
dz(RD–AD)
t
h(RD–DB)
0ns.min
t
tac3(RD–DB)
t
SU(DB–RD)
40ns.min
8ns.max
t
d(AD–RD)
0ns.min
t
h(BCLK–AD)
t
d(BCLK–AD)
25ns.max
4ns.min
ADi
BHE
t
h(BCLK–ALE)
t
h(RD–AD)
(tcyc/2)ns.min
–4ns.min
ALE
RD
t
d(BCLK–ALE)
25ns.max
t
d(BCLK–RD)
t
h(BCLK–RD)
0ns.min
25ns.max
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
tcyc
t
d(BCLK–CS)
25ns.max
t
h(WR–CS)
(tcyc/2)ns.min
CSi
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
40ns.max
ADi
/DBi
Address
d(AD–ALE)
Data input
Address
td(DB–WR)
t
h(WR–DB)
t
(tcyc*3/2–40)ns.min
(tcyc/2–25)ns.min
(tcyc/2)ns.min
t
h(BCLK–AD)
4ns.min
td(BCLK–AD)
25ns.max
ADi
BHE
t
h(BCLK–ALE)
–4ns.min
t
h(WR–AD)
(tcyc/2)ns.min
t
d(AD–WR)
0ns.min
ALE
t
d(BCLK–ALE)
25ns.max
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
WR,WRL,
WRH
Measuring conditions :
• VCC = 5V
• Input timing voltage : Determined with VIL = 0.8V, VIH = 2.5V
• Output timing voltage : Determined with VOL = 0.8V, VOH = 2.0V
120
Mitsubishi microcomputers
M16C / 60 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.66. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHz
with wait)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
P0
P3
P6
P8
0
0
0
6
to P0
to P3
to P6
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7
7
4
7
,
,
,
HIGH output
voltage
V
OH
OH
I
OH = –1mA
2.5
V
,P87,P9
0
to P9
7,P10
0
to P10
HIGHPOWER
LOWPOWER
I
OH = –0.1mA
2.5
2.5
HIGH output
voltage
V
XOUT
V
V
V
I
OH = –50µA
P00
P30
P60
P86
to P0
to P3
to P6
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7
7
4
7
,
,
,
LOW output
voltage
V
OL
OL
I
OL = 1mA
0.5
,P87,P90 to P97,P100 to P10
HIGHPOWER
LOWPOWER
IOL = 0.1mA
0.5
0.5
LOW output
voltage
V
X
OUT
I
OL = 50µA
Hysteresis HOLD, RDY, TA0IN to TA4IN
TB0IN to TB2IN, INT to INT
, CLK
,
0
2,
V
T+-
V
T-
0.2
0.8
V
ADTRG, CTS
CLK
RESET
0
, CTS
1
0,
1
V
T+-
V
V
T-
T-
0.2
0.2
1.8
0.8
V
V
Hysteresis
Hysteresis
V
T+-
X
IN
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
to P2
to P5
to P8
7
7
7
,
,
,
HIGH input
current
0
0
I
IH
V
I
= 3V
= 0V
4.0
µA
µA
,P100 to P107,
XIN, RESET, CNVss, BYTE
P00
P30
P60
P90
to P0
to P3
to P6
to P9
7
7
7
7
,P1
,P4
,P7
0
0
0
to P1
to P4
to P7
7
7
7
,P2
,P5
,P8
0
0
0
to P2
to P5
to P8
7
7
7
,
,
,
LOW input
current
I
IL
VI
–4.0
,P100 to P107,
X
IN, RESET, CNVss, BYTE
V
RAM
RAM retention voltage
When clock is stopped
2.0
V
f(XIN) = 7MHz
Square wave,
no division
6.0
1.6
15.0
mA
f(XIN) = 7MHz
Square wave,
division by 8
mA
µA
When reset
in single-chip
mode, the
output-only
pins are
f(XCIN) = 32kHz
When a WAIT
instruction is
executed.
Oscillation capacity
High (Note)
Icc
Power supply current
2.8
0.9
open and
other pins
are VSS
f(XCIN) = 32kHz
When a WAIT
instruction is
executed.
Oscillation capacity
Low (Note)
µA
µA
Ta=25 C when
clock is stopped
1.0
Ta=85 C when
clock is stopped
20.0
Note: With one timer operated using fc32.
121
Mitsubishi microcomputers
M16C / 60 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.67. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS =
0V at Ta = 25oC, f(XIN) = 7MHz unless otherwise specified)
Standard
Min. Typ. Max
10
Symbol
Parameter
Measuring condition
Unit
Bits
Resolution
V
REF = VCC
–
–
Sample & hold function not
available (8 bit)
V
REF = VCC = 3V,
AD = f(XIN)/2
Absolute
accuracy
± 2
LSB
10
40
kΩ
R
LADDER
Ladder resistance
Conversion time(8bit)
Reference voltage
Analog input voltage
V
REF = VCC
14.0
t
CONV
µs
V
V
REF
IA
2.7
0
VCC
V
REF
V
V
Table 1.68. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
at Ta = 25oC, f(XIN) = 7MHz unless otherwise specified)
Standard
Min. Typ. Max
Symbol
Parameter
Measuring condition
Unit
Bits
%
µs
Resolution
Absolute accuracy
Setup time
8
1.0
3
–
–
tsu
R
O
kΩ
Output resistance
4
10
20
(Note)
1.0
I
VREF
Reference power supply input current
mA
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
122
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.69. External clock input
Standard
Symbol
Parameter
Unit
Min.
143
60
Max.
ns
ns
ns
ns
ns
t
c
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
60
t
r
18
18
t
f
External clock fall time
Table 1.70. Memory expansion and microprocessor modes
Standard
Symbol
Parameter
Unit
Min.
Max.
(Note)
t
ac1(RD-DB)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input access time (no wait)
t
ac2(RD-DB)
(Note)
(Note)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
t
ac3(RD-DB)
t
su(DB-RD)
80
60
80
0
t
su(RDY-BCLK )
RDY input setup time
t
su(HOLD-BCLK )
HOLD input setup time
Data input hold time
t
h(RD-DB)
t
h(BCLK -RDY)
0
RDY input hold time
HOLD input hold time
HLDA output delay time
t
h(BCLK-HOLD )
0
t
d(BCLK-HLDA)
100
Note: Calculated according to the BCLK frequency as follows:
109
[ns]
[ns]
[ns]
– 90
– 90
– 90
tac1(RD – DB) =
f(BCLK) X 2
3 X 109
tac2(RD – DB) =
f(BCLK) X 2
3 X 109
tac3(RD – DB) =
f(BCLK) X 2
123
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.71. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
60
Table 1.72. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.73. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.74. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
t
w(TAL)
Table 1.75. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
t
w(UPH)
w(UPL)
su(UP-TIN
h(TIN-UP)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
t
t
)
t
TAiOUT input hold time
600
124
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.76. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
t
w(TBH)
w(TBL)
c(TB)
w(TBH)
w(TBL)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
t
60
t
300
160
160
t
t
Table 1.77. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.78. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.79. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
ns
ns
t
w(ADL)
Table 1.80. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
ns
ns
ns
ns
ns
ns
ns
t
t
t
d(C-Q)
h(C-Q)
160
t
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.81. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
INTi input HIGH pulse width
INTi input LOW pulse width
ns
ns
t
w(INL)
125
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 1.82. Memory expansion and microprocessor modes (with no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
60
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
ns
ns
Address output hold time (BCLK standard)
4
0
0
t
h(RD-AD)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
ns
ns
t
t
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
60
60
60
t
Chip select output hold time (BCLK standard)
4
–4
0
t
d(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
ns
ns
ns
ns
Figure 1.90
t
h(BCLK-ALE)
t
d(BCLK-RD)
h(BCLK-RD)
t
t
d(BCLK-WR)
WR signal output delay time
60
80
ns
ns
ns
ns
t
h(BCLK-WR)
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
0
t
d(BCLK-DB)
h(BCLK-DB)
t
4
(Note 1)
0
t
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
ns
Data output hold time (WR standard) (Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
109
– 80
td(DB – WR) =
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC, C = 30pF, R = 1kW, hold time
of output “L” level is
t = – 30pF X 1kW X ln (1 – 0.2VCC / VCC
)
126
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 1.83. Memory expansion and microprocessor modes
(when accessing external memory area with wait)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
60
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
ns
ns
ns
4
0
0
t
h(RD-AD)
t
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
ns
d(BCLK-CS)
60
t
h(BCLK-CS)
Chip select output hold time (BCLK standard)
4
– 4
0
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
60
60
60
ns
ns
Figure 1.90
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
WR signal output delay time
ns
ns
ns
t
t
d(BCLK-WR)
h(BCLK-WR)
t
WR signal output hold time
0
ns
ns
ns
t
t
d(BCLK-DB)
h(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
80
4
(Note 1)
0
t
d(DB-WR)
Data output delay time (WR standard)
ns
ns
t
h(WR-DB)
Data output hold time (WR standard) (Note 2)
Note 1: Calculated according to the BCLK frequency as follows:
109
td(DB – WR) =
[ns]
– 80
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
R
C
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
DBi
For example, when VOL = 0.2VCC, C = 30pF, R = 1kW, hold time
of output “L” level is
t = – 30pF X 1kW X ln (1 – 0.2VCC / VCC)
= 6.7ns.
127
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, CM15 = “1” unless
otherwise specified)
Table 1.84. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
ns
Min.
Max.
60
t
d(BCLK-AD)
t
t
h(BCLK-AD)
h(RD-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
ns
ns
(Note)
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
(Note)
ns
ns
t
t
t
d(BCLK-CS)
60
h(BCLK-CS)
h(RD-CS)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
4
ns
ns
ns
(Note)
(Note)
th(WR-CS)
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
60
60
80
ns
ns
0
0
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
ns
ns
Figure 1.90
t
d(BCLK-DB)
h(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
ns
ns
ns
t
4
td(DB-WR)
(Note)
t
h(WR-DB)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
(Note)
ns
ns
td(BCLK-ALE)
60
t
h(BCLK-ALE)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
– 4
(Note)
ns
ns
td(AD-ALE)
t
h(ALE-AD)
ALE signal output hold time(Address standard)
Post-address RD signal output delay time
Post-address WR signal output delay time
50
0
0
ns
ns
ns
t
t
d(AD-RD)
d(AD-WR)
tdZ(RD-AD)
Address output floating start time
8
ns
Note: Calculated according to the BCLK frequency as follows:
10 9
th(RD – AD) =
[ns]
f(BCLK) X 2
10 9
th(WR – AD) =
th(RD – CS) =
th(WR – CS) =
[ns]
[ns]
[ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9 X 3
– 80
– 60
td(DB – WR) =
th(WR – DB) =
[ns]
[ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9
td(AD – ALE) =
[ns]
f(BCLK) X 2
128
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
tc(TA)
tw(TAH)
TAiIN input
t
w(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
t
su(UP–TIN)
t
h(TIN –UP)
(When count on falling edge
is selected)
TAiIN input
(When count on rising edge
is selected)
tc(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
tc(AD)
t
w(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
–
th(C Q)
TxDi
RxDi
t
su(D– C)
td(C– Q)
–
th(C D)
tw(INL)
INTi input
t
w(INH)
129
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
RDY input
t
su(RDY – BCLK)
t
h(BCLK – RDY)
(Valid with or without wait)
BCLK
th(BCLK – HOLD)
t
su(HOLD – BCLK)
HOLD input
HLDA output
td(BCLK – HLDA)
t
d(BCLK – HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi – Z
Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit
(PM06) of processor mode register 0 selects the function of ports P4 to P4
0
3.
Measuring conditions :
• VCC = 3V
• Input timing voltage : Determined with VIL = 0.6V, VIH = 2.4V
• Output timing voltage : Determined with VOL = 1.5V, VOH = 1.5V
130
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
60ns.max
CSi
tcyc
th(RD–CS)
0ns.min
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(RD–AD)
0ns.min
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
60ns.max
ALE
RD
DB
t
d(BCLK–RD)
60ns.max
t
h(BCLK–RD)
0ns.min
t
ac1(RD-DB)
Hi–Z
th(RD–DB)
tSU(DB–RD)
0ns.min
80ns.min
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
60ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(WR–AD)
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
0ns.min
60ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
60ns.max
WR,WRL,
WRH
t
d(BCLK–DB)
t
h(BCLK–DB)
80ns.max
4ns.min
DB
Hi–Z
t
h(WR–DB)
0ns.min
td(DB–WR)
(tcyc/2–80)ns.min
131
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
VCC = 3V
Read timing
BCLK
t
h(BCLK–CS)
t
d(BCLK–CS)
4ns.min
60ns.max
CSi
t
h(RD–CS)
tcyc
0ns.min
t
h(BCLK–AD)
t
d(BCLK–AD)
4ns.min
60ns.max
ADi
BHE
t
h(RD–AD)
t
h(BCLK–ALE)
td(BCLK–ALE)
60ns.max
–4ns.min
0ns.min
ALE
RD
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
60ns.max
tac2(RD–DB)
DB
Hi–Z
t
h(RD–DB)
0ns.min
tSU(DB–RD)
80ns.min
Write timing
BCLK
t
d(BCLK–CS)
t
h(BCLK–CS)
4ns.min
60ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
60ns.max
ADi
BHE
t
h(WR–AD)
t
h(BCLK–ALE)
td(BCLK–ALE) 60ns.max
0ns.min
–4ns.min
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
60ns.max
WR,WRL,
WRH
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
80ns.max
DBi
t
h(WR–DB)
t
d(DB–WR)
0ns.min
(tcyc–80)ns.min
Measuring conditions :
• VCC = 3V
• Input timing voltage : Determined with VOL = 0.48V, VOH = 1.5V
• Output timing voltage : Determined with VIL = 1.5V, VIH = 1.5V
132
Mitsubishi microcomputers
M16C / 60 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
60ns.max
tcyc
th(RD–CS)
(tcyc/2)ns.min
CSi
t
d(AD–ALE)
(tcyc/2–60)ns.min
Address
t
dz(RD–AD)
8ns.max
ADi
/DBi
Address
Data input
t
h(RD–DB)
tac3(RD–DB)
t
SU(DB–RD)
80ns.min
t
h(ALE–AD)
50ns.min
0ns.min
t
d(AD–RD)
0ns.min
t
d(BCLK–AD)
60ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(RD–AD)
(tcyc/2)ns.min
t
h(BCLK–ALE)
–4ns.min
ALE
RD
60ns.max
t
h(BCLK–RD)
t
d(BCLK–RD)
0ns.min
60ns.max
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
tcyc
t
h(WR–CS)
t
d(BCLK-CS)
60ns.max
(tcyc/2)ns.min
CSi
th(BCLK–DB)
t
d(BCLK-DB)
80ns.max
4ns.min
ADi
/DBi
Address
d(AD–ALE)
Data input
Address
t
d(DB–WR)
t
t
h(WR–DB)
(tcyc/2)ns.min
(tcyc/2–60)ns.min
(tcyc*3/2–80)ns.min
t
h(BCLK–AD)
t
d(BCLK–AD)
60ns.max
4ns.min
ADi
BHE
t
h(BCLK–ALE)
td(BCLK–ALE)
t
h(WR–AD)
t
d(AD–WR)
0ns.min
(tcyc/2)ns.min
–4ns.min
ALE
60ns.max
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
60ns.max
WR,WRL,
WRH
Measuring conditions :
• VCC = 3V
• Input timing voltage : Determined with VOL = 0.48V, VOH = 1.5V
• Output timing voltage : Determined with VIL = 1.5V, VIH = 1.5V
133
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH00 39B <67A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30600M8-XXXFP/GP
Date :
MASK ROM CONFIRMATION FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
.
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Please specify the name of the product being ordered and the EPROM being supplied.
We require 3 sets of EPROMs per pattern (please mark the box).
Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30600M8-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30600M8-XXXGP
(hex)
27C101
Address
0000016
Product : Area
containing ASCII
code for M30600M8 -
0000F16
0001016
0FFFF16
1000016
ROM(64K)
1FFFF16
Address
0000816
0000916
Address
0000016
0000116
0000216
(1) Write “FF16” to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
' M
'
= 4D16
'
'
2D16
FF16
'
3
' = 3316
'
'
'
0
6
0
'
'
'
= 3016
= 3616
= 3016
0000A16
0000B16
0000C16
FF16
FF16
FF16
The ASCII code for 'M30600M8-' is shown at right.
The data in this table must be written to address
0000316
0000416
0000516
0000016 to 0000F16
.
'
0
'
= 3016
0000D16
0000E16
0000F16
FF16
FF16
FF16
Both address and data are shown in hex.
'
'
M ' = 4D16
8 ' = 3816
0000616
0000716
134
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ SH00 39B <67A1>
Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30600M8-XXXFP/GP
MASK ROM CONFIRMATION FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type
27C101
Code entered in
source program
* = $00000
.BYTE ' M30600M8-'
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for
submission to Mitsubishi.
For the M30600M8-XXXFP, submit the 100P6S mark specification sheet. For the M30600M8-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHZ
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XCIN) =
kHZ
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
4. Special item (Indicate none if there is no specified item)
135
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ-SH00-40B <67A1>
ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30600E8-XXXFP/GP
Date :
ROM WRITING ORDER FORM
Section head Supervisor
signature
signature
Note : Please complete all items marked
Submitted by Supervisor
TEL
(
Company
name
)
Customer
Date
issued
Date :
1. Check sheet
Please specify the name of the product being ordered and the EPROM being supplied.
We require 3 sets of EPROMs per pattern (please mark the box).
Mitsubishi will write to ROM using the data on the EPROMs supplied, providing the data is the
same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any
discrepancy between the data on the EPROM sets and the ROM data written to the product.
Please carefully check the data on the EPROMs being submitted to Mitsubishi.
Microcomputer type No. :
M30600E8-XXXFP
Checksum code for total EPROM area :
EPROM type :
M30600E8-XXXGP
(hex)
27C101
Address
0000016
Product : Area
containing ASCII
code for M30600E8 -
0000F16
0001016
0FFFF16
1000016
ROM(64K)
1FFFF16
Address
0000816
0000916
Address
0000016
0000116
0000216
(1) Write "FF16" to the lined area.
(2) The area from 0000016 to 0000F16 is for storing
data on the product type name.
' M '
' 3 '
= 4D16
= 3316
' 2D16
FF16
'
' 0 '
' 6 '
' 0 '
= 3016
= 3616
= 3016
0000A16
0000B16
0000C16
FF16
FF16
FF16
The ASCII code for 'M30600E8-' is shown at right.
The data in this table must be written to address
0000316
0000416
0000516
0000016 to 0000F16
.
' 0 '
' E '
' 8 '
= 3016
= 4516
= 3816
0000D16
0000E16
0000F16
FF16
FF16
FF16
Both address and data are shown in hex.
0000616
0000716
136
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ-SH00-40B <67A1>
ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT
MICROCOMPUTER M30600E8-XXXFP/GP
ROM WRITING ORDER FORM
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the
pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the
assembler source program.
EPROM type
27C101
Code entered in
source program
* = $00000
.BYTE 'M30600E8-'
Note:
The ROM cannot be processed if the type No. written to the EPROM does not match the type No.
in the check sheet.
2. Mark specification
The mark specification differs according to the type of package. After entering the mark specification on
the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for
submission to Mitsubishi.
For the M30600E8-XXXFP, submit the 100P6S mark specification sheet. For the M30600E8-XXXGP,
submit the 100P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of
the products you ordered.
(1) Which kind of XIN-XOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you use?
f(XIN) =
MHz
(2) Which kind of XCIN-XCOUT oscillation circuit is used?
Ceramic resonator
External clock input
Quartz-crystal oscillator
Other (
)
What frequency do you us?
f(XCIN) =
kHz
(3) Which operation mode do you use?
Single-chip mode
Memory expansion mode
Microprocessor mode
4. Special item (Indicate none if there is no specified item)
137
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
138
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
139
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