M30800SFP [MITSUBISHI]
Microcontroller, 16-Bit, M16C CPU, 20MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100;
| 型号： | M30800SFP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 16-Bit, M16C CPU, 20MHz, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总335页 (文件大小：4790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/80 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/80 Series CPU core and are packaged in a 100-pin and 144-pin plastic molded
QFP. The peripheral functions of 100-pin and 144-pin are common. These single-chip microcomputers
operate using sophisticated instructions featuring a high level of instruction efficiency. With 16M bytes of
address space, they are capable of executing instructions at high speed. They also feature a built-in multi-
plier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other
high-speed processing applications.
Features
• Memory capacity..................................ROM (See ROM expansion figure.)
RAM 10 to 24 Kbytes
• Shortest instruction execution time ......50ns (f(XIN)=20MHz)
• Supply voltage .....................................4.2 to 5.5V (f(XIN)=20MHz)
Mask ROM, external ROM and flash memory versions
2.7 to 5.5V (f(XIN)=10MHz)
Mask ROM, external ROM and flash memory versions
• Low power consumption ......................45mA (M30800MC-XXXFP)
(f(XIN) = 20MHz without software wait,Vcc=5V)
• Interrupts..............................................29 internal and 8 external interrupt sources, 5 software interrupt
sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................5 output timers + 6 input timers
• Serial I/O..............................................5 channels for UART or clock synchronous
• DMAC ..................................................4 channels (trigger: 31 sources)
• DRAMC................................................Used for EDO, FP, CAS before RAS refresh, self-refresh
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter.......................................8 bits X 2 channels
Specifications written in this manual are believed to be ac-
curate, but are not guaranteed to be entirely free of error.
Specifications in this manual may be changed for func-
tional or performance improvements. Please make sure
• CRC calculation circuit.........................1 circuit
• X-Y converter.......................................1 circuit
your manual is the latest edition.
• Watchdog timer....................................1 line
• Programmable I/O ...............................87 lines:100-pin version, 123 lines:144-pin version
_______
• Input port..............................................1 line (P85 shared with NMI pin)
• Memory expansion ..............................Available (16M bytes)
• Chip select output ................................4 lines
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistance, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
------Table of Contents------
CPU .............................................................. 13
Reset............................................................. 18
Processor Mode ............................................ 26
Clock Generating Circuit ............................... 43
Protection ...................................................... 55
Interrupts ....................................................... 56
Watchdog Timer............................................ 78
DMAC ........................................................... 80
Timer ............................................................. 91
Serial I/O ..................................................... 123
A-D Converter ............................................. 165
D-A Converter ............................................. 175
CRC Calculation Circuit .............................. 177
X-Y converter .............................................. 179
DRAM controller.......................................... 182
Programmable I/O Ports ............................. 189
Usage Precaution ....................................... 207
Electric characteristics ................................ 219
Flash memory version................................. 266
1
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configuration (top view) for 100-pin and Figure 1.1.3 shows the pin
configuration (top view) for 144-pin.
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
P4
P4
4
5
6
/CS3/A20(MA12)
/CS2/A21
/CS1/A22
/CS0/A23
/WRL/WR/CASL
/WRH/BHE/CASH
/RD/DW
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P0
P0
P0
P0
P0
P0
7
6
5
4
3
2
/D
/D
/D
/D
/D
/D
7
6
5
4
3
2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P4
7
P5
P5
P5
0
1
2
P01
/D
/D
/KI
/KI
/KI
1
P00
0
3
2
1
P5
3
/BCLK/ALE/CLKOUT
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
P54
/HLDA/ALE
/HOLD
6
5
P55
P56
P57
P60
/ALE/RAS
M16C/80 Group
P10
4
/AN4/KI
0
3
2
1
/RDY
/CTS
P10
P10
P10
3/AN
2/AN
1/AN
0
0
0
/RTS
0
P6
1
/CLK
P6
P6
P6
2/RxD
3
/T
/CTS
/CLK
/RxD
/T
XD0
AVSS
P100/AN
0
4
1/RTS
1
/CTS
0
/CLKS
1
P6
P6
P6
5
1
V
AVcc
/ADTRG/R
REF
6
1
P97
XD
4
7
X
D1
/SCL /STxD
4
4
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note: This port is N-channel open drain output.
Package: 100P6S-A
Figure 1.1.1. Pin configuration for 100-pin version (top view) (1)
2
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
P4
2
/A18(MA10)
/A19(MA11)
P12/D10
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
3
P1
1
/D
/D
9
P4
4
/CS3/A20(MA12)
/CS2/A21
P10
8
P4
5
P07
P06
P05
P04
/D
/D
/D
/D
7
6
5
4
P4
6
/CS1/A22
P4
P5
P5
7
/CS0/A23
/WRL/WR/CASL
/WRH/BHE/CASH
0
1
P0
3
/D
/D
3
2
P02
P5
2
/RD/DW
P0
1
/D
/D
1
0
P5
P5
P5
3
/BCLK/ALE/CLKOUT
4
P00
/HLDA/ALE
/HOLD
P10
P10
P10
7
6
5
/AN
/AN
/AN
7
/KI
/KI
/KI
3
2
1
5
6
5
P5
P5
6
/ALE/RAS
/RDY
7
M16C/80 Group
P10
4
/AN4/KI
0
P60/CTS0/RTS0
P103/AN
3
P61
P62
P63
P64
/CLK
/RxD
/T
/CTS
/CLK
/RxD
/T
/T
/RxD
0
P10
2
/AN
2
1
0
XD0
P10
1
/AN
1
1
1
/RTS1/CTS0/CLKS1
AVSS
P6
P6
P6
5
P100/AN
0
31
30
6
7
VREF
29
28
AVcc
XD1
P9
P9 /ANEX1/T
P9
7
/ADTRG/R
X
D
4
4
/SCL
/SDA
/ANEX0/CLK
4
/STxD
4
P7
0
X
D
2
/SDA
/SCL
/TA1OUT/V
2
/TA0OUT (Note)
27
26
P7
1
2
2/TA0IN/TB5IN (Note)
6
X
D
4/SRxD
4
5
4
P7
2
/CLK
2
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Note: This port is N-channel open drain output.
Package: 100P6Q-A
Figure 1.1.2. Pin configuration for 100-pin version (top view) (2)
3
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
109
P44/CS3/A20(MA12)
P45/CS2/A21
P46/CS1/A22
P47/CS0/A23
P125
P10/D8
P07/D7
P06/D6
P05/D5
P04/D4
P114
72
110
111
71
70
112
113
69
68
P126
114
115
67
66
P113
P127
P112
P50/WRL/WR/CASL
P51/WRH/BHE/CASH
P52/RD/DW
P53/BCLK/ALE/CLKOUT
P130
116
117
65
64
P111
P110
118
63
62
P03/D3
P02/D2
P01/D1
P00/D0
P157
119
120
61
60
P131
121
122
59
VCC
P132
123
124
58
57
P156
VSS
P155
P133
125
126
56
55
P154
P54/HLDA/ALE
P55/HOLD
P56/ALE/RAS
P57/RDY
M16C/80 Group
P153
127
54
53
P152
128
129
P151
52
51
VSS
P134
130
131
P150
P135
50
49
VCC
P136
132
133
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
AVSS
48
P137
P60/CTS0/RTS0
P61/CLK0
P62/RXD0
134
135
47
46
136
137
45
44
P63/TXD0
P64/CTS1/RTS1/CTS0/CLKS1
P65/CLK1
VSS
138
43
42
139
140
41
40
P100/AN0
VREF
P66/RXD1
141
142
VCC
39
38
AVCC
P67/TXD1
143
144
P70/TXD2/SDA2/TA0OUT
P97/ADTRG/RXD4
/SCL4/STxD4
37
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Note: This port is N-channel open drain output.
Package: 144P6Q-A
Figure 1.1.3. Pin configuration for 144-pin version (top view)
4
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.1.4 is a block diagram of the M16C/80 group.
8
8
8
8
8
8
8
I/O ports
Port P3
Port P0
Port P1
Port P2
Port P5
Port P6
Port P4
Internal peripheral functions
Timer
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
System clock generator
X
IN - XOUT
X
CIN - XCOUT
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
UART /clock synchronous SI/O
(8 bits X 5 channels)
Memory
ROM
(Note 1)
X-Y converter
(16 bits X 16 bits)
RAM
(Note 2)
CRC arithmetic circuit (CCITT)
16 12
(Polynomial : X +X +X5+1)
M16C/80 series 16-bit CPU core
Registers
DRAM
controller
FLG
INTB
ISP
USP
PC
R0H
R0H
R0L
R0L
Watchdog timer
(15 bits)
R1H
R1L
DRAM
controller
R2
R3
A0
A1
FB
SB
D-A converter
(8 bits X 2 channels)
SVF
SVP
VCT
Multiplier
Port P13
Port P12
Port P15 Port P14
Port P11
8
7
8
8
5
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Note 3: Ports P11 to P15 exist in 144-pin version.
(Note 3)
Figure 1.1.4. Block diagram of the M16C/80 group
5
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1.1 is a performance outline of M16C/80 group.
Table 1.1.1. Performance outline of M16C/80 group
Item
Performance
Number of basic instructions
106 instructions
50ns(f(XIN)=20MHz)
Shortest instruction execution time
Memory
capacity
I/O port
See ROM expansion figure.
10 to 24 K bytes
ROM
RAM
P0 to P10 (except P85) 8-bit x 10, 7-bit x 1
P0 to P15 (except P85) 8-bit x 13, 7-bit x 2, 5-bit x 1
1 bit x 1
100-pin
144-pin
Input port
Multifunction
timer
P85
16 bits x 5
TA0, TA1, TA2, TA3,TA4
TB0, TB1, TB2, TB3, TB4, TB5
UART0, UART1, UART2,
UART3, UART4
16 bits x 6
Serial I/O
(UART or clock synchronous) x 5
A-D converter
D-A converter
DMAC
10 bits x (8 + 2) channels
8 bits x 2
4 channels
DRAM controller
CRC calculation circuit
X-Y converter
CAS before RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits X 16 bits
Watchdog timer
Interrupt
15 bits x 1 (with prescaler)
29 internal and 8 external sources, 5 software sources, 7
levels
Clock generating circuit
Supply voltage
2 built-in clock generation circuits
(built-in feedback resistance, and external ceramic or
quartz oscillator)
4.2 to 5.5V (f(XIN)=20MHz) Mask ROM, external ROM
and flash memory versions
2.7 to 5.5V (f(XIN)=10MHz) Mask ROM, external ROM
and flash memory versions
45mA (f(XIN) = 20MHz without software wait,Vcc=5V)
Mask ROM 128 Kbytes version
5V
Power consumption
I/O
I/O withstand voltage
Output current
characteristics
5mA
Memory expansion
Operating ambient temperature
Device configuration
Package
Available (up to 16M bytes)
o
–40 to 85 C
CMOS high performance silicon gate
100-pin and 144-pin plastic mold QFP
6
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M16C/80 group:
(1) Support for mask ROM version, external ROM version and flash memory version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM version and flash memory version)
100P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)
144P6Q-A : Plastic molded QFP (mask ROM version and flash memory version)
ROM Size
(Byte)
M30805SGP-BL
M30803SFP/GP-BL
M30802SGP-BL
External
ROM
M30800SFP/GP-BL
M30805SGP
M30803SFP/GP
M30802SGP
M30800SFP/GP
M30803FGFP/GP
M30805FGGP
256K
128K
M30803MG-XXXFP/GP
M30805MG-XXXGP
M30800MC-XXXFP/GP
M30802MC-XXXGP
M30800FCFP/GP
M30802FCGP
Flash memory
version
Mask ROM version
External ROM version
Figure 1.1.5. ROM expansion
The M16C/80 group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/80 group
As of August, 2001
Remarks
Mask ROM version
RAM capacity
10K bytes
Package type
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
Type No
ROM capacity
M30800MC-XXXFP
M30800MC-XXXGP
M30802MC-XXXGP
M30803MG-XXXFP
M30803MG-XXXGP
M30805MG-XXXGP
M30800FCFP
128K bytes
256K bytes
128K bytes
256K bytes
20K bytes
10K bytes
20K bytes
10K bytes
24K bytes
10K bytes
24K bytes
Flash memory version
M30800FCGP
M30802FCGP
M30803FGFP
M30803FGGP
M30805FGGP
*
M30800SFP
External ROM version
*
M30800SGP
M30802SGP
*
M30803SFP
*
M30803SGP
M30805SGP
*
M30800SFP-BL
External ROM version
with built-in boot loader
*
M30800SGP-BL
*
M30802SGP-BL
*
M30803SFP-BL
*
M30803SGP-BL
*
M30805SGP-BL
*
: New product
7
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No.
M 3 0 8 0 2 M C – X X X G P – BL
Boot loader
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM No.
Omitted for blank external ROM version
and flash memory version
ROM capacity:
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/80 Group
M16C Family
Figure 1.1.6. Type No., memory size, and package
8
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description (1)
Pin name
CC, VSS
Signal name I/O type
Function
Power supply
input
V
Supply 4.2 (2.7) to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the VSS
when operating in single-chip or memory expansion mode after reset.
Connect it to the VCC when in microprocessor mode after reset.
CNVSS
CNVSS
I
I
Reset input
An “L” on this input resets the microcomputer.
RESET
X
IN
OUT
Clock input
I
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
X
Clock output
O
X
OUT pin open.
This pin selects the width of an data bus in the external area 3. A 16-
-bit width is selected when this input is “L”; an 8-bit width is selected
when this input is “H”. This input must be fixed to either “H” or “L”.
BYTE
External data
bus width
select input
I
When not using the external bus, connect this pin to VSS
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC
AVCC
AVSS
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS
.
Reference
voltage input
V
REF
I
This pin is a reference voltage input for the A-D converter.
P00
to P0
7
I/O port P0
I/O
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input in single chip mode, the user can
specify in units of four bits via software whether or not they are tied to
a pull-up resistance. In memory expansion and microprocessor
mode, an built-in pull-up resistance cannot be used. However, it is
possible to select pull-up resistance presence to the usable port as I/
O port by setting.
D
0
to D
7
I/O
I/O
When set as a separate bus, these pins input and output data (D
0–D7).
This is an 8-bit I/O port equivalent to P0. P1 to P1 also function as
5
7
P1
0
to P1
7
I/O port P1
I/O port P2
external interrupt pins as selected by software.
D
8
to D15
to P2
I/O
When set as a separate bus, these pins input and output data (D
8–D15).
P2
0
7
I/O
O
This is an 8-bit I/O port equivalent to P0.
A
0
to A7
These pins output 8 low-order address bits (A
0
–A ).
7
I/O
If a multiplexed bus is set, these pins input and output data (D
0
–D
7)
A
0/D
0
to
and output 8 low-order address bits (A0–A7) separated in time by
multiplexing.
A7
/D7
P3
0
to P3
7
I/O port P3
I/O
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A
If the external bus is set as a 16-bit wide multiplexed bus, these pins
A
8
to A15
/D to
O
8–A15).
I/O
A
8
8
input and output data (D –D15) and output 8 middle-order address
8
A
15/D15
bits (A –A15) separated in time by multiplexing.
8
If accessing to DRAM area, these pins output row address and
column address separated in time by multiplexing.
O
MA0 to MA7
9
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description (2)
Pin name
P4 to P4
Signal name I/O type
Function
0
7
I/O port P4
I/O
O
This is an 8-bit I/O port equivalent to P0.
These pins output 8 high-order address bits (A16–A22, A23). Highest
address bit (A23) outputs inversely.
A
A
16 to A22
23
,
O
CS
MA8 to MA12
P5 to P5
0
to CS
3
These pins output CS
signals used to specify an access space.
0–CS3 signals. CS0–CS3 are chip select
If accessing to DRAM area, these pins output row address and
column address separated in time by multiplexing.
O
This is an 8-bit I/O port equivalent to P0. P53 in this port outputs a
divide-by-8 or divide-by-32 clock of XIN or a clock of the same
frequency as XCIN as selected by software.
0
7
I/O port P5
I/O
O
O
O
O
O
I
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the
WRH signal is “L”. Data is read when RD is “L”.
HOLD,
WR, BHE, and RD selected
ALE,
RDY
O
I
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when
using an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs an “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the bus of microcomputer is in the wait state.
O
O
O
O
When accessing to DRAM area while DW signal is “L”, write to DRAM.
CASL and CASH show timing when latching to line address. When
CASL accesses to even address, and CASH to odd, these two pins
become “L”. RAS signal shows timing when latching to row address.
DW,
CASL,
CASH,
RAS
This is an 8-bit I/O port equivalent to P0. When set for input in single
chip mode, microprocessor mode and memory expansion mode the
user can specify in units of four bits via software whether or not they
are tied to a pull-up resistance. Pins in this port also function as
UART0 and UART1 I/O pins as selected by software.
P60
to P6
7
I/O port P6
I/O
This is an 8-bit I/O port equivalent to P6 (P7
open drain output). Pins in this port also function as timer A
timer B5 or UART2 I/O pins as selected by software.
0
and P7
1
are N-channel
–A
P7
0
to P7
7
I/O port P7
I/O port P8
I/O
0
3,
P8
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8 and P8 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
pin) and P8 (XCIN pin). P8 is an input-only port that also functions
0 to P84, P86, and P87 are I/O ports with the same functions as P6.
P8
P8
0
6
to P8
4
,
I/O
I/O
,
6
7
P87
,
I/O
I
6
(XCOUT
P8
5
I/O port P85
7
5
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
P9
0
to P9
7
I/O port P9
I/O
I/O
This is an 8-bit I/O port equivalent to P6. Pins in this port also
function as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D-A
converter output pins, A-D converter extended input pins, or A-D
trigger input pins as selected by software.
P10
0
to P10
7
I/O port P10
This is an 8-bit I/O port equivalent to P6. Pins in this port also
function as A-D converter input pins. Furthermore, P10
4–P107 also
function as input pins for the key input interrupt function.
10
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description (3)
Pin name
P11 to P11
(Note)
Signal name
I/O type
II/O
Function
0
4
I/O port P11
I/O port P12
I/O port P13
I/O port P14
I/O port P15
This is an 5-bit I/O port equivalent to P6.
P12
(Note)
P13 to P13
(Note)
P14 to P14
(Note)
0
to P12
7
7
6
7
II/O
II/O
II/O
II/O
This is an 8-bit I/O port equivalent to P6.
This is an 8-bit I/O port equivalent to P6.
This is an 7-bit I/O port equivalent to P6.
This is an 8-bit I/O port equivalent to P6.
0
0
P150 to P15
(Note)
Note : Port P11 to P15 exist in 144-pin version.
11
t
n
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
e
Mitsubishi Microcomputers
e
d
m
n
p
o
U
l
e
M16C/80 group
v
e
d
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/80 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, DRAM controller and I/O ports.
The following explains each unit.
Memory
Figure 1.2.1 is a memory map of the M16C/80 group. The address space extends the 16 Mbytes from
address 00000016 to FFFFFF16. From FFFFFF16 down is ROM. For example, in the M30800MC-XXXFP,
there is 128K bytes of internal ROM from FE000016 to FFFFFF16. The vector table for fixed interrupts such
_______
as the reset and NMI are mapped to FFFFDC16 to FFFFFF16. The starting address of the interrupt routine
is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 00040016 up is RAM. For example, in the M30800MC-XXXFP, 10 Kbytes of internal RAM is mapped
to the space from 00040016 to 002BFF16. In addition to storing data, the RAM also stores the stack used
when calling subroutines and when interrupts are generated.
The SFR area is mapped to 00000016 to 0003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figure 1.5.1 to 1.5.4 are
location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
The special page vector table is mapped to FFFE0016 to FFFFDB16. If the starting addresses of subrou-
tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc-
tions can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30800MC-XXXFP, the following spaces cannot be used.
• The space between 002C0016 and 00800016 (Memory expansion and microprocessor modes)
• The space between F0000016 and FDFFFF16 (Memory expansion mode)
00000016
SFR area
For details, see
Figures 1.5.1 to
1.5.4
FFFE0016
FFFFDC16
FFFFFF16
00040016
Internal RAM
area
Special page
vector table
XXXXXX16
00800016
Internal reserved
area (Note 1)
<100-pin version>
Address
YYYYY16
Address
XXXXX16
Type No.
Undefined instruction
Overflow
BRK instruction
Address match
M30800MC/FC 002BFF16
M30803MG/FG 0053FF16
FE000016
FC000016
External area
F0000016
Internal reserved
area (Note 2)
<144-pin version>
Address
YYYYY16
Address
Type No.
Watchdog timer
YYYYYY16
XXXXX16
M30802MC/FC 002BFF16
M30805MG/FG 0053FF16
FE000016
FC000016
Internal ROM
area
NMI
Reset
FFFFFF16
M30802S
M30805S
002BFF16
0063FF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Figure 1.2.1. Memory map
12
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 28 registers shown in Figure 1.3.1. Eight of these registers (R0, R1, R2, R3, A0, A1,
SB and FB) come in two sets; therefore, these have two register banks.
General register
b15
b0
FLG
Flag register
b31
R2
R3
R0H
R1H
R0L
R1L
Data register (Note)
R2
R3
b23
A0
Address register (Note)
A1
SB
Static base register (Note)
Frame base register (Note)
FB
User stack pointer
Interrupt stack pointer
Interrupt table register
Program counter
USP
ISP
INTB
PC
High-speed interrupt register
b15
b0
b0
SVF
Flag save register
PC save register
Vector register
b23
SVP
VCT
DMAC related register
b7
DMD0
DMD1
DMA mode register
b15
DCT0
DMA transfer count register
DCT1
DRC0
DRC1
DMA transfer count reload register
DMA memory address register
DMA SFR address register
b23
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
DMA memory address reload register
Note: These registers have two register banks.
Figure 1.3.1. Central processing unit register
13
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can use as 32-bit data
registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
(3) Static base register (SB)
Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.
(4) Frame base register (FB)
Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.
(5) Program counter (PC)
Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.
(6) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.
(7) User stack pointer (USP), interrupt stack pointer (ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Set USP and ISP to an even number so that execution efficiency is increased.
(8) Save flag register (SVF)
This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.
14
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(9) Save PC register (SVP)
This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is
generated.
(10) Vector register (VCT)
This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is
generated.
(11) DMA mode registers (DMD0/DMD1)
These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA.
(12) DMA transfer count registers (DCT0/DCT1)
These registers consist of 16 bits and are used to set the number of DMA transfers performed.
(13) DMA transfer count reload registers (DRC0/DRC1)
These registers consist of 16 bits and are used to reload the DMA transfer count registers.
(14) DMA memory address registers (DMA0/DMA1)
These registers consist of 24 bits and are used to set a memory address at the source or destination of
DMA transfer.
(15) DMA SFR address registers (DSA0/DSA1)
These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA
transfer.
(16) DMA memory address reload registers (DRA0/DRA1)
These registers consist of 24 bits and are used to reload the DMA memory address registers.
15
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(17) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.3.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared
to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank
1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of
software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
16
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
b15
b0
IPL
Flag register (FLG)
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.3.2. Flag register (FLG)
17
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
Rdeesveelotpment
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.4.1 shows the example reset circuit. Figure 1.4.2 shows the reset sequence.
5V
4.2V
V
CC
0V
5V
V
CC
RESET
RESET
0V
0.8V
Example when f(XIN) = 10MHz and VCC = 5V
.
Figure 1.4.1. Example reset circuit
X
IN
More than 20 cycles are needed
BCLK 24cycles
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
CS0
Single chip
mode
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 1.4.2. Reset sequence
18
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____________
Table 1.4.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.4.3 and 1.4.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.4.1. Pin status when RESET pin level is “L”
Status
CNVSS = VCC
Pin name
CNVSS = VSS
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
P1
Data input (floating)
Input port (floating)
P2, P3, P4
Address output (undefined)
Address output (undefined)
P5
P5
P5
P5
0
1
2
3
WR output (“H” level is output) WR output (“H” level is output)
BHE output (undefined) BHE output (undefined)
RD output (“H” level is output) RD output (“H” level is output)
BCLK output BCLK output
HLDA output (The output value HLDA output (The output value
P5
4
Input port (floating)
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P5
P5
P5
5
6
7
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
HOLD input (floating)
RAS output
HOLD input (floating)
RAS output
RDY input (floating)
Input port (floating)
RDY input (floating)
Input port (floating)
P6, P7, P8
0 to P84,
P8 , P8 , P9, P10,
6
7
P11, P12, P13,
P14, P15 (Note)
Input port (floating)
Input port (floating)
Input port (floating)
Note :Port P11 to P15 exist in 144-pin vrsion.
19
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
Rdeesveelotpment
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(30)
(31)
(32)
(33)
Timer B3 interrupt control register
INT5 interrupt control register
INT3 interrupt control register
INT1 interrupt control register
(1) Processor mode register 0 (Note1)
(000416)···
(000516)···
(000616)···
(000716)···
(000816)···
(000916)···
(000A16)···
8016
0016
0816
2016
FF16
0
(007816)···
(007A16)···
(007C16)···
(007E16)···
(008816)···
(008916)···
(008A16)···
(008B16)···
(008C16)···
(008D16)···
(008E16)···
(008F16)···
(009016)···
(009116)···
(009216)···
(009316)···
(009416)···
(009616)···
(009816)···
(009A16)···
(009C16)···
(009E16)···
(009F16)···
(02E016)···
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Wait control register
0
0
0
0
0
0 ?
?
(34)DMA1 interrupt control register
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Address match interrupt
enable register
UART2 transmit/NACK interrupt
(35)
(6)
0
0
0
0
0
0
0
?
control register
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
DMA3 interrupt control register
(7) Protect register
?
UART3 transmit/NACK interrupt
control register
External data bus width control
(8)
(000B16)···
(000C16)···
(000F16)··· 0
(001016)···
(001116)···
(001216)···
(001416)···
(001516)···
(001616)···
(001816)···
(001916)···
(001A16)···
(001C16)···
(001D16)···
(001E16)···
(004016)··· ?
(006816)···
(006916)···
?
0 0
?
register (Note 2)
Timer A1 interrupt control register
(9)
Main clock divided register
0
?
1
0 0
0
?
?
UART4 receive/NACK interrupt
control register
(10)
(11)
Watchdog timer control register
Address match interrupt register 0
0 0
? ? ?
?
Timer A3 interrupt control register
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
?
Bus collision detection(UART2)
interrupt control register
?
UART0 transmit interrupt control register
?
Bus collision detection(UART4)
interrupt control register
(12)
(13)
(14)
Address match interrupt register 1
Address match interrupt register 2
Address match interrupt register 3
?
UART1 transmit interrupt control register
Key input interrupt control register
Timer B0 interrupt control register
Timer B2 interrupt control register
?
?
?
?
(48)Timer B4 interrupt control register
?
(49)
(50)
(51)
(52)
(53)
INT4 interrupt control register
INT2 interrupt control register
INT0 interrupt control register
Exit priority register
0
0 ?
0 0 ? 0
0
0
0
0
0
0
0
0
?
0
0
0
(15)
(16)
(17)
DMAM control register
? ?
?
?
0
0
0
0
0
0
0
XY control register
0 0
?
?
?
?
0 0
DMA0 interrupt control register
Timer B5 interrupt control register
(54)
(55)
(56)
(57)
(58)
0
0
0
0
0
0
0
0
UART4 special mode register 3
UART4 special mode register 2
0016
0016
(02F516)···
(02F616)···
(18)DMA2 interrupt control register
(006A16)···
(006B16)···
(006C16)···
(006D16)···
(006E16)···
UART2 receive/ACK interrupt control
(19)
UART4 special mode register
(02F716)···
(02F816)···
0016
0016
register
UART4 transmit/receive mode register
UART4 transmit/receive control register 0
(20)
(21)
(22)
(23)
Timer A0 interrupt control register
? 0
? 0
UART3 receive/ACK interrupt control
register
(02FC16)···
(02FD16)···
(030016)···
(030816)···
0816
0216
(59) UART4 transmit/receive control register 1
?
0 0
Timer A2 interrupt control register
UART4 receive/ACK interrupt control
register
(60)
(61)
(62)
Timer B3,4,5 count start flag
0
0 0
? 0
? 0
0
0
0
0
(006F16)···
(007016)···
Three-phase PWM control register 0
Three-phase PWM control register 1
0016
(24)
(25)
(26)
(27)
Timer A4 interrupt control register
Bus collision detection(UART3)
interrupt control register
(030916)··· 0 0 0
0
?
0
0 0
? 0
? 0
0
0
0
0
(007116)···
(007216)···
UART0 receive interrupt control
register
(63)
(64)
(65)
Three-phase output buffer register 0
Three-phase output buffer register 1
Timer B3 mode register
(030A16)···
(030B16)···
(031B16)···
0016
0016
A-D conversion interrupt
control register
(007316)···
(007416)···
? 0
? 0
0
0
0
0
UART1 receive interrupt control
register
(28)
(29)
0
0
0
0 ?
0
0
0
0
0
0
0 0
(66)
(67)
Timer B4 mode register
Timer B5 mode register
(031C16)···
(031D16)···
Timer B1 interrupt control register
0
0
?
?
0
0
0
0
(007616)···
? 0
0
0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Note 2: When the BYTE pin is "L", the third bit is "1". When the BYTE pin is "H", the third bit is "0".
Figure 1.4.3. Device's internal status after a reset is cleared
20
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(68) Interrupt cause select register
(69) UART3 special mode register 3
(031F16)···
(032516)···
0 0 0 0 0 0
(112) Function select register A0
(03B016)··· 0
(03B116)···
0 0
0 0
0
0
0
0
0
0
Function select register A1
(113)
0
0 0
0016
(70)
(71)
(72)
(73)
(74)
(75)
(76)
(77)
(78)
(79)
(80)
(81)
(82)
(83)
(84)
(85)
(86)
(87)
(88)
(89)
(90)
(91)
(92)
(93)
(94)
(95)
(96)
(97)
(98)
(032616)···
(032716)···
Function select register B0
(114)
UART3 special mode register 2
(03B216)···
(03B316)···
(03B416)···
(03B516)···
(03B616)···
(03B716)··· 0
0016
0016
UART3 special mode register
(115)
(116)
Function select register B1
0
0
0
0
0
0
UART3 transmit/receive mode register
UART3 transmit/receive control register 0
UART3 transmit/receive control register 1
(032816)···
0016
0816
0216
Function select register A2
Function select register A3
Function select register B2
Function select register B3
(032C16)···
(032D16)···
0016
(117)
(118)
(119)
(120)
(121)
(122)
0
UART2 special mode register 3
UART2 special mode register 2
0
0
0 0
0
0 0
0 0
0
0 0
(033516)···
(033616)···
0016
0016
0016
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
(03C216)···
(03C316)···
0016
0016
UART2 special mode register
UART2 transmit/receive mode register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
Count start flag
(033716)···
(033816)···
(03C616)···
(03C716)···
(03CA16)···
0
0
0
0
0
0 0
(033C16)··· 0
(033D16)···
(034016)···
0
0 1 0 0 0
(123)
(124)
(125)
0016
0016
0216
0016
Port P11 direction register (Note 2)
Port P12 direction register (Note 2)
Port P13 direction register (Note 2)
Port P14 direction register (Note 2)
Port P15 direction register (Note 2)
Pull-up control register 2
(03CB16)···
(03CE16)···
(03CF16)···
(03D216)···
(03D316)···
(03DA16)···
(03DB16)···
(03DC16)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
0 0
Clock prescaler reset flag
(034116)···
(034216)···
(034316)···
(034416)···
0
(126)
(127)
(128)
(129)
(130)
(131)
(132)
(133)
0016
0016
0 0
One-shot start flag
0016
0016
0016
Trigger select flag
0
0
0
0
Up-down flag
0016
0016
0016
X016
0016
0016
0016
0016
0016
0016
Timer A0 mode register
(035616)··· 0 0 0
(035716)··· 0 0 0
(035816)··· 0 0 0
(035916)··· 0 0 0
0
0
0
0
0
0 ?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer A1 mode register
0 ?
0 ?
0 ?
0 ?
Pull-up control register 3 (Note 2)
Pull-up control register 4 (Note 2)
Port P0 direction register
Timer A2 mode register
Timer A3 mode register
(035A16)···
0
0 0
Timer A4 mode register
(132)
(135)
(136)
(137)
(138)
Port P1 direction register
(035B16)··· 0
0
0
0
?
?
?
0
0
0
0
0
0
Timer B0 mode register
Port P2 direction register
(035C16)···
(035D16)···
(036016)···
(036416)···
(036516)···
(036816)···
(036C16)···
(036D16)···
(037016)···
0
0
Timer B1 mode register
Port P3 direction register
Timer B2 mode register
Port P4 direction register
0016
0816
0216
0016
0816
0216
UART0 transmit/receive mode register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART1 transmit/receive mode register
UART1 transmit/receive control register 0
Port P5 direction register
(139)
(140)
(141)
(142)
(143)
(144)
(145)
(146)
(147)
(148)
Pull-up control register 0
(03F016)···
(03F116)···
0016
X016
Pull-up control register 1
Port control register
(03FF16)···
0
Data registers (R0/R1/R2/R3)
Address registers (A0/A1)
Static base register (SB)
000016
(99) UART1 transmit/receive control register 1
(100) UART transmit/receive control register 2
00000016
00000016
00000016
00000016
00000016
00000016
000016
0016
0
?
0 0
0
0
0
0
Frame base register (FB)
Interrupt table register (INTB)
User stack pointer (USP)
(101)
(102)
(103)
(104)
(105)
Flash memory control register 1 (Note 1)
Flash memory control register 0 (Note 1)
DMA0 cause select register
(037616)··· ?
(037716)···
?
0
?
0
?
0
0
0
0
0
?
0
0
0
?
1
0
0
(037816)··· 0
(037916)··· 0
0 0 0
Interrupt stack pointer (ISP)
0
0
0
0
0
0
0
0
0
0
0
0
DMA1 cause select register
(149) Flag register (FLG)
(037A16)··· 0
(037B16)··· 0
(039416)··· 0
(039616)··· 0
(039716)···
0
0
0
0
0
0
0
?
DMA2 cause select register
(150)
(151)
(152)
(153)
DMA mode register (DMD0/DMD1)
(106) DMA3 cause select register
DMA transfer count register (DCT0/DCT1)
??
0
0
(107)
A-D control register 2
A-D control register 0
A-D control register 1
DMA transfer count reload register
(DRC0/DRC1)
??
0 0
0016
0016
?
?
(108)
(109)
DMA memory address register (DMA0/DMA1)
??
(154) DMA SFR address register (DSA0/DSA1)
(110)
(111)
(039C16)···
??
D-A control register
DMA memory address reload register
(155)
Function select register C
(03AF16)···
0
0
??
(DRA0/DRA1)
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
x : Nothing is mapped to this bit
? : Undefined
Note 1:This register exists in the flash memory version.
Note 2:This register exists in 144-pin version.
Figure 1.4.4. Device's internal status after a reset is cleared
21
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
e
d
n
pment
o
U
l
e
M16C/80 group
v
e
SdFR
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016
000116
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Wait control register (WCR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
External data bus width control register (DS)
DMA0 interrupt control register (DM0IC)
Timer B5 interrupt control register (TB5IC)
DMA2 interrupt control register (DM1IC)
UART2 receive/ACK interrupt control register (S2RIC)
Timer A0 interrupt control register (TA0IC)
UART3 receive/ACK interrupt control register (S3RIC)
Timer A2 interrupt control register (TA2IC)
UART4 receive/ACK interrupt control register (S4RIC)
Timer A4 interrupt control register (TA4IC)
Bus collision detection(UART3) interrupt control register (BCN3IC)
Main clock division register (MCD)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
UART0 receive interrupt control register (S0RIC)
A-D conversion interrupt control register (ADIC)
UART1 receive interrupt control register (S1RIC)
Address match interrupt register 1 (RMAD1)
Timer B1 interrupt control register (TB1IC)
Timer B3 interrupt control register (TB3IC)
INT5 interrupt control register (INT5IC)
INT3 interrupt control register (INT3IC)
INT1 interrupt control register (INT1IC)
Address match interrupt register 2 (RMAD2)
Address match interrupt register 3 (RMAD3)
002116 Emulator interrupt vector table register (EIAD)
002216
*
002316
Emulator interrupt detect register (EITD)
*
002416
Emulator protect register (EPRR)
*
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
DMA1 interrupt control register (DM1IC)
UART2 transmit/NACK interrupt control register (S2TIC)
DMA3 interrupt control register (DM3IC)
UART3 transmit/NACK interrupt control register (S3TIC)
Timer A1 interrupt control register (TA1IC)
UART4 transmit/NACK interrupt control register (S4TIC)
Timer A3 interrupt control register (TA3IC)
Bus collision detection(UART2) interrupt control register (BCN2IC)
UART0 transmit interrupt control register (S0TIC)
Bus collision detection(UART4) interrupt control register (BCN4IC)
UART1 transmit interrupt control register (S1TIC)
Key input interrupt control register (KUPIC)
003016
ROM areaset register (ROA)
Debug monitor area set register (DBA)
*
003116
*
003216
Expansion area set register 0 (EXA0)
Expansion area set register 1 (EXA1)
Expansion area set register 2 (EXA2)
Expansion area set register 3 (EXA3)
*
003316
*
003416
Timer B0 interrupt control register (TB0IC)
*
003516
*
003616
Timer B2 interrupt control register (TB2IC)
Timer B4 interrupt control register (TB4IC)
INT4 interrupt control register (INT4IC)
INT2 interrupt control register (INT2IC)
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
INT0 interrupt control register (INT0IC)
Exit priority register (RLVL)
004016
DRAM control register (DRAMCONT)
DRAM refresh interval set register (REFCNT)
004116
004216
004316
004416
As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register.
(The blank area is reserved and cannot be used by user.)
*
Figure 1.5.1. Location of peripheral unit control registers (1)
22
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
SdFevRelopment
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
030016
Timer B3, 4, 5 count start flag (TBSR)
X0 register (X0R) Y0 register (Y0R)
X1 register (X1R) Y1 register (Y1R)
X2 register (X2R) Y2 register (Y2R)
X3 register (X3R) Y3 register (Y3R)
X4 register (X4R) Y4 register (Y4R)
X5 register (X5R) Y5 register (Y5R)
X6 register (X6R) Y6 register (Y6R)
X7 register (X7R) Y7 register (Y7R)
X8 register (X8R) Y8 register (Y8R)
X9 register (X9R) Y9 register (Y9R)
X10 register (X10R) Y10 register (Y10R)
X11 register (X11R) Y11 register (Y11R)
X12 register (X12R) Y12 register (Y12R)
X13 register (X13R) Y13 register (Y13R)
X14 register (X14R) Y14 register (Y14R)
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Timer A4-1 register (TA41)
Three-phase PWM control register 0(INVC0)
Three-phase PWM control register 1(INVC1)
Thrree-phase output buffer register 0(IDB0)
Thrree-phase output buffer register 1(IDB1)
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
X15 register (X15R) Y15 register (Y15R)
XY control register (XYC)
Interrupt cause select register (IFSR)
UART3 special mode register 3 (U3SMR3)
UART3 special mode register 2 (U3SMR2)
032716 UART3 special mode register (U3SMR)
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
UART3 transmit/receive mode register (U3MR)
UART3 bit rate generator (U3BRG)
UART3 transmit buffer register (U3TB)
UART3 transmit/receive control register 0 (U3C0)
UART3 transmit/receive control register 1 (U3C1)
UART3 receive buffer register (U3RB)
UART4 special mode register 3 (U4SMR3)
UART4 special mode register 2 (U4SMR2)
UART4 special mode register (U4SMR)
UART4 transmit/receive mode register (U4MR)
UART4 bit rate generator (U4BRG)
UART2 special mode register 3 (U2SMR3)
UART2 special mode register 2 (U2SMR2)
033716 UART2 special mode register (U2SMR)
033816
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
033916
033A16
033B16
033C16
033D16
033E16
033F16
UART4 transmit buffer register (U4TB)
UART2 transmit buffer register (U2TB)
UART4 transmit/receive control register 0 (U4C0)
UART4 transmit/receive control register 1 (U4C1)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
UART4 receive buffer register (U4RB)
UART2 receive buffer register (U2RB)
(The blank area is reserved and cannot be used by user.)
Figure 1.5.2. Location of peripheral unit control registers (2)
23
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
SdFevRelopment
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
034016
034116
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Count start flag (TABSR)
A-D register 0 (AD0)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer A3 register (TA3)
Timer A4 register (TA4)
Timer B0 register (TB0)
Timer B1 register (TB1)
Timer B2 register (TB2)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
Function select register C(PSC)
Function select register A0 (PS0)
Function select register A1 (PS1)
Function select register B0 (PSL0)
Function select register B1 (PSL1)
Function select register A2 (PS2)
Function select register A3 (PS3)
Function select register B2 (PSL2)
Function select register B3 (PSL3)
UART transmit/receive control register 2 (UCON2)
Flash memory control register 1 (FMR1) (Note)
Flash memory control register 0 (FMR0) (Note)
DMA0 request cause select register (DM0SL)
DMA1 request cause select register (DM1SL)
DMA2 request cause select register (DM2SL)
DMA3 request cause select register (DM3SL)
CRC data register (CRCD)
CRC input register (CRCIN)
(The blank area is reserved and cannot be used by user.)
Note :This register exists in the flash memory version.
Figure 1.5.3. Location of peripheral unit control registers (3)
24
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
SdFevRelopment
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
<100-pin version>
<144-pin version>
03C016
03C016
Port P6 (P6)
Port P7 (P7)
Port P6 (P6)
Port P7 (P7)
03C116
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P11 (P11)
Port P10 direction register (PD10)
Port P11 direction register (PD11)
Port P12 (P12)
Port P13 (P13)
Port P12 direction register (PD12)
Port P13 direction register (PD13)
Port P14 (P14)
Port P15 (P15)
Port P14 direction register (PD14)
Port P15 direction register (PD15)
Port P9 (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 2 (PUR2)
Pull-up control register 3 (PUR3)
Pull-up control register 2 (PUR2)
Pull-up control register 3 (PUR3)
Pull-up control register 4 (PUR4)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
03FC16
03FD16
03FE16
03FF16
03FC16
03FD16
03FE16
03FF16
Port control register (PCR)
Port control register (PCR)
(The blank area is reserved and cannot be used by user.)
Note 1:
Note 2:
Addresses 03C916, 03CB16 to 03D316 area is for future plan.
Must set "FF16" to address 03CB16, 03CE16, 03CF16, 03D216, 03D316 at initial setting.
Address 03DC16 area is for future plan. Must set "0016" to address 03DC16 at initial setting.
Figure 1.5.4. Location of peripheral unit control registers (4)
25
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
e
d
n
U
M16C/80 group
Sdoefvtewlopamreent Reset
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1.
Figure 1.6.3 shows the memory maps applicable for each processor modes.
26
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Address
000416
When reset
8016 (Note 2)
0
R W
Bit symbol
PM00
Bit name
Function
b1 b0
Processor mode bit
(Note 8)
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
PM01
PM02
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
R/W mode select bit
(Note 7)
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
PM03
PM04
PM05
Software reset bit
b5 b4
Multiplexed bus space
select bit (Note 3)
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
Must always be set to “0”
Reserved bit
PM07
0 : BCLK is output (Note 6)
1 : Function set by bit 0,1 of system
clock control register 0
BCLK output disable bit
(Note 5)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 is set
to “1” and PM07 is set to “0”.)
Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when
mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a
result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in
microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and
bit 1 (CM01) of system clock control register 0 (address 000616) = "0". "L" is now output from P5
Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 7: When using 16-bit bus width in DRAM controller, set this bit to "1".
3.
Note 8: Do not set the processor mode bits and other bits simultaneously when setting the processor mode
bits to “01 ” or “11 ”. Set the other bits first, and then change the processor mode bits.
2
2
Figure 1.6.1. Processor mode register 0
27
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 1 (Note 1) :Mask ROM version
ROMless version (144-pin version)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
0016
0
Bit symbol
PM10
Bit name
Function
R W
b1 b0
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
: A20
to P4
, P4
, P4
1 1 : Mode 3 (Note 2)
(P4 to P4 : CS3 to CS0)
7 : A20 to A23)
0 1 : Mode 1 (P4
4
,
P4
5
7
: CS2 to CS0)
: A20, A21
7 : CS1, CS0)
1 0 : Mode 2 (P4
4
5
,
PM11
PM12
P4
6
4
7
Internal memory wait bit
ALE pin select bit (Note 3)
0 : No wait state
1 : Wait state inserted
Must always be set to “0”
Reserved bit
PM14
b5 b4
0 0 : No ALE
0 1 : P5
1 0 : P5
1 1 : P5
3
6
4
/BCLK (Note 4)
/RAS
/HLDA
PM15
Nothing is assinged. When read, the content is indeterminate.
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P53/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Processor mode register 1 (Note 1) :Flash memory version
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
0016
0
R W
Bit symbol
PM10
Bit name
Function
b1 b0
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
: A20
to P4
, P4
, P4
1 1 : Mode 3 (Note 2)
(P4 to P4 : CS3 to CS0)
7 : A20 to A23)
0 1 : Mode 1 (P4
4
,
P4
5
7
: CS2 to CS0)
: A20, A21
7 : CS1, CS0)
1 0 : Mode 2 (P4
4
5
,
PM11
PM12
P4
6
4
7
Internal memory wait bit
ALE pin select bit (Note 3)
0 : No wait state
1 : Wait state inserted
Reserved bit
PM14
Must always be set to “0”
b5 b4
0 0 : No ALE
0 1 : P5
1 0 : P5
1 1 : P5
3
6
4
/BCLK (Note 4)
/RAS
/HLDA
PM15
Must always be set to “1” (Note 5)
Reserved bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
3/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 5: Rewrite this bit when the main clock is in division by 8 mode.
Figure 1.6.2. Processor mode register 1
28
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P
Processor Mode
Figure 1.6.3. Memory maps in each processor mode
29
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Bus Settings
The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the
processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address
000516) are used to change the bus settings.
Table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width
control register and table 1.7.2 shows external area 0 to 3 and external area mode.
Table 1.7.1. Factors for switching bus settings
Bus setting
Switching factor
External data bus width control register
BYTE pin (external area 3 only)
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
You can select the width of the address bus output externally from the 16 Mbytes address space, the
number of chip select signals, and the address area of the chip select signals. (Note, however, that when
____
you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits 0 and
1 of the processor mode register 1 allow you to set the external area mode.
When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and
column addresses.
(2) Selecting external data bus width
You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When
the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;
when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for
external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after
a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits).
During operation, fix the level of the BYTE pin to “H” or “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this bus configuration, input and output is performed on separate data and address buses. The data
bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all
programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is
a programmable IO port. When the external data bus width is set to 16 bits for any of the external
areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus.
When accessing memory using the separate bus configuration, you can select a software wait using
the wait control register.
• Multiplex bus
In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas
for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7
are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the external
data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to A15. When
accessing memory using the multiplex bus configuration, two waits are inserted regardless of whether
you select “No wait” or “1 wait’ in the appropriate bit of the wait control register.
30
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
____
The default after a reset is the separate bus configuration, and the full CS space multiplex bus configu-
____
ration cannot be selected in microprocessor mode. If you select “Full CS space multiplex bus”, the 16
bits from A0 to A15 are output for the address
External data bus width control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DS
Address
000B16
When reset
XXXXX000
2
R W
Bit symbol
DS0
Bit name
Function
External area 0 data bus
width bit
0 : 8 bits data bus width
1 : 16 bits data bus width
External area 1 data bus
width bit
0 : 8 bits data bus width
1 : 16 bits data bus width
0 : 8 bits data bus width
1 : 16 bits data bus width
DS1
DS2
External area 2 data bus
width bit
0 : 8 bits data bus width
1 : 16 bits data bus width
External area 3 data bus
width bit (Note)
DS3
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: The value after a reset is determined by the input via the BYTE pin.
Figure 1.7.1. External data bus width control register
Table 1.7.2. External area 0 to 3 and external area mode
External area mode
Mode 0
(Note 2)
Mode 1
Mode 2
Mode 3
<CS1 area>
10000016 to
1FFFFF16
<CS1 area>
00800016 to
1FFFFF16
<CS1 area>
00800016 to
1FFFFF16
Memory expansion mode
Microprocessor mode
,
00800016 to
1FFFFF16
<CS2 area>
20000016 to
3FFFFF16
<CS2 area>
20000016 to
2FFFFF16
20000016 to
3FFFFF16
No area is
selected.
Memory expansion mode
Microprocessor mode
,
<CS3 area>
C0000016 to
CFFFFF16
<DRAMC area>
40000016 to
BFFFFF16
Memory expansion mode
Microprocessor mode
,
<DRAMC area>
40000016 to
BFFFFF16
40000016 to
BFFFFF16
(Note 1)
<CS0 area>
C0000016 to
EFFFFF16
<CS0 area>
C0000016 to
EFFFFF16
<CS0 area>
E0000016 to
EFFFFF16
C0000016 to
EFFFFF16
Memory expansion mode
Microprocessor mode
<CS0 area>
E0000016 to
FFFFFF16
<CS0 area>
F0000016 to
FFFFFF16
<CS0 area>
C0000016 to
FFFFFF16
C0000016 to
FFFFFF16
Note 1: DRAMC area when using DRAMC.
Note 2: Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register
1 (address 000516).
31
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Table 1.7.3. Each processor mode and port function
Processor
mode
Single-chip
mode
Memory
expansion mode
Memory expansion mode/microprocessor modes
Multiplexed
bus space
select bit
“11” (Note 1)
“00”
“01”, “10”
CS1 or CS2 : multiplexed
bus, and the other :
separate bus
Separate bus
All space multiplexed
bus
Data bus width
BYTE pin level
Some external
area is 16 bits area is 8 bits
All external
All external
area is 8 bits
All external
area is 8 bits
Some external
area is 16 bits
Some external
area is 16 bits
P0
0
to P0
7
I/O port
Data bus
I/O port
Data bus
Data bus
Data bus
I/O port
I/O port
I/O port
P1
0
to P1
7
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P2
0
0
to P2
7
7
Address bus
/data bus
(Note 2)
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
/data bus
Address bus
/data bus
P3
to P3
I/O port
Address bus
Address bus
/data bus
(Note 2)
Address bus
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
/data bus
P4
0
to P4
3
I/O port
I/O port
Address bus
Address bus
I/O port
P4
4
7
to P4
6
CS (chip select) or address bus (A20 to A22
)
(For details, refer to “Bus control”) (Note 5)
P4
I/O port
I/O port
CS (chip select) or address bus (A23
)
(For details, refer to “Bus control”) (Note 5)
Outputs RD, WRL, WRH and BCLK, or RD, BHE, WR and BCLK
(For details, refer to “Bus control”) (Note 3,4)
P50 to P53
P5
4
I/O port
I/O port
I/O port
HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3)
P5
5
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
P5
P5
6
7
RAS (Note 3)
RAS (Note 3) RAS (Note 3) RAS (Note 3)
RAS (Note 3) RAS (Note 3)
I/O port
RDY
RDY
RDY
RDY
RDY
RDY
Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and
BCLK outputs.
Note 5: The CS signal and address bus selection are set by the external area mode.
32
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode.
(1) Address bus/data bus
____
____
There are 24 pins, A0 to A22 and A23 for the address bus for accessing the 16 Mbytes address space. A23
is an inverted output of the MSB of the address.
The data bus consists of pins for data IO. The external data bus control register (address 000B16) selects
the 8-bit data bus, D0 to D7 for each external area, or the 16-bit data bus, D0 to D15. After a reset, there is
by default an 8-bit data bus for the external area 3 when the BYTE pin is “H”, or a 16-bit data bus when the
BYTE pin is “L”.
When shifting from single-chip mode to extended memory mode, the value on the address bus is unde-
fined until an external area is accessed.
When accessing a DRAM area with DRAM control in use, a multiplexed signal consisting of row address
and column address is output to A8 to A20.
(2) Chip select signals
____
The chip select signals share A0 to A22 and A23. You can use bits 0 and 1 of the processor mode register
1 (address 000516) to set the external area mode, then select the chip select area and number of address
outputs.
In microprocessor mode, external area mode 0 is selected after a reset. The external area can be split
into a maximum of four using the chip select signals. Table 1.7.4 shows the external areas specified by
the chip select signals.
Table 1.7.4. External areas specified by the chip select signals
Memory space
expansion
mode
Chip select signal
Processor mode
CS0
CS1
CS2
CS3
Mode 0
Mode 1
(A22)
(A21)
(A20)
(A23)
C0000016 to
DFFFFF16
(2 Mbytes)
Memory expansion mode
00800016 to
1FFFFF16
(2016 Kbytes)
20000016 to
3FFFFF16
(2 Mbytes)
E0000016 to
FFFFFF16
(2 Mbytes)
(A20)
(A20)
Microprocessor mode
C0000016 to
EFFFFF16
(3 Mbytes)
Memory expansion mode
00800016 to
3FFFFF16
(4064 Kbytes)
Mode 2
Mode 3
C0000016 to
FFFFFF16
(4 Mbytes)
(A21)
Microprocessor mode
E0000016 to
EFFFFF16
(1 Mbytes)
Memory expansion mode
C0000016 to
CFFFFF16
(1 Mbytes)
20000016 to
2FFFFF16
(1 Mbytes)
10000016 to
1FFFFF16
(1 Mbytes)
F0000016 to
FFFFFF16
(1 Mbytes)
Microprocessor mode
33
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
The chip select signal turns “L” (active) in synchronize with the address bus. However, its turning “H”
depends on the area accessed in the next cycle. Figure 1.7.2 shows the output examples of the address
bus and chip select signals.
(Example 2) After accessing the external area, only the chip select signal
is changed in the next cycle. (The address bus does not
change.)
(Example 1) After accessing the external area, the address bus and chip
select signal both are changed in the next cycle.
The following example shows the other chip select signal accessing
area (j) in the cycle after having accessed external area (i). In this
case, the address bus and chip select signal both change between the
two cycles.
The following example shows the CPU accesses the internal
ROM/RAM area in the cycle after having accessed external
area. In this case, the chip select signal changes between the
two cycles but the address bus does not.
Access to
external
area (j)
Access to
external
area (i)
Data bus
Data
Data
Data
Data bus
Address bus
Address bus
Address
Address
Chip select
(CSi)
Chip select
Chip select
(CSj)
(Example 3) After accessing the external area, only the address bus is
changed in the next cycle. (The chip select signal does not
change.)
(Example 4) After accessing the external area, the address bus and chip
select signal both are not changed in the next cycle.
The following example shows CPU does not access any
area in the cycle after having accessed external area (no
instruction pre-fetch is occurred). In this case, the address
bus and the chip select signal do not change between the
two cycles.
The following example shows the same chip select signal
accessing area (i) in the cycle after having accessed
external area (i). In this case, the address bus changes
between the two cycles, but the chip select signal does not.
Access to
external
area (i)
Access to
external
area (i)
Access to
external
area
No access
Data
Data bus
Data
Address
Data
Data bus
Address bus
Chip select
Address bus
Address
Chip select
(CSi)
Note: These examples show the address bus and chip select signal for two consecutive cycles.
By combining these examples, chip select signal can be extended beyond two cycles.
Figure 1.7.2. Example of address bus and chip select signal outputs (Separate bus)
34
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(3) Read/write signals
With a 16-bit data bus, bit 2 of the processor mode register 0 (address 000416) select the combinations of
_____ ________
______
_____ ________
_________
RD, BHE, and WR signals or RD, WRL, and WRH signals. With a 8-bit full space data bus, use the
_____ ______
________
combination of RD, WR, and BHE signals as read/write signals. (Set "0" to bit 2 of the processor mode
register 0 (address 000416).) When using both 8-bit and 16-bit data bus widths and you access an 8-bit
_____ ______
________
data bus area, the RD, WR and BHE signals combination is selected regardless of the value of bit 2 of the
processor mode register 0 (address 000416).
Tables 1.7.5 and 1.7.6 show the operation of these signals.
_____ ______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________
_________
Note 2: When using 16-bit data bus width for DRAM controller, select RD, WRL, and WRH signals.
_____ ________
_________
Table 1.7.5. Operation of RD, WRL, and WRH signals
Data bus width
Status of external data bus
RD
L
WRL
H
WRH
H
Read data
H
H
H
H
L
L
H
H
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Write 1 byte of data
16-bit
L
L
L
L (Note)
H (Note)
Not used
Not used
8-bit
Read 1 byte of data
______
Note: It becomes WR signal.
_____ ______
________
Table 1.7.6. Operation of RD, WR, and BHE signals
Data bus width
A0
H
H
L
Status of external data bus
Write 1 byte of data to odd address
RD
H
L
WR
L
BHE
L
H
L
L
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
H
L
H
16-bit
H
L
H
L
H
L
L
L
H
L
L
L
H
L
Not used
Not used
H / L
H / L
Write 1 byte of data
Read 1 byte of data
8-bit
H
35
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls. The ALE output pin is selected using bits 4 and 5 of the processor mode register 1
(address 000516).
The ALE signal is occurred regardless of internal area and external area.
When BYTE pin = “L”
When BYTE pin = “H”
ALE
ALE
/A
Address
Data (Note 1)
D
0
0
to D
7
/A
7
D
0/A0 to D15/A15
Address
Data (Note 1)
A
A
A
8 to A15
Address
A
A
16 to A19
Address (Note 2)
16 to A19
Address (Note 2)
Address or CS
20 to A22, A23
Address or CS
20 to A22, A23
Note 1: Floating when reading.
Note 2: When full space multiplexed bus is selected, these are I/O ports.
Figure 1.7.3. ALE signal and address/data bus
(5) Ready signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
________
Figure 1.7.2, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter
________
the ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table
_____
1.7.7 shows the microcomputer status in the ready state. Figure 1.7.4 shows the example of the RD
________
signal being extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is ap-
________
plied. When no software wait is operating, the RDY signal is ignored, but even in this case, unused pins
must be pulled up.
Table 1.7.7. Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
_____ _____
_____
RD/WR signal, address bus, data bus, CS
Maintain status when ready signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
Note: The ready signal cannot be received immediately prior to a software wait.
36
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Separate bus (2 wait)
1st cycle
2nd cycle
3rd cycle
4th cycle
BCLK
RD
(Note)
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
RDY received timing
3rd cycle
Multiplexed bus (2 wait)
1st cycle
2nd cycle
4th cycle
BCLK
RD
(Note)
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
RDY received timing
: Wait using RDY signal
: Wait using software
RDY signal received timing for i wait(s): i + 1 cycles
(i = 1 to 3)
Note: Chip select may get longer by a state of CPU such as an instruction queue buffer.
_____
________
Figure 1.7.4. Example of RD signal extended by RDY signal
37
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.7.8
shows the microcomputer status in the hold state. The bus is used in the following descending order of
__________
priority: HOLD, DMAC, CPU.
__________
HOLD > DMAC > CPU
_____
________
Figure 1.7.5. Example of RD signal extended by RDY signal
Table 1.7.8. Microcomputer status in hold state
Item
Status
Oscillation
ON
_____ _____
_____ _______
RD/WR signal, address bus, data bus, CS, BHE
Programmable I/O ports P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Floating
Maintains status when hold signal is received
P11, P12, P13, P14, P15 (Note)
__________
HLDA
Output “L”
Internal peripheral circuits
ALE signal
ON (but watchdog timer stops)
Undefined
Note: Ports P11 to P15 exist in 144-pin version.
(7) External bus status when accessing to internal area
Table 1.7.9 shows external bus status when accessing to internal area
Table 1.7.9. External bus status when accessing to internal area
Item
SFR accessing status
Internal ROM/RAM accessing status
Address bus
Remain address of external area accessed immediately before
Data bus When read Floating
When write Floating
_____ ______ ________ _________
RD, WR, WRL, WRH Output "H"
________
BHE
Remain external area status accessed immediately before
____
CS
Output "H"
ALE output
ALE
(8) BCLK output
BCLK output can be selected by bit 7 of the processor mode register 0 (address 000416 :PM07) and bit 1
and bit 0 of the system clock select register 0 (address 000616 :CM01, CM00). Setting PM07 to “0” and
CM01 and CM00 to “00” outputs the BCLK signal from P53. However, in single chip mode, BCLK signal
is not output. When setting PM07 to “1”, the function is as set by CM01 and CM00.
38
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
_______
__________
_____
(9) DRAM controller signals (RAS, _C__A___S__L__, CASH, and DW)
Bits 1, 2, and 3 of the DRAM control register (address 000416) select the DRAM space and enable the
DRAM controller. The DRAM controller signals are then output when the DRAM area is accessed. Table
1.7.10 shows the operation of the respective signals.
_______ __________ __________
_____
Table 1.7.10. Operation of RAS, CASL, CASH, and DW signals
Data bus width
DW
H
H
H
L
Status of external data bus
Read data from both even and odd addresses
Read 1 byte of data from even address
Read 1 byte of data from odd address
Write data to both even and odd addresses
Write 1 byte of data to even address
Write 1 byte of data to odd address
Read 1 byte of data
RAS
CASL
CASH
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
16-bit
L
H
L
L
L
Not used
Not used
H
L
8-bit
Write 1 byte of data
(10) Software wait
A software wait can be inserted by setting the wait control register (address 000816). Figure 1.7.6 shows
wait control register
You can use the external area I wait bits (where I = 0 to 3) of the wait control register to specify from “No
wait” to “3 waits” for the external memory area. When you select “No wait”, the read cycle is executed in
the BCLK1 cycle. The write cycle is executed in the BCLK2 cycle (which has 1 wait). When accessing
external memory using the multiplex bus, access has two waits regardless of whether you specify “No
wait” or “1 wait” in the appropriate external area i wait bits in the wait control register.
Software waits in the internal memory (internal RAM and internal ROM) can be set using the internal
memory wait bits of the processor mode register 1 (address 000516). Setting the internal memory wait bit
= “0” sets “No wait”. Setting the internal memory wait bit = “1” specifies a wait.
The SFR area is not affected by the setting of the internal memory wait bit and is always accessed in the
BCLK2 cycle.
Table 1.7.11 shows the software waits and bus cycles. Figures 1.7.7 and 1.7.8 show example bus timings
when using software waits.
39
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Wait control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WCR
Address
000816
When reset
FF16
R W
Bit symbol
WCR0
Bit name
Function
b1 b0
External area 0 wait bit
0 0: Without wait
0 1: With 1 wait
1 0: With 2 wait
1 1: With 3 wait
WCR1
WCR2
WCR
b3 b2
External area 1 wait bit
0 0: Without wait
0 1: With 1 wait
1 0: With 2 wait
1 1: With 3 wait
b5 b4
WCR4
WCR5
0 0: Without wait
External area 2 wait bit
External area 3 wait bit
0 1: With 1 wait
1 0: With 2 wait
1 1: With 3 wait
b7 b6
WCR6
WCR7
0 0: Without wait
0 1: With 1 wait
1 0: With 2 wait
1 1: With 3 wait
Note 1: When using the multiplex bus configuration, there are two waits regardless of whether
you have specified "No wait" or "1 wait". However, you can specify "2 wait" or "3 wait".
Note 2: When using the separate bus configuration, the read bus cycle is executed in the
BCLK1 cycle, and the write cycle is executed in the BCLK2 cycle (with 1 wait).
Figure 1.7.6. Wait control register
Table 1.7.11. Software waits and bus cycles
Internal
memory wait bit
External memory
area i wait bit
Bus cycle
2 BCLK cycles
Area
SFR
Bus status
0
1
1 BCLK cycle
Internal
ROM/RAM
2 BCLK cycles
Read :1 BCLK cycle
Write : 2 BCLK cycles
002
2 BCLK cycles
3 BCLK cycles
Separate bus
01
10
11
00
01
10
11
2
2
2
2
2
2
2
External
memory
area
4 BCLK cycles
3 BCLK cycle
3 BCLK cycles
Multiplex bus
3 BCLK cycles
4 BCLK cycles
40
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (no wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Input
Output
Address bus (Note 2)
Chip select (Note 2,3)
Address
Address
< Separate bus (with wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Input
Output
Data bus
Address bus (Note 2)
Address
Address
Chip select (Note 2,3)
< Separate bus with 2 wait >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
Data output
Address
Input
Data bus
Address
Address bus (Note 2)
Chip select (Note 2,3)
Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.
Figure 1.7.7. Typical bus timings using software wait
41
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (with 3 wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Data bus
Input
Data output
Address
Address
(Note 2)
Address
Chip select
(Note 2,3)
< Multiplexed bus (with 2 wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
ALE
Address
Address
Data output
Address
Address bus/Data bus
(Note 2)
Address
Address
Input
Chip select
(Note 2,3)
< Multiplexed bus (with 3 wait) >
Bus cycle (Note)
Bus cycle (Note)
BCLK
Write signal
Read signal
Address
Address
Address
Address bus
/Data bus
(Note 2)
Input
Address
Data output
Address
ALE
Chip select
(Note 2,3)
Note 1: This timing example shows bus cycle length. Read cycle and write cycle may be continued after this
bus cycle.
Note 2: Address bus and chip select may get longer by a state of CPU such as an instruction queue buffer.
Note 3: When accessing same external area (same CS area) continuously, chip select may output
continuously.
Figure 1.7.8. Typical bus timings using software wait
42
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.8.1. Main clock and sub clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub clock generating circuit
• CPU’s operating clock source
• Timer A/B’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.8.2 shows some examples
of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.8.1 and 1.8.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistance)
Microcomputer
(Built-in feedback resistance)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation
drive capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Insert a feedback resistance between XIN and XOUT when an oscillation manufacture required.
Figure 1.8.1. Examples of main clock
Microcomputer
(Built-in feedback resistance)
Microcomputer
(Built-in feedback resistance)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistance if required. The resistance will vary depending on the oscillator and the oscillation
drive capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Insert a feedback resistance between XCIN and XCOUT when an oscillation manufacture required.
Figure 1.8.2. Examples of sub clock
43
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.8.3 shows the block diagram of the clock generating circuit.
XCIN
X
COUT
fC32
1/32
f
1
CM04
f
1
SIO2
SIO2
f
AD
f
C
f
8
f
8
Sub clock
f
32SIO2
CM10 “1”
Write signal
f
32
S Q
R
X
IN
XOUT
b
c
a
Divider 1
RESET
Software reset
NMI
Main clock
CM02
CM07=0
e
d
Divider 2
CM05
Interrupt request
level judgment
output
f
C
BCLK
CM07=1
S Q
R
WAIT instruction
c
b
1/2
1/2
1/2
1/2
1/2
a
Details of divider 1
1/N divider
e
a
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
N is set by MCD4 to MCD0 as follow:
N = 1, 2, 3, 4, 6, 8, 10, 12, 14 and 16
Details of divider 2
Figure 1.8.3. Clock generating circuit
44
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Switching to
the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power
dissipation.
When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to stop mode (bit 0 at
address 000716 =1), the main clock division register (address 000C16) is set to the division by 8 ("0816").
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
defaults to “1” when shifting from high-speed or middle-speed mode to stop mode and after a reset.
This bit remains in low-speed and low power dissipation mode.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
When the sub clock is used, set ports P86 and P87 to no pull-up resistance with the input port.
(3) BCLK
The BCLK is the clock that drives the CPU, and is either fc or is derived by dividing the main clock by 1,
2, 3, 4, 6, 8, 10, 12, 14 or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
This signal is output from BCLK pin using CM01, CM00 and PM07 in memory expansion mode and
microprocessor mode.
When main clock is stoped or shifting to stop mode, the main clock division register (address 000C16) is
set to the division by 8 ("0816").
(4) Peripheral function clock
• f1, f8, f32, f1SIO2, f8SIO2, f32SIO2
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
• fAD
This clock has the same frequency as the main clock and is used for A-D conversion.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) f
C
This clock has the same frequency as the sub clock. It is used for BCLK and for the watchdog timer.
Figure 1.8.4 shows the system clock control registers 0 and 1 and figure 1.8.5 shows main clock division
register.
45
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
0816
Bit symbol
Bit
Function
0 0 : I/O port P5
R W
name
b1 b0
Clock output function
CM00
3
select bit (Note 2)
0 1 : f
1 0 : f
C
output (Note 3)
output (Note 3)
8
CM01
CM02
1 1 : f32 output (Note 3)
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral clock in wait
mode
1 : Stop peripheral clock in wait mode
(Note 10)
X
CIN-XCOUT drive capacity
0 : LOW
1 : HIGH
CM03
select bit (Note 4)
Port X select bit
C
0 : I/O port
1 : XCIN-XCOUT generation (Note 11)
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 5, 6)
)
0 : On
1 : Off (Note 7)
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Reset (Note 8)
CM06
CM07
System clock select bit
(Note 9)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: When outputting BCLK (bit 7 of processor mode register 0 is "0"), set these bits to "00". When
outputting ALE to P5 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". The
port P5 function is not selected even when you set "00" in microprocessor or memory expansion
mode and bit 7 of the processor mode register 0 is "1".
Note 3: When selecting f , f or f32 in single chip mode, must use P5
Note 4: Changes to “1” when shifting to stop mode or reset.
3
3
C
8
7 as input port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop the main
clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is stable. Then set this
bit to "1".
Note 6: When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so XIN is pulled
up to XOUT ("H" level) via the feedback resistance.
Note 7: When the main clock is stopped, the main clock division register (address 000C16) is set to the
division by 8 mode.
Note 8: When "1" has been set once, "0" cannot be written by software.
Note 9: To set CM07 "1" from "0", first set CM04 to "1", and an oscillation of sub clock is stable. Then set
CM07. Do not set CM04 and CM07 simultaneously. Also, to set CM07 "0" from "1", first set CM05
to "1", and an oscillation of main clock is stable. Then set CM07.
Note 10: fc32 is not included.
Note 11: When XcIN-XcOUT is used, set port P8
6
and P8
7
to no pull-up resistance with the input port.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
0
0
Bit symbol
CM10
Bit
Function
R W
name
0 : Clock on
All clock stop control bit
1 : All clocks off (stop mode) (Note 4)
(Note 3)
Reserved bit
CM15
Always set to “0”
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
select bit (Note 2)
Reserved bit
Always set to “0”
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting from high-speed or middle-speed mode to stop mode or reset.
This bit is remained in low speed or low power dissipation mode.
Note 3: When this bit is "1", XOUT is "H", and the internal feedback resistance is disabled. XCIN and
X
COUT are high-inpedance.
Note 4: When the main clock is stopped, the main clock division register (address 000C16) is set to the
division by 8 mode.
Figure 1.8.4. System clock control registers 0 and 1
46
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Main clock division register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
MCD
Address
000C16
When reset
XXX01000
2
Bit symbol
MCD0
Bit name
Function
R W
b4 b3 b2 b1 b0
Main clock division select
bit (Note 2)
1 0 0 1 0 : No division mode
0 0 0 1 0 : Division by 2 mode
0 0 0 1 1 : Division by 3 mode
0 0 1 0 0 : Division by 4 mode
0 0 1 1 0 : Division by 6 mode
0 1 0 0 0 : Division by 8 mode
0 1 0 1 0 : Division by 10 mode
0 1 1 0 0 : Division by 12 mode
0 1 1 1 0 : Division by 14 mode
0 0 0 0 0 : Division by 16 mode
MCD1
MCD2
MCD3
MCD4
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to
this register.
Note 2: These bits are "010002" (8-division mode) when main clock is stopped
or you shift to stop mode.
Note 3: Do not attempt to set combinations of values other than those shown in
this figure.
Figure 1.8.5. Main clock division register
Clock Output
In single chip mode, when the BCLK output function select bit (bit 7 at address 000416 :PM07) is “1”, you
can output f8, f32, or fc from the P53/BCLK/ALE/CLKOUT pins by setting the clock output function select
bits (bits 1 and 0 at address 000616 :CM01, CM00).(Note)
Even when you set PM07 to “0” and CM01 and CM00 to “002”, no BCLK is output.
In memory expansion mode or microprocessor mode, when the ALE pin select bits (bits 5 and 4 at ad-
dress 000516 :PM15, PM14) are other than “012(P53/BCLK)” and PM07 is “1”, you can output f8, f32, or fc
from the P53/BCLK/ALE/CLKOUT pins by setting CM01 and CM00.
In memory expansion mode or microprocessor mode, when PM15 and PM14 are other than “012(P53/
BCLK)” and PM07 is “0” and CM01 and CM00 to “002”, BCLK is output from the P53/BCLK/ALE/CLKOUT
pins.
When stopping clock output in memory expansion mode or microprocessor mode, set PM07 to “1” and
CM01 and CM00 to “002” (IO port P53). The P53 function is not selected. When PM15 and PM14 are “012
(P53/BCLK)” and CM01 and CM00 are “002”, PM07 is ignored and the P53 pin is set for ALE output.
When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, f8 or f32 clock
output is stopped when a WAIT command is executed.
Table 1.8.2 shows clock output setting (single chip mode) and Table 1.8.3 shows clock output setting
(memory expansion/microprocessor mode).
Note :When outputting the f8, f32 or fc from port P53/BCLK/ALE/CLKOUT pin in single chip mode, use port
_______
P57/RDY as an input only port.
47
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Clock Generating Circuit
Table 1.8.2. Clock output setting (single chip mode)
BCLK output function Clock output function select
ALE pin select bit
P5
3
/BCLK/ALE/CLKOUT
select bit
PM07
0/1
bit
pin function
CM01
0
CM00
0
PM15
Ignored
Ignored
Ignored
PM14
Ignored
Ignored
Ignored
Ignored
P5
fc output (Note)
output (Note)
f32 output (Note)
3 I/O port
1
0
1
0
1
1
1
f8
1
1
Ignored
Note :Must use P5
7
as input port.
Table 1.8.3. Clock output setting (memory expansion/microprocessor mode)
BCLK output function Clock output function select
ALE pin select bit
P5
3
/BCLK/ALE/CLKOUT
select bit
PM07
0
bit
pin function
CM01
0
CM00
0
PM15
PM14
BCLK output
"L" output (not P5
fc output
1
1
1
1
0
0
1
1
0
0
1
0
1
0
3)
0
1
1
0
0
1
f
8
output
32 output
ALE output
f
1
Ignored
0
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation of BCLK, f1 to f32, f1SIO2 to f32SIO2, fc, fc32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.8.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt.
When using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009F16) for
exiting a stop/wait state. Set the interrupt priority set bits for the exit from a stop/wait state to the same level
as the flag register (FLG) processor interrupt level (IPL). Figure 1.8.6 shows the exit priority register.
When exiting stop mode using an interrupt, the relevant interrupt routine is executed.
Although stop mode is cancelled by hardware reset only, the interrupt enable flag (I flag) must be set to "1".
When shifting to stop mode and reset, the main clock division register (000C16) is set to “0816”.
48
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Clock Generating Circuit
Table 1.8.4. Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
Address bus, data bus, CS0 to CS3, BHE Retains status before stop mode
Single-chip mode
_______
_______ _______
_____ ______ ________ _________ ______ _________
RD, WR, WRL, WRH, DW, CASL,
“H” (Note)
________
CASH
________
RAS
“H” (Note)
__________
HLDA, BCLK
“H”
“H”
ALE
Port
Retains status before stop mode Retains status before stop mode
“H” “H”
Retains status before stop mode Retains status before stop mode
CLKOUT
When fc selected
When f8, f32 selected
________
________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
Exit priority register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RLVL
Address
009F16
When reset
XXXX0000
2
Bit symbol
RLVL0
Bit
Function
R W
b2 b1 b0
name
Interrupt priority set bit for
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
exiting Stop/Wait state
(Note 1,2)
RLVL1
RLVL2
FSIT
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 = high-speed
interrupt
High-speed interrupt
set bit (Note 3)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is
higher than that set in the exit priority register.
Note 2: Set to the same value as the processor interrupt priority level (IPL) set in
the flag register (FLG).
Note 3: The high-speed interrupt can only be specified for interrupts with
interrupt priority level 7. Specify interrupt priority level 7 for only one
interrupt.
Figure 1.8.6. Exit priority register
49
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Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. Table 1.8.5 shows the status of the ports in
wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts using as BCLK the clock that had been selected when the WAIT instruction was
executed.
When using an interrupt to exit Wait mode, the relevant interrupt must have been enabled and set to a
priority level above the level set by the interrupt priority set bits for exiting a stop/wait state (bits 2, 1, and 0
at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the same level as
the flag register (FLG) processor interrupt level (IPL).
When using an interrupt to exit Wait mode, the microcomputer resumes operating the clock that was oper-
ating when the WAIT command was executed as BCLK from the interrupt routine.
Table 1.8.5. Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before wait mode
________
BHE
_____ ______ ________ _________ ______ _________
RD, WR, WRL, WRH, DW, CASL,
“H” (Note)
________
CASH
________
RAS
“H” (Note)
__________
HLDA,BCLK
“H”
ALE
Port
“L”
Retains status before wait mode
Does not stop
Retains status before wait mode
CLKOUT
When fC selected
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop bit
is “0”. When the WAIT peripheral function clock stop bit is “1”,
the status immediately prior to entering wait mode is main-
tained.
________
________
Note :When self-refresh is done in operating DRAM control, CAS and RAS becomes “L”.
50
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Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.8.6 shows the operating modes corresponding to the settings of system clock control
registers 0 and main clock division register.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, reset or stopping main
clock, the main clock division register (address 000C16) is set to “0816”.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 3 mode
The main clock is divided by 3 to obtain the BCLK.
(3) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(4) Division by 6 mode
The main clock is divided by 6 to obtain the BCLK.
(5) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. After reset, this mode is executed. Note that oscillation
of the main clock must have stabilized before transferring from this mode to no-division, division by 2, 6,
10, 12, 14 and 16 mode.
Oscillation of the sub clock must have stabilized before transferring to low-speed and low power dissipa-
tion mode.
(6) Division by 10 mode
The main clock is divided by 10 to obtain the BCLK.
(7) Division by 12 mode
The main clock is divided by 12 to obtain the BCLK.
(8) Division by 14 mode
The main clock is divided by 14 to obtain the BCLK.
(9) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(10) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(11) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(12) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
When the main clock is stoped, the main clock division register (address 000C16) is set to the division by
8 mode.
51
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Note: When count source of BCLK is changed from clock A to clock B (XIN to XCIN or XCIN to XIN), clock B
needs to be stable before changing. Please wait to change modes until after oscillation has stabilized.
Table 1.8.6. Operating modes dictated by settings of system clock control register 0 and main clock division register
CM07 CM05 CM04 MCD4 MCD3 MCD2 MCD1 MCD0
Operating mode of BCLK
No division
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
Division by 2 mode
Division by 3 mode
Division by 4 mode
Division by 6 mode
Division by 8 mode
Division by 10 mode
Division by 12 mode
Division by 14 mode
Division by 16 mode
Invalid Invalid Invalid Invalid Invalid Low-speed mode
1
Invalid Invalid Invalid Invalid Invalid Low power dissipation mode
CM0i: Clock control register 0 (address 000616) bit i
MCDi: Main clock division register (address 000C16) bit i
52
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Power Saving
In Power Save modes, the CPU and oscillator stop and the operating clock is slowed to minimize power
dissipation by the CPU. The following outlines the Power Save modes.
There are three power save modes.
(1) Normal operating mode
• High-speed mode
In this mode, one main clock cycle forms BCLK. The CPU operates on the selected internal clock. The
peripheral functions operate on the clocks specified for each respective function.
• Medium-speed mode
In this mode, the main clock is divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 to form BCLK. The CPU
operates on the selected internal clock. The peripheral functions operated on the clocks specified for
each respective function.
• Low-speed mode
In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the
subclock. The peripheral functions operate on the clocks specified for each respective function.
• Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on
the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the
subclock was selected as the count source continue to run.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving
modes, power savings are greatest in this mode.
Figure 1.8.7 shows the clock transition between each of the three modes, (1), (2), and (3).
53
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Transition of stop mode, wait mode
Reset
WAIT
instruction
CPU operation stopped
All oscillators stopped
CM10=“1”
Interrupt
Medium-speed mode
(Divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Note 1
CPU operation stopped
WAIT
instruction
Interrupt
CM10=“1”
High-speed/medium-
speed mode
Wait mode
Interrupt
Note 2
Note 1
CPU operation stopped
All oscillators stopped
WAIT
instruction
CM10=“1”
Low-speed/low power
dissipation mode
Note 4
Stop mode
Wait mode
Interrupt
Note 3
Interrupt
Normal mode
(Please see the following as transition of normal mode.)
Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped,
transferred to the middle speed mode.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: The main ckock devision register is set to the division by 8 mode (MCD="0816").
Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="0816").
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
Transition of normal mode
Please change according to a direction of an arrow.
BCLK :f(XIN)/8
CM07=“0” MCD=“0816
”
High-speed/medium-speed mode
CM04=“1”
MCD=“XX16
Note 1, 3
MCD=“XX16
Note 1, 3
”
Main clock is oscillating
Sub clock is oscillating
”
Main clock is oscillating
Sub clock is stopped
High-speed mode
High-speed mode
BCLK :f(XIN
)
BCLK :f(XIN
)
CM04=“0”
CM04=“1”
CM07=“0” MCD=“1216
”
CM07=“0” MCD=“1216
”
Medium-speed mode
(divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode)
Medium-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
BCLK :f(XIN /division rate
)
BCLK :f(XIN /division rate
)
CM07=“0” MCD=“XX16
”
CM07=“0” MCD=“XX16
”
Note 4
Note 4
CM07=“0”
Note 1
” Note 3
MCD=“XX16
CM04=“1”
CM07=“1”
Note 2
CM07=“0 Note 1
MCD=“XX16” Note 3
Low-speed/low power dissipation mode
Main clock is stopped
CM07=“1” Note 2
Main clock is oscillating
Sub clock is oscillating
Sub clock is oscillating
CM05=“1”
Low power
dissipation mode
Low-speed mode
CM05=“1”
BCLK :f(XCIN
)
BCLK :f(XCIN
)
CM07=“1”
CM07=“1”
CM05=“0” Note 4
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: When shifting to division by 8 mode, MCD is set to "0816".
Figure 1.8.7. Clock transition
54
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.8.8 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), main clock division register
(address 000C16), port P9 direction register (address 03C716) and function select register A3 (address
03B516) can only be changed when the respective bit in the protect register is set to “1”. Therefore, impor-
tant outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the PRC2 (bit 2 at address 000A16), a value is written to any
address, the bit automatically reverts to “0” (write-inhibited). Change port P9 input/output and function
select register A3 immediately after setting "1" to PRC2. Interrupt and DMA transfer should not be inserted
between instructions. However, the PRC0 (bit 0 at address 000A16) and PRC1 (bit 1 at address 000A16) do
not automatically return to “0” after a value has been written to an address. The program must therefore be
written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX0002
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
R W
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 000716) and main clock
division register (address 000C16)
1 : Write-enabled
Enables writing to processor mode
registers 0 and 1 (addresses 000416
and 000516)
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
Enables writing to port P9 direction
register (address 03C716) and
function select register A3 (address
03B516) (Note)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0”. Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.8.8. Protect register
55
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Interrupt Outline
Types of Interrupts
Figure 1.9.1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
BRK2 instruction
INT instruction
Interrupt
Reset
_______
NMI
Special
Watchdog timer
Single step
Address matched
Hardware
Peripheral I/O*1
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer
system. High-speed interrupt can be used as highest priority in peripheral I/O interrupts.
Figure 1.9.1. Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I
flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
56
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Software Interrupts
Software interrupts are generated by some instruction that generates an interrupt request when ex-
ecuted. Software interrupts are nonmaskable interrupts.
(1) Undefined-instruction interrupt
This interrupt occurs when the UND instruction is executed.
(2) Overflow interrupt
This interrupt occurs if the INTO instruction is executed when the O flag is 1.
The following lists the instructions that cause the O flag to change:
ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA,
SUB, SUBX
(3) BRK interrupt
This interrupt occurs when the BRK instruction is executed.
(4) BRK2 interrupt
This interrupt occurs when the BRK2 instruction is executed. This interrupt is used exclusively for
debugger purposes. You normally do not need to use this interrupt.
(5) INT instruction interrupt
This interrupt occurs when the INT instruction is executed after specifying a software interrupt number
from 0 to 63. Note that software interrupt numbers 0 to 43 are assigned to peripheral I/O interrupts.
This means that by executing the INT instruction, you can execute the same interrupt routine as used
in peripheral I/O interrupts.
The stack pointer used in INT instruction interrupt varies depending on the software interrupt number.
For software interrupt numbers 0 to 31, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose the interrupt stack pointer (ISP) before executing the interrupt sequence. The
previous U flag before the interrupt occurred is restored when control returns from the interrupt rou-
tine. For software interrupt numbers 32 to 63, such stack pointer switchover does not occur.
However, in peripheral I/O interrupts, the U flag is saved when an interrupt occurs and the U flag is
cleared to 0 to choose ISP.
Therefore movement of U flag is different by peripheral I/O interrupt or INT instruction in software
interrupt number 32 to 43.
57
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Hardware Interrupts
There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
• Reset
____________
A reset occurs when the RESET pin is pulled low.
______
• NMI interrupt
______
This interrupt occurs when the NMI pin is pulled low.
• Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
• Address-match interrupt
This interrupt occurs immediately before the instruction at the address indicated by the address match
interrupt register is executed while the address match interrupt enable bit is set to “1”.
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
• Single-step interrupt
This interrupt is used exclusively for debugger purposes, do not use it in other circumstances. A single-
step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated after one
instruction is executed.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
43 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection, start/stop condition detection interrupts (UART2, UART3, UART4), fault
error interrupts (UART3, 4)
This is an interrupt that the serial I/O bus collision detection generates. When I2C mode is selected,
_____
start, stop condition interrupt is selected. When SS pin is selected, fault error interrupt is selected.
• DMA0 through DMA3 interrupts
These are interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, UART3/NACK and UART4/NACK transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, UART3/ACK and UART4/ACK reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
_______
________
• INT0 interrupt through INT5 interrupt
_____
_____
An INT interrupt selects a edge sense or a level sense. In edge sense, an INT interrupt occurs if either
_____
_____
a rising edge or a falling edge or a both edge is input to the INT pin. In level sense, an INT interrupt
_____
occurs if either an "H" level or an "L" level is input to the INT pin.
58
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
High-speed interrupts
High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3
cycles.
When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to
the save flag register (SVF) and save PC register (SVP) and the program is executed from the address
shown in the vector register (VCT).
Execute a FREIT instruction to return from the high-speed interrupt routine.
High-speed interrupts can be set by setting “1” in the high-speed interrupt specification bit allocated to bit
3 of the exit priority register. Setting “1” in the high-speed interrupt specification bit makes the interrupt set
to level 7 in the interrupt control register into a high-speed interrupt.
You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set
multiple interrupts as level 7 interrupts.
The interrupt vector for a high-speed interrupt must be set in the vector register (VCT).
When using a high-speed interrupt, you can use a maximum of two DMAC channels.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.9.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
High address
0 0 0 0
0 0 0 0
Figure 1.9.2. Format for specifying interrupt vector addresses
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• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFFDC16 to FFFFFF16. One vector table comprises four bytes. Set the first address
of interrupt routine in each vector table. Table 1.9.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.9.1. Interrupt factors (fixed interrupt vector addresses)
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction FFFFDC16 to FFFFDF16
Interrupt on UND instruction
Overflow
FFFFE016 to FFFFE316
FFFFE416 to FFFFE716
Interrupt on INTO instruction
BRK instruction
execution
If content of FFFFE716 is filled with FF16, program
starts from the address shown by the vector in the
variable vector table
Address match
FFFFE816 to FFFFEB16
FFFFF016 to FFFFF316
FFFFF816 to FFFFFB16
FFFFFC16 to FFFFFF16
There is an address-matching interrupt enable bit
Watchdog timer
_______
_______
NMI
External interrupt by input to NMI pin
Reset
• Vector table dedicated for emulator
Table 1.9.2 shows interrupt vector address which is vector table register dedicated for emulator (ad-
dress 00002016 to 00002216). These instructions are not effected with interrupt enable flag (I flag)
(non maskable interrupt).
This interrupt is used exclusively for debugger purposes. You normally do not need to use this inter-
rupt. Do not access to the interrupt vector table register dedicated for emulator (address 00002016 to
00002216).
Table 1.9.2. Interrupt vector table register for emulator
Interrupt source
BRK2 instruction
Single step
Vector table addresses
Address (L) to address (H)
Remarks
Interrupt for debugger
Interrupt for debugger
Interrupt vector table register for emulator
00002016 to 00002216
Interrupt vector table register for emulator
00002016 to 00002216
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.9.3 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Set an even address to the start address of vector table setting in INTB so that operating efficiency is
increased.
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Table 1.9.3. Interrupt causes (variable interrupt vector addresses)
Vector table address
Address (L) to address (H)
Software interrupt number
Interrupt source
Remarks
Software interrupt number 0
+0 to +3 (Note 1)
BRK instruction
Cannot be masked I flag
Software interrupt number 8
Software interrupt number 9
Software interrupt number 10
Software interrupt number 11
+32 to +35 (Note 1)
+36 to +39 (Note 1)
+40 to +43 (Note 1)
+44 to +47 (Note 1)
DMA0
DMA1
DMA2
DMA3
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
Software interrupt number 15
Software interrupt number 16
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
Software interrupt number 32
Software interrupt number 33
Software interrupt number 34
Software interrupt number 35
Software interrupt number 36
Software interrupt number 37
Software interrupt number 38
+48 to +51 (Note 1)
+52 to +55 (Note 1)
+56 to +59 (Note 1)
+60 to +63 (Note 1)
+64 to +67 (Note 1)
+68 to +71 (Note 1)
+72 to +75 (Note 1)
+76 to +79 (Note 1)
+80 to +83 (Note 1)
+84 to +87 (Note 1)
+88 to +91 (Note 1)
+92 to +95 (Note 1)
+96 to +99 (Note 1)
+100 to +103 (Note 1)
+104 to +107 (Note 1)
+108 to +111 (Note 1)
+112 to +115 (Note 1)
+116 to +119 (Note 1)
+120 to +123 (Note 1)
+124 to +127 (Note 1)
+128 to +131 (Note 1)
+132 to +135 (Note 1)
+136 to +139 (Note 1)
+140 to +143 (Note 1)
+144 to +147 (Note 1)
+148 to +151 (Note 1)
+152 to +155 (Note 1)
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
INT5
INT4
INT3
INT2
INT1
INT0
Timer B5
UART2 transmit/NACK (Note 2)
UART2 receive/ACK (Note 2)
UART3 transmit/NACK (Note 2)
UART3 receive/ACK (Note 2)
UART4 transmit/NACK (Note 2)
UART4 receive/ACK (Note 2)
Bus collision detection, start/stop
condition detection (UART2) (Note 2)
Software interrupt number 39
+156 to +159 (Note 1)
Bus collision detection, start/stop condition
detection, fault error (UART3) (Note 2, 3)
Software interrupt number 40
Software interrupt number 41
+160 to +163 (Note 1)
+164 to +167 (Note 1)
Bus collision detection, start/stop condition
detection, fault error (UART4) (Note 2, 3)
A-D
Software interrupt number 42
Software interrupt number 43
Software interrupt number 44
+168 to +171 (Note 1)
+172 to +175 (Note 1)
+176 to +179 (Note 1)
Key input interrupt
to
to
Cannot be masked I flag
Software interrupt
Software interrupt number 63
+252 to +255 (Note 1)
Note 1: Address relative to address in interrupt table register (INTB).
2
Note 2: When I C mode is selected, NACK/ACK, start/stop condition detection interrupts are selected.
Note 3: The fault error interrupt is selected when SS pin is selected.
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Interrupt control registers
Peripheral I/O interrupts have their own interrupt control registers. Figure 1.9.3 shows the interrupt con-
trol registers.
When using an interrupt to exit Stop mode or Wait mode, the relevant interrupt must have been enabled
and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits
2, 1, and 0 at address 009F16). Set the interrupt priority set bits for the exit from a stop/wait state to the
same level as the flag register (FLG) processor interrupt level (IPL).
Figure 1.9.4 shows the exit priority register.
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Interrupt control register
Symbol
ADIC
BCNiIC(i=2 to 4)
DMiIC(i=0 to 3)
KUPIC
Address
007316
008F16, 007116, 009116
When reset
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
006816, 008816, 006A16, 008A16
009316
TAiIC(i=0 to 4)
006C16, 008C16, 006E16, 008E16, 007016
XXXXX000
XXXXX000
2
2
b7 b6 b5 b4 b3 b2 b1 b0
TBiIC(i=0 to 5) 009416, 007616, 009616, 007816, 009816, 006916
SiTIC(i=0 to 4)
SiRIC(i=0 to 4)
009016, 009216, 008916, 008B16, 008D16
007216, 007416, 006B16, 006D16, 006F16
XXXXX000
XXXXX000
2
2
Bit symbol
Bit name
Function
R
W
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
(Note)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Symbol
INTiIC(i=0 to 5)
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
009E16, 007E16, 009C16, 007C16, 009A16, 007A16 XX00X000
2
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
(Note 2)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge or L level
1 : Selects rising edge or H level
Level sense/edge
sense select bit
0 : Edge sense
1 : Level sense (Note 3)
LVS
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: When INT3 to INT5 are used for data bus in microprocessor mode or memory
expansion mode, set the interrupt disabled to INT3IC, INT4IC and INT5IC.
Note 3: When level sense is selected, set related bit of interrupt cause select register (
address 031F16) to one edge.
Figure 1.9.3. Interrupt control register
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Exit priority register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RLVL
Address
009F16
When reset
XXXX0000
2
Bit symbol
RLVL0
Bit
Function
R W
b2 b1 b0
Interrupt priority set bit for
0 0 0 : Level 0
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
exiting Stop/Wait state
(Note 1,2)
RLVL1
RLVL2
FSIT
0: Interrupt priority level 7 = normal
interrupt
1: Interrupt priority level 7 = high-speed
interrupt
High-speed interrupt
set bit (Note 3)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Exits the Stop or Wait mode when the requested interrupt priority level is
higher than that set in the exit priority register.
Note 2: Set to the same value as the processor interrupt priority level (IPL) set in
the flag register (FLG).
Note 3: The high-speed interrupt can only be specified for interrupts with
interrupt priority level 7. Specify interrupt priority level 7 for only one
interrupt.
Figure 1.9.4. Exit priority register
Interrupt Enable Flag (I Flag)
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set
(= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag
is automatically cleared to 0 after a reset is cleared.
Interrupt Request Bit
This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared to 0 (but cannot be set to 1) in software.
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When
an interrupt request is generated, the interrupt priority level of this interrupt is compared with the
processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is
greater than the processor interrupt priority level (IPL). This means that you can disable any particu-
lar interrupt by setting its interrupt priority level to 0.
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Table 1.9.4 shows how interrupt priority levels are set. Table 1.9.5 shows interrupt enable levels in
relation to the processor interrupt priority level (IPL).
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag)
• Interrupt request bit
= 1
= 1
• Interrupt priority level
> Processor interrupt priority level (IPL)
The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the proces-
sor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.
Table 1.9.5 IPL and Interrupt Enable Levels
Table 1.9.4 Interrupt Priority Levels
Processor interrupt
priority level (IPL)
Enabled interrupt priority
levels
Interrupt priority
Interrupt priority level
level select bit
Priority
order
b2
b1
b0
IPL1
IPL2
IPL0
I
nterrupt levels 1 and above are enabled.
Level 0 (interrupt disabled)
Level 1
0
0
0
0
0
0
Interrupt levels 2 and above are enabled.
Low
0
0
1
0
0
0
1
1
0
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 5 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Level 2
Level 3
Level 4
Level 5
Level 6
0
1
1
0
1
0
1
1
0
1
1
0
High
1
1
1
Level 7
Rewrite the interrupt control register
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU,
SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed,
and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 00000016 (address 00000216 when high-speed interrupt). After this, the related interrupt
request bit is "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt se-
quence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. Saves in the
flag save register (SVF) in high-speed interrupt.
(5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register
(SVP) in high-speed interrupt.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.9.5 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in interrupt
routine
Interrupt sequence
(b)
Instruction
(a)
Interrupt response time
(a) The period from the occurrence of an interrupt to the completion of the instruction under execution.
(b) The time required for executing the interrupt sequence.
Figure 1.9.5 Interrupt response time
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Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that
consists of 24* cycles.
Time (b) is shown in table 1.9.6.
* It is when the divisor is immediate or register. When the divisor is memory, the following value is
added.
• Normal addressing
• Index addressing
: 2 + X
: 3 + X
• Indirect addressing
• Indirect index addressing
: 5 + X + 2Y
: 6 + X + 2Y
X is number of wait of the divisor area. Y is number of wait of the indirect address stored area.
When X and Y are in odd address or in 8 bits bus area, double the value of X and Y.
Table 1.9.6 Interrupt Sequence Execution Time
Interrupt
Interrupt vector address 16 bits data bus 8 bits data bus
Peripheral I/O
INT instruction
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
Even address
Odd address (Note 1)
Even address
Odd address (Note 1)
Even address (Note 2)
_______
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
14 cycles
17 cycles
19 cycles
19 cycles
16 cycles
19 cycles
19 cycles
21 cycles
Even address (Note 2)
Even address
BRK instruction (Variable vector table)
Odd address (Note 1)
Even address (Note 2)
Single step
BRK2 instruction
BRK instruction (Fixed vector table)
High-speed interrupt (Note 3)
Vector table is internal
register
5 cycles
Note 1: Allocate interrupt vector addresses in even addresses, if possible.
Note 2: The vector table is fixed to even address.
Note 3: The high-speed interrupt is independent of these conditions.
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Changes of IPL When Interrupt Request Acknowledged
When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 1.9.7 is set to the IPL.
Table 1.9.7 Relationship between Interrupts without Interrupt Priority Levels and IPL
Interrupt sources without interrupt priority levels
Value that is set to IPL
_______
Watchdog timer, NMI
7
Reset
Other
0
Not changed
Saving Registers
In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are
saved to the stack area.
The order in which these contents are saved is as follows: First, the FLG register is saved to the stack
area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are
saved. Figure 1.9.6 shows the stack status before an interrupt request is acknowledged and the stack
status after an interrupt request is acknowledged.
In a high-speed interrupt sequence, the contents of the flag register (FLG) is saved to the flag save
register (SVF) and program counter (PC) is saved to PC save register (SVP).
If there are any other registers you want to be saved, save them in software at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP)
by a single instruction.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.
Stack area
Stack area
Address
Address
MSB
LSB
MSB
LSB
Program counter
(PCL)
m-6
m-5
m–4
m–3
m–2
m–1
m
m-6
m-5
[SP]
New stack
pointer value
Program counter
(PCM)
Program counter
(PCH)
m–4
m–3
m–2
m–1
m
0
0
Flag register
(FLGL)
Flag register
(FLGH)
[SP]
Content of
Content of
previous stack
Stack pointer
value before
interrupt occurs
previous stack
Content of
previous stack
Content of
previous stack
m+1
m+1
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 1.9.6 Stack status before and after an interrupt request is acknowledged
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Return from Interrupt Routine
As you execute the REIT instruction at the end of the interrupt routine, the contents of the flag register
(FLG) and program counter (PC) that have been saved to the stack area immediately preceding the
interrupt sequence are automatically restored. In high-speed interrupt, as you execute the FREIT instruc-
tion at the end of the interrupt routine, the contents of the flag register (FLG) and program counter (PC)
that have been saved to the save registers immediately preceding the interrupt sequence are automati-
cally restored.
Then control returns to the routine that was under execution before the interrupt request was acknowl-
edged, and processing is resumed from where control left off.
If there are any registers you saved via software in the interrupt routine, be sure to restore them using an
instruction (e.g., POPM instruction) before executing the REIT or FREIT instruction.
When switching the register bank before executing REIT and FREIT instruction, switched to the register
bank immediately before the interrupt sequence.
Interrupt Priority
If two or more interrupt requests are sampled active at the same time, whichever interrupt request is
acknowledged that has the highest priority.
Maskable interrupts (Peripheral I/O interrupts) can be assigned any desired priority by setting the inter-
rupt priority level select bit accordingly. If some maskable interrupts are assigned the same priority level,
the priority between these interrupts is resolved by the priority that is set in hardware.
Certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer
interrupt have their priority levels set in hardware. Figure 1.9.7 lists the hardware priority levels of these
interrupts.
Software interrupts are not subjected to interrupt priority. They always cause control to branch to an
interrupt routine whenever the relevant instruction is executed.
Interrupt Resolution Circuit
Interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are
sampled active at the same time.
Figure 1.9.8 shows the interrupt resolution circuit.
Reset > _N__M___I_ > Watchdog > Peripheral I/O > Single step > Address match
Figure 1.9.7. Interrupt priority that is set in hardware
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Priority level of each interrupt
Level 0 (initial value)
High
DMA0
DMA1
INT1
DMA2
INT0
DMA3
Timer B5
Timer A0
UART2 transmission/NACK
Timer A1
UART2 reception/ACK
Timer A2
UART3 transmission/NACK
Timer A3
UART3 reception/ACK
Timer A4
UART4 transmission/NACK
UART0 transmission
UART4 reception/ACK
UART0 reception
Bus collision/start, stop
condition(UART2)
UART1 transmission
UART1 reception
Timer B0
Bus collision/start, stop
condition/fault error (UART3)
Bus collision/start, stop
condition/fault error (UART4)
A-D conversion
Timer B1
Timer B2
Key input interrupt
Timer B3
Timer B4
Stop/wait return interrupt level
(RLVL)
Interrupt
request
INT5
INT4
INT3
INT2
accepted.
To CLK
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
Instruction fetch
Address match
Watchdog timer
DBC
Interrupt
request
accepted.
To CPU
Low
NMI
Priority of peripheral I/O interrupts
(if priority levels are same)
Reset
Figure 1.9.8. Interrupt resolution circuit
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______
INT Interrupts
________
________
INT0 to INT5 are external input interrupts. The level sense/edge sense switching bits of the interrupt control
register select the input signal level and edge at which the interrupt can be set to occur on input signal level
and input signal edge. The polarity bit selects the polarity.
With the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling
edges by setting the INTi interrupt polarity switch bit of the interrupt request select register (address
031F16) to “1”. When you select both edges, set the polarity switch bit of the corresponding interrupt control
register to the falling edge (“0”).
When you select level sense, the INTi interrupt polarity switch bit of the interrupt request select register
(address 031F16) to “0”.
Figure 1.9.9 shows the interrupt request select register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR
Address
031F16
When reset
XX000000
2
R
W
Bit symbol
Bit name
Fumction
IFSR0
INT0 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
INT1 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
INT2 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
INT3 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
INT4 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
INT5 interrupt polarity
swiching bit (Note)
0 : One edge
1 : Two edges
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note :When level sense is selected, set this bit to "0".
Figure 1.9.9 Interrupt request cause select register
71
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03C416).
This pin cannot be used as a normal port input.
Notes:
______
______
______
When not intending to use the NMI function, be sure to connect the NMI pin to VCC (pulled-up). The NMI
interrupt is non-maskable. Because it cannot be disabled, the pin must be pulled up.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.9.10 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Setting the key input interrupt disable bit (bit 7 at address 03AF16) to “1” disables key input interrupts from
occurring regardless of the setting in the interrupt control register. When “1” is set in the key input interrupt
disable register, there is no input via the port pin even when the direction register is set to input.
Port P104-P107 pull-up
select bit
Pull-up
Key input interrupt control
(address 009316
)
transistor
Port P107 direction
register
register
Port P107 direction register
P107/KI3
P106/KI2
Port P106 direction
register
Pull-up
transistor
Key input interrupt
request
Interrupt control
circuit
Pull-up
transistor
Port P105 direction
register
P105/KI1
P104/KI0
Port P104 direction
register
Pull-up
transistor
Figure 1.9.10. Block diagram of key input interrupt
72
Preliminary Specifications REV.D
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Four address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.9.11 shows the address match interrupt-related registers.
Set the start address of an instruction to the address match interrupt register.
Address match interrupt is not generated when address such as the middle of instruction or table data is
set.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXX00002
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 2
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER2
AIER3
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Address match interrupt register i (i = 0 ot 3)
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
When reset
00000016
00000016
00000016
00000016
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
001216 to 001016
001616 to 001416
001A16 to 001816
001E16 to 001C16
b0
Function
Values that can be set
00000016 to FFFFFF16
R W
Address setting register for address match
interrupt
Figure 1.9.11. Address match interrupt-related registers
73
Preliminary Specifications REV.D
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(1) Reading addresses 00000016 and 00000216
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence from address 00000016. When high-speed interrupt
is occurred, CPU read from address 00000216.
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 00000016 and 00000216 by software does not set request bit to “0”.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 00000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
_______
at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after
executing the first instruction after reset. Set an even address to the stack pointer so that the operating
efficiency of accessign memory is increased.
(3) The _N__M___I_ interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance
(pull-up) if unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI pin.
(4) External interrupt
• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.9.12 shows the procedure for
______
changing the INT interrupt generate factor.
(5) Rewrite the interrupt control register
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
74
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Set the interrupt priority level to level 0
(Disable INT interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INT interrupt request)
______
Figure 1.9.12. Switching condition of INT interrupt request
(6) Address match interrupt
• Do not set the following addresses to the address match interrupt register.
1. The address of the starting instruction in an interrupt routine.
2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt request
bit of an interrupt control register or an instruction to rewrite an interrupt priority level to a smaller value.
3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable
flag (I flag).
4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor inter-
rupt priority level (IPL) to a smaller value.
Example 1)
Interrupt_A:
; Interrupt A routine
Do not set address match interrupt to the
start address of an interrupt instruction
pushm R0,R1,R2,R3,A0,A1 ; <----
••••
;
Example 2)
mov.b
nop
#0,TA0IC
;Change TA0 interrupt priority level to a smaller value
; 1st instruction
nop
; 2nd instruction
nop
; 3rd instruction
Do not set address match interrupt
nop
; 4th instruction
; 5th instruction
; 6th instruction
; 7th instruction
during this period
nop
nop
nop
75
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example 3)
fset
I
; Set I flag ( interrupt enabled)
; 1st instruction
nop
nop
Do not set address match interrupt
during this period
; 2nd instruction
; 3rd instruction
nop
Example 4)
ldipl
#0
; Rewrite IPL to a smaller value
; 1st instruction
nop
Do not set address match interrupt
during this period
nop
; 2nd instruction
; 3rd instruction
nop
• To return from an interrupt to the address set in an address match interrupt register using return
instruction (reit or freit)
To rewrite the interrupt control register within the interrupt routine, add the below processing to the
end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are
enabled with other interrupts, add the below processing to the end of the interrupt that enables the
multiple interrupts.
If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the
below processing to the end of all interrupts.
Additional process
; Execute after the register reset instruction (popm instruction)
fclr
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack (use "stc SVF,R0" when high-speed
;
interrupt)
ldc
R0,FLG
; Set in FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed (use freit when high-speed interrupt)
Example 5)
If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple
interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt
C routines.
76
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Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt A routine
Interrupt_A:
pushm R0,R1,R2,R3,A0,A1
; Store registers
••••
bclr
••••
3,TA0IC
; Rewrite interrupt control register of interrupt B
popm R0,R1,R2,R3,A0,A1
fclr
; Restore registers
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack
; Set in FLG
ldc
R0,FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed
Interrupt C routine
Interrupt_C:
pushm R0,R1,R2,R3,A0,A1
fset
; Store registers
I
; Multiple interrupt enabled
••••
••••
popm R0,R1,R2,R3,A0,A1
;Restore registers
fclr
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack
; Set in FLG
ldc
R0,FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed
77
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a
watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer.
Watchdog timer interrupt is selected when bit 6 of the system control register 0 (address 000816 :CM06) is
"0" and reset is selected when CM06 is "1". No value other than "1" can be written in CM06. Once when
reset is selected (CM06="1"), watchdog timer interrupt cannot be selected by software.
When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the
prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for
division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Therefore, the
watchdog timer cycle can be calculated as follows. However, errors can arise in the watchdog timer cycle
due to the prescaler.
When XIN is selected in BCLK
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
When XCIN is selected in BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
For example, when BCLK is 20MHz and the prescaler division ratio is set to 16, the monitor timer cycle is
approximately 26.2 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). CM06 is initialized only at reset. After reset,
watchdog timer interrupt is selected.
The watchdog timer and the prescaler stop in stop mode, wait mode and hold status. After exiting these
modes and status, counting starts from the value remained before.
In the stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released. Figure 1.10.1 shows the block diagram
of the watchdog timer. Figure 1.10.2 shows the watchdog timer-related registers.
Prescaler
“CM07 = 0”
“WDC7 = 0”
"CM06=0"
Watchdog timer
interrupt request
1/16
1/128
1/2
“CM07 = 0”
“WDC7 = 1”
BCLK
HOLD
Watchdog timer
"CM06=1"
Reset
“CM07 = 1”
Write to the watchdog timer
start register
(address 000E16)
Set to
“7FFF16”
RESET
Figure 1.10.1. Block diagram of watchdog timer
78
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX
0
0
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
0816
Bit symbol
Bit
name
Function
R W
b1 b0
Clock output function
select bit (Note 2)
CM00
0 0 : I/O port P5
3
0 1 : f
1 0 : f
C
output (Note 3)
output (Note 3)
1 1 : f32 output (Note 3)
8
CM01
CM02
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral clock in wait
mode
1 : Stop peripheral clock in wait mode
(Note 10)
X
CIN-XCOUT drive capacity
0 : LOW
1 : HIGH
CM03
CM04
CM05
select bit (Note 4)
Port X select bit
C
0 : I/O port
1 : XCIN-XCOUT generation (Note 11)
Main clock (XIN-XOUT
stop bit (Note 5, 6)
)
0 : On
1 : Off (Note 7)
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Reset (Note 8)
CM06
CM07
System clock select bit
(Note 9)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: When outputting BCLK (bit 7 of processor mode register 0 is "0"), set these bits to "00". When
outputting ALE to P5 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". The
port P5 function is not selected even when you set "00" in microprocessor or memory expansion
mode and bit 7 of the processor mode register 0 is "1".
Note 3: When selecting f , f or f32 in single chip mode, must use P5
Note 4: Changes to “1” when shifting to stop mode or reset.
3
3
C
8
7 as input port.
Note 5: When entering the power saving mode, the main clock is stopped using this bit. To stop the main
clock, set system clock stop bit (CM07) to "1" while an oscillation of sub clock is stable. Then set this
bit to "1".
Note 6: When this bit is "1", XOUT is "H". Also, the internal feedback resistance remains ON, so XIN is pulled
up to XOUT ("H" level) via the feedback resistance.
Note 7: When the main clock is stopped, the main clock division register (address 000C16) is set to the
division by 8 mode.
Note 8: When "1" has been set once, "0" cannot be written by software.
Note 9: To set CM07 "1" from "0", first set CM04 to "1", and an oscillation of sub clock is stable. Then set
CM07. Do not set CM04 and CM07 simultaneously. Also, to set CM07 "0" from "1", first set CM05
to "1", and an oscillation of main clock is stable. Then set CM07.
Note 10: fc32 is not included.
Note 11: When XcIN-XcOUT is used, set port P86 and P87 to no pull-up resistance with the input port.
Figure 1.10.2. Watchdog timer control and start registers
79
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Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. DMAC is a function that to transmit 1 data of a source address (8 bits /
16 bits) to a destination address when transmission request occurs. When using three or more DMAC
channels, the register bank 1 register and high-speed interrupt register are used as DMAC registers. If you
are using three or more DMAC channels, you cannot, therefore, use high-speed interrupts. The CPU and
DMAC use the same data bus, but the DMAC has a higher bus access privilege than the CPU, and because
of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer
request until one word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 1.11.1 shows the mapping
of registers used by the DMAC. Table 1.11.1 shows DMAC specifications. Figures 1.11.2 to 1.11.5 show the
structures of the registers used.
As the registers shown in Figure 1.11.1 is allocated in CPU, use LDC instruction when writing. When writing
to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use MOV
instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank select
flag (B flag) to "1" and use LDC instruction to set SB and FB registers.
DMAC related register
DMD0
DMA mode register 0, 1
DMD1
DCT0
DMA0, 1 transfer count register
DCT1
DRC0
DMA0,1 transfer count reload register
DRC1
DMA0
DMA0, 1 memory address register
DMA1
DSA0
DMA0, 1 SFR address register
DSA1
DRA0
DMA0, 1 memory address reload register
DRA1
When using three or more DMAC channels
The high-speed interrupt register is used as a DMAC
register
When using three or more DMAC channels
The register bank 1 is used as a DMAC register
Flag save register
SVF
DRA2 (SVP)
DRA1 (VCT)
DCT2 (R0)
DCT3 (R1)
DMA2 transfer count register
DMA3 transfer count register
DMA2 memory address reload register
DMA3 memory address reload register
DMA2 transfer count reload register
DMA3 transfer count reload register
DRC2 (R2)
DRC3 (R3)
DMA2 memory address register
DMA3 memory address register
DMA2 (A0)
When using DMA2 and DMA3, use the CPU
registers shown in parentheses.
DMA3 (A1)
DSA2 (SB)
DSA3 (FB)
DMA2 SFR address register
DMA3 SFR address register
Figure 1.11.1. Register map using DMAC
In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals
output from the functions specified in the DMA request factor select bits are also used. However, in contrast
to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag.
(Note, however, that the number of actual transfers may not match the number of transfer requests if the
DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC
request bit.)
80
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.11.1. DMAC specifications
Item
Specification
No. of channels
4 (cycle steal method)
Transfer memory space
• From any address in the 16 Mbytes space to a fixed address (16
Mbytes space)
• From a fixed address (16 Mbytes space) to any address in the 16 M
bytes space
Maximum No. of bytes transferred 128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
________
________
DMA request factors (Note)
Falling edge of INT0 to INT3 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to UART4 transmission and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 is the first priority)
8 bits or 16 bits
Transfer unit
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer
Transfer ends when the transfer count register is "000016".
• Repeat transfer
When the transfer counter is "000016", the value in the transfer
counter reload register is reloaded into the transfer counter and the
DMA transfer is continued
DMA interrupt request generation timing When the transfer counter register changes from "000116" to "000016".
DMA startup
• Single transfer
Transfer starts when DMA transfer count register is more than
"000116" and the DMA is requested after “012” is written to the
channel i transfer mode select bits
• Repeat transfer
Transfer starts when the DMA is requested after “112” is written to the
channel i transfer mode select bits
DMA shutdown
• Single transfer
When “002” is written to the channel i transfer mode select bits and
DMA transfer count register becomes "000016" by DMA transfer or
write
• Repeat transfer
When “002” is written to the channel i transfer mode select bits
When the transfer counter register changes from "000116" to "000016" in
repeat transfer mode.
Reload timing
Reading / writing the register
Registers are always read/write enabled.
Number of DMA transfer cycles Between SFR and internal RAM : 3 cycles
Between external I/O and external memory : minimum 3 cycles
Note: DMA transfer is not effective to any interrupt.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi request cause select register (i = 0 to 3)(Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiSL
Address
037816 to 037B16
When reset
0X0000002
Function
Bit symbol
DSEL0
Bit name
R
W
b4 b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 0 : Software trigger
0 0 0 0 1 : Falling edge of INTi pin (Note 3)
0 0 0 1 0 : Two edges of INTi pin (Note 3)
0 0 0 1 1 : Timer A0
(Note 2)
0 0 1 0 0 : Timer A1
0 0 1 0 1 : Timer A2
0 0 1 1 0 : Timer A3
0 0 1 1 1 : Timer A4
0 1 0 0 0 : Timer B0
0 1 0 0 1 : Timer B1
0 1 0 1 0 : Timer B2
0 1 0 1 1 : Timer B3
0 1 1 0 0 : Timer B4
0 1 1 0 1 : Timer B5
0 1 1 1 0 : UART0 transmit
0 1 1 1 1 : UART0 receive
1 0 0 0 0 : UART1 transmit
1 0 0 0 1 : UART1 receive
1 0 0 1 0 : UART2 transmit
1 0 0 1 1 : UART2 receive/ACK (Note 4)
1 0 1 0 0 : UART3 transmit
1 0 1 0 1 : UART3 receive/ACK (Note 4)
1 0 1 1 0 : UART4 transmit
1 0 1 1 1 : UART4 receive/ACK (Note 4)
1 1 0 0 0 : A-D conversion
1 1 0 0 1 to 1 1 1 1 1 : Inhibit
DSEL1
DSEL2
DSEL3
DSEL4
DSR
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Software DMA
request bit (Note 5)
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 : Not requested
1 : Requested
DMA request bit
(Note 5,6)
DRQ
Note 1: Please refer to DMAC precautions.
Note 2: Set DMA inhibit before changing the DMA request cause. Set DRQ to "1"
simultaneously.
e.g.) MOV.B #083h, DMiSL
; Set timer A0
Note 3: DMA0-INT0, DMA1-INT1, DMA2-INT2, and DMA3-INT3 correspond to DMAi and
INTi. However, when INT3 pin becomes data bus in microprocessor mode, DMA3-
INT3 cannot be used.
Note 4: UARTi reception and ACK switching are effected using the UARTi special mode
register and UARTi special mode register 2.
Note 5: When setting DSR to "1", set DRQ to "1" using OR instruction etc. simultaneously.
e.g.) OR.B #0A0h, DMiSL
Note 6: Do not write "0" to this bit. There is no need to clear the DMA request bit.
Figure 1.11.2. DMAC register (1)
82
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA mode register 0
(CPU internal register)
Symbol
DMD0
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
R W
Bit symbol
MD00
b1 b0
Channel 0 transfer
mode select bit
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Reserved
1 1 : Repeat transfer
MD01
BW0
0 : 8 bits
1 : 16 bits
Channel 0 transfer
unit select bit
Channel 0 transfer
direction select bit
RW0
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
b5 b4
Channel 1 transfer
mode select bit
MD10
MD11
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Reserved
1 1 : Repeat transfer
0 : 8 bits
1 : 16 bits
Channel 1 transfer
unit select bit
BW1
RW1
Channel 1 transfer
direction select bit
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
DMA mode register 1
(CPU internal register)
Symbol
DMD1
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
MD20
Function
Bit name
R W
b1 b0
Channel 2 transfer
mode select bit
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Reserved
1 1 : Repeat transfer
MD21
Channel 2 transfer
unit select bit
BW2
RW2
MD30
MD31
BW3
RW3
0 : 8 bits
1 : 16 bits
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
Channel 2 transfer
direction select bit
b5 b4
Channel 3 transfer
mode select bit
0 0 : DMA inhibit
0 1 : Single transfer
1 0 : Reserved
1 1 : Repeat transfer
Channel 3 transfer
unit select bit
0 : 8 bits
1 : 16 bits
Channel 3 transfer
direction select bit
0 : Fixed address to memory (forward direction)
1 : Memory (forward direction) to fixed address
Figure 1.11.3. DMAC register (2)
83
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi transfer count register (i = 0 to 3)
(CPU internal register)
Symbol
DCT0
DCT1
DCT2 (bank 1;R0) (Note 1)
DCT3 (bank 1;R1) (Note 1)
When reset
XXXX16
XXXX16
000016
000016
b15
b0
Transfer count
specification
R W
Function
• Transfer counter
Set transfer number
000016 to FFFF16
Note 1: When setting DCT2 and DCT3, set "1" to the register bank select
flag (B flag) of flag register (FLG), and then set desired value to R0
and R1 of register bank 1.
Note 2: When "0" is set to this register, data transfer is not done even if DMA
is requested.
DMAi transfer count reload register (i = 0 to 3)
(CPU internal register)
Symbol
DRC0
DRC1
DRC2 (bank 1;R2) (Note 1)
DRC3 (bank 1;R3) (Note 1)
When reset
XXXX16
XXXX16
000016
b15
b0
000016
Transfer count
specification
Function
R W
• Transfer count register reload value
Set transfer number
000016 to FFFF16
Note: When setting DRC2 and DRC3, set "1" to the register bank select flag
(B flag) of flag register (FLG), and then set desired value to R2 and
R3 of register bank 1.
Figure 1.11.4. DMAC register (3)
84
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi memory address register (i = 0 to 3)
(CPU internal register)
Symbol
DMA0
DMA1
DMA2 (bank 1;A0) (Note 1)
DMA3 (bank 1;A1) (Note 1)
When reset
XXXXXX16
XXXXXX16
00000016
00000016
b0
b23
Transfer address
specification area
R W
Function
• Memory address (Note 2)
Set source or destination memory address
00000016 to FFFFFF16
(16 Mbytes area)
Note 1: When setting DMA2 and DMA3, set "1" to the register bank select flag (B flag) of
flag register (FLG), and set desired value to A0 and A1 of register bank 1.
Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register
is destination memory address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is source memory address.
DMAi SFR address register (i = 0 to 3)
(CPU internal register)
Symbol
DSA0
DSA1
DSA2 (bank 1;SB) (Note 1)
DSA3 (bank 1;FB) (Note 1)
When reset
XXXXXX16
XXXXXX16
00000016
b0
b23
00000016
Transfer address
specification area
Function
R W
• SFR address (Note 2)
Set source or destination fixed address
00000016 to FFFFFF16
(16 Mbytes area)
Note 1: When setting DSA2, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to SB of register bank 1.
When setting DSA3, set "1" to the register bank select flag (B flag) of flag register
(FLG), and set desired value to FB of register bank 1.
Note 2: When the transfer direction select bit is "0" (fixed address to memory), this register
is source fixed address.
When the transfer direction select bit is "1" (memory to fixed address), this register
is destination fixed address.
DMAi memory address reload register (i = 0 to 3)
(CPU internal register)
Symbol
DRA0
DRA1
DRA2 (SVP) (Note)
DRA3 (VCT) (Note)
When reset
XXXXXX16
XXXXXX16
XXXXXX16
XXXXXX16
b23
b0
Transfer address
specification area
Function
R W
• Memory address register reload value
Set source or destination memory address
00000016 to FFFFFF16
(16 Mbytes area)
Note: When setting DRA2, set desired value to save PC register (SVP).
When setting DRA3, set desired value to vector register (VCT).
Figure 1.11.5. DMAC register (4)
85
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of external data bus width control register
When in memory expansion mode or microprocessor mode, the transfer cycle changes according to
the data bus width at the source and destination.
1. When transferring 16 bits of data and the data bus width at the source and at the destination is 8
bits (data bus width bit = “0”), there are two 8-bit data transfers. Therefore, two bus cycles are
required for reading and two cycles for writing.
2. When transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit
= “0”) and the data bus width at the destination is 16 bits (data bus width bit = “1”), the data is read
in two 8-bit blocks and written as 16-bit data. Therefore, two bus cycles are required for reading
and one cycle for writing.
3. When transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit
= “1”) and the data bus width at the destination is 8 bits (data bus width bit = “0”), 16 bits of data are
read and written as two 8-bit blocks. Therefore, one bus cycle is required for reading and two
cycles for writing.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.11.6 shows the example of the transfer cycles for a source read. Figure 1.11.6 shows the desti-
nation is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source
read cycles for the different conditions. In reality, the destination write cycle is subject to the same condi-
tions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer
cycle, remember to apply the respective conditions to both the destination write cycle and the source read
cycle. For example (2) in Figure 1.11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus
cycles are required for both the source read cycle and the destination write cycle.
86
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) •When 8-bit data is transferred
•When 16-bit data is transferred on a 16-bit data bus and the source address is even
BCLK
Address
bus
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
CPU use
(2) •When 16-bit data is transferred and the source address is odd
•When 16-bit data is transferred and the width of data bus at the source is 8-bit
(When the width of data bus at the destination is 8-bit, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
CPU use
Destination
Source + 1
(3) •When one wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Source
Destination
CPU use
CPU use
RD signal
WR signal
Data
bus
Source
CPU use
Destination
CPU use
(4) •When one wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are
two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Source + 1
Destination
CPU use
Source
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.11.6. Example of the transfer cycles for a source read
87
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.11.2. No. of DMAC transfer cycles
Memory expansion mode
Single-chip mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
1
cycles
1
cycles
1
cycles
1
16-bit
(DSi = “1”)
8-bit
Even
Odd
8-bit transfers
(BWi = “0”)
1
—
—
1
1
—
—
1
1
1
1
1
2
2
2
1
1
1
1
2
2
2
Even
Odd
(DSi = “0”)
16-bit
Even
Odd
16-bit transfers
(BWi = “1”)
(DSi = “1”)
8-bit
2
2
Even
Odd
—
—
—
—
(DSi = “0”)
Coefficient j, k
Internal Memory
Internal ROM/RAM
External Memory
SFR area
Separate bus
Multiplex bus
No wait
j=1
With wait
j=2
No wait One wait Two waits Three waits Two waits Three waits
j=2
j=1
j=2
j=3
j=4
j=3
j=4
k=1
k=2
k=2
k=2
k=2
k=3
k=4
k=3
k=4
DMA Request Bit
The DMAC can issue DMA requests using preselected DMA request factors for each channel as trig-
gers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i
transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request
is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Internal factors
The DMAi request flag is set to “1” in response to internal factors at the same time as the interrupt
request bit of the interrupt control register for each factor is set. This is because, except for software
trigger DMA factors, they use the interrupt request signals output by each function.
The DMAi request bit is cleared to "0" when the DMA transfer starts or the DMA transfer is in disable
state (channel i transfer mode select bits are "00" and the DMAi transfer count register is "0").
(2) External factors
______
These are DMA request factors that are generated by the input edge from the INTi pin (where i indi-
______
cates the DMAC channel). When the INTi pin is selected by the DMAi request factor select bit as an
external factor, the inputs from these pins become the DMA request signals.
When an external factor is selected, the DMAi request bit is set, according to the function specified in the
______
DMA request factor select bit, on either the falling edge of the signal input via the INTi pins, or both edges.
When an external factor is selected, the DMAi request bit is cleared, in the same way as the DMAi
request bit is cleared for internal factors, when the DMA transfer starts or the DMA transfer is in
disable state.
(3) Relationship between external factor request input and DMAi request flag, and DMA transfer timing
When the request inputs to DMAi occur in the same sampling cycle (between the falling edge of BCLK
and the next falling edge), the DMAi request bits are set simultaneously, but if the DMAi enable bits
are all set, DMA0 takes priority and the transfer starts. When one transfer unit is complete, the bus
privilege is returned to the CPU. When the CPU has completed one bus access, DMA1 transfer starts,
and, when one transfer unit is complete, the privilege is again returned to the CPU.
The priority is as follows: DMA0 > DMA1 > DMA2 > DMA3.
Figure 1.11.7. DMA transfer example by external factors shows what happens when DMA0 and DMA1
requests occur in the same sampling cycle.
In this example, DMA transfer request signals are input simultaneously from
external factors and the DMA transfers are executed in the minimum cycles.
BCLK
DMA0
DMA1
Bus
priviledge
acquired
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.11.7. DMA transfer example by external factors
89
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DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for DMAC
(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer is
not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select
register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL
; DMiSL is DMAi request cause select register
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to
the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled
before changing the DMAi request cause select bit. At least 2 instructions are needed from the instruc-
tion to write to the DMAi request cause select register to enable DMA.
Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer after
DMA initial setting
push.w
stc
R0
; Store R0 register
DMD0, R0
#11111100b, R0L
R0, DMD0
; Read DMA mode register 0
; Clear DMA0 transfer mode select bit to "00"
; DMA0 disabled
and.b
ldc
mov.b
#10000011b, DM0SL ; Select timer A0
; (Write "1" to DMA request bit simultaneously)
mov.b
or.b
R0L, R0L
#00000001b, R0L
R0, DMD0
R0
; Dummy cycle
At least 2 instructions are
needed until DMA enabled.
; Set DMA0 single transfer
; DMA0 enabled
ldc
pop.w
; Restore R0 register
90
r
Preliminary Specifications REV.D
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Mitsubishi Microcomputers
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Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.12.1 and 1.12.2 show the block diagram of timers.
Clock prescaler
f
f
1
8
fC32
XIN
1/32
Reset
X
CIN
1/8
Clock prescaler reset flag (bit 7
at address 034116) set to “1”
f
32
1/4
f1 f8 f32 fC32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2
Timer A3
Timer A4
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
• Event counter mode
Timer B2 overflow
Figure 1.12.1. Timer A block diagram
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock prescaler
f
1
8
fC32
XIN
1/32
Reset
X
CIN
f
1/8
Clock prescaler reset flag (bit 7
at address 034116) set to “1”
f
32
1/4
f1 f8 f32 fC32
Timer B2 overflow (to timer A count source)
• Timer mode
• Pulse width measuring mode
Timer B0 interrupt
Timer B1 interrupt
Noise
filter
TB0IN
TB1IN
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B2 interrupt
Noise
filter
TB2IN
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B3 interrupt
Timer B4 interrupt
Noise
filter
TB3IN
TB4IN
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B5 interrupt
Noise
filter
TB5IN
Timer B5
• Event counter mode
Figure 1.12.2. Timer B block diagram
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.13.1 shows the block diagram of timer A. Figures 1.13.2 to 1.13.4 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f
1
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f
32
Reload register (16)
f
C32
• Event counter
Clock selection
Counter (16)
Polarity
selection
Up count/down count
TAiIN
Always down count except
in event counter mode
(i = 0 to 4)
Count start flag
(Address 034016
)
TAi
Addresses
TAj
TAk
Down count
Timer A0 034716 034616
Timer A1 034916 034816
Timer A2 034B16 034A16 Timer A1 Timer A3
Timer A3 034D16 034C16 Timer A2 Timer A4
Timer A4 034F16 034E16 Timer A3 Timer A0
Timer A4 Timer A1
Timer A0 Timer A2
TB2 overflow
External
trigger
Up/down flag
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
(Address 034416
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Figure 1.13.1. Block diagram of timer A
Timer Ai mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i=0 to 4) 035616 to 035A16 00000X00
2
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
This bit is invalid in M16C/80 series.
– –
Port output control is set by the function select registers A and B.
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.13.2. Timer A-related registers (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note 1)
Symbol
TA0
TA1
TA2
TA3
TA4
Address
034716,034616
034916,034816
034B16,034A16
034D16,034C16
034F16,034E16
When reset
(b15)
b7
(b8)
b0b7
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b0
Values that can be set
Function
R W
• Timer mode
Counts an internal count source
000016 to FFFF16
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
000016 to FFFF16
• One-shot timer mode (Note 2, 3)
Counts a one shot width
• Pulse width modulation mode (16-bit PWM) (Note 2, 4)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM) (Note 2, 4)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(High-order address)
0016 to FF16
(Low-order address)
Note 1: Read and write data in 16-bit units.
Note 2: Use MOV instruction to write to this register.
Note 3: When the timer Ai register is set to "000016", the counter does not
operate and the timer Ai interrupt request is not generated. When
the pulse is set to output, the pulse does not output from the TAiOUT
pin.
Note 4: When the timer Ai register is set to "000016", the pulse width
modulator does not operate and the output level of the TAiOUT pin
remains "L" level, therefore the timer Ai interrupt request is not
generated. This also occurs in the 8-bit pulse width modulator mode
when the significant 8 high-order bits in the timer Ai register are set
to "0016".
Count start flag
Symbol
TABSR
Address
034016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag (Note)
Symbol
UDF
Address
034416
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0UD
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
Bit name
Function
Timer A0 up/down flag
0 : Down count
1 : Up count
Timer A1 up/down flag
Timer A2 up/down flag
Timer A3 up/down flag
Timer A4 up/down flag
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
Timer A2 two-phase pulse
signal processing select bit
TA3P
TA4P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Timer A4 two-phase pulse
signal processing select bit
Note: Use MOV instruction to write to this register.
Figure 1.13.3. Timer A-related registers (2)
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag
Symbol
ONSF
Address
034216
When reset
b7 b6 b5 b4 b3 b2 b1 b0
0016
R W
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
TAZIE
1 : Timer start
When read, the value is “0”
0 : Invalid
1 : Valid
Z phase input enable bit
b7 b6
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding function select register A to I/O port, and port
direction register to “0”.
Trigger select register
Symbol
TRGSR
Address
034316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding function select register A to I/O port, and port
direction register to “0”.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
034116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.13.4. Timer A-related registers (3)
95
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.1.) Figure 1.13.5
shows the timer Ai mode register in timer mode.
Table 1.13.1. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
Programmable I/O port or gate input
TAiOUT pin function
Programmable I/O port or pulse output (Setting by the corresponding function
select registers A and B)
Read from timer
Write to timer
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TAiMR(i=0 to 4) 035616 to 035A16 00000X002
0
0 0
Bit symbol
Bit name
Function
0 0 : Timer mode
R W
– –
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 1): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 2)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 2)
MR3
0 (Set to “0” in timer mode)
b7 b6
Count source select bit
0 0 : f1
TCK0
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
Note 1: The bit can be “0” or “1”.
Note 2: Set the corresponding port function select register to I/O port, and port
direction register to “0”.
Figure 1.13.5. Timer Ai mode register in timer mode
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-
phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table
1.13.2 lists timer specifications when counting a single-phase external signal. Figure 1.13.6 shows the timer Ai
mode register in event counter mode. Table 1.13.3 lists timer specifications when counting a two-phase
external signal. Figure 1.13.7 shows the timer Ai mode register in event counter mode.
Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Count source
Specification
• External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflows or underflows, TAj overflows or underflows
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Count operation
Divide ratio
• 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input (Setting by
the corresponding function select registers A and B
)
Read from timer
Write to timer
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Free-run count function
Select function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TAiMR(i=0 to 4) 035616 to 035A16 00000X00
When reset
2
0
0 1
R W
Bit symbol
Bit name
Function
0 1 : Event counter mode
b1 b0
TMOD0
TMOD1
Operation mode select bit
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
MR0
MR1
MR2
– –
Count polarity
select bit (Note 1)
0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 2)
Up/down switching
cause select bit
0 : (Set to “0” in event counter mode)
MR3
Count operation type
select bit
TCK0
0 : Reload type
1 : Free-run type
Two-phase pulse signal
processing operation
select bit
TCK1
When not using two-phase pulse signal
processing, set this bit to “0”
Note 1: This bit is valid when only counting an external signal.
Note 2: Set the corresponding function select register A to I/O port, and port direction
register to “0”.
Figure 1.13.6. Timer Ai mode register in event counter mode
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Table 1.13.3. Timer specifications in event counter mode
Item Specification
Count source • Two-phase pulse signals input to TAiIN or TAiOUT pin
Count operation
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio
• 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function
Two-phase pulse input
TAiOUT pin function
Two-phase pulse input (Set the corresponding function select registers A to I/
O port)
Read from timer
Write to timer
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation (TimerA2 and timer A3)
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is “H”
Select function (Note 2)
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation (TimerA3 and timer A4)
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count down all edges
Count up all edges
TAiIN
(i=3,4)
Count up all edges
Count down all edges
(when processing two-phase pulse signal with timers A2, A3, and A4)
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A3 is selectable. Timer A2 is fixed to normal processing operation and timer A4 is fixed to
multiply-by-4 operation.
98
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol
Address
When reset
b6 b5 b4 b3 b2 b1 b0
b7
TAiMR(i=2 to 4) 035816 to 035A16 00000X00
2
0
1 0
0 1
Bit symbol
Bit name
Function
0 1 : Event counter mode
R W
– –
b1 b0
TMOD0
TMOD1
Operation mode select bit
(Note 1)
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
MR0
MR1
MR2
MR3
TCK0
0 (Set to “0” when using two-phase pulse signal processing)
1 (Set to “1” when using two-phase pulse signal processing)
0 (Set to “0” when using two-phase pulse signal processing)
0 : Reload type
1 : Free-run type
Count operation type
select bit
Two-phase pulse
processing operation
select bit (Note 2)(Note 3)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: Set the corresponding function select register A to I/O port.
Note 2: This bit is valid for timer A3 mode register.
Timer A2 is fixed to normal processing operation and timer A4 is fixed to multiply-by-4
processing operation.
Note 3: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 034416) is set to “1”. Also, always be
sure to set the event/trigger select bit (addresses 034316) to “00”.
Figure 1.13.7. Timer Ai mode register in event counter mode
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• Counter Resetting by Two-Phase Pulse Signal Processing
This function resets the timer counter to “0” when the Z-phase (counter reset) is input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode, two-phase pulse signal processing,
free-run type, and multiply-by-4 processing. The Z phase is input to the INT2 pin.
When the Z-phase input enable bit (bit 5 at address 034216) is set to “1”, the counter can be reset by
Z-phase input. For the counter to be reset to “0” by Z-phase input, you must first write “000016” to the
timer A3 register (address 034D16 and 034C16).
The Z-phase is input when the INT2 input edge is detected. The edge polarity is selected by the INT2
polarity switch bit (bit 4 at address 009C16). The Z-phase must have a pulse width greater than 1 cycle
of the timer A3 count source. Figure 1.13.8 shows the relationship between the two-phase pulse (A
phase and B phase) and the Z phase.
The counter is reset at the count source following Z-phase input. Figure 1.13.9 shows the timing at
which the counter is reset to “0”.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
INT2 (Note)
(Z phase)
The pulse must be wider than this width.
Note: When the rising edge of INT2 is selected
Figure 1.13.8. The relationship between the two-phase pulse (A phase and B phase) and the Z phase
100
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
(Note)
INT2
(Z phase)
Count value
m
m+1
1
2
3
4
5
Becoming "0" at this timing.
Note: When the rising edge of INT2 is selected
Figure 1.13.9. The counter reset timing
Note that timer A3 interrupt requests occur successively two times when timer A3 underflow and
INT2 input reload are happened at the same timing.
Do not use timer A3 interrupt request when this function is used.
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(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 1.13.10 shows the timer Ai mode register in one-shot timer mode.
Table 1.13.4. Timer specifications in one-shot timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a
new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TAiIN pin function
Programmable I/O port or trigger input
TAiOUT pin function
Programmable I/O port or pulse output (Setting by the corresponding function
select registers A and B)
Read from timer
Write to timer
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0
1 0
TAiMR(i=0 to 4) 035616 to 035A16 00000X00
2
Bit symbol
Bit name
R W
– –
Function
1 0 : One-shot timer mode
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
MR1
MR2
0 : Falling edge of TAiIN pin's input signal (Note 2)
External trigger select
1 : Rising edge of TAiIN pin's input signal (Note 2)
bit (Note 1)
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Set to “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port function select register to I/O port, and port direction
register to “0”.
Figure 1.13.10. Timer Ai mode register in one-shot timer mode
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.13.11 shows the
timer Ai mode register in pulse width modulation mode. Figure 1.13.12 shows the example of how a 16-bit pulse
width modulator operates. Figure 1.13.13 shows the example of how an 8-bit pulse width modulator operates.
Table 1.13.5. Timer specifications in pulse width modulation mode
Item
Count source
Specification
f1, f8, f32, fC32
Count operation
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
• Cycle time
n / fi n : Set value
(2 -1) / fi fixed
16
8-bit PWM
• High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (2 -1) (m+1) / fi m:values set to timer Ai register’s low-order address
8
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
Programmable I/O port or trigger input
TAiOUT pin function
Pulse output (TAiOUT output is selected by the corresponding function select
registers A and B)
Read from timer
Write to timer
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
1
1
TAiMR(i=0 to 4) 035616 to 035A16 00000X002
R W
– –
Bit symbol
Bit name
Function
1 1 : Pulse width modulaten (PWM) mode
b1 b0
TMOD0
TMOD1
Operation mode
select bit
MR0
MR1
MR2
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
External trigger select
bit (Note 1)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
0: Count start flag is valid
1: Selected by event/trigger select register
Trigger select bit
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1
8
1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 034216 and 034316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding function select register A to I/O port, and port direction
register to “0”.
Figure 1.13.11. Timer Ai mode register in pulse width modulation mode
103
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Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
“H”
“L”
TAiIN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
1
8
)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
.
Figure 1.13.12. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (28 – 1)
Count source (Note1)
“H”
TAiIN pin input signal
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2)
“L”
1 / fi X (m + 1) X n
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
Timer Ai interrupt
request bit
“0”
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” when interrupt request is accepted, or cleaerd by software
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16
.
Figure 1.13.13. Example of how an 8-bit pulse width modulator operates
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Timer B
Figure 1.14.1 shows the block diagram of timer B. Figures 1.14.2 and 1.14.3 show the timer B-related
registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f
1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f
f
8
32
fC32
Counter (16)
• Event counter
Count start flag
(address 034016
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow
Timer B0 035116 035016 Timer B2
Timer B1 035316 035216 Timer B0
Timer B2 035516 035416 Timer B1
Timer B3 031116 031016 Timer B5
Timer B4 031316 031216 Timer B3
Timer B5 031516 031416 Timer B4
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Figure 1.14.1. Block diagram of timer B
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 5) 035B16 to 035D16
031B16 to 031D16
00XX0000
00XX0000
2
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
TMOD1
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.2. Timer B-related registers (1)
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Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
When reset
035116, 035016 Indeterminate
035316, 035216 Indeterminate
035516, 035416 Indeterminate
031116, 031016 Indeterminate
031316, 031216 Indeterminate
031516, 031416 Indeterminate
Timer Bi register (Note)
(b15)
(b8)
b7
b0 b7
b0
Values that can be set
Function
R W
• Timer mode
Counts the timer's period
000016 to FFFF16
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
034016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer B3, 4, 5 count start flag
Symbol
TBSR
Address
030016
When reset
000XXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
R W
Bit symbol
Bit name
Function
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
0 : Stops counting
1 : Starts counting
TB3S
TB4S
TB5S
Timer B3 count start flag
Timer B4 count start flag
Timer B5 count start flag
Clock prescaler reset flag
Symbol
CPSRF
Address
034116
When reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Clock prescaler reset flag
Figure 1.14.3. Timer B-related registers (2)
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(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.4
shows the timer Bi mode register in timer mode.
Table 1.14.1. Timer specifications in timer mode
Item
Count source
Specification
f1, f8, f32, fC32
• Counts down
Count operation
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i = 0 to 5) 035B16 to 035D16
031B16 to 031D16
00XX0000
00XX0000
2
0
0
2
Bit symbol
R
W
Bit name
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 0 : Timer mode
Invalid in timer mode
Can be “0” or “1”
MR1
MR2
MR3
0 (Set to “0” in timer mode ; i = 0, 3)
(Note 1)
(Note 2)
Nothing is assiigned (i = 1, 2, 4, 5).
When write, set "0". When read, its content is indeterminate.
Invalid in timer mode.
When write, set "0". When read in timer mode, its content is
indeterminate.
b7 b6
Count source select bit
TCK0
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.4. Timer Bi mode register in timer mode
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(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.2.)
Figure 1.14.5 shows the timer Bi mode register in event counter mode.
Table 1.14.2. Timer specifications in event counter mode
Item
Count source
Specification
• External signals input to TBiIN pin
Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
• TBi overflows or underflows
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input (Set the corresponding function select register A to I/O port.)
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00XX0000
00XX0000
TBiMR(i = 0 to 5) 035B16 to 035D16
031B16 to 031D16
2
0
1
2
R
W
Bit symbol
Bit name
Function
TMOD0
TMOD1
MR0
b1 b0
Operation mode
select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's falling edges
0 1 : Counts external signal's rising edges
1 0 : Counts external signal's falling and
rising edges
MR1
MR2
1 1 : Inhibited
0 (Set to “0” in event counter mode; i = 0, 3)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
When write, set "0". When read, its content is indeterminate.
Invalid in event counter mode.
When write, set "0". When read in event counter mode, its
content is indeterminate.
MR3
Invalid in event counter mode.
Can be “0” or “1”.
TCK0
TCK1
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
Event clock select
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Figure 1.14.5. Timer Bi mode register in event counter mode
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(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.3.)
Figure 1.14.6 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.14.7 shows the operation timing when measuring a pulse period. Figure 1.14.8 shows the operation
timing when measuring a pulse width.
Table 1.14.3. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from timer
Measurement pulse input (Set the corresponding function select register A to I/O port.)
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i = 0 to 5) 035B16 to 035D16
031B16 to 031D16
00XX0000
00XX0000
2
1
0
2
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
MR2
0 (Set to “0” in pulse period/pulse width measurement mode; i = 0, 3)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
When write, set "0". When read, its content is indeterminate.
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
1
8
1 1 : fC32
Note 1: It is indeterminate when reset.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.6. Timer Bi mode register in pulse period/pulse width measurement mode
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When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
Measurement pulse
“L”
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.7. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.8. Operation timing when measuring a pulse width
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Three-phase motor control timers’ functions
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms.
Figures 1.15.1 through 1.15.3 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
030816
When reset
0016
R
W
Bit symbol
Bit name
Description
Effective interrupt output
polarity select bit
0: A timer B2 interrupt occurs when the
timer A1 reload control signal is “0”.
1: A timer B2 interrupt occurs when the
timer A1 reload control signal is “1”.
Effective only in three-phase mode 1
INV0
0
1
Effective interrupt output
0: Not specified.
specification bit
1: Selected by the effective interrupt
output polarity selection bit.
Effective only in three-phase mode 1
(Note 4)
INV0
Mode select bit
(Note 2)
0: Normal mode
1: Three-phase PWM output mode
INV0
INV0
2
3
Output control
bit
0: Output disabled
1: Output enabled
Positive and negative
phases concurrent L output 1: Feature enabled
disable function enable bit
0: Feature disabled
INV0
4
Positive and negative
phases concurrent L output 1: Already detected
detect flag
0: Not detected yet
INV0
INV0
INV0
5
6
7
(Note 1)
Modulation mode select
bit (Note 3)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
1: Trigger generated
The value, when read, is “0”.
Software trigger bit
Note 1: No value other than “0” can be written.
Note 2: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits, and the
timer B2 interrupt occurrences frequency set circuit works.
For U, U, V, V, W and W output from P80, P81, and P72 through P75, setting of function select registers A, B and C is
required.
Note 3: In triangular wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer Ai
output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in
synchronization with the transfer trigger signal after writing to the three-phase output buffer register.
In sawtooth wave modulation mode: The dead time timer starts in synchronization with the falling edge of timer A
output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the three-
phase output shift register is made with respect to every transfer trigger.
Note 4: Set bit 1 of this register to "1" after setting timer B2 interrupt frequency set counter.
T
hree-phase PWM control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
030916
When reset
XXX0X000
2
R
W
Bit symbol
Bit name
Description
0: Timer B2 overflow signal
1: Timer B2 overflow signal,
signal for writing to timer B2
Timer Ai start trigger
signal select bit
INV1
0
Timer A1-1, A2-1, A4-1
control bit
0: Three-phase mode 0
1: Three-phase mode 1
INV1
INV1
1
2
Dead time timer count
source select bit
0 : f1
1
1 : f
/2
Carrier wave detect flag
(Note)
0: Rising edge of triangular waveform
1: Falling edge of triangular waveform
INV1
INV1
3
4
X
–
Output porality control bit
0 : Low active
1 : High active
Noting is assigned.
When write, set "0". When read, their contents are "0".
–
Note : INV1 is valid when INV0 = 0 and INV1 = 1.
3
6
1
Figure 1.15.1. Registers related to timers for three-phase motor control
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Three-phase output buffer register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0
Address
030A16
When reset
0016
R
W
Bit Symbol
Bit name
Function
DU0
DUB0
DV0
U phase output buffer 0
U phase output buffer 0
V phase output buffer 0
Setting in U phase output buffer 0
Setting in U phase output buffer 0
Setting in V phase output buffer 0
DVB0
DW0
V phase output buffer 0
Setting in V phase output buffer 0
W phase output buffer 0 Setting in W phase output buffer 0
W phase output buffer 0 Setting in W phase output buffer 0
DWB0
Nothing is assigned.
When write, set "0". When read, its content is "0".
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Three-phase output buffer register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB1
Address
030B16
When reset
0016
R
W
Bit Symbol
DU1
Bit name
Function
U phase output buffer 1
U phase output buffer 1
V phase output buffer 1
V phase output buffer 1
Setting in U phase output buffer 1
Setting in U phase output buffer 1
Setting in V phase output buffer 1
Setting in V phase output buffer 1
DUB1
DV1
DVB1
DW1
W phase output buffer 1 Setting in W phase output buffer 1
W phase output buffer 1 Setting in W phase output buffer 1
DWB1
Nothing is assigned.
When write, set "0". When read, its content is "0".
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Dead time timer (Note)
b7
b0
Symbol
DTT
Address
030C16
When reset
Indeterminate
R
W
Function
Values that can be set
1 to 255
Set dead time timer
Note: Use MOV instruction to write to this register.
Timer B2 interrupt occurrences frequency set counter (Note 1 to 3)
b3
b0
Symbol
ICTB2
Address
030D16
When reset
Indeterminate
R
W
Function
Values that can be set
1 to 15
Set occurrence frequency of timer B2
interrupt request
Note 1: When the effective interrupt output specification bit (INV01: bit 1 at 030816) is set to
"1" and three-phase motor control timer is operating, do not rewrite to this register.
Note 2: Do not write to this register at the timing of timer B2 overflow.
Note 3: Use MOV instruction to write to this register.
Figure 1.15.2. Registers related to timers for three-phase motor control
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Timer Ai register (Note)
Symbol
TA1
TA2
TA4
TB2
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0
034916,034816
034B16,034A16
034F16,034E16
035516,035416
b0 b7
Function
R W
Values that can be set
000016 to FFFF16
• Timer mode
Counts an internal count source
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2, 3)
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "000016", the counter does not operate
and a timer Ai interrupt does not occur.
Note 3: When writing to this register, use MOV instruction.
Timer Ai-1 register (Note)
(b15)
b7
(b8)
b0 b7
Symbol
TA11
TA21
TA41
Address
When reset
Indeterminate
Indeterminate
Indeterminate
b0
030316,030216
030516,030416
030716,030616
Function
R W
Values that can be set
000016 to FFFF16
Counts an internal count source
Note: Read and write data in 16-bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1
b0
Symbol
TRGSR
Address
034316
When reset
0016
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
TA4TGL
TA4TGH
Timer A4 event/trigger
select bit
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port function select register to I/O port, and port direction
register to "0".
Count start flag
Symbol
TABSR
Address
034016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Figure 1.15.3. Registers related to timers for three-phase motor control
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Three-phase motor driving waveform output mode (three-phase PWM output mode)
Setting “1” in the mode select bit (bit 2 at 030816) shown in Figure 1.15.1 causes three-phase PWM
output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.15.4, set
timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode
using the respective timer mode registers.
Timer Ai mode register
Symbol
TA1MR
TA2MR
TA3MR
Address
035716
035816
035A16
When reset
00000X00
00000X00
00000X00
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
0
1
1 0
Function
Bit symbol
Bit name
R W
– –
TMOD0
TMOD1
b1 b0
Operation mode
select bit
1 0 : One-shot timer mode
MR0
This bit is invalid in M16C/80 series.
Port output control is set by the function select registers A and B.
MR1
MR2
Invalid in three-phase PWM output mode.
External trigger select
bit
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Set to “0” in one-shot timer mode)
b7 b6
0 0 : f
TCK0
Count source select bit
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Timer B2 mode register
Symbol
TB2MR
Address
035D16
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00XX0000
2
0
0 0
Bit symbol
R W
Bit name
Function
b1 b0
0 0 : Timer mode
TMOD0
TMOD1
MR0
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
MR1
MR2
MR3
0 (Set to “0” in timer mode)
Invalid in timer mode.
When write, set "0". When read in timer mode, its content is
indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Figure 1.15.4. Timer mode registers in three-phase PWM output mode
114
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Figure 1.15.5 shows the block diagram for three-phase waveform mode. In “L” active output polarity in
three-phase waveform mode, the positive-phase waveforms (U phase, V phase, and W phase) and
___
___
___
negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output from P80, P81,
P72, P73, P74, and P75 as active on the “L” level. Of the timers used in this mode, timer A4 controls the U
___
___
phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the W phase and
___
W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2.
In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform
___
output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U
___
___
phase, V phase, and W phase).
To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (030C16), the value is written to the
reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2 at 030916). The timer can receive another
trigger again before the workings due to the previous trigger are completed. In this instance, the timer
performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the
timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to
come.
___
___
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
___
phase, and W phase) in three-phase waveform mode are output from respective ports by means of
setting “1” in the output control bit (bit 3 at 030816). Setting “0” in this bit causes the ports to be the high-
impedance state. This bit can be set to “0” not only by use of the applicable instruction, but by entering a
_______
falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases
___
concurrent L output disable function enable bit (bit 4 at 030816) causes one of the pairs of U phase and U
___
___
phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the output
control bit becomes the high-impedance state.
115
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Figure 1.15.5. Block diagram for three-phase waveform mode
116
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Triangular wave modulation
To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit
(bit 6 at 030816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 030916). In this mode, each
of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the
counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective interrupt
output specification bit (bit 1 at 030816), the frequency of interrupt requests that occur every time the timer
B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (030D16) for setting the
frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting π 0).
Setting “1” in the effective interrupt output specification bit (bit 1 at 030816) provides the means to choose
which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to
occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 030816).
An example of U phase waveform is shown in Figure 1.15.6, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16). And set “0” in DUB0 (bit 1 at 030A16). In
addition, set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16). Also, set “0” in the effective
interrupt output specification bit (bit 1 at 030816) to set a value in the timer B2 interrupt occurrence
frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content
becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output specifi-
cation bit (bit 1 at 030816), set in the effective interrupt polarity select bit (bit 0 at 030816) and set "1" in the
interrupt occurrence frequency set counter (030D16). These settings cause a timer B2 interrupt to occur
every other interval when the U phase output goes to “H”.
When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this
instance, the content of DU1 (bit 0 at 030B16) and that of DU0 (bit 0 at 030A16) are set in the three-phase
output shift register (U phase), the content of DUB1 (bit 1 at 030B16) and that of DUB0 (bit 1 at 030A16)
___
are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected,
however, no setting is made in the shift register even though the timer B2 counter’s content becomes
000016.
___
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-
___
tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output
signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for
___
setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of the U
phase waveform, which has the opposite phase of the former. The U phase waveform output that started
from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses
even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the
one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already
shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L"
level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts counting the
value written to timer A4-1 (030716, 030616), and starts outputting one-shot pulses. When timer A4 fin-
ishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the
three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level
changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot
pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the
three-phase output shift register on the U phase side is used, the workings in generating a U phase
waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U
117
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in
which the "L" level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the
opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the
___
___
values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases,
the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with
___
the U and U phases to generate an intended waveform.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Timber B2 interrupt occurres
Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
interrupt by use of the interrupt occurrences frequency
set circuit
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
The three-phase
shift register
shifts in
m
n
m
n
m
p
o
Timer A4 output
synchronization
with the falling
edge of the A4
output.
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
(Note 1)
U phase
Dead time
U phase
(Note 2)
U phase
Dead time
INV13(Triangular wave
modulation detect flag)
(Note 3)
Note 1: When INV14="0" (output wave Low active)
Note 2: When INV14="1" (output wave High active)
Note 3: Set to triangular wave modulation mode and to three-phase mode 1.
Figure 1.15.6. Timing chart of operation (1)
118
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Assigning certain values to DU0 (bit 0 at 030A16) and DUB0 (bit 1 at 030A16), and to DU1 (bit 0 at 030B16)
and DUB1 (bit 1 at 030B16) allows you to output the waveforms as shown in Figure 1.15.7, that is, to
___
___
output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase alone.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Rewriting timer A4 every timer B2 interrupt occurres.
Timer B2 interrupt occurres.
Rewriting three-phase buffer register.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
m
m
m
p
n
n
o
Timer A4 output
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to triangular wave modulation mode and to three-phase mode 1.
Figure 1.15.7. Timing chart of operation (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit
6 at 030816). Also, set “0” in the timers A4, A1, and A2-1 control bit (bit 1 at 030916). In this mode, the
timer registers of timers A4, A1, and of A2 comprise conventional timers A4, A1, and A2 alone, and reload
the corresponding timer register’s content to the counter every time the timer B2 counter’s content be-
comes 000016. The effective interrupt output specification bit (bit 1 at 030816) and the effective interrupt
output polarity select bit (bit 0 at 030816) go nullified.
An example of U phase waveform is shown in Figure 1.15.8, and the description of waveform output
workings is given below. Set “1” in DU0 (bit 0 at 030A16), and set “0” in DUB0 (bit 1 at 030A16). In addition,
set “0” in DU1 (bit 0 at 030B16) and set “1” in DUB1 (bit 1 at 030B16).
When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer
registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of
DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer
register’s content is set in the three-phase shift register every time the timer B2 counter’s content be-
comes 000016.
___
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (034F16, 034E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one
___
position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U
output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time
used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of
___
the U phase waveform, which has the opposite phase of the former. The U phase waveform output that
started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot
pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the effect of
the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already
shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L”
level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase buffer
registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of DUB1 and
___
DUB0 are set in the three-phase shift register (U phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase
___
___
output shift register on the U phase side is used, the workings in generating a U phase waveform, which
has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In
this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of
the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of
the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2
___
___
and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase
___
of the former, have the corresponding timers work similarly to dealing with the U and U phases to gener-
ate an intended waveform.
120
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Data transfer is made from the three-
phase buffer register to the three-
phase shift register in step with the
timing of the timer B overflow.
Interrupt occurres.
Rewriting the value of timer A4.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
The three-phase
shift register
n
p
Timer A4 output
m
o
shifts in
synchronization
with the falling
edge of timer A4.
U phase output
signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 1.15.8. Timing chart of operation (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
___
Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U
phase output to “H” as shown in Figure 1.15.9.
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Interrupt occurres.
Rewriting the value of timer A4.
Interrupt occurres.
Rewriting the value of timer A4.
Data transfer is made from the three-
phase buffer register to the three-
phase shift register in step with the
timing of the timer B overflow.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Rewriting three-phase
output buffer register
The three-phase
shift register shifts
in synchronization
Timer A4 output
m
n
p
with the falling
edge of timer A4.
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 1.15.9. Timing chart of operation (4)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O is configured as five channels: UART0 to UART4.
UART0 to 4
UART0 to UART4 each have an exclusive timer to generate a transfer clock, so they operate independently
of each other.
Figure 1.16.1 and 1.16.2 show the block diagram of UARTi (i=0 to 4). Figures 1.16.3 and 1.16.4 show the
block diagram of the transmit/receive unit.
UARTi has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 036016,
036816, 033816, 032816 and 02F816) determine whether UARTi is used as a clock synchronous serial I/O or
as a UART.
Although a few functions are different, UART0 to UART4 have almost the same functions.
UART2 to UART4, in particular, are compliant with the SIM interface with some extra settings added in
clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates
an interrupt request if the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 to UART4, and Figures 1.16.5 through 1.16.11
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 1.16.1. Comparison of functions of UART0 to UART4
UART4
Function
UART0
UART1
UART2
UART3
Possible(Note 1)
(Note 1)
(Note 1)
CLK polarity selection
Possible(Note 1) Possible(Note 1) Possible
Possible
Possible
Possible
Possible(Note 2)
(Note 2)
(Note 1)
(Note 2)
LSB first / MSB first selection Possible(Note 1) Possible(Note 1) Possible
(Note 1)
(Note 1)
Possible(Note 1) Possible(Note 1) Possible
Continuous receive mode
selection
Possible
Transfer clock output from
multiple pins selection
Possible(Note 1) Impossible
Impossible
Impossible
Possible(Note 4)
Impossible
Possible
Impossible
Impossible
Possible(Note 4)
Impossible
Possible
Impossible
Possible
Separate CTS/RTS pins
Serial data logic switch
Sleep mode selection
Impossible
Impossible
Impossible
(Note 4)
Impossible
Possible
Possible(Note 3) Possible(Note 3) Impossible
TxD, RxD I/O polarity switch Impossible
TxD, RxD port output format CMOS output
Impossible
CMOS output
Impossible
Impossible
Possible
N-channel open
drain output
CMOS output
Possible(Note 4)
Possible
CMOS output
Possible(Note 4)
Possible
(Note 4)
Parity error signal output
Bus collision detection
Impossible
Impossible
Possible
Possible
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART0)
TxD0
RxD0
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate
generator
f
f
f
1
Internal
8
Transmit
clock
UART transmission
32
1/16
1 / (n0+
1)
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
RTS
0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS/RTS separated
CTS
0
CTS0 from UART1
(UART1)
RxD1
TxD1
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
control circuit
Clock source selection
Clock synchronous type
Bit rate
generator
f
f
1
Internal
8
UART transmission
1/16
Transmit
clock
f
32
1 / (n1+1)
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
External
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK1
CTS/RTS disabled
CTS/RTS separated
RTS
1
CTS1 / RTS1
/ CTS0 / CLKS1
V
CC
Clock output pin
select switch
CTS/RTS disabled
CTS
1
CTS
0
CTS0 to UART0
(UART2)
TxD
RxD polarity
reversing circuit
polarity
reversing
circuit
RxD2
TxD2
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
f
f
f
1
Bit rate
generator
Internal
8
UART transmission
1/16
Transmit
clock
1 / (n2+1)
32
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK2
CTS/RTS
selected
CTS/RTS disabled
RTS
2
CTS2 / RTS2
Vcc
CTS/RTS disabled
CTS
2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART3)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD3
TxD3
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate
generator
f
f
f
1
Internal
8
UART transmission
1/16
Transmit
clock
32
1 / (n2+1)
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK3
CTS/RTS
selected
CTS/RTS disabled
RTS
3
CTS3 / RTS3
Vcc
CTS/RTS disabled
CTS
3
(UART4)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD4
TxD4
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate
generator
f
f
f
1
Internal
8
UART transmission
1/16
Transmit
clock
1 / (n2+1)
32
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK4
CTS/RTS
selected
CTS/RTS disabled
RTS
4
4
CTS4 / RTS4
Vcc
CTS/RTS disabled
CTS
n3 : Values set to UART3 bit rate generator (BRG3)
n4 : Values set to UART4 bit rate generator (BRG4)
Figure 1.16.2. Block diagram of UARTi (i = 3, 4)
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Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
PAR
enabled
UART
UART (9 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D8
D7
D6
D
5
D
4
D
3
D2
D
1
D0
Address 036616
Address 036716
Address 036E16
Address 036F16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D
7
D
6
D5
D4
D3
D2
D1
D0
D8
Address 036216
Address 036316
Address 036A16
Address 036B16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
SP: Stop bit
PAR: Parity bit
“0”
Clock synchronous
type
Figure 1.16.3. Block diagram of UARTi (i = 0, 1) transmit/receive unit
126
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
No reverse
RxD data
RxDi
reverse circuit
Reverse
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UARTi receive register
PAR
disabled
UART(7 bits)
1SP
2SP
PAR
SP
SP
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address 033E16
Address 033F16
Address 032E16
Address 032F16
Address 02FE16
Address 02FF16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D
7
D
6
D5
D
4
D
3
D
2
D
1
D
0
D
8
Address 033A16
Address 033B16
Address 032A16
Address 032B16
Address 02FA16
Address 02FB16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
Clock
synchronous
type
PAR
disabled
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UARTi transmit register
“0”
Clock
synchronous type
Error signal output
disable
No reverse
TxDi
TxD data
reverse circuit
Error signal
output circuit
Reverse
Error signal output
enable
SP : Stop bit
PAR : Parity bit
i
: 2 to 4
Figure 1.16.4. Block diagram of UARTi (i = 2 to 4) transmit/receive unit
127
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Symbol
U0TB
U1TB
U2TB
U3TB
U4TB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
UARTi transmit buffer register (Note)
036316, 036216
036B16, 036A16
033B16, 033A16
032B16, 032A16
02FB16, 02FA16
(b15)
b7
(b8)
b0 b7
b0
Function
R W
Transmit data
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register
Symbol
U0RB
U1RB
U2RB
U3RB
U4RB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
036716, 036616
036F16, 036E16
033F16, 033E16
032F16, 032E16
02FF16, 02FE16
(b8)
(b15)
b7
b0 b7
b0
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
Arbitration lost detecting
flag (Note 2)
0 : Not detected
1 : Detected
Invalid
ABT
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
Parity error flag (Note 1)
Error sum flag (Note 1)
Invalid
Invalid
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
036016, 036816, 033816, 032816 and 02F816) are set to “000
“0”.
2” or the receive enable bit is set to
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0”
when the lower byte of the UARTi receive buffer register (addresses 036616, 036E16, 033E16
032E16 and 02FE16) is read out.
,
Note 2: Arbitration lost detecting flag is allocated to U2RB, U3RB and U4RB and nothing but “0” may
be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set "0". When read,
the value of this bit is “0”.
Symbol
U0BRG
U1BRG
U2BRG
U3BRG
U4BRG
Address
036116
036916
033916
032916
02F916
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
UARTi bit rate generator (Note 1, 2)
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
Figure 1.16.5. Serial I/O-related registers (1)
128
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
036016, 036816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock (Note 1)
1 : External clock (Note 2)
0 : Internal clock
1 : External clock (Note 2)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Set to “0”
Note 1: Select CLK output by the corresponding function select registers A, B and C.
Note 2: Set the corresponding function select register A to the I/O port.
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR (i=2 to 4)
Address
033816, 032816, 02F816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
SMD0
Must be fixed to 001
b2 b1 b0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : (Note)
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock (Note 2)
1 : External clock (Note 3)
0 : Internal clock
1 : External clock (Note 3)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
Invalid
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
IOPOL
Usually set to “0”
Usually set to “0”
2
Note 1: Bit 2 to bit 0 are set to “010
2
” when I C mode is used.
Note 2: Select CLK output by the corresponding function select registers A, B and C.
Note 3: Set the corresponding function select register A to the I/O port.
Figure 1.16.6. Serial I/O-related registers (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
036416, 036C16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
b1 b0
CLK0 BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
NCH
CTS/RTS disable bit
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Set to “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Set to “0”
Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 2: Select RTS output using the corresponding function select registers A and B.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
033C16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
b1 b0
CLK0
CLK1
BRG count source
select bit
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
1
8
is selected
is selected
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Inhibited
1
is selected
is selected
8
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
Nothing is assigned.
When write, set “0”. When read, the value of this bit is “0”.
0 : Transmit data is output at
Set to “0”
CKPOL CLK polarity select bit
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
Transfer format select bit
(Note 3)
UFORM
Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 2: Select RTS output using the corresponding function select registers A and B.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.16.7. Serial I/O-related registers (3)
130
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=3,4)
Address
032C16, 02FC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
R W
Bit name
b1 b0
b1 b0
CLK0 BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Inhibited
1 0 : f32 is selected
1 1 : Inhibited
CLK1
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
NCH
CTS/RTS disable bit
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Set to “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
UFORM
Transfer format select bit
(Note 3)
Note 1: Set the corresponding function select register A to I/O port, and port direction register to “0”.
Note 2: Select RTS output using the corresponding function select registers A and B.
Note 3: Valid only in clock syncronous serial I/O mode and 8 bits UART mode.
Figure 1.16.8. Serial I/O-related registers (4)
131
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
036516 036D16
When reset
0216
,
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1 (i=2 to 4)
Address
033D16, 032D16, 02FD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
UiIRS UARTi transmit interrupt 0 : Transmit buffer empty
0 : Transmit buffer empty
(TI = 1)
cause select bit
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
1 : Transmit is completed
(TXEPT = 1)
UiRRM UARTi continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
UiLCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
UiERE Error signal output
enable bit
Set to “0”
0 : Output disabled
1 : Output enabled
Figure 1.16.9. Serial I/O-related registers (5)
132
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
037016
When reset
X00000002
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
UART1 transmit
interrupt cause select bit
Set to “0”
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Set to “0”
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 : CTS/RTS shared pin
1 : CTS/RTS separated
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
UARTi special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR (i=2 to 4)
Address
033716, 032716, 02F716
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
IIC mode select bit
0 : Normal mode
1 : IIC mode
Set to “0”
IICM
ABC
BBS
Arbitration lost detecting 0 : Update per bit
Set to “0”
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
Bus busy flag
Set to “0”
Set to “0”
(Note1)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
0 : Rising edge of transfer clock
1 : Underflow signal of timer Ai
(Note 2)
Bus collision detect
sampling
clock select bit
Set to “0”
ABSCS
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
Auto clear function
select bit of transmit
enable bit
Set to “0”
Set to “0”
0 : Ordinary
1 : Falling edge of RxDi
Transmit start condition
select bit
SSS
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note 1: Nothing but "0" may be written.
Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4
underflow signal.
Figure 1.16.10. Serial I/O-related registers (6)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR2 (i=2 to 4)
Address
033616, 032616, 02F616
When reset
0016
Bit
symbol
Function
Bit name
R W
0 : NACK/ACK interrupt
DMA source - ACK
IICM2 IIC mode select bit 2
Transfer to receive buffer at the rising edge of
last bit of receive clock
Receive interrupt is occurred at the rising
edge of last bit of receive clock
1 : UART transfer/receive interrupt
DMA source - UART receive
Transfer to receive buffer at the falling edge
of last bit of receive clock
Receive interrupt is occurred at the falling
edge of last bit of receive clock
0 : Disabled
1 : Enabled
CSC Clock synchronous bit
SWC SCL wait output bit
0 : Disabled
1 : Enabled
ALS SDA output stop flag
0 : Disabled
1 : Enabled
STC UARTi initialize bit
0 : Disabled
1 : Enabled
SWC2 SCL wait output bit 2
0 : UARTi clock
1 : 0 output
SDHI SDA output inhibit bit
0 : Enabled
1 : Disabled (high impedance)
SHTC Start/stop condition
control bit
Must set to "1" in selecting IIC mode.
Figure 1.16.11. Serial I/O-related registers (7)
134
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
033516
When reset
000XXXXX
2
Bit name
Function
R W
Bit symbol
Nothing is assigned. These bits can neither be set nor reset. When read,
their contents are indeterminate.
b7 b6 b5
SDA2(TxD2) digital
DL0
000:Without delay
delay time set bit
(Note 1,2)
001:2-cycle of 1/f(XIN
010:3-cycle of 1/f(XIN
011:4-cycle of 1/f(XIN
100:5-cycle of 1/f(XIN
101:6-cycle of 1/f(XIN
110:7-cycle of 1/f(XIN
111:8-cycle of 1/f(XIN
)
)
)
)
)
)
)
DL1
DL2
Note 1: These bits are used for SDA
2(TxD2) output digital delay when using UART2 for IIC interface.
Otherwise, must set to "000".
Note 2: When external clock is selected, delay is increased approx. 100ns.
UARTi special mode register 3 (i=3,4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
032516
02F516
When reset
U3SMR3
U4SMR3
00000000
00000000
2
2
Bit symbol
R W
Bit name
Function
SS port function enable bit
(Note 3)
0: SS function disable
1: SS function enable
SSE
0: Without clock delay
1: With clock delay
Clock phase set bit
CKPH
DINC
0: Select TxDi and RxDi
(master mode) (Note 5)
1: Select STxDi and SRxDi
(slave mode) (Note 6)
Serial input port set bit
0: CLKi is CMOS output
1: CLKi is N-channel open drain
output
NODC
ERR
Clock output select bit
Fault error flag
0: Without fault error
1: With fault error
(Note 4)
b7 b6 b5
SDAi(TxD2) digital
000 :Without delay
DL0
DL1
DL2
delay time set bit
(Note 1,2)
001 :2-cycle of 1/f(XIN
010 :3-cycle of 1/f(XIN
011 :4-cycle of 1/f(XIN
100 :5-cycle of 1/f(XIN
101 :6-cycle of 1/f(XIN
110 :7-cycle of 1/f(XIN
111 :8-cycle of 1/f(XIN
)
)
)
)
)
)
)
Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface.
Otherwise, must set to "000".
Note 2: When external clock is selected, delay is increased approx. 100ns.
Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control
register 0) to "1".
Note 4: Nothing but "0" may be written.
Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the
RxDi function select register A for input/output port and the port direction register to "0".
Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and
SRxDi function select register A for input/output port and the port direction register to "0".
Figure 1.16.12. Serial I/O-related registers (8)
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(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.17.1
and 1.17.2 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.1 shows the
UARTi transmit/receive mode register.
Table 1.17.1. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 036016, 036816, 033816,
Transfer data format
Transfer clock
032816, 02F816 = “0”) : fi/ 2(n+1) (Note)
fi = f1, f8, f32
_
CLK is selected by the corresponding port function select register, periph-
eral function select register and peripheral subfunction select register.
• When external clock is selected (bit 3 at addresses 036016, 036816, 033816 ,
032816, 02F816= “1”) : Input from CLKi pin
_
Set the corresponding function select register A to I/O port
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0”
_______
_______
_
_
When CTS function selected, CTS input level = “L”
TxD output selected by the corresponding function select register A, B and C.
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,
032C16, 02FC16) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,
032C16, 02FC16) = “1”: CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”
_
Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16, 032D16, 02FD16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,
032C16, 02FC16) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,
032C16, 02FC16) = “1”: CLKi input level = “L”
• When transmitting
_
Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at address
Interrupt request
033D16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer from
generation timing
UARTi transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 037016, bit 4 at
address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data
transmission from UARTi transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Note : “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
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Clock synchronous serial I/O mode
Table 1.17.2. Specifications of clock synchronous serial I/O mode (2)
Item
Specification
Error detection
• Overrun error (Note 1)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Select function
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note 2)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
_______ _______
• Separate CTS/RTS pins (UART0) (Note 2)
_______
_______
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2 to UART4)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2 to UART4)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Note 1: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit will not change.
_______ _______
Note 2: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
036016, 036816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock (Note 1)
1 : External clock (Note 2)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Set to “0” in clock synchronous serial I/O mode)
Note 1: Select CLK output by the corresponding function select registers A, B and C.
Note 2: Set the corresponding function select register A to the I/O port.
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR (i=2 to 4)
Address
033816, 032816, 02F816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock (Note 2)
1 : External clock (Note 3)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note 1)
0 : No reverse
1 : Reverse
Note 1: Usually set to “0”.
Note 2: Select CLK output by the corresponding function select registers A, B and C.
Note 3: Set the corresponding function select register A to the I/O port.
Figure 1.17.1. UARTi transmit/receive mode register in clock synchronous serial I/O mode
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Clock synchronous serial I/O mode
Table 1.17.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
_______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
_______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open drain is selected, this
pin is in floating state.)
Table 1.17.3. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
(Outputs dummy data when performing reception only)
Serial data output
(Note 1)
(P6 , P6
3
7
, P70,
P9 , P9
2
6)
RxDi
(P6 , P6
P9 , P9
Serial data input
(Note 2)
Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
(Can be used as an input port when performing transmission only)
2
6
, P71,
1
7)
Transfer clock output
(Note 1)
Internal/external clock select bit (bit 3 at addresses 036016, 036816
033816, 032816, 02F816) = “0”
,
CLKi
(P6 , P6
P9 , P9
1
5
, P72,
0
5)
Internal/external clock select bit (bit 3 at addresses 036016, 036816
,
Transfer clock input
(Note 2)
033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = “0”
CTSi/RTSi
(P6 , P6 , P7
P9 , P9
CTS input
3,
(Note 2)
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16
,
0
4
4)
02FC16) =“0”
3
CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16
032C16, 02FC16) = “0”
,
Port P6
0, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
RTS output (Note 1)
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16
,
032C16, 02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16
,
032C16, 02FC16) = “1”
Programmable I/O port
(Note 2)
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16
032C16, 02FC16) = “1”
,
_______ _______
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B
and C.
Note 2: Select I/O port by the corresponding function select register A.
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• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
“0”
“1”
“0”
“H”
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
D0
D
1
D2
D3
D4
D5
D6
D7
D0
D
1
D2
D3
D4
D5
D
6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = TCLK = 2(n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
“H”
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLKi
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
fEXT: frequency of external clock
Figure 1.17.2. Typical transmit/receive timings in clock synchronous serial I/O mode
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Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.17.3, the CLK polarity select bit (bit 6 at addresses 036416, 036C16, 033C16,
032C16, 02FC16) allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK
i
Note 1: The CLK pin level when not
transferring data is “H”.
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D
0
D
1
D
2
D
D4
D
D
D
RXDi
• When CLK polarity select bit = “1”
CLK
i
Note 2: The CLK pin level when not
transferring data is “L”.
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Figure 1.17.3. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.17.4, when the transfer format select bit (bit 7 at addresses 036416, 036C16,
033C16, 032C16, 02FC16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format
is “MSB first”.
• When transfer format select bit = “0”
CLK
i
D0
D
1
D
2
D
3
D
D
4
4
D
5
D
6
D7
TXDi
LSB first
D
1
D
2
D
3
D
5
D
6
D7
D
0
RXDi
• When transfer format select bit = “1”
CLK
i
D
D
7
7
D
6
D
5
D
4
D
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
2
D
1
D0
RXDi
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.17.4. Transfer format
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(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the port function select register (bits of related to-P64 and P65). (See Figure 1.17.5.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
_______ _______
this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.17.5. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 037016, bit 5 at address 033D16,
032D16, 02FD16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the
receive buffer register is read out, the unit simultaneously goes to a receive enable state without
having to set dummy data to the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2 to UART4)
When the data logic select bit (bit6 at address 033D16, 032D16, 02FD16) = “1”, and writing to transmit
buffer register or reading from receive buffer register, data is reversed. Figure 1.17.6 shows the
example of serial data logic switch timing.
•When LSB first
“H”
Transfer clock
“L”
“H”
i
TxD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(no reverse)
“L”
“H”
“L”
TxD
i
(reverse)
Figure 1.17.6. Serial data logic switch timing
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Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.18.1 and 1.18.2 list the specifications of the UART mode. Figure 1.18.1 shows the
UARTi transmit/receive mode register.
Table 1.18.1. Specifications of UART Mode (1)
Item
Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816,
02F816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 036016, 036816, 033816, 032816,
02F816 =“1”) : fEXT/16(n+1)(Note 1) (Note 2)
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 036516, 036D16, 033D16, 032D16,
02FD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 036516, 036D16, 033D16,
032D16, 02FD16) = “0”
_______
_______
- When CTS function selected, CTS input level = “L”
- TxD output is selected by the corresponding function select register A, B
and C.
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 036516, 036D16, 033D16, 032D16,
02FD16) = “1”
- Start bit detection
Interrupt request
generation timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 037016, bit 4 at
address 033D16, 032D16, 02FD16) = “0”: Interrupts requested when data transfer
from UARTi transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 037016, bit 4 at
address 033D16, 032D16, 02FD16) = “1”: Interrupts requested when data
transmission from UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
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Clock asynchronous serial I/O (UART) mode
Table 1.18.2. Specifications of UART Mode (2)
Item
Specification
Error detection
• Overrun error (Note)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
_______ _______
Select function
• Separate CTS/RTS pins (UART0)
_______
_______
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2 to UART4)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TxD, RxD I/O polarity switch (UART2 to UART4)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Note: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit will not change.
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Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
036016, 036816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
0 : Internal clock
1 : External clock (Note)
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note: Set the corresponding port function select register A to I/O port.
UARTi transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR (i=2 to 4)
Address
033816, 032816, 02F816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
0 : Internal clock
1 : External clock (Note 2)
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note 1)
0 : No reverse
1 : Reverse
Note 1: Usually set to “0”.
Note 2: Set the corresponding port function select register A to I/O port.
Figure 1.18.1. UARTi transmit/receive mode register in UART mode
145
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 1.18.3 lists the functions of the input/output pins during UART mode. This table shows the pin
_______ _______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel
open drain is selected, this pin is in floating state.)
Table 1.18.3. Input/output pin functions in UART mode
Pin name
TxDi
(P6 , P6
P9 , P9
RxDi
(P6 , P6
P9 , P9
Function
Method of selection
Serial data output
(Note 1)
3
7, P70,
6)
2
Serial data input
(Note 2)
Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
(Can be used as an input port when performing transmission only)
2
6
, P7
1
,
,
1
7)
Programmable I/O port
(Note 2)
Internal/external clock select bit (bit 3 at addresses 036016, 036816
033816, 032816, 02F816) = “0”
,
CLKi
(P6 , P6
P9 , P9
1
5
)
, P7
2
0
5
Transfer clock input
(Note 2)
Internal/external clock select bit (bit 3 at addresses 036016, 036816
033816, 032816, 02F816) = “1”
,
Port P6
1, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bits 0 and 5 at address 03C716) = “0”
CTSi/RTSi
(P6 , P6 , P7
P9 , P9
CTS input
(Note 2)
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16
032C16, 02FC16) =“0”
CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16
,
0
4
3,
3
4)
,
032C16, 02FC16) = “0”
Port P6
0, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16
02FC16) = “0”
,
RTS output
(Note 1)
CTS/RTS function select bit (bit 2 at addresses 036416, 036C16, 033C16
,
032C16, 02FC16) = “1”
Programmable I/O port
(Note 2)
________ _______
CTS/RTS disable bit (bit 4 at addresses 036416, 036C16, 033C16, 032C16
02FC16) = “1”
,
(When separate CTS/RTS pins function is not selected)
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B
and C.
Note 2: Select I/O port by the corresponding function select register A.
146
Preliminary Specifications REV.D
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transmit enable bit = “0”
Start
bit
Parity Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
The above timing applies to the following settings :
• Parity is enabled.
1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
• One stop bit.
n : value set to BRGi
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1
, f8, f32)
• Two stop bits.
fEXT : frequency of BRGi count source (external clock)
• CTS function is disabled.
n : value set to BRGi
• Transmit interrupt cause select bit = “0”.
Figure 1.18.2. Typical transmit timings in UART mode
147
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
D
1
D7
RxDi
D0
Sampled “L”
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
“0”
“H”
“L”
RTSi
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Figure 1.18.3. Typical receive timing in UART mode
_______ _______
(a) Separate CTS/RTS pins function (UART0)
_______ _______
_______
With the separate CTS/RTS bit (bit 6 at address 037016) is set to “1”, the unit outputs/inputs the CTS
_______
and RTS signals on different pins. (See Figure 1.18.4.) This function is valid only for UART0. Note
_______ _______
that if this function is selected, the CTS/RTS function for UART1 cannot be used.
_______ _______
_______ _______
Set both CTS/RTS function select bit (bit 2 at address 036C16) of UART1and CTS/RTS disable bit (bit
4 at address 036C16)of UART1 to "0" and set P64 to input port by the function select register.
Microcomputer
IC
TX
D
0
(P6
3)
IN
R
XD0
(P6
2)
OUT
RTS0 (P6
0
)
CTS
RTS
CTS0 (P6
4
)
_______ _______
Figure 1.18.4. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
036016, 036816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
148
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(c) Function for switching serial data logic (UART2 to UART4)
When the data logic select bit (bit 6 of address 033D16, 032D16, 02FD16) is assigned 1, data is inverted
in writing to the transmission buffer register or reading the reception buffer register. Figure 1.18.5
shows the example of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
“H”
Transfer clock
“L”
“H”
TxD
i
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
“L”
“H”
“L”
TxD
i
(reverse)
ST : Start bit
P : Even parity
SP : Stop bit
Figure 1.18.5. Timing for switching serial data logic
(d) TxD, RxD I/O polarity reverse function (UART2 to UART4)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(e) Bus collision detection function (UART2 to UART4)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.18.6
shows the example of detection timing of a buss collision (in UART mode).
“H”
Transfer clock
“L”
“H”
TxD
i
i
ST
ST
SP
SP
“L”
“H”
“L”
RxD
Bus collision detection
interrupt request signal
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
ST : Start bit
SP : Stop bit
Figure 1.18.6. Detection timing of a bus collision (in UART mode)
149
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding some
extra settings in UART2 to UART4 clock-asynchronous serial I/O mode allows the user to effect this function.
Table 1.19.1 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface).
Table 1.19.1. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 to 0 of addresses 033816, 032816, 02F816 = “1012”)
• One stop bit (bit 4 of addresses 033816, 032816, 02F816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 033D16, 032D16, 02FD16 = “0”).
Set transfer format to LSB (bit 7 of address 033C16, 032C16, 02FC16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and 6 of addresses 033816, 032816, 02F816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 033D16, 032D16, 02FD16 = “1”)
Set transfer format to MSB (bit 7 of address 033C16, 032C16, 02FC16 = “1”)
• With the internal clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “0”)
Transfer clock
: fi / 16 (n + 1)
• With an external clock chosen (bit 3 of addresses 033816, 032816, 02F816 = “1”)
: fEXT / 16 (n+1) (Note 1) (Note 2)
(Note 1) : fi=f1, f8, f32
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 033C16, 032C16, 02FC16 = “1”)
Other settings
• The sleep mode select function is not available for UART2 and UART3
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 033D16,
032D16, 02FD16 = “1”)
• Set N-channel open drain output to TxD and RxD pins in UART3 and 4 (bit 5 of
address 032C16, 02FC16 = “1”)
Transmission start condition
Reception start condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 033D16, 032D16, 02FD16) = “1”
- Transmit buffer empty flag (bit 1 of address 033D16, 032D16, 02FD16) = “0”
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 033D16, 032D16, 02FD16) = “1”
- Detection of a start bit
• When transmitting
Interrupt request
generation timing
When data transmission from the UART2 to UART4 transfer register is completed (bit
4 of address 033D16, 032D16, 02FD16 = “1”)
• When receiving
When data transfer from the UART2 to UART4 receive register to the UART2 to
UART4 receive buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TxDi pin by use of the parity
error signal output function (bit 7 of address 033D16, 032D16, 02FD16 = “1”) when a
parity error is detected
- On the transmission side, a parity error is detected by the level of input to the RxDi
pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi
receive interrupt request bit will not change.
150
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
(Note 1)
Data is set in UARTi transmit buffer register
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
Parity
bit
Stop
bit
TxD
i
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
SP
SP
RxD
i
A “L” level returns from SIM card due
to the occurrence of a parity error.
The level is detected by the
interrupt routine.
Signal conductor level
(Note 2)
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D6
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
The level is detected by
the interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings : Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
• Parity is enabled.
fi : frequency of BRGi count source (f
1, f8, f32)
• One stop bit.
f
EXT : frequency of BRGi count source (external clock)
• Transmit interrupt cause select bit = “1”.
n : value set to BRGi
Tc
Transfer clock
“1”
Receive enable
bit (RE)
“0”
Parity
bit
Stop
bit
Start
bit
RxD
i
SP
ST
D
0
D
1
D
2
D
D
3
D
4
D
D
5
D
7
P
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
SP
D6
TxD
i
A “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 2)
SP
ST
D
0
D
1
D2
3
D4
5
D7
P
D
0
D
1
D
2
D
3
D
4
D
5
D7
D6
SP
D6
“1”
Receive complete
flag (RI)
“0”
Read to receive buffer
Read to receive buffer
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings : Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
fi : frequency of BRGi count source (f
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
1, f8, f32)
f
Note 1: After writing to the transfer buffer at above timing, transmission starts at the timing of BRG overflow.
Note 2: Equal in waveform because TxD and RxD are connected.
i
i
Figure 1.19.1. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
151
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
With the error signal output enable bit (bit 7 of address 033D16, 032D16, 02FD16) assigned “1”, you
can output an “L” level from the TxDi pin when a parity error is detected. In step with this function, the
generation timing of a transmission completion interrupt changes to the detection timing of a parity
error signal. Figure 1.19.2 shows the output timing of the parity error signal.
• LSB first
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxDi
TxDi
“L”
“H”
“L”
Hi-Z
“1”
“0”
Receive
complete flag
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.19.2. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxDi. If you choose the inverse format, D7 data is inverted and
output from TxDi.
Figure 1.19.3 shows the SIM interface format.
Transfer
clcck
TxDi
(direct)
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0
P
P
TxDi
(inverse)
P : Even parity
Figure 1.19.3. SIM interface format
152
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Figure 1.19.4 shows the example of connecting the SIM interface. Connect TxDi and RxDi and apply pull-
up.
Microcomputer
(Note)
SIM card
TxD
i
RxD
i
Note :TxDi pin is N-channel open drain and needs a pull-up resistance.
Figure 1.19.4. Connecting the SIM interface
153
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
ent
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e
d
m
n
p
o
U
l
e
M16C/80 group
v
e
d
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
UARTi Special Mode Register (i = 2 to 4)
UART2 to UART4 operate the IIC bus interface (simple IIC bus) using the UARTi special mode register
(addresses 033616, 032616 and 02F616 [i = 2 to 4]) and UARTi special mode register 2 (addresses
033616, 032616 and 02F616 [i = 2 to 4]). UART3 and UART4 add special functions using UARTi special
mode resister 3 (addresses 032516 and 02F516 [i = 3 or 4]).
(1) IIC Bus Interface Mode
2
The I C bus interface mode is provided with UART2 to UART4.
Table 1.20.1 shows the construction of the UARTi special mode register and UARTi special mode regis-
ter 2.
2
2
When the I C mode select bit (bit 0 in addresses 033716, 032716 and 02F716) is set to “1”, the I C bus
2
(simple I C bus) interface circuit is enabled.
2
To use the I C bus, set the SCLi and the SDAi of both master and slave to output with the function select
register. In UART3 and 4, set the data output select bit (bit 5 in address 032C16 and 02FC16) to N-channel
open drain output.
Table 1.20.1 shows the relationship of the IIC mode select bit to control. To use the chip in the clock
synchronized serial I/O mode or clock asynchronized serial I/O mode, always set this bit to “0”.
Table 1.20.1. Features in I2C mode
2
Function
Normal mode
I C mode (Note 1)
Start condition detection or stop
condition detection
Bus collision detection
Factor of interrupt number 39 to 41 (Note 2)
1
2
3
4
5
6
7
Factor of interrupt number 33, 35, 37 (Note 2)
Factor of interrupt number 34, 36, 38 (Note 2)
UARTi transmission output delay
UARTi transmission
UARTi reception
Not delayed
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed
P7
P7
P7
0
, P9
, P9
, P9
2
, P9
, P9
, P9
6
at the time when UARTi is in use
at the time when UARTi is in use
at the time when UARTi is in use
TxD
RxD
CLKi
i
(output)
(input)
SDAi (input/output) (Note 3)
SCLi (input/output)
1
1
7
i
2
0
5
P72, P90, P95
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
Acknowledgment detection (ACK)
8
9
UARTi reception
Noise filter width
15ns
50ns
Reading the terminal when 0 is
assigned to the direction register value of the direction register
Reading the terminal regardless of the
10 Reading P7
1, P91, P97
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P7
when the port is selected (Note 3)
0, P92, P96
11 Initial value of UARTi output
2
Note 1: Make the settings given below when I C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UARTi transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when IIC mode (IIC mode select bit = "1") is valid and serial I/O is invalid.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
UARTi special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR (i=2 to 4)
Address
033716, 032716, 02F716
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit
R W
name
I C mode select bit
2
0 : Normal mode
1 : I C mode
IICM
Set to “0”
2
ABC
BBS
Arbitration lost detecting 0 : Update per bit
Set to “0”
Set to “0”
Set to “0”
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
Bus busy flag
(Note 1)
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling clock select bit
Set to “0”
Set to “0”
Set to “0”
0 : Rising edge of transfer
ABSCS
clock
(Note 2)
1 : Underflow signal of timer Ai
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
SSS
Auto clear function
select bit of transmit
enable bit
0 : Ordinary
1 : Falling edge of RxDi
Transmit start condition
select bit
Nothing is assigned.
When write, set "0". When read, the content is "0".
Note 1: Nothing but "0" may be written.
Note 2: UART2 : timer A0 underflow signal, UART3 : timer A3 underflow signal, UART4 : timer A4
underflow signal.
UARTi special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiSMR2 (i=2 to 4)
Address
033616, 032616, 02F616
When reset
0016
Bit
symbol
Function
Bit name
R W
Refer to Table 1.20.2.
IICM2
IIC mode select bit 2
0 : Disabled
1 : Enabled
CSC
Clock synchronous bit
SCL wait output bit
SWC
0 : Disabled
1 : Enabled
ALS
SDA output stop flag
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
STC
UARTi initialize bit
SWC2
SCL wait output bit 2
0 : UARTi clock
1 : 0 output
SDHI
SDA output inhibit bit
0 : Enabled
1 : Disabled (high impedance)
SHTC
Start/stop condition
control bit
Set to "1" in selecting IIC mode.
Figure 1.20.1. UART2 special mode register
155
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
P70/TXD2/SDA
Timer
I/O
To DMAi
UART2
transmission/NACK
interrupt request
Selector
UART2
IICM=1
IICM=0
IICM=0 or IICM2=1
delay
Transmission register
UART2
IICM=1 and
IICM2=0
SDHI
ALS
To DMAi
D
Q
Arbitration
IICM=1
T
IICM=0 or
IICM2=1
Noize
UART2 reception/ACK
interrupt request
DMAi request
Filter
Reception register
UART2
IICM=0
IICM=1 and
IICM2=0
Start condition detection
Bus
busy
S
R
Q
Stop condition detection
L-synchronous
NACK
D
Q
Q
Falling edge
detection
output enabling bit
T
P71/RXD2/SCL
D
R
I/0
ACK
T
Data register
9th pulse
Bus collision/start, stop
condition detection
interrupt request
Selector
IICM=1
Internal clock
SWC2
UART2
IICM=1
IICM=1
Bus collision
detection
CLK
control
IICM=0
Noize
Filter
UART2
External clock
Noize
Filter
Falling edge of 9th pulse
SWC
R
S
IICM=0
Port reading
UART2
IICM=0
* With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P71 of the direction register.
P72/CLK2
Serector
I/0
Timer
Figure 1.20.2. Functional block diagram for I2C mode
Figure 1.20.2 is a block diagram of the IIC bus interface.
To explain the control bit of the IIC bus interface, UART2 is used as an example.
UART2 Special Mode Register (Address 033716)
Bit 0 is the IIC mode select bit. When set to “1”, ports P70, P71 and P72 operate respectively as the
SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P72. A delay circuit is added to
SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P71
(SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2
transmission output is initially set to port P70 in this mode. Furthermore, interrupt factors for the bus
collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change
respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and
acknowledge detection interrupt.
156
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
The start condition detection interrupt is generated when the fall at the SDA2 pin (P70) is detected
while the SCL2 pin (P71) is in the H state. The stop condition detection interrupt is generated when the
rise at the SDA2 pin (P70) is detected while the SCL2 pin (P71) is in the H state.
The acknowledge non-detection interrupt is generated when the H level at the SDA2 pin is detected at
the 9th rise of the transmission clock.
The acknowledge detection interrupt is generated when the L level at the SDA2 pin is detected at the
9th rise of the transmission clock. Also, DMA transfer can be started when the acknowledge is de-
tected if UART2 transmission is selected as the DMAi request factor.
Bit 2 is the bus busy flag. It is set to “1” when the start condition is detected, and reset to “0” when the
stop condition is detected.
Bit 1 is the arbitration lost detection flag control bit. Arbitration detects a conflict between data trans-
mitted at SCL2 rise and data at the SDA2 pin. This detection flag is allocated to bit 11 in UART2
transmission buffer register (address 033E16). It is set to “1” when a conflict is detected. With the
arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes.
When this bit is set to “1”, update is set to units of byte. If a conflict is then detected, the arbitration lost
detection flag control bit will be set to “1” at the 9th rise of the clock. When updating in units of byte,
always clear (“0” interrupt) the arbitration lost detection flag control bit after the 1st byte has been
acknowledged but before the next byte starts transmitting.
Bit 3 is the SCL2 L synchronization output enable bit. When this bit is set to “1”, the P71 data register
is set to “0” in sync with the L level at the SCL2 pin.
Bit 4 is the bus collision detection sampling clock select bit. The bus collision detection interrupt is
generated when RxDi and TxDi level do not conflict with one another. When this bit is “0”, a conflict is
detected in sync with the rise of the transfer clock. When this bit is “1”, detection is made when timer
Ai (timer A0 with UART2, timer A3 with UART3 and timer A4 with UART4) underflows. Operation is
shown in Figure 1.20.3.
Bit 5 is the transmission enable bit automatic clear select bit. By setting this bit to “1”, the transmission
bit is automatically reset to “0” when the bus collision detection interrupt factor bit is “1” (when a conflict
is detected).
Bit 6 is the transmission start condition select bit. By setting this bit to “1”, TxDi transmission starts in
sync with the falling at the RxDi pin.
157
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
1. Bus collision detect sampling clock select bit (Bit 4 of the UARTi special mode register)
0: Rising edges of the transfer clock
CLKi
TxDi/RxDi
1: Timer A0 underflow
Timer Ai
2. Auto clear function select bit of transmit enable bit (Bit 5 of the UARTi special mode
register)
CLKi
TxDi/RxDi
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UARTi special mode register)
0: In normal state
CLKi
TxDi
Enabling transmission
With "1: falling edge of RxDi" selected
CLKi
TxDi
RxDi
Figure 1.20.3. Some other functions added
158
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
UART2 Special Mode Register 2 (Address 033616)
Bit 0 is the IIC mode select bit 2. Table 1.20.2 gives control changes by bit when the IIC mode select
bit is “1”. Start and stop condition detection timing characteristics are shown in Figure 1.20.4. Always
set bit 7 (start/stop condition control bit) to “1”.
Bit 1 is the clock synchronization bit. When this bit is set to “1”, if the rise edge is detected at pin SCL2
while the internal SCL is H level, the internal SCL is changed to L level, the baud rate generator value
is reloaded and the L sector count starts. Also, while the SCL2 pin is L level, if the internal SCL
changes from L level to H, baud rate generator stops counting. If the SCL2 pin is H level, counting
restarts. Because of this function, the UART2 transmission-reception clock takes the AND condition
for the internal SCL and SCL2 pin signals. This function operates from the clock half period before the
1st rise of the UART2 clock to the 9th rise. To use this function, select the internal clock as the transfer
clock.
Bit 2 is the SCL wait output bit. When this bit is set to “1”, output from the SCL2 pin is fixed to L level
at the clock’s 9th rise. When set to “0”, the L output lock is released.
Bit 3 is the SDA output stop bit. When this bit is set to “1”, an arbitration lost is generated. If the
arbitration lost detection flag is “1”, the SDA2 pin simultaneously becomes high impedance.
Bit 4 is the UART2 initialize bit. While this bit is set to “1”, the following operations are performed when
the start condition is detected.
1. The transmission shift register is initialized and the content of the transmission register is trans-
mitted to the transmission shift register. As such, transmission starts with the 1st bit of the next
input clock. However, the UART2 output value remains the same as when the start condition
was detected, without changing from when the clock is input to when the 1st bit of data is output.
2. The reception shift register is initialized and reception starts with the 1st bit of the next input
clock.
3. The SCL wait output bit is set to “1”. As such, the SCL2 pin becomes L level at the rise of the 9th
bit of the clock.
When UART transmission-reception has been started using this function, the content of the transmis-
sion buffer available flag does not change. Also, to use this function, select an external clock as the
transfer clock.
Bit 5 is SCL wait output bit 2. When this bit is set to “1” and serial I/O has been selected, an L level can
be forcefully output from the SCL2 pin even during UART operation. When this bit is set to “0', the L
output from the SCL2 pin is canceled and the UART2 clock is input and output.
Bit 6 is the SDA output disable bit. When this bit is set to “1”, the SDA2 pin is forcefully made high
impedance. To overwrite this bit, do so at the rise of the UART2 transfer clock. The arbitration lost
detection flag may be set.
159
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Specifications in this manual are tentative and subject to change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
Table 1.20.2. Functions changed by I2C mode select bit 2
IICM2 = 0
IICM2 = 1
Function
Acknowrege not detect (NACK) UART2 transfer (rising edge of )
Interrupt no. 33, 35, 37 factor
Interrupt no. 34, 36, 38 factor
DMA factor
Acknowrege detect (ACK)
Acknowrege detect (ACK)
Acknowrege detect (ACK)
Acknowrege detect (ACK)
Rising edge of the last bit of re- Rising edge of the last bit of re-
ceive clock ceive clock
Data transfer timing from UARTi (i
= 2 to 4) receive shift register to re-
ceive buffer
Rising edge of the last bit of re- Rising edge of the last bit of re-
ceive clock ceive clock
UARTi(i = 2 to 4) receive / ACK in-
terrupt request generation timing
3 to 6 cycles < set up time (Note)
3 to 6 cycles < hold time (Note)
Note : Cycle number shows main clock input oscillation frequency f(XIN) cycle number.
Hold time
Set up time
SCL
SDA
(Start condition)
SDA
(Stop condition)
Figure 1.20.4. Start/stop condition detect timing characteristics
UART2 Special Mode Register 3 (Address 033516)
Bits 5 to 7 are the SDA2 digital delay setting bits. By setting these bits, it is possible to turn the SDA2
delay OFF or set the f(XIN) delay to 2 to 8 cycles.
160
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
(2) Serial Interface Special Function
_____
UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure
1.20.5). The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In
this case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/
_____
masters using the SSi input pins. Figure 1.20.6 shows the structure of UARTi special mode register 3
(addresses 032516 and 02F516 [i = 3 or 4]) which controls this mode.
_____
SSi input pins function between the master and slave are as follows.
IC1
IC2
P1
3
2
P1
P93(SS
3)
P93(SS
3)
P90(CLK
3
)
P90(CLK
3
)
P91(RxD
3)
P91(STxD
3
)
)
P92(TxD
3
)
P92(SRxD
3
M16C/80 (M)
M16C/80 (S)
IC3
P93(SS
3)
P90(CLK
3
)
P91(STxD
3
)
)
M :Master
S :Slave
P92(SRxD
3
M16C/80 (S)
Figure 1.20.5 Serial bus communication control example using the SSi input pins
< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
_____
When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock
input becomes effective and serial communications are enabled. (i = 3 or 4)
< Master Mode (TxDi and RxDi are selected, DINC = 0) >
_____
_____
The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
_____
sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the
trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error
is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans-
mission-reception mode register (address 032816 and 02F816 [i = 3 or 4]) to “0”.
The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection
interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode
register 3 (address 032516 and 02F516 [i = 3 or 4]) to “1”.
When the trouble error flag is set to “0”, output is restored to the clock output and data output pins. In
_____
_____
the master mode, if an SSi input pin is H level, “0” can be written for the trouble error flag. When an SSi
input pin is L level, “0” cannot be written for the trouble error flag. In the slave mode, the “0” can be
_____
written for the trouble error flag regardless of the input to the SSi input pins.
161
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
UARTi special mode register 3 (i=3,4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
032516
02F516
When reset
U3SMR3
U4SMR3
00000000
00000000
2
2
Bit symbol
R W
Bit name
Function
SS port function enable bit
(Note 3)
0: SS function disable
1: SS function enable
SSE
0: Without clock delay
1: With clock delay
Clock phase set bit
CKPH
DINC
0: Select TxDi and RxDi
(master mode) (Note 5)
1: Select STxDi and SRxDi
(slave mode) (Note 6)
Serial input port set bit
0: CLKi is CMOS output
1: CLKi is N-channel open drain
output
NODC
ERR
Clock output select bit
Fault error flag
0: Without fault error
1: With fault error
(Note 4)
b7 b6 b5
SDAi(TxD2) digital
000 :Without delay
DL0
DL1
DL2
delay time set bit
(Note 1,2)
001 :2-cycle of 1/f(XIN
010 :3-cycle of 1/f(XIN
011 :4-cycle of 1/f(XIN
100 :5-cycle of 1/f(XIN
101 :6-cycle of 1/f(XIN
110 :7-cycle of 1/f(XIN
111 :8-cycle of 1/f(XIN
)
)
)
)
)
)
)
Note 1: These bits are used for SDAi(TxDi) output digital delay when using UARTi for IIC interface.
Otherwise, must set to "000".
Note 2: When external clock is selected, delay is increased approx. 100ns.
Note 3: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control
register 0) to "1".
Note 4: Nothing but "0" may be written.
Note 5: Set CLKi and TxDi both for output using the CLKi and TxDi function select register A. Set the
RxDi function select register A for input/output port and the port direction register to "0".
Note 6: Set STxDi for output using the STxDi function select registers A and B. Set the CLKi and
SRxDi function select register A for input/output port and the port direction register to "0".
Figure 1.20.6. UARTi special mode register 3 (i=3,4)
162
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UARTi Special Mode Register
Clock Phase Setting
With bit 1 of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or 4]) and bit 6 of
UARTi transmission-reception control register 0 (addresses 032C16 and 02FC16 [i = 3 or 4]), four
combinations of transfer clock phase and polarity can be selected.
Bit 6 of UARTi transmission-reception control register 0 (addresses 032C16 and 02FC16 [i = 3 or 4])
sets transfer clock polarity, whereas bit 1 of UARTi special mode register 3 (addresses 032516 and
02F516 [i = 3 or 4]) sets transfer clock phase.
Transfer clock phase and polarity must be the same between the master and slave involved in the
transfer.
< Master (Internal Clock) (DINC = 0) >
Figure 1.20.7 shows the transmission and reception timing.
< Slave (External Clock) (DINC = 1) >
• With “0” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the serial transmission start condition is satisfied, though output is indeterminate. After that, serial
transmission is synchronized with the clock. Figure 1.20.8 shows the timing.
• With “1” for bit 1 (CKPH) of UARTi special mode register 3 (addresses 032516 and 02F516 [i = 3 or
4]), when an SSi input pin is H level, output data is high impedance. When an SSi input pin is L level,
the first data is output. After that, serial transmission is synchronized with the clock. Figure 1.20.9
shows the timing.
"H"
Master SS input
"L"
"H"
Clock output
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock output
(CKPOL=1, CKPH=0)
Clock output
(CKPOL=0, CKPH=1)
"H"
"L"
"H"
"L"
Clock output
(CKPOL=1, CKPH=1)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.20.7. The transmission and reception timing in master mode (internal clock)
163
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi Special Mode Register
"H"
SS input
"L"
"H"
Clock input
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock input
(CKPOL=1, CKPH=0)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
High-
inpedance
High-
inpedance
Indeterminate
Figure 1.20.8. The transmission and reception timing (CKPH=0) in slave mode (external clock)
"H"
SS input
"L"
"H"
Clock input
"L"
(CKPOL=0, CKPH=0)
"H"
"L"
Clock input
(CKPOL=1, CKPH=0)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
High-
inpedance
High-
inpedance
Figure 1.20.9. The transmission and reception timing (CKPH=1) in slave mode (external clock)
164
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Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
der
n
U
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 039716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 039716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.21.1 shows the performance of the A-D converter. Figure 1.21.1 shows the block diagram of the
A-D converter, and Figures 1.21.2 and 1.21.3 show the A-D converter-related registers.
Table 1.21.1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock fAD (Note 2)
VCC = 5V
VCC = 3V
fAD, fAD/2, fAD/4
fAD/2, fAD/4
fAD=f(XIN)
fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
VCC = 5V
Absolute precision
• 8-bit resolution
±2LSB
• 10-bit resolution
±3LSB
However, when using AN0 to AN7 in the mode which external operation amp
is connected : ±7LSB
VCC = 3V
• Without sample and hold function (8-bit resolution)
±2LSB
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles
• With sample and hold function
8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Without sample and hold function, set the fAD frequency to 250kHz min.
With the sample and hold function, set the fAD frequency to 1MHz min.
165
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
CKS1=0
CKS0=1
CKS0=0
φ
AD
f
AD
1/2
1/2
A-D conversion rate
selection
V
REF
VCUT=0
Resistance ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 039716
)
)
A-D control register 0 (address 039616
Addresses
(038116, 038016
(038316, 038216
(038516, 038416
)
)
)
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
V
ref
(038716, 038616
(038916, 038816
(038B16, 038A16
(038D16, 038C16
(038F16, 038E16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
V
IN
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
CH2,CH1,CH0=000
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=1,1
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1,OPA0=0,1
Figure 1.21.1. Block diagram of A-D converter
166
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A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
00000XXX2
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
Analog input pin select bit
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
CH1
CH2
MD0
MD1
(Note 2)
(Note 2)
b4 b3
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
mode 0 are selected
b1 b0
A-D sweep pin
select bit
SCAN0
SCAN1
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN
1
(2 pins)
to AN
to AN
2
3
(3 pins)
(4 pins)
0 : Any mode other than repeat sweep mode 1
1 : Repeat sweep mode 1
A-D operation mode
select bit 1
MD2
BITS
CKS1
8/10-bit mode select 0 : 8-bit mode
bit 1 : 10-bit mode
Frequency select bit 0 : fAD/2 or fAD/4 is selected
1 (Note 2)
1 : fAD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used(Note 3)
0 1 : ANEX0 input is A-D converted(Note 4)
1 0 : ANEX1 input is A-D converted(Note 5)
1 1 : External op-amp connection mode(Note 6)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 4: Set "1" to PSL3_5 of the function select register B3.
Note 5: Set "1" to PSL3_6 of the function select register B3.
Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.2. A-D converter-related registers (1)
167
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
Symbol
ADCON2
Address
039416
When reset
XXXXXXX0
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
Must always set to “0”
Reserved bit
Nothing is assigned.
When write, set "0". When read, their content is "0".
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi(i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
038016 to 038F16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
When write, set "0". When read, their content is "0".
Figure 1.21.3. A-D converter-related registers (2)
168
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.21.2 shows the specifications of one-shot mode. Figure 1.21.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.21.2. One-shot mode specifications
Item
Specification
Function
Start condition
Stop condition
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
2
00000XXX
0
0
Bit symbol
Bit name
Function
R W
b2 b1 b0
Analog input pin select
bit
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
(Note 2)
(Note 2)
MD0
MD1
b4 b3
0 0 : One-shot mode
A-D operation mode
select bit 0
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
1: fAD/2 is selected
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
select bit
Function
R W
Invalid in one-shot mode
SCAN0
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
MD2
BITS
CKS1
8/10-bit mode select
bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
(Note 2)
Vref connect bit
1 : Vref connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used(Note 3)
0 1 : ANEX0 input is A-D converted(Note 4)
1 0 : ANEX1 input is A-D converted(Note 5)
1 1 : External op-amp connection mode(Note 6)
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 4: Set "1" to PSL3_5 of the function select register B3.
Note 5: Set "1" to PSL3_6 of the function select register B3.
Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.4. A-D conversion register in one-shot mode
169
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.21.3 shows the specifications of repeat mode. Figure 1.21.5 shows the A-D control register in
repeat mode.
Table 1.21.3. Repeat mode specifications
Item
Specification
The pin selected by the analog input pin select bit is used for repeated A-D
conversion
Function
Star condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
00000XXX2
0
1
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
R W
b2 b1 b0
Analog input pin
select bit
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
CH1
CH2
(Note 2)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 1 : Repeat mode
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
select bit
Function
R W
Invalid in repeat mode
SCAN0
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
(Note 2)
CKS1
VCUT
OPA0
Vref connect bit
1 : Vref connected
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used(Note 3)
0 1 : ANEX0 input is A-D converted(Note 4)
1 0 : ANEX1 input is A-D converted(Note 5)
1 1 : External op-amp connection mode(Note 6)
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 3: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 4: Set "1" to PSL3_5 of the function select register B3.
Note 5: Set "1" to PSL3_6 of the function select register B3.
Note 6: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.5. A-D conversion register in repeat mode
170
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.21.4 shows the specifications of single sweep mode. Figure 1.21.6 shows the A-D
control register in single sweep mode.
Table 1.21.4. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one
A-D conversion
Start condition
Stop condition
Writing “1” to A-D converter start flag
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7
(8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
00000XXX
0
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in single sweep mode
CH0
CH1
CH2
MD0
MD1
b4 b3
1 0 : Single sweep mode
A-D operation mode
select bit 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
1
0
Bit symbol
Bit name Function
A-D sweep pin select bit When single sweep and repeat sweep mode 0
are selected
R W
SCAN0
SCAN1
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
(Note 3)
CKS1
VCUT
OPA0
Vref connect bit
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used(Note 4)
0 1 : ANEX0 input is A-D converted(Note 5)
1 0 : ANEX1 input is A-D converted(Note 6)
1 1 : External op-amp connection mode(Note 7)
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 5: Set "1" to PSL3_5 of the function select register B3.
Note 6: Set "1" to PSL3_6 of the function select register B3.
Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.6. A-D conversion register in single sweep mode
171
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.21.5 shows the specifications of repeat sweep mode 0. Figure 1.21.7 shows the
A-D control register in repeat sweep mode 0.
Table 1.21.5. Repeat sweep mode 0 specifications
Item
Specification
The pins selected by the A-D sweep pin select bit are used for repeat sweep
A-D conversion
Function
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7
(8 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
MD0
MD1
b4 b3
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
1
0
Bit symbol
SCAN0
Bit name Function
A-D sweep pin select bit When single sweep and repeat sweep mode 0
are selected
R W
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
SCAN1
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
(Note 3)
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
OPA0
Vref connect bit
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used(Note 4)
0 1 : ANEX0 input is A-D converted(Note 5)
1 0 : ANEX1 input is A-D converted(Note 6)
1 1 : External op-amp connection mode(Note 7)
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 5: Set "1" to PSL3_5 of the function select register B3.
Note 6: Set "1" to PSL3_6 of the function select register B3.
Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.7. A-D conversion register in repeat sweep mode 0
172
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.21.6 shows the specifications of repeat sweep mode 1. Figure
1.21.8 shows the A-D control register in repeat sweep mode 1.
Table 1.21.6. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 to AN7
With emphasis on the pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
039616
When reset
00000XXX
1
1
2
Bit symbol
Bit name
Function
R W
Analog input pin
select bit
Invalid in repeat sweep mode 1
CH0
CH1
CH2
MD0
MD1
b4 b3
1 1 : Repeat sweep mode 1
A-D operation mode
select bit 0
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
039716
When reset
0016
1
1
Bit symbol
SCAN0
Bit name
Function
R W
A-D sweep pin select bit When repeat sweep mode 1 is selected
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
to AN
to AN
1
SCAN1
2
3
(3 pins)
(4 pins)
A-D operation mode
select bit 1
1 : Repeat sweep mode 1
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Frequency select bit 1
(Note 3)
VCUT
OPA0
Vref connect bit
1 : Vref connected
b7 b6
External op-amp
connection mode
bit (Note 2)
0 0 : ANEX0 and ANEX1 are not used(Note 4)
0 1 : ANEX0 input is A-D converted(Note 5)
1 0 : ANEX1 input is A-D converted(Note 6)
1 1 : External op-amp connection mode(Note 7)
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit.
Note 3: When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing.
Note 4: Set "0" to PSL3_5 and PSL3_6 of the function select register B3.
Note 5: Set "1" to PSL3_5 of the function select register B3.
Note 6: Set "1" to PSL3_6 of the function select register B3.
Note 7: Set "1" to PSL3_5 and PSL3_6 of the function select register B3.
Figure 1.21.8. A-D conversion register in repeat sweep mode 1
173
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Ad-eDveloCpmoenntverter
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 039416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is
achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 039716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 039716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
Set the related input peripheral function of the function select register B3 to disabled.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 039716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.21.9 is an example of how to
connect the pins in external operation amp mode.
Set the related input peripheral function of the function select register B3 to disabled.
Resistance ladder
Successive conversion register
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
Analog
input
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.21.9. Example of external op-amp connection mode
174
t
n
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
e
Mitsubishi Microcomputers
e
d
m
n
p
o
U
l
e
M16C/80 group
v
e
d
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Set the
function select register A to I/O port, the related input peripheral function of the function select register B3 to
disabled and the direction register to input mode. When the D-A output is enabled, the pull-up function of
the corresponding port is automatically disabled.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.22.1 lists the performance of the D-A converter. Figure 1.22.1 shows the block diagram of the D-A
converter. Figure 1.22.2 shows the D-A control register.
Table 1.22.1. Performance of D-A converter
Item
Conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 channels
Data bus low-order bits
(Address 039816, 039A16
)
D-A register i (8) (i = 0, 1)
R-2R resistance ladder
D-Ai output enable bit (i = 0, 1)
P9 / DA
P9 / DA
3
0
4
1
Figure 1.22.1. Block diagram of D-A converter
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D-A Converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
039C16
When reset
0016
Bit symbol
DA0E
Bit name
Function
R W
0 : Output disabled
1 : Output enabled
D-A0 output enable bit
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
When write, set "0". When read, the value of these bits is "0".
D-A register i
b7
Symbol
DAi (i = 0,1)
Address
039816 039A16
When reset
Indeterminate
b0
,
Function
R W
Output value of D-A conversion
Figure 1.22.2. D-A control register
D-A0 output enable bit
"0"
R
R
R
R
R
R
R
2R
DA0
"1"
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
D-A register 0
"1"
"0"
AVSS
VREF
Note 1: In the above figure, the D-A register value is "2A16".
Note 2: This circuit is the same in D-A1.
Note 3: To save power when not using the D-A converter, set the D-A output enable bit to "0"
and the D-A register to "0016", and prevent current flowing to the R-2R resistance.
Figure 1.22.3. D-A converter equivalent circuit
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CRC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-
16
12
5
puter uses a generator polynomial of CRC_CCITT (X + X + X + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-
pleted in two machine cycles.
Figure 1.23.1 shows the block diagram of the CRC circuit. Figure 1.23.2 shows the CRC-related registers.
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 037D16, 037C16
)
CRC code generating circuit
x
16 + x12 + x5 + 1
CRC input register (8) (Address 037E16
)
Figure 1.23.1. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
037D16, 037C16
When reset
Indeterminate
b0
Values that
can be set
Function
R W
CRC calculation result output register
000016 to FFFF16
CRC input register
b7
b0
Symbo
CRCIN
Address
037E16
When reset
Indeterminate
Values that
can be set
Function
R W
Data input register
0016 to FF16
Figure 1.23.2. CRC-related registers
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CRC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
b15
b0
b0
CRC data register CRCD
[037D16, 037C16
(1) Setting 000016
]
b7
CRC input register
2 cycles
CRCIN
[037E16
(2) Setting 0116
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[037D16, 037C16
118916
]
The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
16
12
5
16
(X + X + X + 1), becomes the remainder resulting from dividing (1000 0000) X by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
MSB
9
8
1
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
CRCIN
[037E16
(3) Setting 2316
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[037D16, 037C16
0A4116
]
Figure 1.23.3. CRC example
178
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
X-Y Converter
X-Y Converter
X-Y conversion rotates the 16 x 16 matrix data by 90 degrees. It can also be used to invert the top and
bottom of the 16-bit data. Figure 1.24.1 shows the XY control register.
The Xi and the Yi registers are 16-bit registers. There are 16 of each (where i= 0 to 15).
The Xi and Yi registers are mapped to the same address. The Xi register is a write-only register, while the
Yi register is a read-only register. Be sure to access the Xi and Yi registers in 16-bit units from an even
address. Operation cannot be guaranteed if you attempt to access these registers in 8-bit units.
XY control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
XYC
Address
02E016
When reset
XXXXXX00
2
Bit symbol
XYC0
Bit name
Function
R W
0 : Data conversion
1 : No data conversion
Read-mode set bit
Write-mode set bit
0 : No bit mapping conversion
1 : Bit mapping conversion
XYC1
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
Figure 1.24.1. XY control register
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Xd-eYveloCpmoenntverter
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The reading of the Yi register is controlled by the read-mode set bit (bit 0 at address 02E016).
When the read-mode set bit (bit 0 at address 02E016) is “0”, specific bits in the Xi register can be read at the
same time as the Yi register is read.
For example, when you read the Y0 register, bit 0 is read as bit 0 of the X0 register, bit 1 is read as bit 0 of
the X1 register, ..., bit 14 is read as bit 0 of the X14 register, bit 15 as bit 0 of the X15 register. Similarly,
when you read the Y15 register, bit 0 is bit 15 of the X0 register, bit 1 is bit 15 of the X1 register, ..., bit 14 is
bit 15 of the X14 register, bit 15 is bit 15 of the X15 register.
Figure 1.24.2 shows the conversion table when the read mode set bit = “0”. Figure 1.24.3 shows the X-Y
conversion example.
Read address
X15 register (0002DE16
X14 register (0002DC16
X13 register (0002DA16
)
)
)
X12 register (0002D816
X11 register (0002D616
X10 register (0002D416
)
)
)
X9 register (0002D216
X8 register (0002D016
)
)
Write address
X7 register (0002CE16
X6 register (0002CC16
)
)
X5 register (0002CA16
X4 register (0002C816
X3 register (0002C616
X2 register (0002C4
X1 register (0002C21166
X0 register (0002C016
)
)
)
)
)
)
b15
b0
Bit of Xi register
Figure 1.24.2. Conversion table when the read mode set bit = “0”
(X register)
(Y register)
X0-Reg
X1
Y0-Reg
Y1
X2
Y2
X3
Y3
X4
Y4
X5
Y5
X6
Y6
X7
Y7
X8
Y8
X9
Y9
X10
X11
X12
X13
X14
X15
Y10
Y11
Y12
Y13
Y14
Y15
Figure 1.24.3. X-Y conversion example
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X-Y Converter
When the read-mode set bit (bit 0 at address 02E016) is “1”, you can read the value written to the Xi register
by reading the Yi register. Figure 1.24.4 shows the conversion table when the read mode set bit = “1”.
X15,Y15 register (0002DE
X14,Y14 register (0002DC1166
)
)
X13,Y13 register (0002DA16
)
X12,Y12 register (0002D816
X11,Y11 register (0002D616
X10,Y10 register (0002D416
)
)
)
X9,Y9 register (0002D216
X8,Y8 register (0002D016
)
)
Write address
Read address
X7,Y7 register (0002CE16
)
X6,Y6 register (0002CC16
X5,Y5 register (0002CA16
)
)
X4,Y4 register (0002C816
X3,Y3 register (0002C616
X2,Y2 register (0002C416
X1,Y1 register (0002C216
X0,Y0 register (0002C016
)
)
)
)
)
b15
b0
Bit of Xi register
Bit of Yi register
Figure 1.24.4. Conversion table when the read mode set bit = “1”
The value written to the Xi register is controlled by the write mode set bit (bit 1 at address 02E016).
When the write mode set bit (bit 1 at address 02E016) is “0” and data is written to the Xi register, the bit
stream is written directly.
When the write mode set bit (bit 1 at address 02E016) is “1” and data is written to the Xi register, the bit
sequence is reversed so that the high becomes low and vice versa. Figure 1.24.5 shows the conversion
table when the write mode set bit = “1”.
b15
b15
b0
b0
Write address
Bit of Xi register
Figure 1.24.5. Conversion table when the write mode set bit = “1”
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DRAM Controller
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DRAM Controller
There is a built in DRAM controller to which it is possible to connect between 512 Kbytes and 8 Mbytes of
DRAM. Table 1.25.1 shows the functions of the DRAM controller.
Table 1.25.1. DRAM Controller Functions
DRAM space
Bus control
Refresh
512KB, 1MB, 2MB, 4MB, 8MB
2CAS/1W
________
________
CAS before RAS refresh
Self refresh-compatible
Function modes
Waits
EDO-compatible, fast page mode-compatible
1 wait or 2 waits, programmable
To use the DRAM controller, use the DRAM space select bit of the DRAM control register (address 004016)
to specify the DRAM size. Figure 1.25.1 shows the DRAM control register.
The DRAM controller cannot be used in external memory mode 3 (bits 1 and 2 at address 000516 are “112”).
Always use the DRAM controller in external memory modes 0, 1, or 2.
When the data bus width is 16-bit in DRAM area, set "1" to R/W mode select bit (bit 2 at address 000416).
Set wait time between after DRAM power ON and before memory processing, and processing necessary
for dummy cycle to refresh DRAM by software.
DRAM control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRAMCONT
Address
0004016
When reset
Indeterminate (Note 4)
Function
Bit symbol
WT
Bit name
R W
0 : Two wait
1 : One wait
Wait select bit (Note 1)
DRAM space select bit
b3 b2 b1
AR0
AR1
AR2
0 0 0 : DRAM ignored
0 0 1 : Inhibit
0 1 0 : 0.5MB
0 1 1 : 1MB
1 0 0 : 2MB
1 0 1 : 4MB
1 1 0 : 8MB
1 1 1 : Inhibit
Nothing is assigned.
When write, set "0". When read, the value of these bits is indeterminate.
Self-refresh mode bit
(Note 2)
0: Self-refresh OFF
1: Self-refresh ON
SREF
Note 1: The number of cycles with 2 waits is 3-2-2. With 1 wait, it is 2-1-1.
Note 2: When you set "1", both RAS and CAS change to "L". When you set "0",
RAS and CAS change to "H" and then normal operation (read/write, refresh)
is resumed. In Stop mode, there is no control.
Note 3: Set the bus width using the external data bus width control register (address
000B16). When selecting 8-bit bus width, CASH is indeterminate.
Note 4: After reset, the content of this register is indeterminate.
DRAM controller starts the operation after writing to this register.
Figure 1.25.1. DRAM control register
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DRAM Controller
• DRAM Controller Multiplex Address Output
The DRAM controller outputs the row addresses and column addresses as a multiplexed signal to the
address bus A8 to A20. Figure 1.25.2 shows the output format for multiplexed addresses.
8-bit bus mode
MA11 MA10
MA7 MA6
(A15) (A14) (A13) (A12) (A11) (A10)
MA5
MA2
MA1
(A9)
MA0
(A8)
MA12
(A20)
MA9 MA8
(A17) (A16)
MA4 MA3
Pin function
(A19)
(A18)
(A20) (A19)
A18
A17
A8
A16
A7
A15
A6
A14
A5
A13
A4
A12
A3
A11
A2
A10
A1
A9
A0
–
–
Row address
(A22) (A22) A19
Column address
512KB, 1MB
(A20)
(A22)
A19
A21
A18
A20
A16
A7
A15
A14
A13
A12
A3
A11
A2
A10
A1
A9
A0
–
–
A17
A8
Row address
A6
A5
A4
Column address
2MB, 4MB
A20
A19
A22
A18
A21
A17
A8
A16
A7
A15
A14
A5
A13
A4
A12
A3
A11
A2
A10
A1
A9
A0
–
–
Row address
A6
8MB
(A22)
Column address
16-bit bus mode
MA12 MA11 MA10 MA9
(A20) (A19) (A18) (A17) (A16)
MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1
MA0
(A8)
Pin function
(A15)
(A14) (A13) (A12) (A11) (A10) (A9)
A18
A9
A17
A8
A16
A7
A15
A14
A13
A4
A12
A3
A11
A2
A10
A1
(A9)
(A0)
–
–
(A20) (A19)
(A22) (A20)
Row address
A6
A5
Column address
512KB
A19
A20
A18
A9
A17
A8
A16
A7
A15
A14
A13
A4
A12
A3
A11
A2
A10
A1
(A9)
(A0)
–
–
(A20)
(A22)
Row address
A6
A5
Column address
1MB, 2MB
A20
A22
A19
A21
A18
A9
A15
A14
A13
A4
A12
A3
A11
A2
A10
A1
(A9)
(A0)
–
–
A17
A8
A16
A7
Row address
A6
A5
Column address
(Note 2)
4MB, 8MB
Note 1: ( ) invalid bit:
space).
bits that change according to selected mode (8-bit/16-bit bus mode, DRAM
Note 2: The figure is for 4Mx1 or 4Mx4 memory configuration. If you are using a 4Mx16 configuration,
use combinations of the following: For row addresses, MA0 to MA12; for column addresses
MA2 to MA8, MA11, and MA12. Or for row addresses MA1 to MA12; for column addresses
MA2 to MA9, MA11, MA12.
Note 3: "–" is indeterminate.
Figure 1.25.2. Output format for multiplexed addresses
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DRAM Controller
• Refresh
_______
_______
The refresh method is CAS before RAS. The refresh interval is set by the DRAM refresh interval set
register (address 004116). The refresh signal is not output in HOLD state. Figure 1.25.3 shows the
DRAM refresh interval set register.
Use the following formula to determine the value to set in the refresh interval set register.
Refresh interval set register value (0 to 255) = refresh interval time / (BCLK frequency X 32) - 1
DRAM refresh interval set register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
REFCNT
Address
0004116
When reset
Indeterminate
R W
Bit symbol
REFCNT0
Bit name
Refresh interval set bit
Function
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 : 1.6 µs
REFCNT1
REFCNT2
REFCNT3
REFCNT4
REFCNT5
REFCNT6
REFCNT7
0 0 0 0 0 0 0 1 : 3.2 µs
0 0 0 0 0 0 1 0 : 4.8 µs
•
•
•
1 1 1 1 1 1 1 1 : 409.6 µs
(Note)
Note: Refresh interval at 20 MHz operating (no division)
Refresh interval = BCLK frequency X (refresh interval set bit + 1) X 32
Figure 1.25.3. DRAM refresh interval set register
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DRAM Controller
The DRAM self-refresh operates in STOP mode, etc.
When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT
;DRAM ignored, one wait is selected
;Set self-refresh, select 4MB and one wait
;Two nops are needed
mov.b #10001011b,DRAMCONT
nop
nop
•••
;
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT
;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT
;Select 4MB and one wait
nop
nop
•••
;Inhibit instruction to access DRAM area
Figures 1.25.4 to 1.25.6 show the bus timing during DRAM access.
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DRAM Controller
< Read cycle (wait control bit = 0) >
BCLK
Column
address 2
Row
address
Column
address 1
Column
address 3
MA0 to MA12
RAS
CASH
CASL
'H'
DW
D
0
to D15
(EDO mode)
Note : Only CASL is operating in 8-bit data bus width.
< Write cycle (wait control bit = 0) >
BCLK
Column
address 1
Column
address 2
Column
address 3
Row
address
MA0 to MA12
RAS
CASH
CASL
DW
D0 to D15
Note : Only CASL is operating in 8-bit data bus width.
Figure 1.25.4. The bus timing during DRAM access (1)
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DRAM Controller
< Read cycle (wait control bit = 1) >
BCLK
Column
address 1
Row
address
Column
address 2
Column
address 3
Column
address 4
MA0 to MA12
RAS
CASH
CASL
'H'
DW
D
0
to D15
(EDO mode)
Note : Only CASL is operating in 8-bit data bus width.
< Write cycle (wait control bit = 1) >
BCLK
Column
Column
Column
Column
address 4
Row
address
MA0 to MA12
RAS
address 1 address 2 address 3
CASH
CASL
DW
D0 to D15
Note : Only CASL is operating in 8-bit data bus width.
Figure 1.25.5. The bus timing during DRAM access (2)
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DRAM Controller
BCLK
RAS
CASH
CASL
"H"
DW
< CAS before RAS refresh cycle >
Note : Only CASL is operating in 8-bit data bus width.
BCLK
RAS
CASH
CASL
"H"
DW
< Self refresh cycle >
Note : Only CASL is operating in 8-bit data bus width.
Figure 1.25.6. The bus timing during DRAM access (3)
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Pdreoveglorpammentmable I/O Port
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 87 programmable I/O ports for 100-pin version: P0 to P10 (excluding P85). There are 123 pro-
grammable I/O ports for 144-pin version: P0 to P15 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.26.1 to 1.26.3 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), set the corresponding function select registers A, B and C. When pins are to be used as the outputs
for the D-A converter, set the function select register of each pin to I/O port, and set the direction registers
to input mode.
Table 1.26.1 lists each port and peripheral function.
See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figures 1.26.4 and 1.26.5 show the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of
_____ _____
_____
_______
_______
_______ _____ _________
_______ _______
_______
pins A0 to A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW,
_________
_________
_______
_______
BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note: There is no direction register bit for P85.
(2) Port registers
Figures 1.26.6 and 1.26.7 show the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to
______
_______
_______
_______ _____ _________
_______ _______ _______
_____ _____
A22, A23, D0 to D15, MA0 to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/
_________
_________
_______
_______
CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
(3) Function select register A
Figures 1.26.8 and 1.26.9 show the function select registers A.
The register is used to select port output and peripheral function output when the port functions for both
port output and peripheral function output.
Each bit of this register corresponds to each pin that functions for both port output and peripheral function
output.
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(4) Function select register B
Figures 1.26.10 and 1.26.11 show the function select registers B.
This register selects the 1st peripheral function output and second peripheral function output when mul-
tiple peripheral function outputs are assigned to a pin. For pins with a third peripheral function, this regis-
ter selects whether to enable the function select register C, or output the second peripheral function.
Each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it.
This register is enabled when the bits of the corresponding function select register A are set for peripheral
functions.
The bit 3 to bit 6 of function select register B3 is ignored bit for input peripheral function. When using DA0/
DA1 and ANEX0/ANEX1, set related bit to "1". When not using DA0/DA1 or ANEX0/ANEX1, set related
bit to "0".
(5) Function select register C
Figure 1.26.12 shows the function select register C.
This register is used to select the first peripheral function output and the third peripheral function output
when three peripheral function outputs are assigned to a pin.
This register is effective when the bits of the function select register A of the counterpart pin have selected
a peripheral function and when the function select register B has made effective the function select
register C.
The bit 7 (PSC_7) is assigned the key-in interrupt inhibit bit. Setting 1 in the key-in interrupt inhibit bit
causes no key-in interrupts regardless of the settings in the interrupt control register even if L is entered
in pins KI0 to KI3. With 1 set in the key-in interrupt inhibit bit, input from a port pin cannot be effected even
if the port direction register is set to input mode.
(6) Pull-up control registers
Figures 1.26.13 and 1.26.14 show the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
Since P0 to P5 operate as the bus in memory expansion mode and microprocessor mode, do not set the
pull-up control register. However, it is possible to select pull-up resistance presence to the usable port as
I/O port by setting.
(7) Port control register
Figure 1.26.15 shows the port control register.
This register is used to choose whether to make port P1 a CMOS port or an Nch open drain. In the Nch
open drain, the port P1 has no function that a complete open drain but keeps the CMOS port’s Pch
always turned off. Thus the absolute maximum rating of the input voltage falls within the range from - 0.3
V to Vcc + 0.3 V.
The port control register functions similarly to the above also in the case in which port P1 can be used as
a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in
memory expansion mode.
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Figure 1.26.1. Programmable I/O ports (1)
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Pull-up selection
Direction register
P82
to P8
4
Data bus
Port latch
Input to respective peripheral functions
Note
P6
0
5
, P6
, P8
1
1
, P6
, P9
4
0
, P6
, P9
5
1
, P7
, P9
2
2
, P7
, P9
3
7
Pull-up selection
Function select
register A
P7
(inside dotted-line included)
P5 , P6 , P6 , P7 , P7 , P8
(inside dotted-line not included)
Direction register
Port latch
3
3
7
4
6
0, P86
Output from respective
peripheral functions
Data bus
Input to respective peripheral functions
Note : P5
3
is connected to clock output function select bit.
P85
Data bus
NMI interrupt input
Function select
register A
P70, P71
Direction register
Output from respective
peripheral functions
Data bus
Port latch
Input to respective peripheral functions
Figure 1.26.2. Programmable I/O ports (2)
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Pull-up selection
Direction register
P100 to P103
Data bus
Port latch
Analog input
Pull-up selection
Direction register
P104 to P107
Data bus
Port latch
Input to respective peripheral functions
Analog input
Pull-up selection
Function select
register A
P9
3, P9
4
Direction register
Output from respective
peripheral functions
Data bus
Port latch
Input to respective peripheral functions
Analog input
D-A output enabled
P95
P96
(inside dotted-line included)
(inside dotted-line not included)
Pull-up selection
Function select
register A
Direction register
Output from respective
peripheral functions
Data bus
Port latch
Analog input
Input to respective peripheral functions
Figure 1.26.3. Programmable I/O ports (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Note 1,2, 3)
Symbol
PDi (i = 0 to 15,
Address
When reset
03E216, 03E316, 03E616, 03E716, 0016
b7 b6 b5 b4 b3 b2 b1 b0
except 8, 11 and 14)
03EA16, 03EB16, 03C216, 03C316,
03C716, 03CA16, 03CE16, 03CF16
03D316
,
Bit symbol
PDi_0
Bit name
0 direction register
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
1
direction register
direction register
direction register
direction register
direction register
direction register
2
(Functions as an output port)
3
(i = 0 to 15 except 8, 11 and 14)
4
Port Pi
Port Pi
Port Pi
5
6
7
PDi_7
direction register
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port
P9 direction register.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port direction register of pins A0 to A22, A23, D0 to D15, MA0 to
MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/ALE/
CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 3: Port P12, P13 and P15 direction registers exist in 144-pin version.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03C616
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
PD8_1
1
PD8_2
2
(Functions as an output port)
PD8_3
Port P8
Port P8
3
4
PD8_4
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
7
direction register
direction register
(Functions as an output port)
Figure 1.26.4. Direction register (1)
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Port P11 direction register (Note)
Symbol
PD11
Address
03CB16
When reset
XXX000002
b7 b6 b5 b4 b3 b2 b1 b0
,
Bit symbol
PD11_0
PD11_1
PD11_2
PD11_3
PD11_4
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P11
0
direction register
direction register
direction register
direction register
direction register
Port P11
Port P11
Port P11
Port P11
1
2
3
4
(Functions as an output port)
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note: This register exists in 144-pin version.
Port P14 direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD14
Address
03D216
When reset
X0000000
2
Bit symbol
PD14_0
PD14_1
PD14_2
PD14_3
PD14_4
PD14_5
PD14_6
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P14
0
direction register
direction register
direction register
direction register
direction register
direction register
direction register
Port P14
Port P14
Port P14
Port P14
1
2
3
4
(Functions as an output port)
Port P14
Port P14
5
6
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note: This register exists in 144-pin version.
Figure 1.26.5. Direction register (2)
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Port Pi register (Note 1, 3)
Symbol
Pi (i = 0 to 15,
Address
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03C016, 03C116
When reset
Indeterminate
,
,
b7 b6 b5 b4 b3 b2 b1 b0
except 8, 11 and 14)
03C516, 03C816, 03CC16, 03CD16
,
03D116
Bit symbol
PDi_0
Bit name
Function
R W
Port Pi
0
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
PDi_1
Port Pi
Port Pi
1
2
PDi_2
1 : “H” level data (Note 2)
PDi_3
PDi_4
PDi_5
PDi_6
Port Pi
Port Pi
Port Pi
Port Pi
3
4
5
6
register
register
register
register
(i = 0 to 15 except 8, 11 and 14)
PDi_7
Port Pi
7
register
Note 1: In memory expansion and microprocessor mode, the contents of
corresponding port Pi direction register of pins A to A22, A23, D0 to D15, MA0
0
to MA12, CS0 to CS 3, WRL/WR/CASL, WRH/BHE/CASH, RD/DW, BCLK/
ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and RDY are not changed.
Note 2: P7
0 and P71 are N-channel open drain ports and high inpedance outputs.
Note 3: Port P12, P13 and P15 registers exist in 144-pin version.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03C416
When reset
Indeterminate
Bit symbol
PD8_0
Bit name
Function
R W
Port P80 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
PD8_1
PD8_2
PD8_3
Port P81 register
Port P82 register
Port P83 register
PD8_4
PD8_5
Port P84 register
Port P85 register
PD8_6
PD8_7
Port P86 register
Port P87 register
Figure 1.26.6. Port register (1)
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Port P11 register (Note)
Symbol
P11
Address
03C916
When reset
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name
Function
R W
P11_0
P11_1
P11_2
P11_3
P11_4
Port P11
0
register
register
register
register
register
Data is input and output to and
from each pin by reading and
writing to and from each
corresponding bit
0 : “L” level data
1 : “H” level data
Port P11
Port P11
Port P11
Port P11
1
2
3
4
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note: This register exists in 144-pin version.
Port P14 register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P14
Address
03D016
When reset
Indeterminate
Bit symbol
Bit name
Function
R W
P14_0
P14_1
P14_2
Port P14
Port P14
Port P14
0
register
register
register
Data is input and output to and
from each pin by reading and
writing to and from each
corresponding bit
0 : “L” level data
1 : “H” level data
1
2
3
4
P14_3
P14_4
P14_5
P14_6
Port P14
Port P14
register
register
register
register
Port P14
Port P14
5
6
Nothing is assigned.
When set, write "0". When read, its content is indeterminate.
Note: This register exists in 144-pin version.
Figure 1.26.7. Port register (2)
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Table 1.26.1. Each port and peripheral output function (Note 1)
Port
P6
Periphral output function 1
Periphraloutput function 2
Periphral output function 3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
RTS
CLK
0
output
output
P6
P6
P6
P6
P6
P6
P6
P7
P7
P7
P7
P7
P7
P7
0
T
X
D
0
output
output
output
RTS
CLK
1
CLKS1 output
1
TX
D
1
output
(Note 2)
(Note 2)
T
X
D2(SDA2) output
TA0OUT output
SCL
2
2
output
output
output
CLK
TA1OUT output
V phase output
W phase output
V phase output
RTS
2
TA2OUT output
W phase output
TA3OUT output
P7
7
0
P8
TA4OUT output
U phase output
U phase output
P8
P8
P8
P8
P8
P8
P8
P9
P9
P9
P9
P9
P9
P9
P9
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
CLK
3
3
output
output
SCL
STXD3 output
T
T
X
X
D3(SDA3) output
RTS
RTS
3
4
output
output
output
CLK
4
D4(SDA4) output
SCL output
3
STXD4 output
Note 1: When using peripheral input function, set the corresponding function select register A to "0" (I/O port).
Note 2: N-channel open drain output.
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Function select register A0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PS0
Address
03B016
When reset
0X000X00
2
Bit name
Function
R W
Bit symbol
PS0_0
Port P6
0
1
function select bit
0 : I/O port
1 : RTS output
0 : I/O port
1 : CLK output
0
PS0_1
Port P6
function select bit
0
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
0 : I/O port
1 : TXD output
function select bit 0 : I/O port
1 : Peripheral function output
(PSL0_4 enabled)
PS0_3
PS0_4
Port P6
3
function select bit
0
Port P6
4
PS0_5
Port P6
5
function select bit
0 : I/O port
1 : CLK output
1
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
0 : I/O port
1 : TXD output
PS0_7
Port P6
7
function select bit
1
Function select register A1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PS1
Address
03B116
When reset
X0000000
2
R W
Bit name
Function
Bit symbol
PS1_0
Port P7
(Note)
0
function select bit 0 : I/O port
1 : Peripheral function output
(PSL1_0 enabled)
0 : I/O port
PS1_1
PS1_2
Port P7
(Note)
1
2
function select bit
1 : SCL
function select bit 0 : I/O port
1 : Peripheral function output
(PSL1_2, PSC_0 enabled)
function select bit 0 : I/O port
2 output
Port P7
PS1_3
PS1_4
Port P7
3
4
1 : Peripheral function output
(PSL1_3 enabled)
Port P7
function select bit 0 : I/O port
1 : Peripheral function output
(PSL1_4 enabled)
PS1_5
PS1_6
Port P7
5
6
function select bit
function select bit
0 : I/O port
1 : W phase output
Port P7
0 : I/O port
1 : TA3OUT output
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Note: This port is N-channel open drain output.
Figure 1.26.8. Function select register A (1)
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Function select register A2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PS2
Address
03B416
When reset
XXXXXX00
2
Bit name
function select bit 0 : I/O port
Function
R W
Bit symbol
PS2_0
Port P8
0
1 : Peripheral function output
(PSL2_0 enabled)
0 : I/O port
PS2_1
Port P8
1
function select bit
1 : U phase output
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Function select register A3 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PS3
Address
03B516
When reset
0016
R W
Bit name
function select bit
Function
Bit symbol
PS3_0
Port P9
0
0 : I/O port
1 : CLK3 output
PS3_1
Port P9
1
function select bit 0 : I/O port
1 : Peripheral function output
(PSL3_1 enabled)
0 : I/O port
1 : TxD (SDA3) output
PS3_2
PS3_3
PS3_4
Port P9
Port P9
Port P9
2
3
4
function select bit
function select bit
function select bit
3
0 : I/O port
1 : RTS3 output
0 : I/O port
1 : RTS4 output
PS3_5
PS3_6
PS3_7
Port P9
Port P9
Port P9
5
6
7
function select bit
function select bit
0 : I/O port
1 : CLK4 output
0 : I/O port
1 : TxD
4(SDA4) output
function select bit 0 : I/O port
1 : Peripheral function output
(PSL3_7 enabled)
Note: Set bit 2 of protect register (address 000A16) to “1” before rewriting to this register.
Figure 1.26.9. Function select register A (2)
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Function select register B0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PSL0
Address
03B216
When reset
XXX0XXXX2
Bit name
Function
R W
Bit symbol
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
0 : RTS1 output
1 : CLKS1 output
PSL0_4
Port P64 peripheral function
select bit
(Enabled when PS0_4 = 1)
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Function select register B1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PSL1
Address
03B316
When reset
XXX000X02
R W
Bit name
Function
Bit symbol
PSL1_0
0 : TxD2(SDA2) port
1 : TA0OUT output
Port P70 peripheral function
select bit
(Enabled when PS1_0 = 1)
(Note 2)
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
PSL1_2
Port P72 peripheral function
select bit
(Enabled when PS1_2 = 1)
0 : Port P72 peripheral
subfunction select bit
(PSC_0) is enabled
1 : TA1OUT output (Note 1)
Port P73 peripheral function
select bit
(Enabled when PS1_3 = 1)
PSL1_3
PSL1_4
0 : RTS2 port
1 : V phase output
Port P74 peripheral function
select bit
(Enabled when PS1_4 = 1)
0 : TA2OUT port
1 : W phase output
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Note 1: Set PSC_0 to “1”.
Note 2: This port is N-channel open drain output.
Function select register B2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PSL2
Address
03B616
When reset
XXXXXXX02
Bit symbol
PSL2_0
Bit name
Function
R W
Port P80 peripheral function select
bit (Enabled when PS2_0 = 1)
0 : TA4OUT output
1 : U phase output
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
Figure 1.26.10. Function select register B (1)
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Function select register B3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PSL3
Address
03B716
When reset
00000X0X
2
Bit symbol
Nothing is assigned.
R W
Bit name
Function
When write, set "0". When read, the content is indeterminate.
0 : SCL output
1 : STxD output
3
PSL3_1
Port P91 peripheral function
select bit
3
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
PSL3_3
Port P9
3
peripheral function 0 : Input peripheral function
enabled (Except DA0 output)
(Note)
1 : Input peripheral function
disabled (DA0 output)
0 : Input peripheral function
enabled (Except DA1 output)
(Note)
1 : Input peripheral function
disabled (DA1 output)
PSL3_4
PSL3_5
PSL3_6
PSL3_7
Port P9
Port P9
Port P9
Port P9
4
5
6
7
peripheral function
peripheral function
peripheral function
peripheral function
0 : Input peripheral function
enabled (Except ANEX0 use)
(Note)
1 : Input peripheral function
disabled (ANEX0 use)
0 : Input peripheral function
enabled (Except ANEX1 use)
(Note)
1 : Input peripheral function
disabled (ANEX1 use)
0 : SCL
1 : STxD
4
output
output
select bit
4
Note: Although DA0, DA1 output and ANEX0, ANEX1 can be used when "0" is set in
these bits, the power supply may be increased.
Figure 1.26.11. Function select register B (2)
Function select register C
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PSC
Address
03AF16
When reset
0XXXXXX0
2
R W
Bit name
Port P72 peripheral subfunction
select bit (Enabled when PS1_2 =
1 and PSL1_2 = 0)
Function
Bit symbol
PSC_0
(Note 1)
0 : CLK2 output
1 : V phase output
Nothing is assigned.
When write, set "0". When read, the content is indeterminate.
PSC_7
(Note 2)
Key input interrupt disable bit
0 : Enabled
1 : Disabled
Note 1: Set this bit to "0" when PSL1_2 = "1".
Note 2: When this bit is "1", key input interrupt for interrupt controller is disabled
regardless of port input and setting of interrupt control register.
When changing this bit, set key input interrupt disabled by key input interrupt
control register.
Figure 1.26.12. Function select register C
202
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03F016
When reset
0016
Bit symbol
Bit name
Function
R W
PU00
P0
P0
P1
P1
P2
P2
P3
P3
0
to P0
to P0
to P1
to P1
to P2
to P2
to P3
to P3
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
PU01
PU02
PU03
PU04
PU05
PU06
PU07
4
0
4
0
4
0
4
7
3
7
3
7
3
7
1 : Pulled high
Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor
mode, do not set the pull-up control register. However, it is possible to select pull-
up resistance presence to the usable port as I/O port by setting.
Pull-up control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03F116
When reset
X016
Bit symbol
PU10
Bit name
Function
R W
P4
0
4
to P4
3
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
PU11
P4
to P4
7
PU12
P5
P5
0
4
to P5
to P5
3
7
1 : Pulled high
PU13
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: Since P0 to P5 operate as the bus in memory expansion mode and microprocessor
mode, do not set the pull-up control register. However, it is possible to select pull-
up resistance presence to the usable port as I/O port by setting.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03DA16
When reset
0016
Bit symbol
Bit name
Function
R W
PU20
PU21
PU22
PU23
PU24
P6
P6
0
4
to P6
to P6
3
7
pull-up
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
pull-up
P7
P7
P8
0
to P7
to P7
to P8
3
pull-up (Note 1)
1 : Pulled high
4
7 pull-up
0
3
pull-up
PU25
PU26
P8
4
0
to P8
7
3
pull-up (Note 2)
pull-up
P9
to P9
PU27
P9
4
to P9
7
pull-up
Note 1: Since P7
Note 2: Except port P8
0 and P71 are N-channel open drain ports, pull-up is not available for them.
5.
Figure 1.26.13. Pull-up control register (1)
203
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
100-pin version
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR3
Address
03DB16
When reset
0016
0
0 0 0 0 0
Bit symbol
Bit name
Function
R W
PU30
P10
0
4
to P10
3
pull-up
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
PU31
P10
to P10
7
pull-up
1 : Pulled high
Reserved bit
Must always be set to "0"
144-pin version
Pull-up control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR3
Address
03DB16
When reset
0016
Bit
Bit
name
Function
R W
symbol
PU30
P10
P10
P11
0
4
0
to P10
to P10
to P11
3
7
3
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
PU31
PU32
PU33
PU34
PU35
PU36
PU37
1 : Pulled high
P114 pull-up
P12
P12
P13
P13
0
4
0
4
to P12
to P12
to P13
to P13
3
pull-up
pull-up
pull-up
pull-up
7
3
7
Pull-up control register 4 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR4
Address
03DC16
When reset
XXXX00002
Bit symbol
PU40
Bit name
to P14 pull-up
Function
R W
P14
P14
P15
P15
0
4
0
4
3
The corresponding port is pulled
high with a pull-up resistance
0 : Not pulled high
PU41
to P14
to P15
to P15
6
3
7
pull-up
pull-up
pull-up
PU42
1 : Pulled high
PU43
Nothing is assigned.
When write, set "0". When read, their contents are “0”.
Note: This register exists in 144-pin version.
Figure 1.26.14. Pull-up control register (2)
204
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Port control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PCR
Address
03FF16
When reset
XXXXXXX0
2
R W
Bit symbol
PCR0
Bit name
Function
Port P1 control register
0 : Function as common CMOS
port
1 : Function as N-ch open drain
port
(Note 2)
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note 1: Since P1 operates as the data bus in memory expansion mode and
microprocessor mode, do not set the port control register. However, it is
possible to select the CMOS port or N-channel open drain to the usable port
as I/O port by setting.
Note 2: This function is designed to permanently turn OFF the Pch of the CMOS port.
It does not make port 1 a full open drain. Therefore, the absolute maximum
input voltage rating is [-3 to Vcc + 0.3V].
Figure 1.26.15. Port control register
205
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Table 1.26.2. Example connection of unused pins in single-chip mode
Pin name
Connection
After setting for input mode, connect every pin to VSS via a resistance
(pull-down); or after setting for output mode, leave these pins open.
Ports P0 to P15 (excluding P8
Note 1)
5) (
XOUT (Note 2)
Open
Connect via resistance to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
Connect to VSS
Note 1: Port P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.
Table 1.26.3. Example connection of unused pins in memory expansion mode and microprocessor mode
Pin name
Connection
After setting for input mode, connect every pin to VSS via a resistance
(pull-down); or after setting for output mode, leave these pins open.
Ports P6 to P15(excluding P8
Note 1)
5) (
Open
BHE, ALE, HLDA,
XOUT(Note 2), BCLK
Connect via resistance to VCC (pull-up)
Connect to VCC
HOLD, RDY, NMI
AVCC
AVSS, VREF
Connect to VSS
Note 1: Port P11 to P15 exist in 144-pin version.
Note 2: With external clock input to XIN pin.
Microcomputer
Microcomputer
Port P6 to P15 (except for P8
(Note)
5)
Port P0 to P15 (except for P8
(Note)
5)
(Input mode)
(Input mode)
·
·
·
·
·
·
·
·
·
·
·
·
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
NMI
BHE
HLDA
ALE
NMI
X
OUT
Open
Open
VCC
X
OUT
BCLK
V
CC
AVCC
BYTE
AVSS
HOLD
RDY
V
REF
AVCC
AVSS
VSS
V
SS
V
REF
In memory expansion mode or
in microprocessor mode
In single-chip mode
Note: Port P11 to P15 exist in 144-pin version.
Figure 1.26.16. Example connection of unused pins
206
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Mitsubishi Microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Usage Precaution
SFR (100-pin version)
(1) Addresses 03C916, 03CB16 to 03D316 , 03DC16 area is for future plan. Must set "FF16" to address
03CB16, 03CE16, 03CF16, 03D216, 03D316 and "0016" to address 03DC16 at initial setting.
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading
the timer Ai register after setting a value in the timer Ai register with a count halted but before the
counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by under-
flow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai
register with a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
(3) In the case of using as “Free-Run type”, the timer register contents may be unknown when count-
ing begins. If the timer register is set before counting has started, then the starting value will be
unknown.
• In the case where the up/down count will not be changed.
Enable the “Reload” function and write to the timer register before counting begins. Re-
write the value to the timer register immediately after counting has started. If counting
up, rewrite “000016” to the timer register. If counting down, rewrite “FFFF16” to the timer
register. This will cause the same operation as “Free-Run type” mode.
• In the case where the up/down count has changed.
First set to “Reload type” operation. Once the first counting pulse has occurred, the timer
may be changed to “Free-Run type”.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The output from the one-shot timer synchronizes with the count source generated internally.
Therefore, when an external trigger has been selected, a delay of one cycle of count source as
maximum occurs between the trigger input to the TAiIN pin and the one-shot timer output.
207
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Usage precaution
(3) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the
above listed changes have been made.
(4) If a trigger occurs while a count is in progress, after the counter performs one down count following the
reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To
generate a trigger while a count is in progress, generate the second trigger after an elapse longer than
one cycle of the timer's count source after the previous trigger occurred.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance,
the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
208
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Usage precaution
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
(3) The value of the counter is indeterminate at the beginning of a count. Therefore, the timer Bi overflow
flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count
start and an effective edge input.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading from the WAIT instruc-
tion and the instruction that sets all clock stop control bits to “1” in the instruction queue. Therefore,
insert a minimum of 4 NOPs after the WAIT instruction and the instruction that sets all clock stop
control bits to “1” in order to flush the instruction queue.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
(5) When f(XIN) is faster than 10 MHz, make the frequency 10 MHz or less by dividing.
(6) Output impedance of sensor at A-D conversion (Reference value)
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 1.27.1 has to
be completed within a specified period of time T. Let output impedance of sensor equivalent circuit be
R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-
D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
209
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Usage precaution
t
–
C (R0 + R)
Vc is generally VC = VIN {1 – e
}
X
Y
X
Y
And when t = T,
VC=VIN –
VIN=VIN(1 –
)
T
–
X
C (R0 + R)
e
–
=
Y
T
C (R0 +R)
T
X
Y
=ln
Hence, R0 = –
– R
X
Y
C • ln
With the model shown in Figure 1.27.1 as an example, when the difference between VIN and VC becomes
0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in
time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at
time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added
to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 us in the A-D conversion mode with sample & hold. Output
impedance R0 for sufficiently charging capacitor C within time T is determined as follows.
T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence,
0.3 X 10-6
3
3
R0 = –
–7.8 X10
3.0 X 10
0.1
3.0 X 10 –12 • ln
1024
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con-
verter turns out to be approximately 3.0 kΩ. Tables 1.27.1 and 1.27.2 show output impedance values
based on the LSB values.
Microprocessor's inside
Sensor-equivalent circuit
Ω
R (7.8k )
R0
VIN
C (3.0pF)
VC
Figure 1.27.1 A circuit equivalent to the A-D conversion terminal
210
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Usage precaution
Tables 1.27.1. Output impedance values based on the LSB values (10-bit mode) Reference value
f(XIN)
(MHz)
Cycle
(µs)
Sampling time
(µs)
R
C
(pF)
Resolution
(LSB)
R0max
(Kohm)
(Kohm)
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
3.0
4.5
5.3
5.9
6.4
6.8
7.2
7.5
7.8
8.1
0.4
0.9
1.3
1.7
2.0
2.2
2.4
2.6
2.8
10
0.1
0.3
(3 X cycle,
Sample & hold
bit is enabled)
7.8
3.0
10
0.1
0.2
(2 X cycle,
Sample & hold
bit is enabled)
7.8
3.0
Tables 1.27.2. Output impedance values based on the LSB values (8-bit mode) Reference value
Cycle
(µs)
R
C
(pF)
Resolution
(LSB)
R0max
(Kohm)
f(XIN)
(MHz)
Sampling time
(µs)
(Kohm)
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
10
0.1
0.3
(3 X cycle,
Sample & hold
bit is enabled)
7.8
3.0
4.9
7.0
8.2
9.1
9.9
10.5
11.1
11.7
12.1
12.6
0.7
2.1
2.9
3.5
4.0
4.4
4.8
5.2
5.5
10
0.1
0.2
(2 X cycle,
Sample & hold
bit is enabled)
7.8
3.0
5.8
211
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Usage precaution
Interrupts
(1) Setting the stack pointer
• The value of the stack pointer is initialized to 00000016 immediately after reset. Accepting an
interrupt before setting a value in the stack pointer may cause runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Regard-
_______
ing the first instruction immediately after reset, generating any interrupts including the NMI inter-
rupt is prohibited.
Set an even address to the stack pointer so that operating efficiency is increased.
_______
(2) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be prohibited. Connect it to the VCC pin via a
resistance (pulled-up) if unused.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8
register allows reading the pin value. Use the reading of this pin only for establishing the pin level
_______
at the time when the NMI interrupt is input.
_______
• Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI
pin.
(3) Address match interrupt
• Do not set the following addresses to the address match interrupt register.
1. The address of the starting instruction in an interrupt routine.
2. Any of the next 7 instructions addresses immediately after an instruction to clear an interrupt
request bit of an interrupt control register or an instruction to rewrite an interrupt priority level to
a smaller value.
3. Any of the next 3 instructions addresses immediately after an instruction to set the interrupt
enable flag (I flag).
4. Any of the next 3 instructions addresses immediately after an instruction to rewrite a processor
interrupt priority level (IPL) to a smaller value.
Example 1)
Interrupt_A:
; Interrupt A routine
Do not set address match interrupt to the
start address of an interrupt instruction
;
pushm R0,R1,R2,R3,A0,A1 ; <----
••••
Example 2)
mov.b #0,TA0IC
;Change TA0 interrupt priority level to a smaller value
nop
nop
nop
nop
nop
nop
nop
; 1st instruction
; 2nd instruction
; 3rd instruction
Do not set address match interrupt
during this period
; 4th instruction
; 5th instruction
; 6th instruction
; 7th instruction
Example 3)
fset
I
; Set I flag ( interrupt enabled)
; 1st instruction
nop
nop
nop
Do not set address match interrupt
during this period
; 2nd instruction
; 3rd instruction
212
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Usage precaution
Example 4)
ldipl #0
; Rewrite IPL to a smaller value
; 1st instruction
nop
nop
nop
Do not set address match interrupt
during this period
; 2nd instruction
; 3rd instruction
• To return from an interrupt to the address set in an address match interrupt register using return
instruction (reit or freit)
To rewrite the interrupt control register within the interrupt routine, add the below processing to the
end of the routine (immediately before the reit or freit instruction). Also, if multiple interrupts are
enabled with other interrupts, add the below processing to the end of the interrupt that enables the
multiple interrupts.
If the interrupt control register is being rewritten within the non-maskable interrupt routine, add the
below processing to the end of all interrupts.
Additional process
; Execute after the register reset instruction (popm instruction)
fclr
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack (use "stc SVF,R0" when high-speed
;
interrupt)
ldc
R0,FLG
; Set in FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed (use freit when high-speed interrupt)
Example 5)
If rewriting the interrupt control register for interrupt B with the interrupt A routine and enabling multiple
interrupts with interrupt C, the above processing is required at the end of the interrupt A and interrupt
C routines.
Interrupt A routine
Interrupt_A:
pushm R0,R1,R2,R3,A0,A1
••••
; Store registers
bclr
••••
3,TA0IC
; Rewrite interrupt control register of interrupt B
popm R0,R1,R2,R3,A0,A1
fclr
; Restore registers
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack
; Set in FLG
ldc
R0,FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed
213
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Interrupt C routine
Interrupt_C:
pushm R0,R1,R2,R3,A0,A1
fset
; Store registers
I
; Multiple interrupt enabled
••••
••••
popm R0,R1,R2,R3,A0,A1
;Restore registers
fclr
U
; Select ISP (Unnecessary if the ISP has been selected)
; Store R0 register
pushm R0
mov.w 6[SP],R0
; Read FLG on stack
; Set in FLG
ldc
R0,FLG
popm R0
nop
; Restore R0 register
; Dummy
reit
; Interrupt completed
(4) External interrupt
• Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
to INT5 regardless of the CPU operation clock.
• Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT0 to INT5 regardless of the CPU operation clock. (When XIN=20MHz and no division
mode, at least 250 ns width is necessary.)
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.27.2 shows the procedure for
______
changing the INT interrupt generate factor.
Set the interrupt priority level to level 0
(Disable INT interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INT interrupt request)
______
Figure 1.27.2. Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
214
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
DMAC
(1) Do not clear the DMA request bit of the DMAi request cause select register.
In M16C/80, when a DMA request is generated while the channel is disabled (Note), the DMA transfer
is not executed and the DMA request bit is cleared automatically.
Note :The DMA is disabled or the transfer count register is "0".
(2) When DMA transfer is done by a software trigger, set DSR and DRQ of the DMAi request cause select
register to "1" simultaneously using the OR instruction.
e.g.) OR.B #0A0h, DMiSL
; DMiSL is DMAi request cause select register
(3) When changing the DMAi request cause select bit of the DMAi request cause select register, set "1" to
the DMA request bit, simultaneously. In this case, set the corresponding DMA channel to disabled
before changing the DMAi request cause select bit. At least 2 instructions are needed from the
instruction to write to the DMAi request cause select register to enable DMA.
Example) When DMA request cause is changed to timer A0 and using DMA0 in single transfer
after DMA initial setting
push.w
stc
R0
; Store R0 register
DMD0, R0
; Read DMA mode register 0
; Clear DMA0 transfer mode select bit to "00"
; DMA0 disabled
and.b
ldc
#11111100b, R0L
R0, DMD0
mov.b
#10000011b, DM0SL
; Select timer A0
; (Write "1" to DMA request bit simultaneously)
mov.b
or.b
R0L, R0L
#00000001b, R0L
R0, DMD0
R0
; Dummy cycle
At least 2 instructions
are needed until DMA
enabled.
; Set DMA0 single transfer
; DMA0 enabled
ldc
pop.w
; Restore R0 register
Noise
(1) A bypass capacitor should be inserted between Vcc-Vss line for reducing noise and latch-up
Connect a bypass capacitor (approx. 0.1µF) between the Vcc and Vss pins using short wiring and
thicker circuit traces.
Precautions for using CLKOUT pin
When using the Clock Output function of P53/CLKOUT pin (f8, f32 or fc output) in single chip mode, use
port P57 as an input only port (port P57 direction register is "0").
Although port P57 may be set as an output port, it will become high impedance and will not output "H" or
"L" levels.
__________
HOLD signal
__________
When using the HOLD input while P40 to P47 and P50 to P52 are set as output ports in single-chip mode,
you must first set all pins for P40 to P47 and P50 to P52 as input ports, then shift to microprocessor mode
or memory expansion mode.
215
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Reducing power consumption
(1) When A-D conversion is not performed, select the Vref not connected with the Vref connect bit of A-D
control register 1. When A-D conversion is performed, start the A-D conversion at least 1 µs or longer
after connecting Vref.
(2) When using AN4 (P104) to AN7 (P107), select the input disable of the key input interrupt signal with
the key input interrupt disable bit of the function select register C .
When selecting the input disable of the key input interrupt signal, the key input interrupt cannot be
used. Also, the port cannot be input even if the direction register of P104 to P107 is set to input (the
input result becomes undefined). When the input disable of the key input interrupt signal is selected,
use all AN4 to AN7 as A-D inputs.
(3) When ANEX0 and ANEX1 are used, select the input peripheral function disable with port P95 and P96
input peripheral function select bit of the function select register B3.
When the input peripheral function disable is selected, the port cannot be input even if the port direc-
tion register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function except ANEX0 and ANEX1.
(4) When D-A converter is not used, set output disabled with the D-A output enable bit of D-A control
register and set the D-A register to "0016".
(5) When D-A conversion is used, select the input peripheral function disabled with port P93 and P94 input
peripheral function select bit of the function select register B3.
When the input peripheral function disabled is selected, the port cannot be input even if the port
direction register is set to input (the input result becomes undefined).
Also, it is not possible to input a peripheral function.
DRAM controller
When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Shifting to self-refresh
•••
mov.b #00000001b,DRAMCONT
mov.b #10001011b,DRAMCONT
nop
nop
•••
;DRAM ignored, one wait is selected
;Set self-refresh, select 4MB and one wait
;Two nops are needed
;
Disable self-refresh
•••
mov.b #00000001b,DRAMCONT
;Disable self-refresh, DRAM ignored, one wait is
;selected
mov.b #00001011b,DRAMCONT
;Select 4MB and one wait
nop
nop
•••
;Inhibit instruction to access DRAM area
216
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Setting the registers
The registers shown in Table 1.27.3 include indeterminate bit when read. Set immidiate to these regis-
ters.
Store the content of the frequently used register to RAM, change the content of RAM, then transfer to the
register.
Table 1.27.3 The object registers
Register name
Symbol
U4BRG
U4TB
DTT
Address
UART4 bit rate generator
UART4 transfer buffer register
Dead time timer
02F916
02FB16, 02FA16
030C16
Timer B2 interrupt occurrence frequency set counter
UART3 bit rate generator
UART3 transfer buffer register
UART2 bit rate generator
UART2 transfer buffer register
Up-down flag
ICTB2
U3BRG
U3TB
U2BRG
U2TB
UDF
030D16
032916
032B16, 032A16
033916
033B16, 033A16
034416
Timer A0 register (Note)
Timer A1 register (Note)
Timer A2 register (Note)
Timer A3 register (Note)
Timer A4 register (Note)
UART0 bit rate generator
UART0 transfer buffer register
UART1 bit rate generator
UART1 transfer buffer register
TA0
034716, 034616
034916, 034816
034B16, 034A16
034D16, 034C16
034F16, 034E16
036116
TA1
TA2
TA3
TA4
U0BRG
U0TB
U1BRG
U1TB
036316, 036216
036916
036B16, 036A16
Note: In one-shot timer mode and pulse widt modulation mode.
External ROM version (144-pin version)
The external ROM version is operated only in microprocessor mode, so be sure to perform the following:
• Connect CNVss pin to Vcc.
Notes on the microprocessor mode and transition after shifting from the micropro-
cessor mode to the memory expansion mode / sigle-chip mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed.
For that reason, the internal ROM area cannot be accessed.
After the reset has been released and the operation of shifting from the microprocessor mode has started
(“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the
memory expansion mode or single-chip mode.
217
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Flash memory version
Bit 7 and bit 6 of the processor mode register 1 (address 000516) must be set to "112" and this setting
should be done when the main clock is divided by 8.
Rewrite program of external ROM version with built-in boot loader
• Do not use interrupts in rewrite program.
• Do not use absolute address jump instructions (JMP.A, JMPI.A) and absolute address subroutine call
instructions (JSR.A, JSRI.A) in rewrite program.
218
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
nder
U
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Electrical characteristics
Table 1.28.1. Absolute maximum ratings
Symbol
Condition
Rated value
Parameter
Unit
V
Supply voltage
Vcc
V
CC=AVCC
-0.3 to 6.5
-0.3 to 6.5
V
CC=AVCC
Analog supply voltage
AVcc
V
(maskROM : CNVSS, BYTE),
RESET,
P0 -P0
P3 -P3
Input
voltage
0
7
, P1
, P4
, P7
, P10
0
-P1
-P4
-P7
-P10
, P13 -P13
7
, P2
, P5
, P8
, P11
0
-P2
-P5
-P8
7,
0
7
0
7
0
7
,
-0.3 to Vcc+0.3
V
P6
0
-P67
2
7
0
7,
VI
P9
0
-P97
0
7
0
-P114,
P12
P15
0
0
-P12
-P15
7
0
7
, P14
0
-P14
6,
7
,
V
REF, XIN
(Note 1)
-0.3 to 6.5
V
V
P7
P0
0
, P7
1
Output
voltage
0
-P0
7
, P1
,P4
,P7
0
-P1
7
7
, P2
0
-P2
-P5
-P84,
7,
P3
0
-P3
-P6
7
0-P4
, P5
, P8
0
7
,
-0.3 to Vcc+0.3
P60
7
2-P7
7
0
VO
P8
6
, P8
7
, P9
0
-P9
7, P100-P107,
P11
0
-P11
-P14
4
, P12
, P15
0
-P12
-P15
7
, P13
X
0
-P13
(Note 1)
OUT
7,
P14
0
6
0
7,
P7
0, P71
-0.3 to 6.5
500
V
mW
C
Power dissipation
Topr=25
C
Pd
-20 to 85 / -40 to 85 (Note 2)
-65 to 150
T
opr
Operating ambient temperature
Storage temperature
T
stg
C
Note 1: Port P11 to P15 exist in 144-pin version.
Note 2: Specify a product of -40 to 85°C to use it.
219
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Edleevceltorpimceantl characteristics
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.28.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Topr = – 20
o
o
to 85 C / – 40 to 85 C(Note3) unless otherwise specified)
Standard
Typ.
Symbol
Parameter
Unit
Min
Max.
Vcc
2.7
Supply voltage
5.0
Vcc
0
5.5
V
V
V
V
AVcc
Vss
Analog supply voltage
Supply voltage
AVss
0
Analog supply voltage
P40-P47, P50-P57, P60-P67,
P72-P77, P80-P87, P90-P97, P100-P107,
HIGH input
voltage
0.8Vcc
Vcc
V
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5),
XIN, RESET, CNVSS, BYTE
P71
P70 ,
0.8Vcc
0.8Vcc
6.5
Vcc
V
V
VIH
P00-P07, P10-P17, P20-P27, P30-P37
(during single-chip mode)
P00-P07, P10-P17, P20-P27, P30-P37
0.5Vcc
0
Vcc
V
V
(data input function during memory expansion and microprocessor modes)
P40-P47, P50-P57, P60-P67,
P70-P77, P80-P87, P90-P97, P100-P107,
LOW input
voltage
0.2Vcc
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5),
XIN, RESET, CNVSS, BYTE
P00-P07, P10-P17, P20-P27, P30-P37
(during single-chip mode)
VIL
0
0
0.2Vcc
V
V
P00-P07, P10-P17, P20-P27, P30-P37
0.16Vcc
(data input function during memory expansion and microprocessor modes)
P00-P07, P10-P17, P20-P27, P30-P37
P40-P47, P50-P57, P60-P67, P72-P77,
P80-P84, P86, P87, P90-P97, P100-P107,
HIGH peak output
current
IOH (peak)
-10.0
mA
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5)
HIGH average output
current
P00-P07, P10-P17, P20-P27, P30-P37
P40-P47, P50-P57, P60-P67, P72-P77,
P80-P84, P86, P87, P90-P97, P100-P107,
IOH (avg)
-5.0
mA
mA
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5)
P00-P07, P10-P17, P20-P27, P30-P37
P40-P47, P50-P57, P60-P67, P70-P77,
P80-P84, P86, P87, P90-P97, P100-P107,
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5)
LOW peak output
current
IOL (peak)
10.0
P00-P07, P10-P17, P20-P27, P30-P37
P40-P47, P50-P57, P60-P67, P70-P77,
P80-P84, P86, P87, P90-P97, P100-P107,
P110-P114, P120-P127,P130-P137, P140-P146,
P150-P157 (Note 5)
LOW average
output current
IOL (avg)
5.0
20
mA
Main clock input oscillation frequency
No wait
Vcc=4.2V to 5.5V
Vcc=2.7V to 4.2V
0
0
MHz
f (XIN)
MHz
kHz
10
50
f (XcIN)
Subclock oscillation frequency
32.768
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be 80mA max. The total
IOH (peak) for ports P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be -80mA max. The total IOL (peak)
for ports P3, P4, P5, P6, P7,P80 to P84, P12 and P13 must be 80mA max. The total IOH (peak) for ports P3, P4,
P5, P6, P72 to P77, P80 to P84, P12 and P13 must be -80mA max.
Note 3: Specify a product of -40 to 85°C to use it.
Note 4: The specification of VIH and VIL of P87 is not when using as XCIN but when using programmable input port.
Note 5: Port P11 to P15 exist in 144-pin version.
220
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
o
Table 1.28.3. Electrical characteristics (referenced to VCC=5V, VSS=0V at Topr=25 C, f(XIN)=20MHZ
unless otherwise specified)
Standard
Typ. Max.
Measuring condition
Symbol
Parameter
Unit
V
Min
3.0
HIGH output
voltage
P00
P50
P90
-P0
-P5
-P9
7
7
7
, P1
, P6
, P10
0
-P1
-P6
7
, P2
0
2
-P2
-P7
7
7
, P3
, P8
0
-P3
-P8
, P12
7
4
, P4
, P8
0-P127,
0
6
-P4
, P8
7
,
,
0
7, P7
0
7
I
OH= - 5mA
V
V
V
OH
0-P10
7
, P11
0
-P11
4
P13
0
-P13
7
, P14
0
-P14
6
, P15 -P157
0
(Note 1)
P00
P50
P90
-P0
-P5
-P9
7
7
7
, P1
, P6
, P10
0
0
-P1
-P6
7
, P2
, P7
0
2
-P2
-P7
7
7
, P3
, P8
0
0
-P3
-P8
7
4
, P4
, P8
0
-P47,
HIGH output
voltage
7
6, P87,
OH
I
OH= - 200µA
4.7
V
0
-P10
7
, P11
0
-P11
4
, P12
0-P127,
(Note 1)
P13
0
-P13
7
, P14
0
-P14
6
, P15 -P157
0
HIGHPOWER
LOWPOWER
I
OH= - 1mA
3.0
3.0
HIGH output
voltage
X
OUT
V
V
I
OH= - 0.5mA
OH
3.0
1.6
With no load applied
With no load applied
HIGH output
voltage
HIGHPOWER
LOWPOWER
XCOUT
P0
P5
P9
0
-P0
-P5
-P9
7
, P1
, P6
, P10
0
0
-P1
7
, P2
, P7
0
0
-P2
-P7
7
7
, P3
, P8
0
0
-P3
-P8
, P12
7
4
, P4
, P8
0
6
-P47,
, P87,
LOW output
voltage
0
0
7
7
-P67
0
-P10
7
, P11
0
-P11
4
0
-P12
7
,
I
OL=5mA
2.0
V
V
V
OL
OL
P13
0
-P13
7, P14
0
-P14
6
, P15
0
-P157
(Note 1)
P0
P5
P9
0
0
0
-P0
-P5
-P9
7
7
7
, P1
, P6
, P10
0
-P1
-P6
7
, P2
, P7
0
0
-P2
-P7
7
7
, P3
, P8
0
-P3
-P8
, P12
7
4
, P4
, P8
0-P127,
0
6
-P47,
LOW output
voltage
0
7
0
, P8
7
,
IOL=200µA
0.45
V
0
-P10
7
, P11
0
-P11
4
P130-P13
7
, P14
0
-P14
6
, P15
0
-P157
(Note 1)
I
OL=1mA
OL=0.5mA
2.0
HIGHPOWER
LOWPOWER
LOW output
voltage
X
OUT
VOL
V
V
I
2.0
0
0
HIGHPOWER
LOWPOWER
With no load applied
With no load applied
LOW output
voltage
X
COUT
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN
,
Hysteresis
VT+-VT-
INT
0-INT5,
ADTRG, CTS
0
-CTS
4
, CLK
0-CLK4,
0.2
0.2
1.0
1.8
5.0
V
V
TA0OUT-TA4OUT,NMI,KI
0
-KI3,RxD0-RxD4,
SCL
2
-SCL4, SDA
2
-SDA
4
V
T+-VT-
Hysteresis
RESET
P0
P4
P9
P12
X
0
0
0
-P0
-P4
-P9
7
7
7
, P1
, P5
0
0
-P1
-P5
-P10
7
7
, P2
, P6
0
0
-P2
-P6
7
, P3
0
0
-P3
-P7
7
7
,
HIGH input
current
7, P7
, P8
0
-P8
7
,
IIH
µA
,P10
,P13
IN, RESET, CNVss, BYTE
0
7
, P11
0
-P11
4
,
V
V
I
I
=5V
=0V
0
-P12
7
0
-P13
7
, P14
0-P14
6
, P15
0
-P15
7
,
(Note 1)
LOW input P0
0
0
0
-P0
-P4
-P9
7
7
7
, P1
, P5
0
0
-P1
-P5
-P10
7
7
, P2
, P6
0
-P2
-P6
7
7
, P3
, P7
0
0
-P3
-P7
7
7
,
current
P4
P9
0
, P8
0
-P8
7
,
,
,P10
,P13
IN, RESET, CNVss, BYTE
0
7
, P11
0
-P11
4,
IIL
- 5.0
µA
P12
0
-P12
7
0
-P13
7
, P14
0
-P14
6
, P15
0
-P15
7
X
(Note 1)
Pull-up
resistance P5
P9
P0
0
0
0
-P0
-P5
-P9
7
7
7
, P1
, P6
,P10
0
0
-P1
-P6
-P10
7
7
, P2
, P7
0
2
-P2
-P7
7
7
, P3
, P8
0
0
-P3
-P8
7
4
, P4
, P8
0-P127,
0
6
-P4
, P8
7
,
RPULLUP
7,
V
I
=0V
kΩ
30.0
2.0
50.0 167.0
0
7
, P11
0-P11
4
, P12
P13
0
-P13
7
, P14
0
-P14
6, P15
0
-P157
(Note 1)
MΩ
MΩ
V
1.0
6.0
RfXIN
X
IN
Feedback resistance
Feedback resistance
RAM retention voltage
RfXCIN
X
CIN
V
When clock is stopped
RAM
f(XIN)=20MHz
Mask ROM 128 KB version
ROMless RAM 10 KB version(Note 2)
45.0 72.0
50.0 80.0
mA
Measuring condition:
Square wave, no division
In single-chip
Mask ROM 256 KB version
ROMless RAM 24 KB version (Note 2)
mode, the output
pins are open and
other pins are VSS
Flash memory version
50.0 80.0
90.0
Power supply
current
Icc
Mask ROM 128 KB version
ROMless RAM 10 KB version(Note 2)
µA
f(XCIN)=32kHz
Square wave
100.0
Mask ROM 256 KB version
ROMless RAM 24 KB version (Note 2)
Flash memory version
7.0
4.0
mA
µA
f(XCIN)=32kHz
When a WAIT instruction is executed
Topr=25°C when
clock is stopped
Mask ROM 128 KB version
ROMless RAM 10KB version (Note 2)
µA
1.0
2.0
Mask ROM 256 KB version
ROMless RAM 24KB version (Note 2)
Flash memory version
1.0
Topr=85°C when clock is stopped
20.0
Note 1: Port P11 to P15 exist in 144-pin version.
Note 2: ROMless version exists in 144-pin version.
221
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Edleevceltorpimceantl characteristics (Vcc = 5V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.28.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS =
o
0V at Topr = 25 C, f(XIN) = 20MHZ unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition
Unit
10 Bits
Min. Typ. Max.
VREF
=
VCC
Resolution
Absolute
accuracy
LSB
Sample & hold function not
available
VREF = VCC = 5V
±3
Sample & hold function
available (10bit)
AN
0
to AN
7
input
LSB
LSB
±3
±7
V
REF
=
ANEX0, ANEX1 input,
External op-amp
VCC = 5V
connection mode
LSB
Sample & hold function
available (8bit)
V
REF = VCC = 5V
±2
40
R
LADDER
Ladder resistance
Conversion time(10bit)
Conversion time(8bit)
Sampling time
VREF
=
VCC
10
3.3
k
kΩ
t
t
t
CONV
µs
CONV
2.8
0.3
2
µs
µs
V
SAMP
V
REF
IA
VCC
Reference voltage
V
0
VREF
V
Analog input voltage
Note: Divide the frequency if f(XIN) exceeds 10 MHz, and make ØAD equal to or lower than 10 MHz.
Table 1.28.5. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V
o
at Topr = 25 C, f(XIN) = 20MHZ unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
Bits
%
Resolution
Absolute accuracy
Setup time
8
1.0
3
tsu
µs
RO
Output resistance
4
10
20
kΩ
kΩ
IVREF
Reference power supply input current
mA
(
Note
)
1.5
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
“0016”.
The A-D converter's ladder resistance is not included.
Also, when the contents of D-A register is except "0016" and the Vref is unconnected at the A-D
control register 1, IVREF is sent.
222
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tdimeveilnopgme(nVt cc = 5V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.6. External clock input
Standard
Symbol
tc
tw(H)
tw(L)
tr
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
50
Max.
ns
ns
ns
ns
ns
22
22
5
5
tf
External clock fall time
Table 1.28.7. Memory expansion and microprocessor modes
Standard
Min. Max.
Symbol
Parameter
Unit
Data input access time (RD standard, no wait)
Data input access time (AD standard, CS standard, no wait)
Data input access time (RD standard, with wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time (RD standard, when accessing multiplex bus area)
(Note) ns
(Note) ns
(Note) ns
(Note) ns
(Note) ns
tac1(RD-DB)
tac1(AD-DB)
tac2(RD-DB)
tac2(AD-DB)
tac3(RD-DB)
Data input access time (AD standard, CS standard, when accessing
multiplex bus area)
(Note)
tac3(AD-DB)
ns
Data input access time (RAS standard, DRAM access)
Data input access time (CAS standard, DRAM access)
Data input access time (CAD standard, DRAM access)
Data input setup time
(Note)
(Note)
tac4(RAS-DB)
tac4(CAS-DB)
tac4(CAD-DB)
ns
ns
(Note) ns
26
26
30
0
ns
ns
ns
ns
ns
ns
ns
tsu(DB-BCLK)
tsu(RDY-BCLK )
RDY input setup time
tsu(HOLD-BCLK ) HOLD input setup time
th(RD-DB)
Data input hold time
th(CAS -DB)
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
0
0
0
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
ns
25
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
109
(BCLK) X 2
10 9
– 35
t
ac1(RD – DB)
=
=
[ns]
[ns]
f
f
– 35
t
ac1(AD – DB)
f
(BCLK)
109X m
(BCLK) X 2
109X n
(BCLK)
– 35
– 35
– 35
t
ac2(RD – DB)
=
=
=
=
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
t
ac2(AD – DB)
f
109X m
(BCLK) X 2
109X n
(BCLK) X 2
109X m
(BCLK) X 2
109X n
(BCLK) X 2
109X l
t
ac3(RD – DB)
f
– 35 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
– 35 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
– 35 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
– 35 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
t
ac3(AD – DB)
f
tac4(RAS – DB)
=
=
=
f
tac4(CAS – DB)
f
tac4(CAD – DB)
f
(BCLK)
223
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.8. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
ns
ns
ns
tc(TA)
100
TAiIN input cycle time
tw(TAH)
tw(TAL)
40
40
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 1.28.9. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
ns
Min.
400
Max.
tc(TA)
TAiIN input cycle time
ns
tw(TAH)
tw(TAL)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
Table 1.28.10. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
ns
ns
ns
tc(TA)
200
TAiIN input cycle time
tw(TAH)
tw(TAL)
100
100
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 1.28.11. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
tw(TAH)
tw(TAL)
Parameter
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Unit
ns
Min.
Max.
100
100
ns
Table 1.28.12. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
ns
ns
ns
ns
ns
tc(UP)
2000
TAiOUT input cycle time
tw(UPH)
tw(UPL)
1000
1000
400
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
tsu(UP-TIN)
th(TIN-UP)
TAiOUT input hold time
400
224
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tdimeveilnopgme(nVt cc = 5V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.13. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
TBiIN input cycle time (counted on one edge)
t
t
t
t
c(TB)
ns
ns
ns
ns
ns
w(TBH)
w(TBL)
c(TB)
w(TBH)
w(TBL)
40
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
200
t
80
80
t
ns
Table 1.28.14. Timer B input (pulse period measurement mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
t
c(TB)
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
400
200
200
ns
ns
ns
w(TBH)
t
w(TBL)
Table 1.28.15. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
ns
Min.
Max.
t
c(TB)
400
200
200
TBiIN input cycle time
t
t
w(TBH)
ns
ns
TBiIN input HIGH pulse width
w(TBL)
TBiIN input LOW pulse width
Table 1.28.16. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
1000
125
t
w(ADL)
Table 1.28.17. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
Max.
ns
ns
t
t
c(CK)
w(CKH)
200
CLKi input cycle time
CLKi input HIGH pulse width
100
100
t
w(CKL)
ns
ns
CLKi input LOW pulse width
TxDi output delay time
t
t
d(C-Q)
h(C-Q)
80
ns
ns
ns
TxDi hold time
RxDi input setup time
RxDi input hold time
0
30
90
t
su(D-C)
h(C-D)
t
_______
Table 1.28.18. External interrupt INTi inputs
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
t
w(INH)
250
250
INTi input HIGH pulse width
INTi input LOW pulse width
t
w(INL)
225
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.28.19. Memory expansion mode and microprocessor mode (no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
18
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
-3
0
ns
ns
t
h(WR-AD)
(Note)
ns
ns
t
t
t
t
t
t
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
18
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
-3
0
(Note)
ns
ns
ns
h(WR-CS)
Figure 1.28.1
d(BCLK-ALE) ALE signal output delay time
h(BCLK-ALE) ALE signal output hold time
18
10
18
ns
ns
– 2
-5
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
WR signal width
ns
ns
ns
ns
t
t
t
t
d(BCLK-WR)
h(BCLK-WR)
-3
(Note)
d(DB-WR)
h(WR-DB)
(Note)
(Note)
ns
ns
t
w(WR)
Note: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR)
th(WR – DB)
th(WR – AD)
th(WR – CS)
=
=
=
=
– 20
[ns]
f
(BCLK)
10 9
– 10
f
(BCLK) X 2
[ns]
[ns]
[ns]
10 9
– 10
– 10
f
(BCLK) X 2
10 9
f
(BCLK) X 2
10 9
t
w(WR) =
– 15
f
(BCLK) X 2
[ns]
226
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tdimeveilnopgme(nVt cc = 5V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.20. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
18
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
– 3
0
Address output hold time (BCLK standard)
Address output hold time (RD standard)
ns
ns
t
h(WR-AD)
(Note)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
18
– 3
0
(Note)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
ns
ns
ns
t
t
t
h(WR-CS)
Figure 1.28.1
d(BCLK-ALE)
h(BCLK-ALE)
18
10
18
ALE signal output delay time
ALE signal output hold time
ns
ns
– 2
– 5
RD signal output delay time
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output hold time
WR signal output delay time
WR signal output hold time
ns
ns
ns
ns
t
t
t
t
d(BCLK-WR)
h(BCLK-WR)
– 3
(Note)
Data output delay time (WR standard)
d(DB-WR)
h(WR-DB)
Data output hold time (WR standard)
WR signal width
(Note)
(Note)
ns
ns
t
w(WR)
Note: Calculated according to the BCLK frequency as follows:
109 X n
td(DB – WR)
th(WR – DB)
th(WR – AD)
th(WR – CS)
=
=
=
=
– 20
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
f
(BCLK)
10 9
– 10
f
(BCLK) X 2
[ns]
[ns]
[ns]
10 9
– 10
– 10
f
(BCLK) X 2
10 9
f
(BCLK) X 2
109 X n
(BCLK) X 2
t
w( WR) =
– 15
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
f
227
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
18
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
-3
(Note)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
ns
ns
t
h(WR-AD)
(Note)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
18
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
-3
ns
ns
ns
ns
(Note)
(Note)
t
h(WR-CS)
Figure 1.28.1
t
d(BCLK-RD)
h(BCLK-RD)
18
18
t
t
-5
RD signal output hold time
WR signal output delay time
ns
ns
d(BCLK-WR)
t
h(BCLK-WR)
-3
(Note)
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
ns
ns
ns
t
d(DB-WR)
th(WR-DB)
(Note)
ns
t
t
t
t
t
d(BCLK-ALE) ALE signal output delay time (BCLK standard)
18
8
h(BCLK-ALE) ALE signal output hold time (BCLK standard)
– 2
ns
ns
d(AD-ALE)
h(ALE-AD)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output flowting start time
(Note)
(Note)
ns
ns
dz(RD-AD)
t
h(BCLK-DB)
Data output hold time (BCLK standard)
-5
ns
Note: Calculated according to the BCLK frequency as follows:
10 9
t
h(RD – AD) =
– 10
– 10
– 10
– 10
f
f
f
f
(BCLK) X 2
[ns]
[ns]
[ns]
[ns]
10 9
t
h(WR – AD) =
(BCLK) X 2
10 9
t
h(RD – CS) =
(BCLK) X 2
10 9
t
h(WR – CS) =
(BCLK) X 2
109X m
t
d(DB – WR)
h(WR – DB)
=
=
– 25
– 10
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns]
f
(BCLK) X 2
10 9
t
f(BCLK) X 2
9
10
t
d(AD – ALE)
h(ALE – AD)
=
=
– 23
– 10
f
(BCLK) X 2
[ns]
[ns]
9
10
t
f
(BCLK) X 2
228
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tdimeveilnopgme(nVt cc = 5V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
o
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, DRAM area selected)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
-3
Max.
18
t
t
t
t
t
d(BCLK-RAD) Row address output delay time
ns
ns
ns
ns
ns
h(BCLK-RAD) Row address output hold time (BCLK standard)
d(BCLK-CAD) String address output delay time
18
18
h(BCLK-CAD) String address output hold time (BCLK standard)
h(RAS-RAD)
-3
(Note)
Row address output hold time after RAS output
t
t
t
d(BCLK-RAS) RAS output delay time (BCLK standard)
h(BCLK-RAS) RAS output hold time (BCLK standard)
ns
ns
ns
Figure 1.28.1
-3
(Note)
RP
RAS "H" hold time
18
18
t
t
t
t
t
t
t
d(BCLK-CAS) CAS output delay time (BCLK standard)
h(BCLK-CAS) CAS output hold time (BCLK standard)
ns
ns
ns
ns
ns
ns
ns
-3
d(BCLK-DW)
h(BCLK-DW)
su(DB-CAS)
h(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
CAS after DB output setup time
-5
(Note)
DB signal output hold time (BCLK standard)
-7
(Note)
su(CAS-RAS) CAS before RAS setup time (refresh)
Note: Calculated according to the BCLK frequency as follows:
10 9
t
h(RAS – RAD)
=
– 13
f
(BCLK) X 2
[ns]
109 X 3
(BCLK) X 2
t
t
RP =
– 20
f
f
[ns]
10 9
(BCLK)
su(DB – CAS)
=
– 20
[ns]
109
t
su(CAS –RAS) =
– 13
[ns]
f
(BCLK) X 2
229
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
P0
P1
P2
P3
P4
P5
P6
P7
30pF
P8
P9
P10
P11
P12
P13
(Note)
P14
P15
Note: Port P11 to P15 exist in 144-pin version.
Figure 1.28.1. Port P0 to P15 measurement circuit
230
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
der
n
U
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode (without wait)
Read Timing
BCLK
t
d(BCLK-ALE)
18ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
d(BCLK-CS)
t
h(BCLK-CS)
-3ns.min
*1
18ns.max
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
*1
18ns.max
-3ns.min
ADi
BHE
t
h(RD-AD)
0ns.min
t
d(BCLK-RD)
10ns.max
RD
DB
*2
t
h(BCLK-RD)
-5ns.min
t
ac1(RD-DB)
*2
t
ac1(AD-DB)
Hi-Z
t
su(DB-BCLK)
t
h(RD-DB)
*1
26ns.min
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
*2:It depends on operation frequency.
.
t
ac1(RD-DB)=(tcyc/2-35)ns.max
t
ac1(AD-DB)=(tcyc-35)ns.max
Write Timing ( Written by 2 cycles in selecting no wait)
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
*3
tcyc
t
h(WR-CS)
t
d(BCLK-AD)
t
h(BCLK-AD)
-3ns.min
18ns.max
ADi
BHE
*3
h(WR-AD)
t
t
d(BCLK-WR)
18ns.max
*3
tw(WR)
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
*3
*3
d(DB-WR)
t
t
h(WR-DB)
DBi
*3:It depends on operation frequency.
Measuring conditions
• VCC=5V±10%
t
t
t
t
t
d(DB-WR)=(tcyc-20)ns.min
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2-15)ns.min
• Input timing voltage :Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage :Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.2. VCC=5V timing diagram (1)
231
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode (with 1 wait)
Read Timing
BCLK
18ns.max
d(BCLK-ALE)
t
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max*1
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
18ns.max*1
t
h(BCLK-AD)
-3ns.min
ADi
BHE
t
d(BCLK-RD)
t
h(RD-AD)
0ns.min
10ns.max
RD
DB
t
h(BCLK-RD)
-5ns.min
t
ac2(RD-DB)*2
t
ac2(AD-DB)*2
Hi-Z
t
su(DB-BCLK)
26ns.min*1
t
h(RD-DB)
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
*2:It depends on operation frequency.
.
t
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
ac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
18ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
CSi
tcyc
t
t
h(WR-CS)*3
h(WR-AD)*3
t
d(BCLK-AD)
18ns.max
t
h(BCLK-AD)
-3ns.min
ADi
BHE
t
d(BCLK-WR)
18ns.max
tw(WR)*3
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
t
d(DB-WR)*3
th(WR-DB)*3
DBi
*3:It depends on operation frequency.
d(DB-WR)=(tcyc x n-20)ns.min
Measuring conditions
• VCC=5V±10%
t
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.3. VCC=5V timing diagram (2)
232
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Memory expansion Mode and Microprocessor Mode (with 2 wait)
Read Timing
Vcc=5V
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
d(BCLK-CS)
18ns.max*1
t
h(BCLK-CS)
-3ns.min
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
-3ns.min
18ns.max*1
ADi
BHE
t
d(BCLK-RD)
t
h(RD-AD)
0ns.min
10ns.max
RD
DB
t
h(BCLK-RD)
-5ns.min
t
ac2(RD-DB)*2
t
ac2(AD-DB)*2
Hi-Z
t
su(DB-BCLK)
26ns.min*1
t
h(RD-DB)
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
.
*2:It depends on operation frequency.
t
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
ac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
18ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
CSi
tcyc
th(WR-CS)*3
t
d(BCLK-AD)
18ns.max
t
h(BCLK-AD)
-3ns.min
ADi
BHE
th(WR-AD)*3
t
d(BCLK-WR)
18ns.max
t
w(WR)*3
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
t
d(DB-WR)*3
th(WR-DB)*3
DBi
*3:It depends on operation frequency.
d(DB-WR)=(tcyc x n-20)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
Measuring conditions
• VCC=5V±10%
t
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
t
t
t
t
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.4. VCC=5V timing diagram (3)
233
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Memory expansion Mode and Microprocessor Mode (with 3 wait)
Read Timing
Vcc=5V
BCLK
18ns.max
t
h(BCLK-ALE)
-2ns.min
td(BCLK-ALE)
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
*1
18ns.max
t
h(RD-CS)
0ns.min
tcyc
t
h(BCLK-AD)
t
d(BCLK-AD)
*1
18ns.max
-3ns.min
ADi
BHE
t
d(BCLK-RD)
10ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-5ns.min
*2
t
ac2(RD-DB)
*2
t
ac2(AD-DB)
Hi-Z
t
su(DB-BCLK)
26ns.min
t
h(RD-DB)
0ns.min
*1
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
CSi
*3
*3
tcyc
t
t
h(WR-CS)
t
d(BCLK-AD)
18ns.max
t
h(BCLK-AD)
-3ns.min
ADi
BHE
*3
t
d(BCLK-WR)
h(WR-AD)
tw(WR)
18ns.max
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
*3
*3
t
h(WR-DB)
td(DB-WR)
DBi
*3:It depends on operation frequency.
td(DB-WR)=(tcyc x n-20)ns.min
Measuring conditions
• VCC=5V±10%
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
th(WR-DB)=(tcyc/2-10)ns.min
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
:Determined with VOH=2.0V, VOL=0.8V
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.5. VCC=5V timing diagram (4)
234
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with 2 wait, and select multiplexed bus)
)
Read Timing
BCLK
18ns.max
t
h(BCLK-ALE)
-2ns.min
td(BCLK-ALE)
ALE
CSi
t
h(BCLK-CS)
-3ns.min
tcyc
t
d(BCLK-CS)
18ns.max
*1
th(RD-CS)
*1
*1
td(AD-ALE)
th(ALE-AD)
ADi
/DBi
Address
Data input
Address
t
dz(RD-AD)
t
h(RD-DB)
0ns.min
8ns.max
t
su(DB-BCLK)
26ns.min
t
d(BCLK-AD)
t
h(BCLK-AD)
-3ns.min
*1
ac3(RD-DB)
t
18ns.max
ADi
BHE
*1
*1
th(RD-AD)
t
ac3(AD-DB)
t
d(BCLK-RD)
t
h(BCLK-RD)
-5ns.min
18ns.max
RD
*1:It depends on operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-23)ns.min
h(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
ac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
ac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
18ns.max
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
t
ALE
CSi
t
h(BCLK-CS)
tcyc
t
d(BCLK-CS)
18ns.max
-3ns.min
*2
th(WR-CS)
*2
*2
t
h(BCLK-DB)
-5ns.min
t
h(ALE-AD)
td(AD-ALE)
ADi
/DBi
Address
Data output
*2
Address
*2
th(WR-DB)
td(DB-WR)
t
h(BCLK-AD)
-3ns.min
t
d(BCLK-AD)
18ns.max
ADi
BHE
*2
h(WR-AD)
t
t
h(BCLK-WR)
-3ns.min
t
d(BCLK-WR)
18ns.max
WR,WRL,
WRH
*2:It depends on operation frequency.
Measuring conditions
• VCC=5V±10%
t
t
t
t
d(AD-ALE)=(tcyc/2-23)ns.min
h(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
d(DB-WR)=(tcyc/2 x m-25)ns.min
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
(m=3 and 5 when 2 wait and 3 wait, respectively.)
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.6. VCC=5V timing diagram (5)
235
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with 3 wait, and select multiplexed bus)
)
Read Timing
BCLK
18ns.max
t
h(BCLK-ALE)
-2ns.min
td(BCLK-ALE)
ALE
CSi
t
h(BCLK-CS)
-3ns.min
tcyc
t
d(BCLK-CS)
18ns.max
*1
h(RD-CS)
t
*1
d(AD-ALE)
*1
t
th(ALE-AD)
ADi
Address
Data input
Address
t
dz(RD-AD)
/DBi
t
h(RD-DB)
0ns.min
8ns.max
t
su(DB-BCLK)
t
h(BCLK-AD)
-3ns.min
t
d(BCLK-AD)
18ns.max
*1
ac3(RD-DB)
26ns.min
t
ADi
BHE
*1
ac3(AD-DB)
*1
t
t
d(BCLK-RD)
18ns.max
th(RD-AD)
t
h(BCLK-RD)
-5ns.min
RD
*1:It depends on operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-23)ns.min
h(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
ac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
ac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
tcyc
t
d(BCLK-CS)
18ns.max
-3ns.min
*2
th(WR-CS)
*2
t
h(BCLK-DB)
-5ns.min
td(AD-ALE)
*2
t
h(ALE-AD)
ADi
Address
Data output
Address
/DBi
*2
*2
*2
t
h(WR-DB)
td(DB-WR)
t
h(BCLK-AD)
-3ns.min
t
d(BCLK-AD)
18ns.max
ADi
BHE
th(WR-AD)
t
h(BCLK-WR)
-3ns.min
t
d(BCLK-WR)
18ns.max
WR,WRL,
WRH
*2:It depends on operation frequency.
Measuring conditions
• VCC=5V±10%
t
t
t
t
d(AD-ALE)=(tcyc/2-23)ns.min
h(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
d(DB-WR)=(tcyc/2 x m-25)ns.min
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
(m=3 and 5 when 2 wait and 3 wait, respectively.)
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.7. VCC=5V timing diagram (6)
236
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Read Timing
BCLK
tcyc
t
d(BCLK-CAD)
18ns.max*1
t
d(BCLK-RAD)
t
h(BCLK-RAD)
-3ns.min
t
h(BCLK-CAD)
18ns.max
-3ns.min
MAi
String address
Row address
t
h(RAS-RAD)*2
t
RP*2
RAS
t
h(BCLK-RAS)
-3ns.min
t
d(BCLK-RAS)
t
d(BCLK-CAS)
18ns.max*1
18ns.max*1
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
DW
DB
t
ac4(CAS-DB)*2
t
ac4(CAD-DB)*2
t
ac4(RAS-DB)*2
Hi-Z
t
su(DB-BCLK)
26ns.min*1
t
h(CAS-DB)
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as follows:
t
t
t
d(BCLK-RAS) + tsu(DB-BCLK)
d(BCLK-CAS) + tsu(DB-BCLK)
d(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
t
t
t
t
t
ac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
ac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
ac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.8. VCC=5V timing diagram (7)
237
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Write Timing
BCLK
tcyc
t
d(BCLK-RAD)
t
d(BCLK-CAD)
18ns.max
t
h(BCLK-CAD)
18ns.max
t
h(BCLK-RAD)
-3ns.min
-3ns.min
MAi
Row address
String address
*1
RP
*1
h(RAS-RAD)
t
t
RAS
t
h(BCLK-RAS)
-3ns.min
t
d(BCLK-RAS)
18ns.max
t
d(BCLK-CAS)
18ns.max
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
td(BCLK-DW)
18ns.max
DW
DB
t
h(BCLK-DW)
-5ns.min
*1
t
su(DB-CAS)
Hi-Z
t
h(BCLK-DB)
-7ns.min
*1:It depends on operation frequency.
t
t
t
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
su(DB-CAS)=(tcyc-20)ns.min
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.9. VCC=5V timing diagram (8)
238
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
Vcc=5V
Read Timing
BCLK
tcyc
t
d(BCLK-CAD)
18ns.max*1
t
d(BCLK-RAD)
t
h(BCLK-CAD)
t
h(BCLK-RAD)
18ns.max
-3ns.min
-3ns.min
MAi
String address
Row address
t
h(RAS-RAD)*2
t
RP*2
RAS
t
h(BCLK-RAS)
-3ns.min
t
d(BCLK-RAS)
t
d(BCLK-CAS)
18ns.max*1
18ns.max*1
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
DW
DB
t
ac4(CAS-DB)*2
ac4(CAD-DB)*2
ac4(RAS-DB)*2
t
t
Hi-Z
t
su(DB-BCLK)
26ns.min*1
t
h(CAS-DB)
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as follows:
t
t
t
d(BCLK-RAS) + tsu(DB-BCLK)
d(BCLK-CAS) + tsu(DB-BCLK)
d(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
t
t
t
t
t
ac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
ac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
ac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.10. VCC=5V timing diagram (9)
239
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
Vcc=5V
Write Timing
BCLK
tcyc
t
d(BCLK-RAD)
t
d(BCLK-CAD)
18ns.max
t
h(BCLK-CAD)
t
h(BCLK-RAD)
-3ns.min
18ns.max
-3ns.min
MAi
String address
Row address
t
h(RAS-RAD)*1
t
RP*1
RAS
t
d(BCLK-RAS)
18ns.max
t
h(BCLK-RAS)
t
d(BCLK-CAS)
-3ns.min
18ns.max
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
td(BCLK-DW)
18ns.max
DW
DB
t
h(BCLK-DW)
-5ns.min
t
su(DB-CAS)*1
Hi-Z
t
h(BCLK-DB)
-7ns.min
*1:It depends on operation frequency.
t
t
t
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
su(DB-CAS)=(tcyc-20)ns.min
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.11. VCC=5V timing diagram (10)
240
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
Vcc=5V
Memory expansion Mode and Microprocessor Mode
Refresh Timing (CAS before RAS refresh)
BCLK
tcyc
td(BCLK-RAS)
18ns.max
RAS
t
h(BCLK-RAS)
-3ns.min
t
su(CAS-RAS)*1
CASL
CASH
t
d(BCLK-CAS)
t
h(BCLK-CAS)
-3ns.min
18ns.max
DW
*1:It depends on operation frequency.
su(CAS-RAS)=(tcyc/2-13)ns.min
t
Refresh Timing (Self-refresh)
BCLK
tcyc
t
d(BCLK-RAS)
18ns.max
RAS
t
h(BCLK-RAS)
tsu(CAS-RAS)*1
-3ns.min
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
t
d(BCLK-CAS)
18ns.max
DW
*1:It depends on operation frequency.
su(CAS-RAS)=(tcyc/2-13)ns.min
t
Measuring conditions
• VCC=5V±10%
• Input timing voltage
:Determined with VIH=2.5V, VIL=0.8V
• Output timing voltage
:Determined with VOH=2.0V, VOL=0.8V
Figure 1.28.12. VCC=5V timing diagram (11)
241
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
t
c(TA)
t
w(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
tw(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
th(TIN–UP)
tsu(UP–TIN)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
d(C–Q)
t
su(D–C)
t
h(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 1.28.13. VCC=5V timing diagram (12)
242
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
VCC = 5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
t
h(BCLK–RDY)
tsu(RDY–BCLK)
(Valid with or without wait)
BCLK
t
su(HOLD–BCLK)
t
h(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Measuring conditions :
• VCC
=
5V±10%
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 1.28.14. VCC=5V timing diagram (13)
243
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Eldeevcetlorpimceanlt characteristics (Vcc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
o
Table 1.28.23. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25 C, f(XIN) =
10MHZ with wait)
Standard
Measuring condition
Symbol
Parameter
Unit
V
Min
2.5
Typ. Max.
HIGH output P0
0
0
0
-P0
-P3
-P6
,P8
0
7
7
7
,P1
,P4
,P7
,P9 -P9
, P12
, P15
0
0
2
-P1
-P4
-P7
7
7
7
,P2
,P5
,P8
0
0
0
-P2
-P5
-P8
7
7
4
,
,
,
voltage
P3
P6
P8
I
OH= - 1mA
VOH
6
7
0
7
,P10
-P12
-P15
0-P107,
7,P13 -P13
7 (Note 1)
P11
P14
-P11
-P14
4
0
0
7,
0
6
0
HIGHPOWER
I
OH= - 0.1 mA
OH= - 50 µA
2.5
2.5
HIGH output
voltage
XOUT
V
V
LOWPOWER
I
VOH
3.0
1.6
With no load applied
With no load applied
HIGH output
voltage
HIGHPOWER
LOWPOWER
X
COUT
P00
P30
P60
-P0
-P3
-P6
7
7
7
,P1
,P4
,P7
0
0
0
-P1
-P4
-P7
7
7
7
,P2
,P5
,P8
0
0
0
-P2
-P5
-P8
7
,
,
,
LOW output
voltage
7
4
VOL
IOL=1mA
0.5
V
P8
P11
P14
6
,P8
7
,P9
4
0
-P9
7
,P10
-P12
-P15
0
-P10
,P13
(Note 1)
7
0
-P11
-P14
, P12
, P15
0
7
7
0-P137,
0
6
0
I
OL=0.1mA
0.5
HIGHPOWER
LOWPOWER
LOW output
voltage
X
OUT
VOL
V
V
IOL=50µA
0.5
0
0
HIGHPOWER
LOWPOWER
With no load applied
With no load applied
LOW output
voltage
X
COUT
HOLD, RDY, TA0IN-TA4IN
,
Hysteresis
TB0IN-TB2IN, INT
CTS -CTS ,CLK
NMI, KI -KI3, RxD0-RxD4,
SCL -SCL4, SDA -SDA
0
-INT
5
, ADTRG
,
V
T+-VT-
0
4
0
-CLK
4
,TA2OUT-TA4OUT
,
0.2
0.2
1.0
V
0
2
2
4
V
T+-VT-
Hysteresis
RESET
1.8
4.0
V
P0
P3
P6
P9
P12
P15
0
0
0
0
-P0
-P3
-P6
-P9
7
7
7
7
,P1
,P4
,P7
0
0
0
-P1
-P4
-P7
7
7
7
,P2
,P5
,P8
0
0
0
-P2
-P5
-P8
7,
7,
7
,
HIGH input
current
IIH
µA
VI=3V
,P10
0
-P107, P11
,P13 -P13 , P14
(Note 1)
0
-P11
0
4,
-P14
0
-P12
-P15
7
0
7
6
,
,
0
7
X
IN, RESET, CNVss, BYTE
P0
P3
P6
P9
P12
P15
0
0
0
0
-P0
-P3
-P6
-P9
7
7
7
7
,P1
,P4
,P7
0
0
0
-P1
-P4
-P7
7
7
7
,P2
,P5
,P8
0
0
0
-P2
-P5
-P8
7,
7,
7
,
LOW input
current
VI=0V
IIL
- 4.0
µA
,P10
0
-P107, P11
,P13 -P13 , P14
(Note 1)
0
-P11
0
4,
-P146
0
-P12
-P15
7
0
7
0
7
X
IN, RESET, CNVss, BYTE
Pull-up
resistance
RPULLUP
P0
P3
P6
P8
0
0
0
6
-P0
-P3
-P6
7
7
7
,P1
,P4
,P7
0
0
2
-P1
-P4
-P7
7
7
7
,P2
,P5
,P8
0
0
0
-P2
-P5
-P8
7
7
4
,
,
,
V
I=0V
66.0 120.0 500.0
kΩ
,P87
,P9
0
-P9
7
0
,P10
-P12
-P15
0
-P10
,P13
(Note 1)
7
P11
0
0
-P11
-P14
4
6
, P12
, P15
7
0-P137,
P14
0
7
RfXIN
X
IN
3.0
10.0
Feedback resistance
Feedback resistance
RAM retention voltage
MΩ
MΩ
RfXCIN
X
CIN
V
When clock is stopped
2.0
V
RAM
f(XIN)=10MHz
Square wave, no
division
Mask ROM 128 KB version
ROMless RAM 10 KB version (Note 2)
12.0
14.0
20.0
23.0
23.0
mA
In single-chip
mode, the output
pins are open and
other pins are VSS
Mask ROM 256 KB version
ROMless RAM 24 KB version (Note 2)
Flash memory version
14.0
45.0
f(XCIN)=32kHz
Square wave
Mask ROM 128 KB version
ROMless RAM 10 KB version (Note 2)
µA
Power supply
current
Icc
Mask ROM 256 KB version
ROMless RAM 24 KB version (Note 2)
60.0
Flash memory version
3.5
3.0
mA
µA
f(XCIN)=32kHz
When a WAIT instruction is executed.
Oscillation drive capacity is High.
f(XCIN)=32kHz
When a WAIT instruction is executed.
Oscillation drive capacity is Low.
1.5
µA
Mask ROM 128 KB version
ROMless RAM 10 KB version (Note 2)
1.0
1.0
Topr=25°C, when
clock is stopped
Mask ROM 256 KB version
ROMless RAM 24 KB version (Note 2)
µA
Flash memory version
1.0
Topr=85°C, when clock is stopped
20.0
Note 1: Ports P11 to P15 exist in 144-pin version.
Note 2: ROMless version exists in 144-pin version.
244
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.28.24. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS
=
o
0V at Topr = 25 C, f(XIN) = 10MHZ unless otherwise specified)
Standard
Min. Typ. Max
Symbol
Parameter
Measuring condition
Unit
Resolution
VREF = VCC
10
±2
Bits
LSB
Absolute
accuracy
Sample & hold function not
available (8 bit)
VREF = VCC = 3V,
φAD =
fAD/2
RLADDER
tCONV
VREF
Ladder resistance
VREF = VCC
10
9.8
2.7
0
40
kΩ
µs
V
Conversion time(8bit)
VCC
Reference voltage
Analog input voltage
VIA
VREF
V
Table 1.28.25. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V
o
at Topr = 25 C, f(XIN) = 10MHZ unless otherwise specified)
Standard
Min. Typ. Max
Symbol
Parameter
Measuring condition
Unit
Resolution
Absolute accuracy
Setup time
8
1.0
3
Bits
%
µs
tsu
RO
kΩ
Output resistance
4
10
20
IVREF
Reference power supply input current
(Note)
1.0 mA
Note :This applies when using one D-A converter, with the D-A register for the unused D-A converter set
to “0016”. The A-D converter's ladder resistance is not included.
Also, when the contents of D-A register is except "0016" and the Vref is unconnected at the A-D
control register 1, IVREF is sent.
245
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmevienlogpme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.26. External clock input
Standard
Symbol
Parameter
Unit
Min.
Max.
External clock input cycle time
ns
ns
ns
ns
ns
t
t
c
100
40
40
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
w(H)
tw(L)
t
t
r
18
18
f
External clock fall time
Table 1.28.27. Memory expansion and microprocessor modes
Standard
Min. Max.
(Note)
Symbol
Parameter
Unit
Data input access time (RD standard, no wait)
Data input access time (AD standard, CS standard, no wait)
Data input access time (RD standard, with wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time (RD standard, when accessing multiplex bus area)
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
ac1(RD-DB)
(Note)
(Note)
(Note)
(Note)
ac1(AD-DB)
ac2(RD-DB)
ac2(AD-DB)
ac3(RD-DB)
ac3(AD-DB)
Data input access time (AD standard, CS standard, when accessing
multiplex bus area)
(Note)
ns
ns
t
t
t
ac4(RAS-DB)
ac4(CAS-DB)
ac4(CAD-DB)
Data input access time (RAS standard, DRAM access)
Data input access time (CAS standard, DRAM access)
Data input access time (CAD standard, DRAM access)
Data input setup time
(Note)
(Note)
(Note)
40
ns
ns
ns
ns
ns
tsu(DB-BCLK)
60
tsu(RDY-BCLK )
RDY input setup time
tsu(HOLD-BCLK )
HOLD input setup time
Data input hold time
Data input hold time
80
0
th(RD-DB)
th(CAS-DB)
ns
0
RDY input hold time
t
t
t
h(BCLK -RDY)
h(BCLK-HOLD )
d(BCLK-HLDA )
ns
ns
0
0
HOLD input hold time
HLDA output delay time
100
ns
Note: Calculated according to the BCLK frequency as follows:
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
109
(BCLK) X 2
109
– 42
– 55
t
ac1(RD – DB)
=
=
[ns]
[ns]
f
t
ac1(AD – DB)
f
(BCLK)
109X m
(BCLK) X 2
109 X n
– 42
– 55
– 55
– 55
t
ac2(RD – DB)
=
=
=
=
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
f
t
ac2(AD – DB)
f
(BCLK)
109 X m
(BCLK) X 2
109 X n
(BCLK) X 2
t
ac3(RD – DB)
f
t
ac3(AD – DB)
f
109X m
– 55
t
ac4(RAS – DB)
ac4(CAS – DB)
=
=
=
f(BCLK) X 2
109 X n
– 55
– 55
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
t
f
(BCLK) X 2
109X l
t
ac4(CAD – DB)
f
(BCLK)
246
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.28. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
60
Table 1.28.29. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.28.30. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(TA)
TAiIN input cycle time
ns
ns
ns
t
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
Table 1.28.31. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
ns
ns
t
w(TAL)
Table 1.28.32. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
c(UP)
TAiOUT input cycle time
ns
ns
ns
ns
ns
t
w(UPH)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
t
w(UPL)
t
su(UP-TIN
)
t
h(TIN-UP)
TAiOUT input hold time
600
247
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmevienlogpme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise specified)
Table 1.28.33. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
t
c(TB)
TBiIN input cycle time (counted on one edge)
ns
ns
ns
ns
ns
ns
t
w(TBH)
w(TBL)
c(TB)
w(TBH)
w(TBL)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
t
60
t
300
160
160
t
t
Table 1.28.34. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.28.35. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
w(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
Table 1.28.36. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
w(ADL)
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
ns
ns
t
Table 1.28.37. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
ns
ns
ns
ns
ns
ns
ns
t
t
t
d(C-Q)
h(C-Q)
su(D-C)
160
t
0
50
90
t
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.28.38. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
INTi input HIGH pulse width
INTi input LOW pulse width
ns
ns
t
w(INL)
248
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.39. Memory expansion and microprocessor modes (with no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
ns
ns
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
Address output hold time (BCLK standard)
0
0
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
(Note)
t
h(WR-AD)
t
t
t
t
t
t
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
25
Chip select output delay time
ns
ns
ns
ns
ns
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
ALE signal output delay time
0
0
h(WR-CS)
(Note)
d(BCLK-ALE)
h(BCLK-ALE)
25
10
25
Figure 1.28.1
– 2
– 3
ALE signal output hold time
RD signal output delay time
RD signal output hold time
ns
ns
ns
t
t
t
t
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
ns
ns
ns
ns
0
(Note)
(Note)
t
d(DB-WR)
h(WR-DB)
w(WR)
t
ns
t
WR signal width
(Note)
Note: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR)
th(WR – DB)
th(WR – AD)
th(WR – CS)
=
=
=
=
– 40
[ns]
f
(BCLK)
10 9
– 20
f
(BCLK) X 2
[ns]
[ns]
[ns]
10 9
– 20
– 20
f
(BCLK) X 2
10 9
f
(BCLK) X 2
10 9
tw(WR) =
– 20
f
(BCLK) X 2
[ns]
249
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmevienlogpme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.40. Memory expansion and microprocessor modes
(with wait, accessing external memory)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
25
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
0
0
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
ns
(Note)
t
h(WR-AD)
t
t
t
t
t
t
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
25
Chip select output delay time
ns
ns
ns
ns
ns
Chip select output hold time (BCLK standard)
0
0
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
ALE signal output delay time
Figure 1.28.1
h(WR-CS)
(Note)
d(BCLK-ALE)
h(BCLK-ALE)
25
10
25
– 2
– 3
ALE signal output hold time
ns
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
t
t
t
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
WR signal width
ns
ns
ns
0
(Note)
d(DB-WR)
h(WR-DB)
(Note)
(Note)
ns
ns
t
w(WR)
Note: Calculated according to the BCLK frequency as follows:
10 9 X n
td(DB – WR)
th(WR – DB)
th(WR – AD)
th(WR – CS)
=
=
=
=
– 40
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
f
(BCLK)
10 9
– 20
– 20
– 20
[ns]
[ns]
[ns]
f
(BCLK) X 2
10 9
f
(BCLK) X 2
10 9
f
(BCLK) X 2
109 X n
(BCLK) X 2
t
w( WR) =
– 20
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
f
250
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25 C, CM15 = “1” unless
otherwise specified)
Table 1.28.41. Memory expansion and microprocessor modes
(with wait, accessing external memory, multiplex bus area selected)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
Address output delay time
ns
ns
ns
ns
ns
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
0
(Note)
(Note)
h(WR-AD)
d(BCLK-CS)
25
t
t
t
t
t
h(BCLK-CS)
h(RD-CS)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
0
ns
ns
ns
ns
(Note)
(Note)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
25
25
Figure 1.28.1
– 3
RD signal output hold time
WR signal output delay time
ns
ns
t
d(BCLK-WR)
h(BCLK-WR)
d(DB-WR)
t
t
t
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
0
ns
ns
ns
(Note)
h(WR-DB)
(Note)
t
t
t
t
t
d(BCLK-ALE) ALE signal output delay time (BCLK standard)
h(BCLK-ALE) ALE signal output hold time (BCLK standard)
25
8
ns
ns
ns
ns
ns
– 2
(Note)
(Note)
d(AD-ALE)
h(ALE-AD)
dz(RD-AD)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output flowting start time
th(BCLK-DB)
DB signal output hold time (BCLK standard)
0
ns
Note: Calculated according to the BCLK frequency as follows:
10 9
t
t
t
t
h(RD – AD)
h(WR – AD)
h(RD – CS)
h(WR – CS)
=
– 20
– 20
– 20
– 20
[ns]
[ns]
[ns]
[ns]
f
f
f
f
(BCLK) X 2
10 9
=
(BCLK) X 2
10 9
(BCLK) X 2
10 9
=
=
(BCLK) X 2
109X m
t
t
t
d(DB – WR)
h(WR – DB)
d(AD – ALE)
=
=
=
– 40
– 20
f
(BCLK) X 2
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
10 9
f
(BCLK) X 2
10 9
[ns]
[ns]
– 27
– 20
f
f
(BCLK) X 2
10 9
(BCLK) X 2
t
h(ALE – AD)
=
[ns]
251
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmevienlogpme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
o
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25 C unless otherwise
specified)
Table 1.28.42. Memory expansion and microprocessor modes
(with wait, accessing external memory, DRAM area selected)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
t
t
t
t
t
d(BCLK-RAD) Row address output delay time
ns
ns
ns
ns
ns
h(BCLK-RAD) Row address output hold time (BCLK standard)
d(BCLK-CAD) String address output delay time
0
25
25
h(BCLK-CAD) String address output hold time (BCLK standard)
h(RAS-RAD)
0
Row address output hold time after RAS output
(Note)
t
t
t
d(BCLK-RAS) RAS output delay time (BCLK standard)
h(BCLK-RAS) RAS output hold time (BCLK standard)
ns
ns
ns
Figure 1.28.1
0
(Note)
RP
RAS "H" hold time
25
25
t
t
t
t
t
t
t
d(BCLK-CAS) CAS output delay time (BCLK standard)
h(BCLK-CAS) CAS output hold time (BCLK standard)
ns
ns
ns
ns
ns
ns
ns
0
d(BCLK-DW)
h(BCLK-DW)
su(DB-CAS)
h(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
CAS after DB output setup time
– 3
(Note)
DB signal output hold time (BCLK standard)
– 7
(Note)
su(CAS-RAS) CAS before RAS setup time (refresh)
Note: Calculated according to the BCLK frequency as follows:
10 9
t
h(RAS – RAD)
=
– 25
f
(BCLK) X 2
[ns]
109 X 3
(BCLK) X 2
t
t
RP =
– 40
f
f
[ns]
10 9
(BCLK)
su(DB – CAS)
=
– 40
[ns]
109
t
su(CAS –RAS) =
– 25
[ns]
f
(BCLK) X 2
252
r
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
e
d
n
U
M16C/80 group
velopment
e
Tidming (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Vcc=3V
Memory expansion Mode and Microprocessor Mode (without wait)
Read Timing
BCLK
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
*1
25ns.max
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
*1
25ns.max
0ns.min
ADi
BHE
t
h(RD-AD)
0ns.min
t
d(BCLK-RD)
10ns.max
RD
DB
*2
t
h(BCLK-RD)
-3ns.min
t
ac1(RD-DB)
*2
t
ac1(AD-DB)
Hi-Z
t
su(DB-BCLK)
t
h(RD-DB)
*1
40ns.min
0ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
*2:It depends on operation frequency.
.
t
ac1(RD-DB)=(tcyc/2-42)ns.max
t
ac1(AD-DB)=(tcyc-55)ns.max
Write Timing ( Written by 2 cycles in selecting no wait)
BCLK
t
d(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
25ns.max
*3
tcyc
t
h(WR-CS)
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
*3
h(WR-AD)
t
t
d(BCLK-WR)
25ns.max
tw(WR)*3
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
*3
*3
t
h(WR-DB)
td(DB-WR)
DBi
*3:It depends on operation frequency.
Measuring conditions
• VCC=3V±10%
t
t
t
t
t
d(DB-WR)=(tcyc-40)ns.min
h(WR-DB)=(tcyc/2-20)ns.min
h(WR-AD)=(tcyc/2-20)ns.min
h(WR-CS)=(tcyc/2-20)ns.min
w(WR)=(tcyc/2-20)ns.min
• Input timing voltage :Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage :Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.15. VCC=3V timing diagram (1)
253
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Vcc=3V
Memory expansion Mode and Microprocessor Mode (with 1 wait)
Read Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
*1
25ns.max
t
h(RD-CS)
0ns.min
tcyc
t
h(BCLK-AD)
t
d(BCLK-AD)
*1
25ns.max
0ns.min
ADi
BHE
t
d(BCLK-RD)
10ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-3ns.min
*2
t
ac2(RD-DB)
*2
t
ac2(AD-DB)
Hi-Z
t
su(DB-BCLK)
t
h(RD-DB)
0ns.min
*1
40ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
*2:It depends on operation frequency.
.
t
ac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
t
ac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
25ns.max
CSi
*3
*3
tcyc
t
t
h(WR-CS)
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
*3
t
d(BCLK-WR)
25ns.max
h(WR-AD)
t
w(WR)
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
*3
*3
t
h(WR-DB)
td(DB-WR)
DBi
*3:It depends on operation frequency.
d(DB-WR)=(tcyc x n-40)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
Measuring conditions
• VCC=3V±10%
t
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
t
t
t
t
h(WR-DB)=(tcyc/2-20)ns.min
h(WR-AD)=(tcyc/2-20)ns.min
h(WR-CS)=(tcyc/2-20)ns.min
w(WR)=(tcyc/2 x n-20)ns.min
:Determined with VOH=1.5V, VOL=1.5V
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.16. VCC=3V timing diagram (2)
254
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Vcc=3V
Memory expansion Mode and Microprocessor Mode (with 2 wait)
Read Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
*1
25ns.max
t
h(RD-CS)
0ns.min
tcyc
t
h(BCLK-AD)
t
d(BCLK-AD)
*1
25ns.max
0ns.min
ADi
BHE
t
d(BCLK-RD)
10ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-3ns.min
*2
t
ac2(RD-DB)
*2
t
ac2(AD-DB)
Hi-Z
t
su(DB-BCLK)
t
h(RD-DB)
0ns.min
*1
40ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK)
*2:It depends on operation frequency.
.
t
ac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
t
ac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
25ns.max
CSi
*3
*3
tcyc
t
t
h(WR-CS)
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
*3
t
d(BCLK-WR)
25ns.max
h(WR-AD)
t
w(WR)
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
*3
*3
t
h(WR-DB)
td(DB-WR)
DBi
*3:It depends on operation frequency.
d(DB-WR)=(tcyc x n-40)ns.min
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
Measuring conditions
• VCC=3V±10%
t
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
t
t
t
t
h(WR-DB)=(tcyc/2-20)ns.min
h(WR-AD)=(tcyc/2-20)ns.min
h(WR-CS)=(tcyc/2-20)ns.min
w(WR)=(tcyc/2 x n-20)ns.min
:Determined with VOH=1.5V, VOL=1.5V
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.17. VCC=3V timing diagram (3)
255
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Vcc=3V
Memory expansion Mode and Microprocessor Mode (with 3 wait)
Read Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
*1
25ns.max
t
h(RD-CS)
0ns.min
tcyc
t
h(BCLK-AD)
t
d(BCLK-AD)
*1
25ns.max
0ns.min
ADi
BHE
t
d(BCLK-RD)
10ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-3ns.min
*2
t
ac2(RD-DB)
*2
t
ac2(AD-DB)
Hi-Z
t
su(DB-BCLK)
t
h(RD-DB)
0ns.min
*1
40ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-42)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
25ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
25ns.max
CSi
*3
*3
tcyc
t
t
h(WR-CS)
t
d(BCLK-AD)
25ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
*3
t
d(BCLK-WR)
h(WR-AD)
t
w(WR)
25ns.max
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
*3
*3
t
h(WR-DB)
td(DB-WR)
DBi
*3:It depends on operation frequency.
td(DB-WR)=(tcyc x n-40)ns.min
Measuring conditions
• VCC=3V±10%
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
th(WR-DB)=(tcyc/2-20)ns.min
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
th(WR-AD)=(tcyc/2-20)ns.min
th(WR-CS)=(tcyc/2-20)ns.min
:Determined with VOH=1.5V, VOL=1.5V
tw(WR)=(tcyc/2 x n-20)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 1.28.18. VCC=3V timing diagram (4)
256
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Vcc=3V
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with 2 wait, and select multiplexed bus)
Read Timing
BCLK
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
tcyc
t
d(BCLK-CS)
25ns.max
*1
h(RD-CS)
t
*1
*1
td(AD-ALE)
th(ALE-AD)
ADi
/DBi
Address
Address
Data input
t
dz(RD-AD)
t
h(RD-DB)
0ns.min
8ns.max
t
su(DB-BCLK)
40ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
25ns.max
*1
ac3(RD-DB)
0ns.min
t
ADi
BHE
*1
th(RD-AD)
*1
t
d(BCLK-RD)
t
ac3(AD-DB)
t
h(BCLK-RD)
-3ns.min
25ns.max
RD
*1:It depends on operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-27)ns.min
h(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min
ac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
ac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
25ns.max
ALE
CSi
t
h(BCLK-CS)
tcyc
t
d(BCLK-CS)
25ns.max
0ns.min
*2
th(WR-CS)
*2
d(AD-ALE)
t
h(BCLK-DB)
0ns.min
t
*2
h(ALE-AD)
t
ADi
/DBi
Address
Data output
*2
Address
*2
*2
t
h(WR-DB)
td(DB-WR)
t
h(BCLK-AD)
0ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(BCLK-WR)
0ns.min
th(WR-AD)
t
d(BCLK-WR)
25ns.max
WR,WRL,
WRH
*2:It depends on operation frequency.
Measuring conditions
• VCC=3V±10%
t
t
t
t
d(AD-ALE)=(tcyc/2-27)ns.min
h(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD)=(tcyc/2-20)ns.min
h(WR-CS)=(tcyc/2-20)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
d(DB-WR)=(tcyc/2 x m-40)ns.min
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
(m=3 and 5 when 2 wait and 3 wait, respectively.)
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.19. VCC=3V timing diagram (5)
257
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Vcc=3V
Memory expansion Mode and Microprocessor Mode
(When accessing external memory area with 3 wait, and select multiplexed bus)
Read Timing
BCLK
t
d(BCLK-ALE)
25ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
tcyc
t
d(BCLK-CS)
25ns.max
*1
h(RD-CS)
t
*1
*1
td(AD-ALE)
th(ALE-AD)
ADi
Address
Address
Data input
t
dz(RD-AD)
/DBi
t
h(RD-DB)
0ns.min
8ns.max
t
su(DB-BCLK)
40ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
*1
ac3(RD-DB)
0ns.min
25ns.max
t
ADi
BHE
*1
th(RD-AD)
*1
t
d(BCLK-RD)
25ns.max
t
ac3(AD-DB)
t
h(BCLK-RD)
-3ns.min
RD
*1:It depends on operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-27)ns.min
h(ALE-AD)=(tcyc/2-20)ns.min, th(RD-AD)=(tcyc/2-20)ns.min, th(RD-CS)=(tcyc/2-20)ns.min
ac3(RD-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.)
ac3(AD-DB)=(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.)
Write Timing
BCLK
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
25ns.max
ALE
CSi
t
h(BCLK-CS)
tcyc
t
d(BCLK-CS)
25ns.max
0ns.min
*2
th(WR-CS)
*2
t
h(BCLK-DB)
0ns.min
td(AD-ALE)
*2
h(ALE-AD)
t
ADi
Address
Data output
*2
Address
/DBi
*2
*2
t
h(WR-DB)
t
d(DB-WR)
t
h(BCLK-AD)
0ns.min
t
d(BCLK-AD)
25ns.max
ADi
BHE
t
h(BCLK-WR)
0ns.min
t
h(WR-AD)
t
d(BCLK-WR)
25ns.max
WR,WRL,
WRH
*2:It depends on operation frequency.
Measuring conditions
• VCC=3V±10%
t
t
t
t
d(AD-ALE)=(tcyc/2-27)ns.min
h(ALE-AD)=(tcyc/2-20)ns.min, th(WR-AD)=(tcyc/2-20)ns.min
h(WR-CS)=(tcyc/2-20)ns.min, th(WR-DB)=(tcyc/2-20)ns.min
d(DB-WR)=(tcyc/2 x m-40)ns.min
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
(m=3 and 5 when 2 wait and 3 wait, respectively.)
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.20. VCC=3V timing diagram (6)
258
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Vcc=3V
Read Timing
BCLK
tcyc
t
d(BCLK-CAD)
25ns.max*1
t
h(BCLK-CAD)
t
h(BCLK-RAD)
0ns.min
t
d(BCLK-RAD)
0ns.min
25ns.max*1
MAi
String address
Row address
t
h(RAS-RAD)*2
t
RP*2
RAS
t
h(BCLK-RAS)
0ns.min
t
d(BCLK-RAS)
t
d(BCLK-CAS)
25ns.max*1
25ns.max*1
CASL
CASH
t
h(BCLK-CAS)
0ns.min
DW
DB
t
ac4(CAS-DB)*2
t
ac4(CAD-DB)*2
ac4(RAS-DB)*2
t
Hi-Z
t
su(DB-BCLK)
t
h(CAS-DB)
0ns.min
40ns.min*1
*1:It is a guarantee value with being alone. 55ns.max garantees as follows:
t
t
t
d(BCLK-RAS) + tsu(DB-BCLK)
d(BCLK-CAS) + tsu(DB-BCLK)
d(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
t
t
t
t
t
ac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
ac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
ac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
h(RAS-RAD)=(tcyc/2-25)ns.min
RP=(tcyc/2 x 3-40)ns.min
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.21. VCC=3V timing diagram (7)
259
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 1 wait)
Vcc=3V
Write Timing
BCLK
tcyc
t
d(BCLK-RAD)
t
h(BCLK-CAD)
t
d(BCLK-CAD)
25ns.max
t
h(BCLK-RAD)
0ns.min
25ns.max
0ns.min
MAi
String address
Row address
t
RP*1
t
h(RAS-RAD)*1
RAS
t
h(BCLK-RAS)
0ns.min
t
d(BCLK-RAS)
t
d(BCLK-CAS)
25ns.max
25ns.max
CASL
CASH
t
h(BCLK-CAS)
0ns.min
td(BCLK-DW)
25ns.max
DW
DB
t
h(BCLK-DW)
-3ns.min
t
su(DB-CAS)*1
Hi-Z
t
h(BCLK-DB)
-7ns.min
*1:It depends on operation frequency.
t
t
t
h(RAS-RAD)=(tcyc/2-25)ns.min
RP=(tcyc/2 x 3-40)ns.min
su(DB-CAS)=(tcyc-40)ns.min
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.22. VCC=3V timing diagram (8)
260
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
Vcc=3V
Read Timing
BCLK
tcyc
td(BCLK-CAD)
25ns.max*1
th(BCLK-CAD)
0ns.min
th(BCLK-RAD)
td(BCLK-RAD)
25ns.max*1
0ns.min
MAi
String address
Row address
th(RAS-RAD)*2
tRP*2
RAS
th(BCLK-RAS)
0ns.min
td(BCLK-RAS)
25ns.max*1
td(BCLK-CAS)
25ns.max*1
CASL
CASH
th(BCLK-CAS)
0ns.min
DW
DB
tac4(CAS-DB)*2
tac4(CAD-DB)*2
tac4(RAS-DB)*2
Hi-Z
tsu(DB-BCLK)
40ns.min*1
th(CAS-DB)
0ns.min
*1:It is a guarantee value with being alone. 55ns.max garantees as follows:
t
t
t
d(BCLK-RAS) + tsu(DB-BCLK)
d(BCLK-CAS) + tsu(DB-BCLK)
d(BCLK-CAD) + tsu(DB-BCLK)
*2:It depends on operation frequency.
t
t
t
t
t
ac4(RAS-DB)=(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.)
ac4(CAS-DB)=(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.)
ac4(CAD-DB)=(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.)
h(RAS-RAD)=(tcyc/2-25)ns.min
RP=(tcyc/2 x 3-40)ns.min
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.23. VCC=3V timing diagram (9)
261
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
Memory expansion Mode and Microprocessor Mode
(When accessing DRAM area with 2 wait)
Vcc=3V
Write Timing
BCLK
tcyc
t
d(BCLK-RAD)
t
h(BCLK-CAD)
t
d(BCLK-CAD)
25ns.max
t
h(BCLK-RAD)
0ns.min
25ns.max
0ns.min
MAi
String address
Row address
t
RP*1
t
h(RAS-RAD)*1
RAS
t
h(BCLK-RAS)
0ns.min
t
d(BCLK-RAS)
25ns.max
t
d(BCLK-CAS)
25ns.max
CASL
CASH
th(BCLK-CAS)
td(BCLK-DW)
0ns.min
25ns.max
DW
DB
t
h(BCLK-DW)
t
su(DB-CAS)*1
-3ns.min
Hi-Z
t
h(BCLK-DB)
-7ns.min
*1:It depends on operation frequency.
t
t
t
h(RAS-RAD)=(tcyc/2-25)ns.min
RP=(tcyc/2 x 3-40)ns.min
su(DB-CAS)=(tcyc-40)ns.min
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.24. VCC=3V timing diagram (10)
262
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Vcc=3V
Memory expansion Mode and Microprocessor Mode
Refresh Timing (CAS before RAS refresh)
BCLK
tcyc
td(BCLK-RAS)
25ns.max
RAS
t
h(BCLK-RAS)
0ns.min
t
su(CAS-RAS)*1
CASL
CASH
t
d(BCLK-CAS)
t
h(BCLK-CAS)
0ns.min
25ns.max
DW
*1:It depends on operation frequency.
su(CAS-RAS)=(tcyc/2-25)ns.min
t
Refresh Timing (Self-refresh)
BCLK
tcyc
t
d(BCLK-RAS)
25ns.max
RAS
t
h(BCLK-RAS)
0ns.min
tsu(CAS-RAS)*1
CASL
CASH
t
h(BCLK-CAS)
0ns.min
t
d(BCLK-CAS)
25ns.max
DW
*1:It depends on operation frequency.
su(CAS-RAS)=(tcyc/2-25)ns.min
t
Measuring conditions
• VCC=3V±10%
• Input timing voltage
:Determined with VIH=1.5V, VIL=0.5V
• Output timing voltage
:Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.25. VCC=3V timing diagram (11)
263
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 3V)
VCC = 3V
t
c(TA)
t
w(TAH)
TAiIN input
tw(TAL)
t
c(UP)
tw(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
t
h(TIN–UP)
t
su(UP–TIN)
edge is selected)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
tw(TBL)
tc(AD)
t
w(ADL)
ADTRG input
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
d(C–Q)
t
su(D–C)
t
h(C–D)
tw(INL)
INTi input
tw(INH)
Figure 1.28.26. VCC=3V timing diagram (12)
264
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Tidmeveinlopgme(nVt cc = 3V)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
VCC = 3V
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
t
h(BCLK–RDY)
t
su(RDY–BCLK)
(Valid with or without wait)
BCLK
t
su(HOLD–BCLK)
t
h(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Measuring conditions :
• VCC=3V±10%
• Input timing voltage : Determined with VIH=2.4V, VIL=0.6V
• Output timing voltage : Determined with VOH=1.5V, VOL=1.5V
Figure 1.28.27. VCC=3V timing diagram (13)
265
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
Outline Performance
Table 1.29.1 shows the outline performance of the M16C/80 (flash memory version).
Table 1.29.1. Outline Performance of the M16C/80 (flash memory version)
Item
Performance
Power supply voltage
5V version:
f(XIN)=20MHz, without wait, 4.2V to 5.5V
f(XIN)=10MHz, without wait, 2.7V to 5.5V
5V version: 4.2V to 5.5 V
Program/erase voltage
f(BCLK)=12.5MHz, with one wait
f(BCLK)=6.25MHz, without wait
Flash memory operation mode
Three modes (parallel I/O, standard serial I/O, CPU rewrite)
Erase block
division
See Figure 1.29.3
User ROM area
Boot ROM area
One division (8 Kbytes) (Note 1)
In units of pages (in units of 256 bytes)
Collective erase/block erase
Program/erase control by software command
Protected for each block by lock bit
8 commands
Program method
Erase method
Program/erase control method
Protect method
Number of commands
Program/erase count
100 times
Data holding
10 years
Parallel I/O and standard serial modes are supported.
ROM code protect
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in
it when shipped from the factory. This area can be erased and programmed in only parallel
I/O mode.
266
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
The following shows Mitsubishi plans to develop a line of M16C/80 products (flash memory version).
(1) ROM capacity
(2) Package
100P6S-A ... Plastic molded QFP
100P6Q-A ... Plastic molded QFP
144P6Q-A ... Plastic molded QFP
ROM size
(Bytes)
External
ROM
M30805FGGP
M30803FGFP/GP
M30802FCGP
256K
128K
96K
M30800FCFP/GP
64K
Flash memory version
Figure 1.29.1. ROM Expansion
The following lists the M16C/80 products to be supported in the future.
Table 1.29.2. Product List
As of Aug., 2001
Remarks
Type No
M30800FCFP
ROM capacity RAM capacity
Package type
100P6S-A
100P6Q-A
128 Kbytes
256 Kbytes
10 Kbytes
20 Kbytes
M30800FCGP
M30803FGFP
M30803FGGP
M30802FCGP
M30805FGGP
100P6S-A
100P6Q-A
144P6Q-A
128 Kbytes
256 Kbytes
10 Kbytes
20 Kbytes
Type No.
M 3 0 8 0 0 M C – X X X F P
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM No.
Omitted for blank external ROM version
and flash memory version
ROM capacity:
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/80 Group
M16C Family
Figure 1.29.2. Type No., memory size, and package
267
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
Flash Memory
The M16C/80 (flash memory version) contains the flash memory that can be rewritten with a single voltage
of 5 V. For this flash memory, three flash memory modes are available in which to read, program, and
erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a
programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro-
cessing Unit (CPU). Each mode is detailed in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 1.29.3, so that memory can be erased
one block at a time. Each block has a lock bit to enable or disable execution of an erase or program
operation, allowing for data in each block to be protected.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
0FC000016
Block 6 : 64K byte
Flash memory
size
Flash memory
start address
0FD000016
0FE000016
0FF000016
Block 5 : 64K byte
Block 4 : 64K byte
Block 3 : 32K byte
0FE000016
128Kbytes
256Kbytes
0FC000016
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
0FF800016
0FFA00016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
0FFC00016
0FFFFFF16
0FFE00016
8K byte
0FFFFFF16
Boot ROM area
User ROM area
Figure 1.29.3. Block diagram of flash memory version
268
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.29.3 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.29.3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the “boot”
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, lock bit program command, and read lock status command.
269
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
CPU Rewrite Mode (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 037716) is set to “1”, transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-
dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered
address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 1.30.1 shows the flash memory control register 0 and the flash memory control register 1.
_____
Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession when NMI pin is "H" level. The bit can be set to “0” by only writing a “0” .
Bit 2 of the flash memory control register 0 is a lock bit disable bit. By setting this bit to “1”, it is possible to
disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit
only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation
is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To
set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated
only when the CPU rewrite mode select bit = “1”.
Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access
has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To
release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory to
rewrite this bit.
Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When
this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption can be
reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. Use this bit mainly in the low speed mode (when
XCIN is the block count source of BCLK).
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-
sary to set flash memory control register 1.
270
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Figure 1.30.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.30.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
037716
When reset
XX000001
2
0
R W
Bit name
Function
Bit symbol
FMR00
0: Busy (being written or erased)
1: Ready
RY/BY status flag
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
FMR01
(Software commands acceptable)
Lock bit disable bit
(Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
FMR02
FMR03
Flash memory reset bit 0: Normal operation
(Note 3)
1: Reset
Reserved bit
User ROM area select bit (
Must always be set to “0”
0: Boot ROM area is accessed
1: User ROM area is accessed
FMR05
Note 4) (Effective in only
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit. Also write to this
bit when NMI pin is "H" level.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Use the control program except in the internal flash memory for write to this bit.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
037616
When reset
XXXX0XXX
0
0
0
0
0 0 0
2
R W
Bit name
Function
Bit symbol
Reserved bit
Must always be set to “0”
0: Flash memory power supply is
connected
1: Flash memory power supply-off
FMR13
Flash memory power
supply-OFF bit (Note)
Reserved bit
Must always be set to “0”
Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Use the
control program except in the internal flash memory for write to this bit.
During parallel I/O mode,programming,erase or read of flash memory is not controlled by
this bit,only by external pins.
Figure 1.30.1. Flash memory control registers
271
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CPU Rewrite Mode (Flash Memory Version)
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Program in ROM
Program in RAM
Start
*1
(Boot mode only)
Set user ROM area select bit to “1”
Single-chip mode, memory expansion
mode, or boot mode
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
Set processor mode register (Note 1)
Transfer CPU rewrite mode control
program to internal RAM
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
*1
Write “0” to CPU rewrite mode select bit
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
End
Note 1: During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = “0” (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = “1” (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Use the program except in the internal
flash memory for write to this bit. Also write to this bit when NMI pin is "H" level.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
Figure 1.30.2. CPU rewrite mode set/reset flowchart
272
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Program in ROM
Program in RAM
Start
*1
Transfer the program to be executed in the
low speed mode, to the internal RAM.
Set flash memory power supply-OFF bit to “1”
(by writing “0” and then “1” in succession)(Note 1)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Switch the count source of BCLK.
XIN stop. (Note 2)
Process of low speed mode
*1
X
IN oscillating
Wait until the XIN has stabilized
Switch the count source of BCLK (Note 2)
Set flash memory power supply-OFF bit to “0”
Wait time until the internal circuit stabilizes
(Set NOP instruction about twice)
End
Note 1: For flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably.
Figure 1.30.3. Shifting to the low speed mode flowchart
273
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CPU Rewrite Mode (Flash Memory Version)
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Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency as shown below using the main clock division
register (address 000C16):
6.25 MHz or less when wait bit (bit 2 at address 000516) = 0 (without internal access wait state)
12.5 MHz or less when wait bit (bit 2 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
_______
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts each can
be used to change the CPU rewrite mode select bit forcibly to normal mode (FMR01="0") upon occur-
_______
rence of the interrupt. Since the rewrite operation is halted when the NMI and watchdog timer inter-
rupts occur, set the CPU rewite mode select bit to "1" and the erase/program operation needs to be
performed over again.
(4) Reset
Reset input is always accepted.
(5) Access disable
Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit
in an area other than the internal flash memory.
(6) How to access
For CPU rewrite mode select bit, lock bit disable bit, and flash memory power supply-OFF bit to be set
to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it
is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed
during the interval.
Write to the CPU rewrite mode select bit when NMI pin is "H" level.
(7)Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O
mode to rewrite these blocks.
(8)Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
274
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Software Commands
Table 1.30.1 lists the software commands available with the M16C/62A (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
Table 1.30.1. List of software commands (CPU rewrite mode)
First bus cycle
Second bus cycle
Third bus cycle
Command
Data
(D to D
Data
to D
Data
to D7)
Mode Address
Mode Address
Mode
Address
0
7)
(D
0
7
)
(D
0
(Note 6)
Read array
Write
Write
Write
Write
Write
Write
Write
Write
X
FF16
7016
5016
4116
2016
A716
7716
7116
Read status register
Clear status register
X
X
X
X
X
X
X
Read
X
SRD (Note 2)
(Note 3)
(Note 3)
WA0(Note 3)
Page program
WD0
Write
WA1
WD1
Write
Write
Write
Write
Read
BA (Note 4)
Block erase
D016
D016
Erase all unlock block
Lock bit program
Read lock bit status
X
BA
BA
D016
(Note 5)
6
D
Note 1: When a software command is input, the high-order byte of data (D
Note 2: SRD = Status Register Data
8 to D15) is ignored.
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0.
Note 6: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0–D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle, the content of the status register is
read out at the data bus (D0–D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
275
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CPU Rewrite Mode (Flash Memory Version)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Program Command (4116)
Page program allows for high-speed programming in units of 256 bytes. Page program operation
starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through
the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses
A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to
1 upon completion of the auto write operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1
when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 1.30.4 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes to the already programmed pages are prohibited.
Start
Write 4116
n = 0
Write address n and
n = n + 2
data n
NO
n = FE16
YES
NO
RY/BY status flag
= 1?
YES
Check full status
Page program
completed
Figure 1.30.4. Page program flowchart
276
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 1.30.5 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
Start
Write 2016
Write D016
Block address
NO
RY/BY status flag
= 1?
YES
Check full status check
Block erase
completed
Figure 1.30.5. Block erase flowchart
277
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CPU Rewrite Mode (Flash Memory Version)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Unlock Blocks Command (A716/D016)
By writing the command code “A716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter
how the lock bit is set. On the other hand, when the lock bit disable bit = 0, the function of the lock bit
is effective and only nonlocked blocks (where lock bit data = 1) are erased.
Lock Bit Program Command (7716/D016)
By writing the command code “7716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system sets the
lock bit for the specified block to 0 (locked).
Figure 1.30.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit
data) can be read out by a read lock bit status command.
Whether the lock bit program command is terminated can be confirmed by reading the status register
or the flash memory control register 0, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.
Start
Write 7716
Write D016
block address
NO
RY/BY status flag
= 1?
YES
NO
Lock bit program in
error
SR4 = 0?
YES
Lock bit program
completed
Figure 1.30.6. Lock bit program flowchart
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CPU Rewrite Mode (Flash Memory Version)
Read Lock Bit Status Command (7116)
By writing the command code “7116” in the first bus cycle and then the block address of a flash
memory block in the second bus cycle that follows, the system reads out the status of the lock bit of
the specified block on to the data (D6).
Figure 1.30.7 shows an example of a read lock bit program flowchart.
Start
Write 7116
Enter block address
NO
D6 = 0?
YES
Blocks locked
Blocks not locked
Figure 1.30.7. Read lock bit status flowchart
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CPU Rewrite Mode (Flash Memory Version)
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Data Protect Function (Block Lock)
Each block in Figure 1.29.3 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of
each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0’s lock bit disable bit is set.
(1) When the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status
(lock bit data). Blocks whose lock bit data = 0 are locked, so they are disabled against erase/write.
On the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/
write.
(2) When the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are
enabled for erase/write. In this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after
erasure, so that the lock bit-actuated lock is removed.
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 1.30.2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to “8016.”
Each bit in this register is explained below.
Write state machine (WSM) status (SR7)
After power-on, the write state machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device, as for output on the
____
RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon
completion of these operations.
Erase status (SR5)
The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.
280
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CPU Rewrite Mode (Flash Memory Version)
Program status (SR4)
The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status = 1, the following commands entered by command write are
not accepted.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase
(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is
entered, read array is assumed and the command that has been set up in the first bus cycle is
canceled.
Block status after program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
Table 1.30.2. Definition of each bit in status register
Definition
Each bit of
SRD
Status name
"1"
Ready
-
"0"
Busy
-
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Write state machine (WSM) status
Reserved
Erase status
Terminated normally
Terminated in error
Program status
Block status after program
Reserved
Terminated normally
Terminated in error
Terminated normally
Terminated in error
-
-
-
-
-
-
Reserved
Reserved
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program
operations. Figure 1.30.8 shows a full status check flowchart and the action to be taken when each
error occurs.
Read status register
YES
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
SR4=1 and SR5
=1 ?
Command
sequence error
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Block erase error
Program error (page
or lock bit)
Execute the read lock bit status command (7116) to
see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be used.
SR4=0?
YES
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
NO
Program error
(block)
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.
Figure 1.30.8. Full status check flowchart and remedial procedure for errors
282
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions To Inhibit Rewriting Flash Memory (Flash Memory Version)
Functions To Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM code protect function
The ROM code protect function reading out or modifying the contents of the flash memory version by
using the ROM code protect control address (0FFFFFF16) during parallel I/O mode. Figure 1.30.9 shows
the ROM code protect control address (0FFFFFF16). (This address exists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification. ROM code protect is imple-
mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
Symbol
ROMCP
Address
0FFFFFF16
When reset
FF16
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Bit symbol
Bit name
Function
Always set this bit to 1.
Reserved bit
b3 b2
ROM code protect level
2 set bit (Note 1, 2)
ROMCP2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
b5 b4
ROM code protect reset
bit (Note 3)
ROMCR
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROM code protect level
1 set bit (Note 1)
ROMCP1
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against
readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.
Figure 1.30.9. ROM code protect control address
283
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Fduenveclotpiomnenst To Inhibit Rewriting Flash Memory (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID
code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they
match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID
code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFFDF16, 0FFFFE316,
0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716, and 0FFFFFB16. Write a program which has had the
ID code preset at these addresses to the flash memory.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFFDC16 to 0FFFFDF16
0FFFFE016 to 0FFFFE316
0FFFFE416 to 0FFFFE716
0FFFFE816 to 0FFFFEB16
0FFFFEC16 to 0FFFFEF16
0FFFFF016 to 0FFFFF316
0FFFFF416 to 0FFFFF716
0FFFFF816 to 0FFFFFB16
0FFFFFC16 to 0FFFFFF16
BRK instruction vector
ID3 Address match vector
ID4
ID5 Watchdog timer vector
ID6
ID7 NMI vector
Reset vector
4 bytes
Figure 1.30.10. ID code store addresses
284
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpevpeelopnmdenitx Parallel I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
nder
U
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
In this mode, the M16C/80 (flash memory version) operates in a manner similar to the flash memory
M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not avail-
able with the microcomputer and matters related to memory capacity, the M16C/80 cannot be programed
by a programer for the flash memory.
Use an exclusive programer supporting M16C/80 (flash memory version).
Refer to the instruction manual of each programer maker for the details of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.29.3 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 1.29.3.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FFE00016 through
0FFFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, you do not need to write to the boot
ROM area.
285
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
nder
U
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Power input
Description
I/O
Apply 4.2V to 5.5V to Vcc pin and 0 V to Vss pin.
V
CC,VSS
Connect to Vcc pin.
CNVSS
CNVSS
RESET
I
I
Reset input
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
X
IN
Connect a ceramic resonator or crystal oscillator between XIN
and XOUT pins. To input an externally generated clock, input it
to XIN pin and open XOUT pin.
Clock input
I
X
OUT
Clock output
O
I
Connect this pin to Vcc or Vss.
BYTE
BYTE
Connect AVSS to Vss and AVcc to Vcc, respectively.
AVCC, AVSS
Analog power supply input
Reference voltage input
Input port P0
I
I
V
REF
Enter the reference voltage for A-D converter from this pin.
Input "H" or "L" level signal or open.
P0
P1
P2
P3
P4
0
0
0
0
0
to P0
to P1
to P2
to P3
to P4
7
7
7
7
7
I
I
I
I
I
I
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input port P1
Input port P2
Input port P3
Input port P4
P5
P56, P5
1 to P54,
Input port P5
7
Input "H" level signal.
P5
0
5
CE input
I
I
Input "L" level signal.
P5
EPM input
Input port P6
BUSY output
Input "H" or "L" level signal or open.
P6
0
to P63
I
Standard serial mode 1: BUSY signal output pin
Standard serial mode 2: Monitors the program operation check
P6
4
5
O
Standard serial mode 1: Serial clock input pin
Standard serial mode 2: Input "L" level signal.
P6
SCLK input
I
Serial data input pin
P6
6
7
RxD input
I
O
I
Serial data output pin
P6
TxD output
Input port P7
Input port P8
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P7
0
to P77
P8
P8
0
7
to P84, P86,
I
P85
NMI input
Connect this pin to Vcc.
I
Input "H" or "L" level signal or open.
P90 to P97
Input port P9
Input port P10
Input port P11
Input port P12
Input port P13
Input port P14
Input port P15
I
I
I
I
I
I
I
Input "H" or "L" level signal or open.
P10
P11
P12
P13
P14
P15
0
0
0
0
0
0
to P10
to P11
to P12
to P13
to P14
to P15
7
4
7
7
6
7
Input "H" or "L" level signal or open. (Note)
Input "H" or "L" level signal or open. (Note)
Input "H" or "L" level signal or open. (Note)
Input "H" or "L" level signal or open. (Note)
Input "H" or "L" level signal or open. (Note)
Note: Port P11 to P15 exist in 144-pin version.
286
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mode setting
Signal
CNVss
Value
Vcc
EPM
RESET
CE
Vss
Vss >> Vcc
Vcc
P9
6
/ANEX1/T
X
D4
/SDA4/SRxD
4
P10/D8
P9
5
/ANEX0/CLK
4
P11
/D9
P9
P9
P9
4
/DA
1
/TB4IN/CTS
4
/RTS
4
/SS
4
3
3
P1
2
/D10
/D11
/D12
3/DA
0
/TB3IN/CTS
3
/RTS
3
/SS
P1
P1
3
4
2/TB2IN/T
X
D
D
P9
3
/SDA
/SCL
/TB0IN/CLK
3
/SRxD
P15/D13/INT3
P9
1
/TB1IN/R
X
3
3/STxD
3
3
0
P1
6
/D14/INT4
BYTE
CNVss
P1
P2
7/D15/INT5
CNVss
RESET
0
/A
/A
/A
0
(/D
(/D
(/D
0)
1)
P8
7/XCIN
P2
1
1
P8
6
/XCOUT
P2
2
2
2)
P2
3
/A
3(/D
3)
RESET
P2
4
/A
4
(/D
4
)
X
V
OUT
M16C/80(100-pin) Group
Flash Memory Version
(100P6S)
P2
5
/A
6
5
(/D5
6
)
6
SS
P2
P2
Vss
P3 /A
Vcc
P3 /A
/A
7
(/D
7
)
X
IN
7
/A
(/D
)
V
CC
P8
P8
P8
P8
/TA4IN/U
/TA4OUT/U
P7 /TA3IN
P7 /TA3OUT
P7 /TA2IN/W
P7 /TA2OUT/W
/RTS /TA1IN/V
/CLK /TA1OUT/V
/SCL /TA0IN/TB5IN
/T /SDA /TA0OUT
5
/NMI
/INT
/INT
/INT
0
8
(MA0)(/D
8)
4
2
3
1
2
0
1
9
(MA1)(/D9)
P3
P3
2
/A10(MA2)(/D10
/A11(MA3)(/D11
)
)
)
)
)
)
P8
P8
1
0
3
P3
4
/A12(MA4)(/D12
/A13(MA5)(/D13
7
P3
5
6
P3
P3
P4
6
/A14(MA6)(/D14
5
7
/A15(MA7)(/D15
0
4
/A16(MA8)
P7
3
/CTS
P7
/RxD
P7
2
2
P41/A17(MA9)
P4
2
2
2
/A18(MA10)
P7
1
2
2
P4
3/A19(MA11)
0
X
D
2
2
Figure 1.31.1. Pin connections for standard serial I/O mode (1)
287
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mode setting
Signal
CNVss
Value
Vcc
EPM
Vss
RESET
CE
Vss >> Vcc
Vcc
P9
P9
P9
P9
4
/DA
/DA
/TB2IN/TxD
/TB1IN/RxD
P9
1
/TB4IN/CTS
/TB3IN/CTS
/SDA
/SCL
/TB0IN/CLK
4
/RTS
/RTS
/SRxD
4
/SS
3
4
P13/D11
3
0
3
3/SS
P1
P1
P1
4
/D12
/D13/INT3
2
3
3
3
5
1
3
3
/STxD
3
3
6
/D14/INT4
0
P1
P2
P2
7/D15/INT5
BYTE
CNVss
0
/A
/A
/A
/A
/A
0
1
2
3
4
(/D
(/D
(/D
(/D
(/D
0
)
)
1
1
CNVSS
RESET
P87/XCIN
P22
P23
P24
P25
2
)
)
)
P8
6/XCOUT
3
4
RESET
XOUT
/A
/A
/A
5
(/D
(/D
(/D
5)
6
M16C/80(100-pin) Group
Flash Memory Version
(100P6Q)
VSS
P2
P2
6
6
)
XIN
7
7
8
7
)
VCC
Vss
P3
Vcc
P3
P3
P85/NMI
0
/A
(MA0)(/D8)
P8
4
/INT2
/INT1
/INT0
1
/A
/A10(MA2)(/D10
/A11(MA3)(/D11
/A12(MA4)(/D12
9(MA1)(/D9)
P8
3
2
2
)
)
)
)
)
P8
P3
3
P8
P8 /TA4OUT/U
P7 /TA3IN
P7 /TA3OUT
P7 /TA2IN/W
P7 /TA2OUT/W
/RTS /TA1IN/V
1/TA4IN/U
P3
4
0
P35
P36
P37
/A13(MA5)(/D13
/A14(MA6)(/D14
/A15(MA7)(/D15
7
6
)
5
P4
P4
0
1
/A16(MA8)
/A17(MA9)
4
P73
/CTS
2
2
Figure 1.31.2. Pin connections for standard serial I/O mode (2)
288
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mode setting
Signal
CNVss
EPM
Value
Vcc
Vss
RESET
CE
Vss >> Vcc
Vcc
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
108 107 106 105 104 103 102 101 100
P44/CS3/A20(MA12)
P1
P0
P0
P0
P0
P11
P11
P11
P11
P11
P0 /D
P0 /D
P0 /D
P0 /D
P15
P15
P15
P15
P15
P15
P15
0
/D
/D
/D
/D
/D
8
109
110
72
71
P45/CS2/A21
7
7
P4
P4
6/CS1/A22
6
6
111
112
70
69
7/CS0/A23
5
5
4
4
P12
P12
P12
P5 /WRL/WR/CASL
P5
5
113
68
67
4
6
114
115
3
7
66
65
2
0
116
117
CE
1
64
1/WRH/BHE/CASH
0
P5
P5
2/RD/DW
118
119
63
62
3
3
3/BCLK/ALE/CLKOUT
2
2
P130
120
121
61
60
1
1
P131
0
0
VCC
122
123
59
58
7
P132
M16C/80(144-pin) Group
Flash Memory Version
(144P6Q)
6
124
VSS
57
56
5
P13
P5 /HLDA/ALE
P5
3
125
126
4
4
55
54
3
5/HOLD
EPM
127
128
2
P56/ALE/RAS
53
1
P57/RDY
129
130
52
51
VSS
P13
P13
P13
P13
P6 /CTS
P6 /CLK
P6 /R
P6 /T
P6 /CTS
P6 /CLK
4
P150
5
131
132
50
49
VCC
6
P10
P10
P10
P10
7
/AN7/KI3
7
133
134
48
47
6
/AN6/KI2
0
0/RTS0
5
/AN5/KI1
135
1
0
46
45
4
/AN
4
/KI0
/AN
/AN
/AN
AVSS
/AN
2
XD0
136
137
P10
P10
P10
3
3
3
XD0
44
43
2
2
4
1/RTS1/CTS0/CLKS1
138
139
BUSY
1
1
5
1
42
SCLK
RxD
TxD
VSS
140
141
41
40
P100
0
P66/RXD1
V
REF
AVCC
/ADTRG/R
SCL /STxD
V
CC
142
143
39
38
P6
7/T
X
D
1
P97
XD4/
P7
0/T
XD2/SDA2/TA0OUT
144
37
4
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VCC
VSS
Connect
oscillation
circuit
Figure 1.31.3. Pin connections for standard serial I/O mode (3)
289
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
_____
________
leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H"
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 1.31.1 and 1.31.3 show the pin connections for the standard
serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/
O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level
of CLK1 pin when the reset is released.
To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset.
The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer
clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The
RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.
To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the
reset. The operation uses the two UART1 pins RxD1 and TxD1.
In the standard serial I/O mode, only the user ROM area indicated in Figure 1.31.20 can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
290
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1).
Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level.
In reception, software commands, addresses and program data are synchronized with the rise of the trans-
fer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the
read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin.
The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first.
When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is
"H" level. Accordingly, always start the next transfer after the RST1 (BUSY) pin is "L" level.
Also, data and status registers in memory can be read after inputting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained software commands, status
registers, etc.
291
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Software Commands
Table 1.31.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Software commands are
explained here below.
Table 1.31.1. Software commands (Standard serial I/O mode 1)
1st byte
transfer
When ID is
not verified
Not
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Address Address
(middle) (high)
Data
output
Data
output output
Data
Data
output to
259th byte
1
2
FF16
4116
acceptable
Address Address
(middle) (high)
Data
input
Data
input
Data
input
Data input
to 259th
byte
Not
acceptable
Page program
Address Address
D016
Not
acceptable
Not
acceptable
Acceptable
3
4
5
6
7
Block erase
2016
A716
7016
5016
7116
(middle)
(high)
D016
Erase all unlocked blocks
Read status register
Clear status register
Read lock bit status
SRD
output
SRD1
output
Not
acceptable
Not
Address Address Lock bit
(middle)
(high)
data
output
acceptable
Address Address
(middle) (high)
D016
Not
acceptable
Not
acceptable
Not
8
9
Lock bit program
Lock bit enable
7716
7A16
7516
F516
FA16
10 Lock bit disable
acceptable
Address Address Address
11 Code processing function
12 Download function
ID size
ID1
To
To ID7
Acceptable
(low)
(middle)
Size
(high)
Check-
sum
Not
acceptable
Size (low)
(high)
Data required
input number
of times
Version
data
output
Version Version Version Version
Version
data
output to
9th byte
Data
output to
259th
byte
13 Version data output function
FB16
FC16
FD16
data
output
data
output
data
output output
data
Acceptable
Address Address
(middle)
Data
output
Data
output output
Data
Not
acceptable
14 Boot ROM area output
function
(high)
Check
data (low)
Check
data
(high)
Not
acceptable
15 Read check data
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register data1 .
Note 3:All commands can be accepted when the flash memory is totally blank.
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Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK1
A8 to
A15
A16 to
A23
RxD1
(M16C reception data)
FF16
TxD1
(M16C transmit data)
data0
data255
RTS1(BUSY)
Figure 1.31.4. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
CLK1
RxD1
7016
(M16C reception data)
SRD
output
SRD1
output
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.5. Timing for reading the status register
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the
“L” level.
CLK1
RxD1
5016
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.6. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
–D ) for the page (256 bytes) specified with addresses
7
A
8
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
CLK1
RxD1
(M16C reception data)
A8 to A16 to
A15 A23
4116
data0
data255
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.7. Timing for the page program
294
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
CLK1
RxD1
(M16C reception data)
A8 to
A15
A16 to
A23
2016
D016
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.8. Timing for block erasing
295
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register. Each block can be erase-protected with the
lock bit. For more information, see the section on the data protection function.
CLK1
RxD1
(M16C reception data)
A716
D016
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.9. Timing for erasing all unlocked blocks
Lock Bit Program Command
This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, reset proce-
dure and so on, see the section on the data protection function.
CLK1
RxD1
(M16C reception data)
A8 to
A15
A16 to
A23
7716
D016
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.10. Timing for the lock bit program
296
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Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The 6th bit (D6) of output data
is the lock bit data. Write the highest address of the specified block for addresses A8 to A23.
CLK1
A8 to
A15
A16 to
A23
RxD1
(M16C reception data)
7116
TxD1
(M16C transmit data)
DQ6
RTS1(BUSY)
Figure 1.31.11. Timing for reading lock bit status
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
CLK1
RxD1
7A16
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.12. Timing for enabling the lock bit
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Preliminary Specifications REV.D
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Lock Bit Disable Command
This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
CLK1
RxD1
7516
(M16C reception data)
TxD1
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.13. Timing for disabling the lock bit
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK1
Program
data
RxD1
(M16C reception data)
Check
sum
Program
data
FA16
Data size (low)
TxD1
Data size (high)
(M16C transmit data)
RTS1(BUSY)
Figure 1.31.14. Timing for download
298
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Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK1
RxD1
FB16
(M16C reception data)
TxD1
(M16C transmit data)
'V'
'E'
'R'
'X'
RTS1(BUSY)
Figure 1.31.15. Timing for version information output
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK1
RxD1
(M16C reception data)
A
8
to
A
16 to
FC16
A
15
A23
TxD1
(M16C transmit data)
data0
data255
RTS1(BUSY)
Figure 1.31.16. Timing for boot ROM area output
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK1
RxD1
ID size
ID1
ID7
F516
DF16
FF16
0F16
(M16C reception
data)
TxD1
(M16C transmit
data)
RTS1(BUSY)
Figure 1.31.17. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFFDC16 to 0FFFFDF16
0FFFFE016 to 0FFFFE316
0FFFFE416 to 0FFFFE716
0FFFFE816 to 0FFFFEB16
0FFFFEC16 to 0FFFFEF16
0FFFFF016 to 0FFFFF316
0FFFFF416 to 0FFFFF716
0FFFFF816 to 0FFFFFB16
0FFFFFC16 to 0FFFFFF16
BRK instruction vector
ID3 Address match vector
ID4
ID5 Watchdog timer vector
ID6
ID7 NMI vector
Reset vector
4 bytes
Figure 1.31.18. ID code storage addresses
300
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Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Read Check Data
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.
CLK1
RxD1
FD16
(M16C reception data)
TxD1
(M16C transmit data)
Check data (high)
Check data (low)
RTS1(BUSY)
Figure 1.31.19. Timing for the read check data
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Data Protection (Block Lock)
Each of the blocks in Figure 1.31.20 have a nonvolatile lock bit that specifies protection (block lock)
against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command.
Also, the lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable and lock enable bit commands.
(1) After the reset has been cancelled and the lock bit enable command executed, the specified block
can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked
and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked
and can be erased or written in.
(2) After the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that was “0” before the block
was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the
lock bit.
0FC000016
Block 6 : 64K byte
0FD000016
Block 5 : 64K byte
0FE000016
Block 4 : 64K byte
0FF000016
Block 3 : 32K byte
Flash memory
start address
Flash memory
size
0FF800016
0FFA00016
128 Kbytes
256 Kbytes
0FE000016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
0FC000016
0FFC00016
0FFFFFF16
User ROM area
Figure 1.31.20. Blocks in the user area
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.31.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table 1.31.2. Status register (SRD)
Definition
SRD0 bits
Status name
"1"
"0"
Write state machine (WSM) status
Reserved
Ready
Busy
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
-
-
Erase status
Terminated in error
Terminated normally
Program status
Block status after program
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
Reserved
Reserved
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
Program Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.
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Adpepveelopnmdeinxt Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
Under
M16C/80 group
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.31.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON
and the flag status is maintained even after the reset.
Table 1.31.3. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
"1"
"0"
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Not update
Update completed
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Mismatch
Match
00
01
10
11
Not verified
Verification mismatch
Reserved
Verified
SR9 (bit1)
SR8 (bit0)
Data receive time out
Reserved
Normal operation
-
Time out
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
304
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Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure
1.31.21 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
YES
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
SR4=1 and SR5
=1 ?
Command
sequence error
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Block erase error
Program error (page
or lock bit)
Execute the read lock bit status command (7116) to
see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be used.
SR4=0?
YES
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
NO
Program error
(block)
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock
blocks and lock bit program commands is accepted. Execute the clear status register command
(5016) before executing these commands.
Figure 1.31.21. Full status check flowchart and remedial procedure for errors
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for
more information.
Clock input
CLK1
BUSY output
Data input
RTS1(BUSY)
R
XD1
T
XD1
Data output
M16C/80 Flash
memory version
CNVss
NMI
P5
0
5
(CE)
P5
(EPM)
(1) Control pins and external circuitry will vary according to peripheral unit (programmer). For more
information, see the peripheral unit (programmer) manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
Figure 1.31.22. Example circuit application for the standard serial I/O mode 1
305
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Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1).
Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level.
The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.
After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-
ure 1.31.23) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz
input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400, 57,600 or
115,200 bps by executing software commands. However, communication errors may occur because of the
oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and
the baud rate.
After executing commands from a peripheral unit that requires time to erase and write data, as with erase
and program commands, allow a sufficient time interval or execute the read status command and check
how processing ended, before executing the next command.
Data and status registers in memory can be read after transmitting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained initial communications with
peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-
quency of the main clock, by sending the code as prescribed by the protocol for initial communications
with peripheral units (Figure 1.31.23).
(1) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit
rate generator so that "0016" can be successfully received.)
(2) The MCU with internal flash memory outputs the "B016" check code and initial communications end
1
successfully * . Initial communications must be transmitted at a speed of 9,600 bps and a transfer
interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.
*1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main
clock.
MCU with internal
Peripheral unit
flash memory
Reset
(1) Transfer "0016" 16 times
"0016
"
"
1st
At least 15ms
transfer interval
2nd
"0016
"0016
"
"
15 th
16th
"0016
"B016
"
(2) Transfer check code "B016"
The bit rate generator setting completes (9600bps)
Figure 1.31.23. Peripheral unit and initial communication
306
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Mitsubishi Microcomputers
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
How frequency is identified
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the
bit rate generator is set to match the operating frequency (2 - 20 MHz). The highest speed is taken from
the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit
rate generator value for a baud rate of 9,600 bps.
Baud rate cannot be attained with some operating frequencies. Table 1.31.4 gives the operation fre-
quency and the baud rate that can be attained for.
Table 1.31.4 Operation frequency and the baud rate
Operation frequency
(MH
Baud rate
9,600bps
Baud rate
19,200bps
Baud rate
38,400bps
Baud rate
57,600bps
Baud rate
115,200bps
Z)
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
–
–
–
–
–
–
–
–
–
–
–
–
–
–
√
√
√
√
√
√
√
√
√
√
√
√
√
√
–
√
√
√
√
√
√
√
–
–
√
–
–
√
–
–
20MHz
√
√
√
√
√
√
√
√
√
√
√
–
√
√
–
16MH
12MH
11MH
10MH
Z
Z
Z
Z
8MH
Z
7.3728MH
Z
6MH
Z
Z
5MH
4.5MH
4.194304MH
4MH
3.58MH
Z
Z
Z
Z
3MH
Z
Z
2MH
: Communications possible
– : Communications not possible
√
307
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.31.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2
adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft-
ware commands of standard serial I/O mode 1. Software commands are explained here below.
Table 1.31.5. Software commands (Standard serial I/O mode 2)
1st byte
transfer
When ID is
not verified
Not
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Address Address
(middle) (high)
Data
output
Data
output output
Data
Data
output to
259th byte
Data input
to 259th
byte
1
2
FF16
4116
acceptable
Address Address
(middle) (high)
Data
input
Data
input
Data
input
Not
acceptable
Page program
Address Address
D016
Not
acceptable
Not
acceptable
Acceptable
3
4
5
6
7
Block erase
2016
A716
7016
5016
7116
(middle)
D016
(high)
Erase all unlocked blocks
Read status register
Clear status register
Read lock bit status
SRD
output
SRD1
output
Not
acceptable
Not
acceptable
Address Address Lock bit
(middle)
(high)
data
output
D016
Address Address
(middle) (high)
Not
acceptable
Not
acceptable
Not
8
9
Lock bit program
Lock bit enable
7716
7A16
7516
F516
FA16
10 Lock bit disable
acceptable
Address Address Address
11 Code processing function
12 Download function
ID size
ID1
To
To ID7
Acceptable
(low)
(middle)
Size
(high)
Check-
sum
Not
acceptable
Size (low)
(high)
Data required
input number
of times
Version
data
output
Version Version Version Version
Version
data
output to
9th byte
Data
output to
259th byte
13 Version data output function
FB16
data
output
data
output
data
output output
data
Acceptable
Address Address
(middle)
Data
output
Data
output output
Data
Not
acceptable
14 Boot ROM area output
function
FC16
FD16
(high)
Check
data (low)
Check
data
(high)
Not
acceptable
15 Read check data
16 Baud rate 9600
17 Baud rate 19200
18 Baud rate 38400
19 Baud rate 57600
20 Baud rate 115200
Acceptable
Acceptable
Acceptable
Acceptable
Acceptable
B016
B116
B216
B316
B416
B016
B116
B216
B316
B416
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register data 1.
Note 3:All commands can be accepted when the flash memory is totally blank.
308
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
A8 to
A15
A16 to
A23
RxD1
(M16C reception data)
FF16
TxD1
(M16C transmit data)
data0
data255
Figure 1.31.24. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
RxD1
7016
(M16C reception data)
SRD
output
SRD1
output
TxD1
(M16C transmit data)
Figure 1.31.25. Timing for reading the status register
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
RxD1
5016
(M16C reception data)
TxD1
(M16C transmit data)
Figure 1.31.26. Timing for clearing the status register
309
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
–D ) for the page (256 bytes) specified with addresses
7
A
8
The result of the page program can be known by reading the status register. For more information,
see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
RxD1
(M16C reception data)
A8 to A16 to
A15 A23
4116
data0
data255
TxD1
(M16C transmit data)
Figure 1.31.27. Timing for the page program
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A16 to A23.
After block erase ends, the result of the block erase operation can be known by reading the status
register. For more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
RxD1
(M16C reception data)
A8 to
A15
A16 to
A23
2016
D016
TxD1
(M16C transmit data)
Figure 1.31.28. Timing for block erasing
310
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
The result of the erase operation can be known by reading the status register. Each block can be erase-
protected with the lock bit. For more information, see the section on the data protection function.
RxD1
(M16C reception data)
A716
D016
TxD1
(M16C transmit data)
Figure 1.31.29. Timing for erasing all unlocked blocks
Lock Bit Program Command
This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the “7716” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
Lock bit status can be read with the read lock bit status command. For information on the lock bit
function, reset procedure and so on, see the section on the data protection function.
RxD1
(M16C reception data)
A
8
to
A
16 to
7716
D016
A
15
A23
TxD1
(M16C transmit data)
Figure 1.31.30. Timing for the lock bit program
311
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of
the specified block for addresses A8 to A23.
A
8
to
A16 to
A23
RxD1
(M16C reception data)
7116
A
15
TxD1
(M16C transmit data)
DQ6
Figure 1.31.31. Timing for reading lock bit status
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code “7A16” is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
RxD1
7A16
(M16C reception data)
TxD1
(M16C transmit data)
Figure 1.31.32. Timing for enabling the lock bit
312
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Lock Bit Disable Command
This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, “0” (locked)
lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
RxD1
7516
(M16C reception data)
TxD1
(M16C transmit data)
Figure 1.31.33. Timing for disabling the lock bit
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
Program
data
RxD1
(M16C reception data)
Check
sum
Program
data
FA16
Data size (low)
TxD1
Data size (high)
(M16C transmit data)
Figure 1.31.34. Timing for download
313
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
RxD1
FB16
(M16C reception data)
TxD1
(M16C transmit data)
'V'
'E'
'R'
'X'
Figure 1.31.35. Timing for version information output
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
RxD1
(M16C reception data)
A
8
to
A16 to
A23
FC16
A
15
TxD1
(M16C transmit data)
data0
data255
Figure 1.31.36. Timing for boot ROM area output
314
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD1
ID size
ID1
ID7
F516
DF16
FF16
0F16
(M16C reception
data)
TxD1
(M16C transmit
data)
Figure 1.31.37. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFFDF16, 0FFFFE316, 0FFFFEB16, 0FFFFEF16, 0FFFFF316, 0FFFFF716 and
0FFFFFB16. Write a program into the flash memory, which already has the ID code set for these
addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFFDC16 to 0FFFFDF16
0FFFFE016 to 0FFFFE316
0FFFFE416 to 0FFFFE716
0FFFFE816 to 0FFFFEB16
0FFFFEC16 to 0FFFFEF16
0FFFFF016 to 0FFFFF316
0FFFFF416 to 0FFFFF716
0FFFFF816 to 0FFFFFB16
0FFFFFC16 to 0FFFFFF16
BRK instruction vector
ID3 Address match vector
ID4
ID5 Watchdog timer vector
ID6
ID7 NMI vector
Reset vector
4 bytes
Figure 1.31.38. ID code storage addresses
315
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Check Data
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.
RxD1
FD16
(M16C reception data)
TxD1
(M16C transmit data)
Check data (high)
Check data (low)
Figure 1.31.39. Timing for the read check data
Baud Rate 9600
This command changes baud rate to 9,600 bps. Execute it as follows.
(1) Transfer the "B016" command code with the 1st byte.
(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD1
B016
(M16C reception data)
TxD1
B016
(M16C transmit data)
Figure 1.31.40. Timing of baud rate 9600
316
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Baud Rate 19200
This command changes baud rate to 19,200 bps. Execute it as follows.
(1) Transfer the "B116" command code with the 1st byte.
(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD1
B116
(M16C reception data)
TxD1
B116
(M16C transmit data)
Figure 1.31.41. Timing of baud rate 19200
Baud Rate 38400
This command changes baud rate to 38,400 bps. Execute it as follows.
(1) Transfer the "B216" command code with the 1st byte.
(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD1
B216
(M16C reception data)
TxD1
B216
(M16C transmit data)
Figure 1.31.42. Timing of baud rate 38400
Baud Rate 57600
This command changes baud rate to 57,600 bps. Execute it as follows.
(1) Transfer the "B316" command code with the 1st byte.
(2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD1
B316
(M16C reception data)
TxD1
B316
(M16C transmit data)
Figure 1.31.43. Timing of baud rate 57600
317
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Adpepveelonpmdeinxt Standard Serial I/O Mode 2 (Flash Memory Version)
Mitsubishi Microcomputers
Under
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Baud Rate 115200
This command changes baud rate to 115,200 bps. Execute it as follows.
(1) Transfer the "B416" command code with the 1st byte.
(2) After the "B416" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD1
B416
(M16C reception data)
TxD1
B416
(M16C transmit data)
Figure 1.31.44. Timing of baud rate 115200
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK1
RTS1(BUSY)
D1
Monitor output
Data input
R
X
T
XD1
Data output
M16C/80 Flash
memory version
CNVss
NMI
P5
0(CE)
P5
5(EPM)
(1) In this example, the microprocessor mode and standard serial I/O
mode are switched via a switch.
Figure 1.31.45. Example circuit application for the standard serial I/O mode 2
318
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix External ROM version with built-in boot loader
Description
External ROM version of M16C/80 is available with built-in boot loader (firmware). By using the boot loader,
users can download their rewrite program of Flash memory to the internal RAM. When using Mitsubishi
Flash memory*, reprogramming of the external Flash memory can be done without downloading the rewrite
program.
For more detail, please refer to the "Volume Boot Loader" in the application note of M16C/80 external ROM
version.
*: M5M29GB/T160BVP, M5M29GB/T320BVP and the equivalent of these.
The following shows Mitsubishi plans to develop a line of M16C/80 products with built-in boot loader.
(1) ROM capacity
(2) Package
100P6S-A ... Plastic molded QFP
100P6Q-A ... Plastic molded QFP
144P6Q-A ... Plastic molded QFP
ROM size
(Bytes)
M30805SGP-BL
External
ROM
M30803SFP/GP-BL
M30802SGP-BL
M30800SFP/GP-BL
256K
128K
External ROM version
Figure 1.32.1. ROM Expansion
The following lists the M16C/80 products to be supported in the future.
Table 1.32.1. Product List
As of Aug., 2001
Remarks
Type No
ROM capacity RAM capacity
10 Kbytes
Package type
M30800SFP-BL
100P6S-A
100P6Q-A
144P6Q-A
External ROM version
with built-in boot loader
*
M30800SGP-BL
*
M30802SGP-BL
*
M30803SFP-BL
100P6S-A
100P6Q-A
24 Kbytes
*
M30803SGP-BL
*
M30805SGP-BL
144P6Q-A
*
*
: New product
319
Preliminary Specifications REV.D
Mitsubishi Microcomputers
Under
Specifications in this manual are tentative and subject to change.
Adpepveelopnmdenitx External ROM version with built-in boot loader
M16C/80 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Type No.
M 3 0 8 0 2 M C – X X X G P – BL
Boot loader
Package type:
FP : Package 100P6S-A
GP : Package 100P6Q-A, 144P6Q-A
ROM No.
Omitted for blank external ROM version
and flash memory version
ROM capacity:
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/80 Group
M16C Family
Figure 1.32.2. Type No., memory size, and package
320
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
M
D
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I
2
–
–
–
Detail F
y
M
M
D
E
–
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
Weight(g)
0.63
Lead Material
Cu Alloy
MD
LQFP100-P-1414-0.50
–
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A1
0
0.1
A
2
–
1.4
b
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
c
D
E
e
25
51
H
H
L
D
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
L
M
b2
0.225
–
14.4
14.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
321
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MMP
144P6Q-A
Plastic 144pin 20✕20mm body LQFP
EIAJ Package Code
JEDEC Code
Weight(g)
1.23
Lead Material
Cu Alloy
M
D
LQFP144-P-2020-0.50
–
HD
D
144
109
l2
1
108
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
1
0.05
–
0.125
1.4
A2
b
0.17
0.105
19.9
19.9
–
0.22
0.125
20.0
20.0
0.5
0.27
0.175
20.1
20.1
–
c
D
E
e
36
73
H
H
L
D
21.8
21.8
0.35
–
0.45
–
–
–
0°
22.0
22.0
0.5
1.0
0.6
0.25
–
–
22.2
22.2
0.65
–
0.75
–
0.08
0.1
8°
E
37
72
A
L1
L1
F
Lp
A3
x
e
y
–
b
2
–
0.95
–
0.225
–
20.4
20.4
–
–
–
–
b
L
y
x
M
I
2
Lp
Detail F
M
M
D
E
–
322
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision History
Revision
date
Version
Contents for change
1 M byte --> 16 M bytes
REV.B • Page 1 line 5
• Page 1 line 15
'98. 10.19
10 MHz with software one wait --> 10 MHz : under planning
• Page 1 line 16
35 mW (f(XIN)=20MHz, without software wait, Vcc=5V; M30800MC-
XXXFP target value ) --> 45 mA (M30800MC-XXXFP)
• Page 1
X-Y converter ---- 1 circuit Addition
• Page 4 line 28
35 mA --> 45 mA
• Page 6 figure 1.1.4
• Page 18 figure 1.5.4 and corresponding pages
(106) Peripheral subfunction select register --> Function select register C
(107) Port function select register 0 --> Function select register A0
(108) Port function select register 1 --> Function select register A1
(109) Peripheral function select register 0 --> Function select register B0
(110) Peripheral function select register 1 --> Function select register B1
(111) Port function select register 2 --> Function select register A2
(112) Port function select register 3 --> Function select register A3
(113) Peripheral function select register 2 --> Function select register B2
• Page 21 figure 1.6.3
• Page 24 figure 1.8.1
Register name change same as figure 1.5.4
Processor mode register 0
Note 6 --> Note 7, Note 6 Addition
Processor mode register 1 Note 3
• Page 31 line 4
Addition: The ALE signal is occurred regardless of internal area and external area.
__
_____
• Page 31 table 1.10.4, Page 33 table 1.10.5
R/W --> RD/_W___R__
• Page 42 table 1.11.4
System clock control register 0 Note 2
• Page 51 line 7, table 1.15.1
port function select register 3 (address 03B516) --> port function select register 3 (ad-
dress 03B516) and D-A control register (address 039C16)
• Page 60 line 3
level and input signal edge.
• Page 65 line 10 Set register --> When writing to DCT2, DCT3, DRC2, DRC3, DMA2 and
DMA3, set register
• Page 67 table 1.20.2
the interrupt occurs. --> the interrupt can be set to occur on input signal
Addition: Note 5
• Page 86 line 1
• Page 93 line 16
successively when --> successively two times when
Count source input --> Count source input (Set the corresponding func-
tion select register A to I/O port.)
• Page 114 table 1.25.6, page 122 table 1.26.1
UARTi transmit/receive mode register
UARTi transmit/receive mode register
Addition: Note 2
Addition: Note 3
• Page 115 table 1.25.7
UARTi transmit/receive mode register 0 Delate: Note 3
• Page 120 line 13 Addition: -Set the corresponding function select register A to I/O port
• Page 123 table 1.26.3
• Page 130 table 1.27.3
• Page 139 figure 1.29.2
• Page 142 line 2
062316 --> 032616
• Page 144 table 1.29.5
• Page 156 table 1.31.2
• Page 164 figure 1.34.2
D-A control register (Note) Addition: Note
____
16-bit bus mode A9 --> A9
• Page 165 line 5
f32 --> BCLK(frequency x 32)
323
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
• Page 165 figure 1.34.3
• Page 169
operation clock --> BCLK
REV.B
'98.10.19
they function as output regardless of the contents of the direction registers. When pins
are to be used as the outputs for the D-A converter, do not set the direction registers to
output mode.
-->
set the corresponding function select registers A, B and C. When pins are to be used
as the outputs for the D-A converter, set the function select register of each pin to I/O
port, and set the direction registers to input mode.
Table 1.35.1 lists each port and peripheral function.
REV.C
'98.3.2
All page
Page 2 Figure 1
Page 3 Figure 3
M30800MC-XXXFP --> M16C/80 (100-pin version) group
changed, GP package is added
Note 1 and Note 2 is added
Page 5 Figure 4, Table 2 New type no. is added
Page 6 Figure 5
Page 10 Line 2
GP is added
18 registers --> 28 registers
Page 11 (7) Set USP and ISP to an even number so that execution efficiency is increased.
--> added
Page 17 Figure 11 (54) UART4 special mode register 3 --> added
Page 18 Figure 12
UART3 special mode register 3 --> added
UART2 special mode register 3 --> added
Function select register B3 --> added
Page 20 Figure 14
UART4 special mode register 3 --> added
UART3 special mode register 3 --> added
UART2 special mode register 3 --> added
Page 21 Figure 15 Function select register B3 --> added
Page 24 Figure 23 PM1 Note 4 -->added
Page 31 Figure 26
Page 45 Table 14, Page 46 Table 15
Note --> added
Page 50 Figure 32-4
Page 51 Line 6
Changed
port function select register 3 --> function select register A3
FFFFE416 to FFFFE716 are all --> FFFFE716 is
Page 52 Line 17
Page 53 Table 17 BRK instruction
If the vector is --> If the contents of FFFFE716 is
Page 53 Table 18 Instruction fetch and DBC --> delated
Page 58 Figure 36 IPL --> RLVL
Page 61 Figure 38 004D16 --> 009316
Page 67 Figure 44-1Note 3 and 6 --> added
Page 68 Figure 45 memory --> memory (forward direction)
Page 70 Figure 46-2DMAi memory address reload register Note:
vector register (SVP) --> save PC register (SVP)
Page 84 Figure 56 Note 4 addresses 034216 and 034316 --> address 034316
Page 93 Table 30 Count source: TBj overflow --> added
Page 96 Figure 69
Three-phase PWM control register 0 Note 4:both bit 0 and 1 --> bit 1
324
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
REV.C
Contents for change
'98.3.2
Three-phase PWM control register 1
Page 100 Line 1 In three-phase --> In "L" active output polarity in three-phase
Page 100 Line 26,31
the state of set by port direction register --> the high-impedance state
Page 101 Figure 73 Right: INV14 --> added
Page 103 Figure 74
Page 108 Table 32 UART4 LSB first/MSB first selection : Note 1 --> Note 2
Page 118 Figure 83 UART transmit/receive control register 2
Page 119 Figure
Page 126 Line 3
UART 3,4 special mode register 3 --> added
CLK and CLKS select bit (bits 4 and 5 at address 037016) -->
port function select register (bits of related to-P64 and P65)
Page 145
Page 176 Table 124P91: STxD3 output --> added
P97: STxD4 output --> added
Page 178 Figure 125-2
Page 179 Figure 125-3
Page 180 Figure 125-4
Function select register A3
Function select register B0
Function select register B3
Page 187 A-D Converter (5)
Page 188
DMAC
Page1
Supply voltage 4.0V-5.5V, Mask ROM version is added.
'98.4.12
Page 5 Table 1.1.1 DMAC 2 channels --> 4 channels
Page 8
Page 9
P0 description is changed
P6 description is changed
P7, 8, 9, 10 equivalent to P0 --> P6
Page 10 Figure 1.2.1
Page 18 Figure 1.4.3
Page 19 Figure 1.4.4
Page 20 Figure 1.5.1
M30800FC, M30803FG are added.
(15) DRAM control register 0XXX0000 --> ?XXX????
Delate Note, (143)-(147) 00 --> ??
Add Note
Page 25 Figure 1.6.1 Processor mode register 1
When reset 0016 --> C016
Page 30 Line 15
... output to A9 to A20 --> A8 to A20
Page 32 Figure 1.7.2
Page 35 (8) BCLK output
Page 38 Figure 1.7.6
Page 39 Figure 1.7.7
Page 40 Figure 1.8.1 and 1.8.2
Page 42
Note
Page 43 Figure 1.8.4
Page 44 Figure 1.8.5
Page 45
Note 2, Line 6 Pin outputs "L" is delated.
Page 47 Line 15
... as BCLK --> as BCLK from the interrupt routine
Table 1.8.3
Page 48 Status Transition of BCLK
Page 51 Figure 1.8.7
Page 52 Line 6, Figure 1.8.6
Page 56 Line 14
Delate D-A control register
325
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
REV.C Page 58 Table 1.9.3Software interrupt number 40,41, Add fault error, Add Note 2
Page 59 Interrupt control register Line 4 delate
Page 64 Interrupt sequence (1)
Page 66 Saving registers Last line added
Page 67 Interrupt Priority *1 delated, Last line added
Page 72 (2) Setting the stack pointer Last line added
Page 74 Watchdog timer Line 2
A watchdog timer interrupt is generated when --> Whether a watchdog timer interrupt
is generated or reset is selected when
Last part :Watchdog timer function select bit is initialized only at reset. After reset,
watchdog timer interrupt is selected. added
Page 75 Figure 75 System clock control register 0 added
Page 97 Figure 1.13.9
Page 181 Figure 1.25.4
Page 182 Figure 1.25.5
Count value
Page 131 Figure 1.16.12 Both register Note2 added
Page 135 Table 1.17.3
Page 132 Table 1.18.3
Page 147 Figure 1.19.1
RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ...
RxDi bit 1 and 6 at address 03C716 --> bit 1 and 7 ...
Upper figure changed, note added
Page 153
Bit 4 overflow --> underflow
Page 154 Figure 1.20.3
overflow --> underflow
Page 159 Clock phase setting
UARTi transmission-reception control register 0 ..., whereas UARTi special mode
register 3 ... --> Bit 6 of UARTi transmission-reception control register 0 ..., whereas
bit 1 of UARTi special mode register 3 ...
Line 15
... output is high impedance. --> ... output is indeterminate.
Page 171 Line 3
input mode. added
Page 171 Figure 1.22.2
Page 176 Figure 1.24.3 added
Set the function select register A to I/O port and the direction register to
Note delate
Page 178 Figure 1.25.1
When reset --> indeterminate, Note 4 is added.
Page 200 Table 1.26.2 and 1.26.3 and Figure 1.26.14
CNVss is added
Page 204- Electric characteristics added
99.5.12
Rev.C1
Page 214 Table 1.28.22
Page 220 Figure 1.28.6
Page 223 Figure 1.28.9
th(BCLK-DW) add
th(BCLK-CAS) --> th(BCLK-DW)
WR, WRL, WRH(sepalate bus) wave change
99.5.20
99.6.4
Rev.C2 Page 24 Line 3
same ...
A software reset has almost the same ... --> A software reset has the
Page 161 Note 2:
When f(XIN) is over 10 MHz, the fAD frequency must be under 10 MHz by dividing. -->
addition
99.7.6
Page 18 Figure 1.4.3
(60) Timer B3,4,5 count start flag value change
Flash memory control register 0 and 1 added
Flash memory control register 0 and 1 added
Page 19 Figure 1.4.4
Page 22 Figure 1.5.3
326
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
CM0 Note 5 delate
Page 43 Figure 1.8.4
Page 81 Figure 1.11.5 DMAi memory address reload register
Address DRA2, DRA3 00000016 --> XXXXXX16
Page 181, 182 Figures 1.25.4-1.25.5
D0-D15 waveform changed
Page 185 (6) Pull up control register changed
Page 208 Table 1.28.3
VT+-VT-
TB0IN-TB2IN --> TB0IN-TB5IN,
TA2OUT-TA4OUT --> TA0OUT-TA4OUT
Page 211 Table 1.28.19
Page 212 Table 1.28.20
Page 213 Table 1.28.21
Page 214 Table 1.28.22
Page 216 Figure 1.28.2
Page 217 Figure 1.28.3
Page 218 Figure 1.28.4
Page 219 Figure 1.28.5
Page 220 Figure 1.28.6
Page 221 Figure 1.28.7
Page 223 Figure 1.28.9
99.9.24
99.12.8
Rev.C3
Rev.D
Flash memory ROM version added
Page 2,3 Figure 1.1.1, 1.1.2
Japanese font change to English font
14/3/'00
Page 1
• DMAC...4 channels (trigger: 24 sources) --> 31 sources
• Supply voltage 4.2 to 5.5V (f(XIN)=20MHz) Flash memory version--> addition
• Interrupt...4 software --> 5 software
Page 1,5 Table 1.1.1
Feature • Memory capacity ROM 128 Kbytes --> (See ROM expansion figure.)
RAM 10K --> 10/20 Kbytes
Page 5 Table 1.1.1 Interrupt...4 software --> 5 software
Page 2, 3 Figure 1.1.1, 1.1.2
Note 1 addition
Page 6 Figure 1.1.4, Table 1.1.2 M30803MG-XXXFP/GP addition
Page 7 Figure1.1.5 ROM capacity G:256 Kbytes addition
Page 8 P00 to P07
However, it is possible to select pull-up resistance presence to the usable port as I/O
port by setting. --> addition
CNVss
Connect it to the Vss pin when operating in single-chip or memory
expansion mode. Connect it to the Vcc pin when in microprocessor mode. -->
Connect it to the Vss pin when operating in single-chip or memory expansion mode
after reset. Connect it to the Vcc pin when in microprocessor mode after reset.
BYTE
When operating in single-chip mode,connect this pin to VSS. --> When
not using the external bus,connect this pin to VSS.
Page 9 P50 to P57 In single chip mode, --> delate
Page 10 Figure 1.2.1
Page 13 Figure 1.4.3
M30803FG --> M30803MG/FG
(2) processor mode register C016 --> 0016
Page 20 to 23 Figure 1.5.1 to 1.5.4
Note addition
Page 23 Figure 1.5.4 Note 2 addition
327
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
Page 25 Figure 1.6.1, 1.6.2 Figure 1.6.1 is divided to Figure 1.6.1and 1.6.2
Page 30 Table 1.7.4
Page 34 Figure 1.7.3
Page 36 Line 3
Note addition
the chip select control register --> the wait control registe
Page 38, 39 Figure 1.7.6, 1.7.7
Page 42 Line 7 addition
Note change
When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to
stop mode (bit 0 at address 000716 =1), the main clock division register (address
000C16) is set to the divided-8 mode.
Page 42 (3)BCLK When shifting to stop mode, --> When main clock is stoped or shifting to
stop mode,
Page 43 Figure 1.8.4
Page 44 Figure 1.8.5
Page 48 Line 5
CM0 Note 6 change, Note 7, 8 addition, CM1 Note 4 addition
Note 2 change
When shifting to stop mode and reset, --> When shifting to stop mode,
reset or stopping main clock,
(12) Low power dissipation mode addition
When the main clock is stoped, the main clock division register (address 000C16) is
set to the division by 8 mode.
Page 51 Figure 1.8.7. Clock transition
Page 52 Line 9 addition
Note 3, 4 addition
Page 54 Software Interrupts (2) Overflow interrupt, "CMPX" addition
Page 55 (2) Peripheral I/O interrupts
• Bus collision detection/start, stop condition (UART2, UART3, UART4) interrupts -->
change
Page 57 • Variable vector tables addition
Set an even address to the start address of vector table setting in INTB so that
operating efficiency is increased.
Page 58 Table 1.9.3
Bus collision detection/start, stop condition interrupts --> Bus collision detection, start/
stop condition detection interrupts
Page 58 Table 1.9.3, page 68 Figure 1.9.8
Software interrupt number 40, 41 fault errir --> addition
Page 71 Address match interrupt Line 7 addition
Page 72 (3) The _N__M___I_ interrupt
• Do not reset the CPU with the input to the _N__M___I_ pin being in the “L” state. --> • Signal
of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for
_______
NMI pin.
Page 72 (4) External interrupt
Page 74 Figure 1.10.1
Page 76 Line 2
"DMAC is a function that to transmit 1 data of a source address (8 bits /16 bits) to a
destination address when transmission request occurs. " addition.
Page 76 Line 12 addition
When writing to DSA2 and DSA3, set register bank select flag (B flag) to "1" and use
LDC instruction to set SB and FB registers.
Page 76 Figure 1.11.1
Page 77 Table 1.11.1
Transfer memory space (16 Mbyte space) --> addition
328
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
Page 78 Figure 1.11.2
Note :6 OR instruction --> OR instruction etc.
Page 80 Figure 1.11.4
Page 81 Figure 1.11.5
DRCi • Transfer counter --> • Transfer count register
DMAi, DSAi, DRAi Transfer count specification "(16 Mbytes area)" addition
DRAi memory address counter --> memory address register
Page 85 Line 9 addition
(1) Internal factors, (2) External factors change
"Timer B2 overflow" addition
Page 87 Fugure 1.12.1
Page 88 Fugure 1.12.2
Page 93 Table 1.13.2
Timer A --> Timer B2 overflow (to timer A count source)
Cout source • TB2 overflows, TAj overflows --> •TB2 overflows
or underflows , TAj overflows or underflows
Page 95 Figure 1.13.7
Page 102 Figure 1.14.3
When using two-phase signal processing Note 3 --> addition
TBSR When reset 0016 --> 000XXXXXX16
b4-b0 When read, the value is "0" --> indeterminate
Page 104 Table 1.14.2
Page 124 Figure 1.16.5
Cout source • TBj overflows --> •TBj overflows or underflows
UiTB Note 1 delate
Page 126-127 Figure 1.16.7 to 1.16.8
CRD change
Page 130 Figure 1.16.11 SDHI Enabled <--> Disabled
_______ _______
Page 144
(a) Separate CTS/RTS pins function (UART0)
Addition in "Other things"
Page 146 Table 1.19.1
Page 147 Figure 1.19.1 è„Figure
A "L" level returns from TxD due to the occurrence of a parity error. --> A "L" level
returns from SIM card...
Page 149 Figure 1.19.4
Page 150 Table 1.20.1
Page 156 Figure 1.20.4
Note addition
Note 1: LSB first --> MSB first, Note 3 Change
4 to 5 cycles --> 3 to 6 cycles
Page 163, 165-169 Figure 1.21.2-Figure 1.21.8 ADCON1 Note 2-6 addition
Page 170 Line 14,23 addition
Page 171 Line 5 addition
Page 172 Figure 1.22.3
Page 176 Figure 1.24.3
Note :3 D-A control register --> D-A register
Page 178 Figure 1.25.1 Note 1 position change
Page 178 Line 10 DRAM controler --> addition
Page 179 Figure 1.25.2 Note 1 --> change
Page 184 (1) Direction registers, (2) Port registers --> change
Page 185 (4) Function select register B --> change
Page 189 Figure 1.26.4
Page 190 Figure 1.26.5
Page 191 Table 1.26.1
Page 192 Figure 1.26.6
Page 194 Figure 1.26.8
Page 195 Figure 1.26.9
Port Pi direction register Note 2 addition
Port Pi register Note 1 and 2 addition
Note addition
Function select register A1 Note 1 addition
Function select register B1 Note 2 addition
Function select register B3
Note 1 --> addition, PSL3_3-PSL3_6 change
Page 196 Figure 1.26.13 Port control register Note 2 addition
Page 197 Figure 1.26.4 Port Pi direction register Note 2 addition
Page 200 Precaution on A-D converter (6) --> addition
Page 203 Stop Mode and Wait Mode (2) all clock stop bits --> all clock stop control bits
Page 203 Noise addition
Page 203 Precaution on interrupt (1) line 7 --> addition
329
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
Page 204 Making power consumption electricity small --> addition
Page 207 Table 1.28.3 VT+ – VT- SCL2-SCL4, SDA2-SDA4 Addition
Page 208 Table 1.28.5 Note Change
Page 215 Table 1.28.22
tRP expression change
Page 217-220 Figure 1.28.2-1.28.5
Page 219, 220, 222, 223, 225
tw(WR) addition, th(BCLK-DB) delate
Figure 1.28.4, 1.28.5, 1.28.7, 1.28.8, 1.28.10 addition
Page 225, 226 Figure 1.28.10, 1.28.11
th(BCLK-DB) -5 ns.min --> -7 ns.min
Page 227 Figure 1.28.12 Refresh timing (self refresh) RAS timing
Page 230
3V of electric characteristics addition
Page 246 Table 1.29.1
Page 247 Figure 1.29.2
Data hold --> addition
Package type 144P6Q --> 144P6Q-A
Page 248 Flash memory line 5 change
Page 250 Function outline Line 24 (Parallel ... function ) --> delate
Page 269 Standard serial I/O mode Line 26 externl device --> external device ( programmer)
Page 285 Figure1.31.21 programer --> peripheral unit ( programmer)
Rev.D3
19/6/'00
Page 43 Figure1.8.4 Note of the system clock control register 0-->addition
Page 44 Line 4 Note-->addition
Page 45 Table1.8.2 Note-->addition
Page 71 Line 9 "Address match interrupt is not generated with a start instruction of interrupt
routine."-->Delete
Page 73 (6) Precaution of Address mach interrupt-->addition
Page 79 Figure1.11.2 Note-->change
Page 87 Precaution for DMAC-->addition
Page 131 Figure1.16.11 Bit 7-->Must set to "1" in selecting IIC mode.
Page 152 Figure1.20.1 Bit 7-->Must set to "1" in selecting IIC mode.
Page 182 Addition
Page 205 (3) Address match interrupt in Interrupt precautions-->addition
Page 206 (2) DMAC-->addition
Page 207 Precautions for using CLKOUT pin-->addition
Page 210 Table1.28.3 Icc when clock stop Topr=25Co-->change
Page 212 Table1.28.6 External clock input HIGH and LOW pulse waidth 22-->20
External clock rise and fall time 10-->5
Page 215, 216 Table1.28.19, 20 th(BCLK-DB)-->delete, tw(WR)-->addition
Page 218 Table1.28.22 th(BCLK-DB) -5ns --> -7ns
Page 233 Table1.28.23 Icc when clock stop Topr=25Co-->change
Page 235 Table1.28.27 th(CAS-DB)-->addition
Page 238, 239 Table1.28.39, 40 tw(WR) -->addition, th(BCLK-RD) 0ns-->-3ns
Page 240 Table1.28.41 td(AD-ALE)=109/(f(BCLK)X2)-20 -->109/(f(BCLK)X2)-27
Page 241 Table1.28.42 th(BCLK-CAS) 0ns-->-3ns
Page 242 Figure1.28.15 tac1(RD-DB) min-->max, tac1(AD-DB) min-->max
Page 243 Figure1.28.16 tac2(RD-DB) min-->max, tac2(AD-DB) min-->max
Page 244, 255 Figure1.28.17 2 wait, Figure1.28.18 3 wait-->addition
Page 246 Figure1.28.19 tac3(AD-DB)-->addition, tsu(DB-RD)-->tsu(DB-BCLK), th(BCLK-RD) 0ns -->-
3ns, td(AD-ALE)=(tcyc/2-20)ns--> ... -27)ns
Page 247 Figure1.28.20 Addition
Page 248, 249 Figure1.28.21, 1.28.22 -->addition
330
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
Page 250 Figure1.28.23 th(BCLK-DB)-->th(CAS-DB)
Page 251 Figure 1.28.24 td(DB-CAS)-->tsu(DB-CAS), th(BCLK-CAS)-->th(BCLK-DB)
Page 252 Figure1.28.25 td(CAS-RAS)-->tsu(CAS-RAS)
Page 255 Table1.29.1 Power supply (under planning)-->delete, Program/erase voltage
f(XIN)-->f(BCLK), 2.7V-5.5V-->delete
144-pin version description addition
Rev.E
09/02/'01
Pages 1, 6 •Supply voltage --> external ROM version addition
Page 7 (3) Package 144P6Q --> 144P6Q-A
Page 21 Figure 1.4.4 (111) Function select register C 0016 --> 0XXXXXX0
(119) Function select register B3 ?0000??? --> 00000X0X
Similarly, page 202 Figures 1.26.11 When reset ?0000??? --> 00000X0X
Figures 1.26.12 When reset 0016 --> 0XXXXXX0
Page 28 Figure 1.6.2 ROMless version addition
Page 29 Figure 1.6.3 External area 0 to 3 addition
Page 34 Addition
_______
_______
Page 37 Figure 1.7.4 Input RDY signal at i + 1 cycles for i wait --> RDY signal received timing
for i wait: i +1
Page 46 Figure 1.8.4 System clock control register 0 CM0 --> contents of the Function
changed, Notes 10, 11 addition
Page 48 On the second line from the bottom, 'Although stop mode ... must be set to "1".'
-->addition
_______
_______
_______ _______ _______
_______
___ _________
Page 49 Table 1.8.4 CS0 to CS3 --> CS0 to C___S__3__, BHE
WR, BHE, WRL, WRH, W, CASL
_______
_______
_________
-->_W___R___, WRL, WRH, D___W___, CASL
Page 52 Table 1.8.6 CM0i: Clock control register 0 (address 000616) bit i, MCDi: Main clock
division register (address 000C16) bit i --> addition
Page 60 • Vector table dedicated for emulator
Interrupt vector address (address 00002016 to 00002316)-->... (address
00002016 to 00002216)
Page 69 Interrupt priority
'the interrupt that a request came to most in the first place is accepted at first, and
then,' --> delete
Page 75 (6) Explanation of No.1 and No. 2 are partly revised.
Page 76, 77 From "• To return from an interrupt..." to the end of page 77 --> addition
Page 78 "In the stop...released." on the third line from the bottom --> addition
Page 79 Figure 1.10.2 Notes 10, 11 --> addition
Page 87 Figure 1.11.6 is partly revised.
Page 88 Table for "Coefficient j, k" is partly revised.
Page 89 Figure 1.11.7 is partly revised.
Page 90 Explanation of (3) is partly revised.
Page 94 Figure 1.13.3 Timer Ai register -->Notes 2 to 4 addition, •Pulse width modulation
mode (8-bit PWM) --> Values that can be set is changed, Up/down flag --> Note addi-
tion
Page 97 Figure 1.13.6 --> change
Page 98 Table 1.13.3 --> Note 2 addition, •Normal processing operation --> •Normal pro-
cessing operation (Timer A2 and timer A3), •Multiply-by-4 processing operation -->
•Multiply-by-4 processing operation (Timer A3 and timer A4)
Page 99 Figure 1.13.7 Timer Ai mode register (When using two-phase pulse signal process-
331
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
ing) --> "Note 2 Timer A2 is fixed to ... multiply-by-4 processing operation." is added,
note 3 change
Page 109 Figure 1.14.6 Note 1 It is indeterminate when reset --> addition
Page 112 Figure 1.15.2 Dead time timer-->Note 1 addition, Timer B2 interrupt occurrence
frequency set counter-->Note 3 addition
Page 113 Notes 2, 3 --> addition
Page 114 three-phase waveform mode --> three phase PWM output mode
Page 128 Figure 1.16.5 UARTi bit rate generator --> Note 2 addition
Page 128 Figure 1.16.5 UARTi transmit buffer register, UARTi bit rate generator-->Note 1
addition
Page 129 Figure 1.16.6 UARTi transmit/receive mode register-->Note 2 addition in CKDIR of
UART mode
Page 133 Figure 1.16.10 UART transmit/receive control register 2-->Note delete
Page 136 Note 2, Page 143 Note 3 ... the UARTi receive interrupt request bit is not set to "1"
--> ... the UARTi receive interrupt request bit will not change
Page 145 Figure 1.18.1 UARTi transmit/receive mode register (i=0,1) --> Note 1 addition,
UARTi transmit/receive mode register (i=2 to 4) --> Note 2 addition
Page 157 On the 12th line, ... allocated to bit 3 in UART2 transmission buffer register 1
(address 033F16) ... --> ... allocated to bit 11 in UART2 transmission buffer register
(address 033E16) ...
Page 161 < Master Mode (TxDi and RxDi are selected, DINC = 0) >
..., and the STxDi, SRxDi and CLKi pins ...--> ..., and the TxDi, RxDi and CLKi
pins ...
Page 165 Table 1.21.1 Absolute precision --> change
Page 170 Table 1.21.3 Reading of result of A-D converter --> (at any time) addition
Page 173 Table 1.21.6 Input pin --> change to AN0 to AN7, With emphasis on the pin -->
addition
Page 182 On the second line from the bottom, ..., and dummy cycle for refresh ... --> ..., and
processing necessary for dummy cycle to refresh DRAM ...
Page 183 Figure 1.25.2 is partly revised.
Page 189 On the 18th and 27th lines, page 194 Port Pi direction register Note 2, page 196
Port Pi register Note 1 ... for setting of bus control such as address bus and data bus is
_____
_______
_______ _____ _________
... --> of pins A0 to A22, A23, D0 to D15, MA0 to MA12, _C__S___0_ to CS 3, WRL/WR/CASL,
_______ _______
_______
_____ _____
_________
_________
_______
WRH/BHE/CASH, RD/DW, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE/RAS, and
_______
RDY are ...
Page 203 Figure 1.26.13 is partly revised.
Page 207, 208 Timer A (event counter mode) --> (3) addition, Timer A (one-shot timer mode)
--> (2) changes to (3), (2) and (4) addition
Page 209 Timer B (pulse period/pulse width measurement mode) --> (3) addition
Page 212 to 214 (2)_N___M___I_interrupt •The_N___M___I_pin also serves as P85, ... •Signal of "L" level ...
--> addition
(3) Address match interrupt From "• To return from an interrupt..." to
"; Interrupt completed" on page 77 --> addition
(4) External interrupt, (5) Rewrite the interrupt control register --> addition
Page 215 Explanation of (3) is partly revised.
__________
Page 215 HOLD signal --> addition
Page 216 DRAM controller --> addition
332
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi Microcomputers
Under
M16C/80 group
development
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision history
Revision
date
Version
Contents for change
Page 217 Setting the registers, Notes on the microprocessor mode ... single-chip mode
->addition
-
Page 217 Explanation of note on Flash memroy version is added.
Page 219 Note 2 80mA --> –80mA
Page 220 Table 1.28.3 Ta --> Topr, Note2 --> addition
Pages 220, 243 Tables 1.28.3, 1.28.23 Icc Power supply current ROMless version --> addi-
tion, Ta --> Topr, Note 2 --> addition
Page 227 Calculation for td(AD-ALE) is partly revised.
Page 234, 235 Figures 1.28.6 and 1.28.7 Timing for td(AD-ALE) is partly revised.
Page 243 Table 1.28.23 Topr=25°C, when clock is stopped: 2.0µA --> 1.0µA, Notes 1, 2 -->
addition
Page 250 Table 1.28.41 th(BCLK-RD) Min. 0 ns --> –3 ns
Pages 251, 258 to 262 Table 1.28.42, figures 1.28.21 to 1.28.25 th(BCLK-CAS): –3 ns -->
0 ns
Pages 251, 259, 261 Table 1.28,42, figures 1.28.22, 1.28.24 th(BCLK-DW): 0 ns --> –3 ns
Page 266 Table 1.29.2 M30805FGGP RAM capacity 24 Kbytes --> 20 Kbytes
Page 270 Figure 1.30.1 Flash memory control register 0 Note 1 Also write to this bit ... "H"
level. --> addition
Page 273 (3) Disabling erase or ... serial I/O mode --> delete, (7), (8) --> addition
Page 285 Note --> addition
Page 288 --> addition
Pages 291, 307 Tables 1.31.1, 1.31.5 Note 2 ... status register 1 data --> ... status register
data 1
Page 319 144P6Q-A version --> addition
Rev.E1
Rev.E2
16/03/'01
10/05/'01
Page 32 Table 1.7.3 --> change
Page 28 Figure 1.6.1 Note 8 --> addition
Page 88 Table for "Coefficient j, k" is partly revised.
Rev.E3
Page 7 Figure 1.1.5 and Table 1.1.2, product names --> added
Page 8 Figure 1.1.6, Boot loader (BL) -->addition
20/08/'01
Page 85 Figure 1.11.5, DMAi SFR address register, Note 2, destination fixed address -->
source fixed address, source fixed address --> destination fixed address
Page 218 Precaution of boot loader --> addition
Page 319 Appendix boot loader --> addition
333
Keep safety first in your circuit designs!
✕
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
✕
✕
✕
These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication
of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
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The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
by various means, including the Mitsubishi Semiconductor home page (http://
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✕
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responsibility for any damage, liability or other loss resulting from the information
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Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
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restrictions, they must be exported under a license from the Japanese government
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and/or the country of destination is prohibited.
✕
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
ductor product distributor for further details on these materials or the products con
tained therein.
MITSUBISHI SEMICONDUCTORS
M16C/80 Group DATA SHEET REV. E3
August First Edition 2001
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©2001 MITSUBISHI ELECTRIC CORPORATION
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