M34501E4FP_技术文档

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DESCRIPTION

ꢀTimers

The 4501 Group is a 4-bit single-chip microcomputer designed with

CMOS technology. Its CPU is that of the 4500 series using a

simple, high-speed instruction set. The computer is equipped with

two 8-bit timers (each timer has a reload register), interrupts, and

10-bit A-D converter.

Timer 1...................................... 8-bit timer with a reload register

Timer 2...................................... 8-bit timer with a reload register

ꢀInterrupt ........................................................................ 4 sources

ꢀKey-on wakeup function pins ................................................... 12

ꢀInput/Output port ...................................................................... 14

ꢀA-D converter .................. 10-bit successive comparison method

ꢀWatchdog timer

The various microcomputers in the 4501 Group include variations

of the built-in memory size as shown in the table below.

ꢀClock generating circuit (ceramic resonator/RC oscillation)

ꢀLED drive directly enabled (port D)

FEATURES

ꢀMinimum instruction execution time ................................ 0.68 µs

(at 4.4 MHz oscillation frequency, in high-speed mode)

ꢀSupply voltage .........................................................VRST to 5.5 V

(VRST: detection voltage of voltage drop detection circuit)

ꢀPower-on reset circuit

ꢀVoltage drop detection circuit........................... VRST: Typ. 3.5 V

(Ta = 25 °C)

APPLICATION

Electrical household appliance, consumer electronic products, of-

fice automation equipment, etc.

ROM (PROM) size

RAM size

(ꢀ 4 bits)

128 words

256 words

Product

Package

ROM type

(ꢀ 10 bits)

M34501M2-XXXFP

M34501M4-XXXFP

M34501E4FP (Note)

2048 words

4096 words

20P2N-A

Mask ROM

One Time PROM

Note: Shipped in blank.

PIN CONFIGURATION

P0

P1

0

1

2

3

0

1

2

3

1

2

20

19

18

17

16

15

14

13

12

11

V

DD

SS

IN

OUT

V

3

X

4

X

5

CNVSS

RESET

6

7

/CNTR

/INT

P2

1

/AIN1

/AIN0

8

0

9

D

0

1

D

3

/K

/C

10

2

Outline 20P2N-A

Pin configuration (top view) (4501 Group)

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

BLOCK DIAGRAM

Block diagram (4501 Group)

2

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PERFORMANCE OVERVIEW

Parameter

Function

Number of basic instructions

Minimum instruction execution time

111

0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode)

2048 words ꢀ 10 bits

ROM

Memory sizes

M34501M2

M34501M4/E4 4096 words ꢀ 10 bits

M34501M2 128 words ꢀ 4 bits

M34501M4/E4 256 words ꢀ 4 bits

RAM

D0–D3

Input/Output

ports

I/O

Four independent I/O ports.

Input is examined by skip decision.

Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both func-

tions can be switched by software.

Ports D2 and D3 are also used as ports C and K, respectively.

P00–P03

P10–P13

I/O

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

Ports P12 and P13 are also used as CNTR and INT, respectively.

P20, P21

I/O

2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software.

Ports P20 and P21 are also used as AIN0 and AIN1, respectively.

C

I/O

1-bit I/O; Port C is also used as port D2.

1-bit I/O; Port K is also used as port D3.

1-bit I/O; CNTR pin is also used as port P12.

K

I/O

CNTR

INT

Timer I/O

Interrupt input 1-bit input; INT pin is also used as port P13.

AIN0, AIN1

Timer 1

Timer 2

Analog input

Two independent I/O ports. AIN0–AIN1 is also used as ports P20, P21, respectively.

Timers

8-bit programmable timer with a reload register.

8-bit programmable timer with a reload register and has a event counter.

10-bit wide, This is equipped with an 8-bit comparator function.

2 channel (AIN0 pin, AIN1 pin)

A-D converter

Interrupt

Analog input

Sources

4 (one for external, two for timer, one for A-D)

1 level

Nesting

Subroutine nesting

Device structure

Package

8 levels

CMOS silicon gate

20-pin plastic molded SOP (20P2N-A)

–20 °C to 85 °C

Operating temperature range

Supply voltage

VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage

drop detection circuit characteristics.)

Power

dissipation

Active mode

1.7 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors

in the cut-off state)

(typical value)

RAM back-up mode

0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

3

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION

Name

Power supply

Ground

Input/Output

Function

VDD

VSS

—

Connected to a plus power supply.

Connected to a 0 V power supply.

CNVSS

RESET

CNVSS

—

Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.

Reset input/output

I/O

An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the

voltage drop detection circuit cause the system to be reset, the RESET pin outputs

“L” level.

XIN

System clock input

System clock output

I/O port D

Input

Output

I/O

I/O pins of the system clock generating circuit. When using a ceramic resonator, connect

it between pins XIN and XOUT. A feedback resistor is built-in between them. When using

the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.

XOUT

D0–D3

Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-

put latch. For input use, set the latch of the specified bit to “1.” Input is examined by

skip decision. The output structure is N-channel open-drain. Ports D2 and D3 are

equipped with a pull-up function and a key-on wakeup function. Both functions can

be switched by software.

Ports D2 and D3 are also used as ports C and K, respectively.

P00–P03

P10–P13

I/O

Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch

is set to “1.” The output structure is N-channel open-drain. Port P0 has a key-on

wakeup function and a pull-up function. Both functions can be switched by software.

I/O port P1

Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch

is set to “1.” The output structure is N-channel open-drain. Port P1 has a key-on

wakeup function and a pull-up function. Both functions can be switched by software.

Ports P12 and P13 are also used as CNTR and INT, respectively.

P20, P21

Port C

Port K

I/O port P2

I/O

Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch

is set to “1.” The output structure is N-channel open-drain. Port P2 has a key-on

wakeup function and a pull-up function. Both functions can be switched by software.

Ports P20 and P21 are also used as AIN0 and AIN1, respectively.

I/O port C

1-bit I/O port. Port C can be used as inputs when the output latch is set to “1.” The

output structure is N-channel open-drain. Port C has a key-on wakeup function and

a pull-up function. Both functions can be switched by software. Port C is also used

as port D2.

I/O port K

1-bit I/O port. Port K can be used as inputs when the output latch is set to “1.” The

output structure is N-channel open-drain. Port K has a key-on wakeup function and

a pull-up function. Both functions can be switched by software. Port K is also used

as port D3.

CNTR

Timer input/output

CNTR pin has the function to input the clock for the timer 2 event counter, and to out-

put the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port

P12.

INT

Interrupt input

Analog input

Input

INT pin accepts external interrupts. It has the key-on wakeup function which can be

switched by software. This pin is also used as port P13.

AIN0–AIN1

A-D converter analog input pins. AIN0 and AIN1 are also used as ports P20 and P21,

respectively.

MULTIFUNCTION

D2

D3

Multifunction

P20

P21

Multifunction

P20

P21

C

K

AIN0

AIN1

D2

D3

C

AIN0

AIN1

K

CNTR

INT

P12

P13

CNTR

INT

P12

P13

Notes 1: Pins except above have just single function.

2: The input/output of D2, D3, P12 and P13 can be used even when C, K, INT and CNTR (input) are selected.

3: The input of P12 can be used even when CNTR (output) is selected.

4: The input/output of P20, P21 can be used even when AIN0, AIN1 are selected.

4

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DEFINITION OF CLOCK AND CYCLE

ꢀꢀInstruction clock

ꢀꢀOperation source clock

The instruction clock is a signal derived by dividing the system

clock by 3. The one instruction clock cycle generates the one

machine cycle.

The operation source clock is the source clock to operate this

product. In this product, the following clocks are used.

• External ceramic resonator

ꢀꢀMachine cycle

• External RC oscillation

The machine cycle is the standard cycle required to execute the

instruction.

• Clock (f(XIN)) by the external clock

• Clock (f(RING)) of the ring oscillator which is the internal oscil-

lator.

ꢀꢀSystem clock

The system clock is the basic clock for controlling this product.

The system clock is selected by the bits 2 and 3 of the clock con-

trol register MR.

Table Selection of system clock

Register MR

System clock

(Note 1)

Operation mode

MR3

MR2

0

1

0

1

0

1

f(XIN) or f(RING)

f(XIN)/2 or f(RING)/2

f(XIN)/4 or f(RING)/4

f(XIN)/8 or f(RING)/8

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

Notes 1: The ring oscillator clock is f(RING), the clock by the ce-

ramic resonator, RC oscillation or external clock is f(XIN).

2: The default mode is selected after system is released

from reset and is returned from RAM back-up.

PORT FUNCTION

Input

Output

I/O

Control

Port

Output structure

Remark

unit instructions registers

I/O

(4)

1

SD, RD

Port D D0, D1

D2/C

N-channel open-drain

Built-in programmable pull-up

functions

Key-on wakeup functions

(programmable)

SZD, CLD

SCP, RCP

SNZCP

PU2, K2

PU0, K0

D3/K

IAK, OKA

Built-in programmable pull-up

functions

Key-on wakeup functions

(programmable)

I/O

(4)

4

2

OP0A

IAP0

Port P0 P00–P03

N-channel open-drain

Built-in programmable pull-up

functions

Key-on wakeup functions

(programmable)

I/O

(4)

OP1A

IAP1

PU1, K1

W6, I1

Port P1 P10, P11

P12/CNTR,

P13/INT

Built-in programmable pull-up

functions

I/O

(2)

OP2A

IAP2

PU2, K2

Q1

Port P2 P20/AIN0

P21/AIN1

Key-on wakeup functions

(programmable)

5

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

CONNECTIONS OF UNUSED PINS

Connection

Usage condition

Connect to VSS.

System operates by the ring oscillator. (Note 1)

XIN

Open.

System operates by the external clock.

XOUT

(The ceramic resonator is selected with the CMCK instruction.)

System operates by the RC oscillator.

(The RC oscillation is selected with the CRCK instruction.)

System operates by the ring oscillator. (Note 1)

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

D0, D1

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

The key-on wakeup function is not selected. (Note 4)

D2/C

D3/K

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

The key-on wakeup function is not selected. (Note 4)

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

P00–P03

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

The key-on wakeup function is not selected. (Note 4)

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

P10, P11

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

The key-on wakeup function is not selected. The input to INT pin is disabled.

(Notes 4, 5)

P12/CNTR

Open. (Output latch is set to “1.”)

P13/INT

Open. (Output latch is set to “0.”)

Connect to VSS.

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

The key-on wakeup function is not selected. (Note 4)

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

P20/AIN0

P21/AIN1

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the ring oscillator (internal oscillator).

2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function.

3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state.

Do not select the key-on wakeup function.

4: When selecting the key-on wakeup function, select also the pull-up function.

5: Clear the bit 3 (I13) of register I1 to “0” to disable to input to INT pin (after reset: I13 = “0”)

(Note when connecting to VSS and VDD)

ꢀꢀConnect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.

6

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PORT BLOCK DIAGRAMS

Skip decision

(SZD instruction)

Register Y

Decoder

D

0

, D

1

CLD

instruction

(Note 1)

S

SD instruction

RD instruction

R

Q

Pull-up

transistor

Register Y

Decoder

PU2

2

K22

“L” level

detection circuit

Key-on wakeup

Skip decision

CLD

instruction

(SZD instruction)

Skip decision

(SNZCP

(Note 1)

D

S

(Note 2)

/C

2

instruction)

SD instruction

RD instruction

R

S

Q

SCP instruction

RCP instruction

R

Pull-up

transistor

Register Y

Decoder

PU2

3

K23

“L” level

Key-on wakeup

detection circuit

Skip decision

(SZD instruction)

CLD

instruction

IAK instruction

Register A

(Note 1)

S

(Note 2)

D3/K

SD instruction

RD instruction

R

D

Q

A

0

T

OKA instruction

Notes 1:

This symbol represents a parasitic diode on the port.

/C and D /K must be VDD or less.

2: Applied potential to ports D

2

3

Port block diagram (1)

7

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Pull-up transistor

(Note 2)

PU0

i

IAP0 instruction

Register A

Ai

(Note 1)

(Note 2)

P00, P01 (Note 4)

D

A

i

OP0A instruction

Q

T

K0

i

“L” level

detection circuit

Key-on wakeup input

Pull-up transistor

(Note 3)

PU0

j

IAP0 instruction

Register A

Aj

(Note 1)

(Note 3)

₃(Note 4)

P02, P0

D

A

j

OP0A instruction

Q

T

K0

j

“L” level detection

Key-on wakeup

circuit

Notes 1:

This symbol represents a parasitic diode on the port.

2: i represents 0 or 1.

3: j represents 2 or 3.

4: Applied potential to port P0 must be VDD or less.

Port block diagram (2)

8

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Pull-up transistor

PU1

i

(Note 2)

K1i

(Note 2)

“L” level

detection circuit

Key-on wakeup input

IAP1 instruction

Register A

Ai

(Note 1)

P1

(Note 2)

Ai

0

, P11 (Note 3)

D

T

Q

OP1A instruction

Pull-up transistor

PU1

2

K12

“L” level

detection circuit

Key-on wakeup input

W21

W20

Clock input for timer 2 event counter

IAP1 instruction

Register A

(Note 1)

P1

A

2

/CNTR (Note 3)

A

2

D

W60

0

OP1A instruction

T

Q

1

Timer 1 or timer 2 underflow

signal divided by 2

K13

Pull-up transistor

PU1

“L” level

detection circuit

3

Key-on wakeup input

K13

External 0 interrupt

Register A

External interrupt circuit

IAP1 instruction

(Note 1)

P1

A

3

/INT (Note 3)

A

3

D

OP1A instruction

Q

T

Notes 1:

2: i represents 0 or 1.

3: Applied potential to port P1 must be VDD or less.

This symbol represents a parasitic diode on the port.

Port block diagram (3)

9

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

K20

Pull-up transistor

PU2

“L” level

detection circuit

Key-on wakeup input

0

IAP2 instruction

Register A

(Note 1)

P2

A

0

_IN0(Note 3)

/A

0

D

A0

T

Q

OP2A instruction

Q1

Decoder

Analog input

Pull-up transistor

PU2

K21

“L” level

detection circuit

1

Key-on wakeup input

IAP2 instruction

Register A

(Note 1)

P2 /AIN1 (Note 3)

A1

1

D

A1

OP2A instruction

Q

T

Q1

Decoder

Analog input

Notes 1:

2: i represents 0 or 1.

3: Applied potential to ports P2 and P3 must be VDD or less.

This symbol represents a parasitic diode on the port.

Port block diagram (4)

10

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

I1

2

One-sided edge

detection circuit

Falling

I1

0

1

(Note)

/INT

0

External 0

interrupt

P13

EXF0

1

I13

Both edges

detection circuit

Rising

Timer 1 count start

synchronization

circuit input

Wakeup

Skip

K13

SNZI0 instruction

•

This symbol represents a parasitic diode on the port.

External interrupt circuit structure

11

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

FUNCTION BLOCK OPERATIONS

CPU

<Carry>

(CY)

(1) Arithmetic logic unit (ALU)

(M(DP))

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-

bit data addition, comparison, AND operation, OR operation, and

bit manipulation.

ALU

Addition

(A)

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer, ex-

change, and I/O operation.

Fig. 1 AMC instruction execution example

Carry flag CY is a 1-bit flag that is set to “1” when there is a carry

with the AMC instruction (Figure 1).

<Set>

<Clear>

SC instruction

RC instruction

It is unchanged with both A n instruction and AM instruction. The

value of A0 is stored in carry flag CY with the RAR instruction (Fig-

ure 2).

Carry flag CY can be set to “1” with the SC instruction and cleared

to “0” with the RC instruction.

CY

A3

A2

A1 A0

RAR instruction

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit

data, and for 8-bit data transfer together with register A.

Register E is an 8-bit register. It can be used for 8-bit data transfer

with register B used as the high-order 4 bits and register A as the

low-order 4 bits (Figure 3).

A0

CY A

3

A2 A1

Fig. 2 RAR instruction execution example

Register E is undefined after system is released from reset and re-

turned from the RAM back-up. Accordingly, set the initial value.

Register B TAB instruction Register A

B3

B2

B1

B0

A3 A2 A1 A0

(4) Register D

Register D is a 3-bit register.

TEAB instruction

It is used to store a 7-bit ROM address together with register A and

is used as a pointer within the specified page when the TABP p,

BLA p, or BMLA p instruction is executed (Figure 4).

Register D is undefined after system is released from reset and re-

turned from the RAM back-up. Accordingly, set the initial value.

Register E E

7

E6

E

5

E

4

E

3

E

2

E1

E0

TABE instruction

A3

A2

A1

A0

B3

B2

B1

B0

Register B TBA instruction Register A

Fig. 3 Registers A, B and register E

TABP p instruction

ROM

8

4

0

Specifying address

Low-order 4bits

PCH

PCL

A3 A2 A1 A0

Register A (4)

Register B (4)

p6 p5 p4 p3 p2 p1 p0

DR2DR1DR0

Middle-order 4 bits

Immediate field

value p

The contents of The contents of

register D register A

Fig. 4 TABP p instruction execution example

12

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contents of

program counter (PC) just before branching until returning to the

original routine when;

Program counter (PC)

Executing BM

instruction

Executing RT

instruction

• branching to an interrupt service routine (referred to as an inter-

rupt service routine),

SK

0

(SP) = 0

(SP) = 1

(SP) = 2

(SP) = 3

(SP) = 4

(SP) = 5

(SP) = 6

(SP) = 7

SK

1

2

3

4

5

6

7

• performing a subroutine call, or

• executing the table reference instruction (TABP p).

Stack registers (SKs) are eight identical registers, so that subrou-

tines can be nested up to 8 levels. However, one of stack registers

is used respectively when using an interrupt service routine and

when executing a table reference instruction. Accordingly, be care-

ful not to over the stack when performing these operations

together. The contents of registers SKs are destroyed when 8 lev-

els are exceeded.

Stack pointer (SP) points “7” at reset or

returning from RAM back-up mode. It points “0”

by executing the first BM instruction, and the

contents of program counter is stored in SK0.

When the BM instruction is executed after eight

stack registers are used ((SP) = 7), (SP) = 0

and the contents of SK0 is destroyed.

The register SK nesting level is pointed automatically by 3-bit

stack pointer (SP). The contents of the stack pointer (SP) can be

transferred to register A with the TASP instruction.

Figure 5 shows the stack registers (SKs) structure.

Figure 6 shows the example of operation at subroutine call.

Fig. 5 Stack registers (SKs) structure

(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When an inter-

rupt occurs, this register (SDP) is used to temporarily store the

contents of data pointer, carry flag, skip flag, register A, and regis-

ter B just before an interrupt until returning to the original routine.

Unlike the stack registers (SKs), this register (SDP) is not used

when executing the subroutine call instruction and the table refer-

ence instruction.

(SP) ← 0

(SK0) ← 000116

(PC) ← SUB1

Main program

Address

Subroutine

SUB1 :

(7) Skip flag

0000¹⁶NOP

NOP

·

Skip flag controls skip decision for the conditional skip instructions

and continuous described skip instructions. When an interrupt oc-

curs, the contents of skip flag is stored automatically in the interrupt

stack register (SDP) and the skip condition is retained.

0001¹⁶BM SUB1

000216 NOP

RT

(PC) ← (SK

(SP) ← 7

0)

Note :

Returning to the BM instruction execution

address with the RT instruction, and the BM

instruction becomes the NOP instruction.

Fig. 6 Example of operation at subroutine call

13

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Program counter

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (page and

address). It determines a sequence in which instructions stored in

ROM are read. It is a binary counter that increments the number of

instruction bytes each time an instruction is executed. However,

the value changes to a specified address when branch instructions,

subroutine call instructions, return instructions, or the table refer-

ence instruction (TABP p) is executed.

p6

p

5

p4

p3

p2

p1

p0

a6 a5 a4 a3 a2 a1 a0

PC

H

PC

L

Specifying page

Specifying address

Program counter consists of PCH (most significant bit to bit 7)

which specifies to a ROM page and PCL (bits 6 to 0) which speci-

fies an address within a page. After it reaches the last address

(address 127) of a page, it specifies address 0 of the next page

(Figure 7).

Fig. 7 Program counter (PC) structure

Data pointer (DP)

Make sure that the PCH does not specify after the last page of the

built-in ROM.

Z

1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and consists

of registers Z, X, and Y. Register Z specifies a RAM file group, reg-

ister X specifies a file, and register Y specifies a RAM digit (Figure

8).

Specifying

RAM digit

Register Y (4)

Register X (4)

Specifying RAM file

Register Y is also used to specify the port D bit position.

When using port D, set the port D bit position to register Y certainly

and execute the SD, RD, or SZD instruction (Figure 9).

Register Z (2)

Specifying RAM file group

• Note

Fig. 8 Data pointer (DP) structure

Register Z of data pointer is undefined after system is released

from reset.

Also, registers Z, X and Y are undefined in the RAM back-up. After

system is returned from the RAM back-up, set these registers.

Specifying bit position

Set

D3

D2

D1

D0

0

1

Register Y (4)

Port D output latch

Fig. 9 SD instruction execution example

14

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PROGRAM MEMOY (ROM)

The program memory is a mask ROM. 1 word of ROM is composed

of 10 bits. ROM is separated every 128 words by the unit of page

(addresses 0 to 127). Table 1 shows the ROM size and pages. Fig-

ure 10 shows the ROM map of M34501M4.

9

8

7

6

5

4

3

2 1 0

000016

007F16

008016

00FF16

010016

017F16

018016

Page 0

Page 1

Page 2

Page 3

Interrupt address page

Subroutine special page

Table 1 ROM size and pages

ROM (PROM) size

Product

M34501M2

Pages

(ꢀ 10 bits)

2048 words

4096 words

16 (0 to 15)

32 (0 to 31)

M34501M4

M34501E4

0

FFF16

A part of page 1 (addresses 008016 to 00FF16) is reserved for in-

terrupt addresses (Figure 11). When an interrupt occurs, the

address (interrupt address) corresponding to each interrupt is set

in the program counter, and the instruction at the interrupt address

is executed. When using an interrupt service routine, write the in-

struction generating the branch to that routine at an interrupt

address.

Page 31

Fig. 10 ROM map of M34501M4/M34501E4

9 8

7

6

5

4

3

2

1 0

Page 2 (addresses 010016 to 017F16) is the special page for sub-

routine calls. Subroutines written in this page can be called from

any page with the 1-word instruction (BM). Subroutines extending

from page 2 to another page can also be called with the BM in-

struction when it starts on page 2.

008016 External 0 interrupt address

008216

ROM pattern (bits 7 to 0) of all addresses can be used as data ar-

eas with the TABP p instruction.

008416

008616

008816

008A16

008C16

008E16

Timer 1 interrupt address

Timer 2 interrupt address

A-D interrupt address

00FF16

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure

15

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DATA MEMORY (RAM)

Table 2 RAM size

1 word of RAM is composed of 4 bits, but 1-bit manipulation (with

the SB j, RB j, and SZB j instructions) is enabled for the entire

memory area. A RAM address is specified by a data pointer. The

data pointer consists of registers Z, X, and Y. Set a value to the

data pointer certainly when executing an instruction to access

RAM.

Product

M34501M2

M34501M4

M34501E4

RAM size

128 words ꢀ 4 bits (512 bits)

256 words ꢀ 4 bits (1024 bits)

Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note

Register Z of data pointer is undefined after system is released

from reset.

Also, registers Z, X and Y are undefined in the RAM back-up. After

system is returned from the RAM back-up, set these registers.

RAM 256 words ꢀ 4 bits (1024 bits)

Register Z

0

...

........

Register X

0

2

3

6

7

15

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

256 words (1024 bits) M34501M4/E4

Z=0, X=0 to 15

Z=0, X=0 to 7

128 words (512 bits) M34501M2

Fig. 12 RAM map

16

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 3 Interrupt sources

INTERRUPT FUNCTION

Priority

level

Interrupt

address

The interrupt type is a vectored interrupt branching to an individual

address (interrupt address) according to each interrupt source. An

interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)

• Interrupt enable bit is enabled (“1”)

Interrupt name

Activated condition

1

2

3

4

External 0 interrupt Level change of INT Address 0

in page 1

Timer 1 interrupt

Timer 2 interrupt

A-D interrupt

Timer 1 underflow

Address 4

in page 1

• Interrupt enable flag is enabled (INTE = “1”)

Timer 2 underflow

Address 6

in page 1

Table 3 shows interrupt sources. (Refer to each interrupt request

flag for details of activated conditions.)

Completion of

A-D conversion

Address C

in page 1

(1) Interrupt enable flag (INTE)

Table 4 Interrupt request flag, interrupt enable bit and skip in-

struction

The interrupt enable flag (INTE) controls whether the every inter-

rupt enable/disable. Interrupts are enabled when INTE flag is set to

“1” with the EI instruction and disabled when INTE flag is cleared to

“0” with the DI instruction. When any interrupt occurs, the INTE flag

is automatically cleared to “0,” so that other interrupts are disabled

until the EI instruction is executed.

Request flag Skip instruction Enable bit

Interrupt name

External 0 interrupt

Timer 1 interrupt

Timer 2 interrupt

A-D interrupt

EXF0

T1F

SNZ0

SNZT1

SNZT2

SNZAD

V10

V12

V13

V22

T2F

ADF

(2) Interrupt enable bit

Table 5 Interrupt enable bit function

Use an interrupt enable bit of interrupt control registers V1 and V2

to select the corresponding interrupt or skip instruction.

Table 4 shows the interrupt request flag, interrupt enable bit and

skip instruction.

Occurrence of interrupt

Interrupt enable bit

Skip instruction

Invalid

Enabled

Disabled

1

0

Valid

Table 5 shows the interrupt enable bit function.

(3) Interrupt request flag

When the activated condition for each interrupt is satisfied, the cor-

responding interrupt request flag is set to “1.” Each interrupt

request flag is cleared to “0” when either;

• an interrupt occurs, or

• the next instruction is skipped with a skip instruction.

Each interrupt request flag is set when the activated condition is

satisfied even if the interrupt is disabled by the INTE flag or its in-

terrupt enable bit. Once set, the interrupt request flag retains set

until a clear condition is satisfied.

Accordingly, an interrupt occurs when the interrupt disable state is

released while the interrupt request flag is set.

If more than one interrupt request flag is set when the interrupt dis-

able state is released, the interrupt priority level is as follows

shown in Table 3.

17

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(4) Internal state during an interrupt

The internal state of the microcomputer during an interrupt is as fol-

lows (Figure 14).

• Program counter (PC)

............................................................... Each interrupt address

• Program counter (PC)

• Stack register (SK)

An interrupt address is set in program counter. The address to be

executed when returning to the main routine is automatically

stored in the stack register (SK).

The address of main routine to be

....................................................................................................

executed when returning

• Interrupt enable flag (INTE)

INTE flag is cleared to “0” so that interrupts are disabled.

• Interrupt request flag

.................................................................. 0 (Interrupt disabled)

Only the request flag for the current interrupt source is cleared to

“0.”

• Interrupt request flag (only the flag for the current interrupt

source) ................................................................................... 0

• Data pointer, carry flag, skip flag, registers A and B

The contents of these registers and flags are stored automatically

in the interrupt stack register (SDP).

• Data pointer, carry flag, registers A and B, skip flag

........ Stored in the interrupt stack register (SDP) automatically

(5) Interrupt processing

Fig. 14 Internal state when interrupt occurs

When an interrupt occurs, a program at an interrupt address is ex-

ecuted after branching a data store sequence to stack register.

Write the branch instruction to an interrupt service routine at an in-

terrupt address.

INT pin

Address 0

(L→H or

in page 1

EXF0

Use the RTI instruction to return from an interrupt service routine.

Interrupt enabled by executing the EI instruction is performed after

executing 1 instruction (just after the next instruction is executed).

Accordingly, when the EI instruction is executed just before the RTI

instruction, interrupts are enabled after returning the main routine.

(Refer to Figure 13)

V1

0

H→L input)

Timer 1

underflow

Address 4

in page 1

T1F

V12

Address 6

in page 1

Timer 2

underflow

T2F

V13

Main

routine

Address C

in page 1

Completion of

A-D conversion

ADF

V22

INTE

Activated

condition

Request flag

(state retained)

Enable

bit

Enable

flag

Interrupt

service routine

Interrupt

Fig. 15 Interrupt system diagram

occurs

•

EI

RTI

Interrupt is

enabled

: Interrupt enabled state

: Interrupt disabled state

Fig. 13 Program example of interrupt processing

18

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(6) Interrupt control registers

• Interrupt control register V2

• Interrupt control register V1

The A-D interrupt enable bit is assigned to register V2. Set the

contents of this register through register A with the TV2A instruc-

tion. The TAV2 instruction can be used to transfer the contents of

register V2 to register A.

Interrupt enable bits of external 0, timer 1 and timer 2 are as-

signed to register V1. Set the contents of this register through

register A with the TV1A instruction. The TAV1 instruction can be

used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

Interrupt control register V1

Timer 2 interrupt enable bit

at reset : 00002

at RAM back-up : 00002

R/W

0

1

0

1

0

1

0

1

Interrupt disabled (SNZT2 instruction is valid)

V13

V12

V11

V10

Interrupt enabled (SNZT2 instruction is invalid) (Note 2)

Interrupt disabled (SNZT1 instruction is valid)

Timer 1 interrupt enable bit

Not used

Interrupt enabled (SNZT1 instruction is invalid) (Note 2)

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZ0 instruction is valid)

External 0 interrupt enable bit

Interrupt enabled (SNZ0 instruction is invalid) (Note 2)

Interrupt control register V2

Not used

at reset : 00002

at RAM back-up : 00002

R/W

0

1

0

1

0

1

0

1

V23

V22

V21

V20

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZAD instruction is valid)

A-D interrupt enable bit

Not used

Interrupt enabled (SNZAD instruction is invalid) (Note 2)

This bit has no function, but read/write is enabled.

Not used

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: These instructions are equivalent to the NOP instrucion.

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt en-

able bits (V10, V12, V13, V22), and interrupt request flag are “1.”

The interrupt actually occurs 2 to 3 machine cycles after the cycle

in which all three conditions are satisfied. The interrupt occurs after

3 machine cycles only when the three interrupt conditions are sat-

isfied on execution of other than one-cycle instructions (Refer to

Figure 16).

19

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Fig. 16 Interrupt sequence

20

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

EXTERNAL INTERRUPTS

The 4501 Group has the external 0 interrupt. An external interrupt

request occurs when a valid waveform is input to an interrupt input

pin (edge detection).

The external interrupt can be controlled with the interrupt control

register I1.

Table 7 External interrupt activated conditions

Valid waveform

selection bit

Name

Input pin

Activated condition

I11

I12

External 0 interrupt

INT

When the next waveform is input to INT pin

• Falling waveform (“H”→“L”)

• Rising waveform (“L”→“H”)

• Both rising and falling waveforms

I1

2

One-sided edge

detection circuit

Falling

I11

(Note)

0

External 0

interrupt

P13/INT

EXF0

1

I13

Both edges

detection circuit

Rising

Timer 1 count start

synchronization

circuit input

Wakeup

Skip

K13

SNZI0 instruction

•

This symbol represents a parasitic diode on the port.

Fig. 17 External interrupt circuit structure

(1) External 0 interrupt request flag (EXF0)

➀➀Set the bit 3 of register I1 to “1” for the INT pin to be in the input

enabled state.

External 0 interrupt request flag (EXF0) is set to “1” when a valid

waveform is input to INT pin.

➀ Select the valid waveform with the bits 1 and 2 of register I1.

➀ Clear the EXF0 flag to “0” with the SNZ0 instruction.

➀ Set the NOP instruction for the case when a skip is performed

with the SNZ0 instruction.

The valid waveforms causing the interrupt must be retained at their

level for 4 clock cycles or more of the system clock (Refer to Figure

16).

The state of EXF0 flag can be examined with the skip instruction

(SNZ0). Use the interrupt control register V1 to select the interrupt

or the skip instruction. The EXF0 flag is cleared to “0” when an in-

terrupt occurs or when the next instruction is skipped with the skip

instruction.

➀ Set both the external 0 interrupt enable bit (V10) and the INTE

flag to “1.”

The external 0 interrupt is now enabled. Now when a valid wave-

form is input to the INT pin, the EXF0 flag is set to “1” and the

external 0 interrupt occurs.

• External 0 interrupt activated condition

External 0 interrupt activated condition is satisfied when a valid

waveform is input to INT pin.

The valid waveform can be selected from rising waveform, falling

waveform or both rising and falling waveforms. An example of

how to use the external 0 interrupt is as follows.

21

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(2) External interrupt control registers

• Interrupt control register I1

Register I1 controls the valid waveform for the external 0 inter-

rupt. Set the contents of this register through register A with the

TI1A instruction. The TAI1 instruction can be used to transfer the

contents of register I1 to register A.

Table 8 External interrupt control register

Interrupt control register I1

at reset : 00002

INT pin input disabled

INT pin input enabled

at RAM back-up : state retained

R/W

0

1

INT pin input control bit (Note 2)

I13

I12

Falling waveform (“L” level of INT pin is recognized with the SNZI0

0

1

Interrupt valid waveform for INT pin/

return level selection bit (Note 2)

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

0

1

0

1

I11

I10

INT pin edge detection circuit control bit

INT pin

timer 1 control enable bit

Enabled

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-

struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

performed with the SNZ0 instruction.

22

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

➀ Note [3] on bit 2 of register I1

(3) Notes on interrupts

When the interrupt valid waveform of the P13/INT pin is changed

with the bit 2 of register I1 in software, be careful about the fol-

lowing notes.

➀ Note [1] on bit 3 of register I1

When the input of the INT pin is controlled with the bit 3 of regis-

ter I1 in software, be careful about the following notes.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 2 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)

and then, change the bit 2 of register I1 is changed.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 3 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)

and then, change the bit 3 of register I1.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

after executing at least one instruction (refer to Figure 20➀).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 20➀).

In addition, execute the SNZ0 instruction to clear the EXF0 flag

after executing at least one instruction (refer to Figure 18➀).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 18➀).

LA

4

; (➀➀➀02)

LA

4

8

; (➀➀➀02)

TV1A

LA

; The SNZ0 instruction is valid ...........➀

TV1A

LA

; The SNZ0 instruction is valid ...........➀

; (1➀➀➀2)

12

TI1A

NOP

SNZ0

; Interrupt valid waveform is changed

........................................................... ➀

; The SNZ0 instruction is executed

(EXF0 flag cleared)

TI1A

NOP

SNZ0

; Control of INT pin input is changed

........................................................... ➀

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ➀

NOP

........................................................... ➀

➀ : these bits are not used here.

Fig. 20 External 0 interrupt program example-3

Fig. 18 External 0 interrupt program example-1

➀ Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared, the RAM back-up mode is

selected and the input of INT pin is disabled, be careful about the

following notes.

• When the key-on wakeup function of port P13 is not used (regis-

ter K13 = “0”), clear bits 2 and 3 of register I1 before system

enters to the RAM back-up mode. (refer to Figure 19➀).

LA

0

; (00➀➀2)

TI1A

DI

; Input of INT disabled........................➀

EPOF

POF

; RAM back-up

➀ : these bits are not used here.

Fig. 19 External 0 interrupt program example-2

23

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

TIMERS

• Fixed dividing frequency timer

The 4501 Group has the following timers.

The fixed dividing frequency timer has the fixed frequency divid-

ing ratio (n). An interrupt request flag is set to “1” after every n

count of a count pulse.

• Programmable timer

The programmable timer has a reload register and enables the

frequency dividing ratio to be set. It is decremented from a set-

ting value n. When it underflows (count to n + 1), a timer interrupt

request flag is set to “1,” new data is loaded from the reload reg-

ister, and count continues (auto-reload function).

FF16

n : Counter initial value

Count starts

Reload

n

1st underflow

2nd underflow

0016

Time

n+1 count

“1”

Timer interrupt

request flag

“0”

An interrupt occurs or

a skip instruction is executed.

Fig. 21 Auto-reload function

The 4501 Group timer consists of the following circuits.

• Prescaler : frequency divider

Prescaler and timers 1 and 2 can be controlled with the timer con-

trol registers W1, W2 and W6. The 16-bit timer is a free counter

which is not controlled with the control register.

• Timer 1 : 8-bit programmable timer

• Timer 2 : 8-bit programmable timer

(Timers 1 and 2 have the interrupt function, respectively)

• 16-bit timer

Each function is described below.

Table 9 Function related timers

Frequency

dividing ratio

Control

register

Circuit

Structure

Count source

Use of output signal

Prescaler

Timer 1

Frequency divider

8-bit programmable

binary down counter

(link to INT input)

• Instruction clock

4, 16

• Timer 1 and 2 count sources

• Timer 2 count source

• CNTR output

W1

W2

• Prescaler output (ORCLK) 1 to 256

• Timer 1 interrupt

• CNTR output

Timer 2

8-bit programmable

binary down counter

• Timer 1 underflow

• Prescaler output (ORCLK)

• CNTR input

1 to 256

65536

W2

• Timer 2 interrupt

• System clock

16-bit timer

• Instruction clock

• Watchdog timer

16-bit fixed dividing

frequency binary down

counter

(The 16th bit is counted twice)

24

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Instruction clock

System clock

Prescaler

W13

W12

MR3, MR2

Division circuit

divided by 8

divided by 4

divided by 2

11

10

01

00

1/4

0

1

0

Internal clock

generating circuit

(divided by 3)

1

1/16

Clock

XIN

generation

circuit

ORCLK

I1

2

Falling

1

One-sided edge

detection circuit

(Note 1)

W1

1

0

P1

I1

3/INT

S

Q

1

Both edges

detection circuit

3

0

Rising

R

I1

0

W2

2

Timer 1 underflow signal

(Note 2)

W1

0

1

Timer 1

interrupt

Timer 1 (8)

T1F

Reload register R1 (8)

T1AB

(TR1AB)

(TAB1)

Register B

Register A

Timer 1 underflow signal

W2

00

1,W20

W2

3

(Note 2)

0

1

01

10

11

Timer 2

interrupt

Timer 2 (8)

T2F

Reload register R2 (8)

(T2AB)

(TAB2)

Register B

Register A

W6

0

W6

1

P12 output

P1

2/CNTR

0

1/2

1

Timer 2 underflow signal

16-bit timer (WDT)

Instruction clock

Data is set automatically from each reload

register when timer 1 or 2 underflows

(auto-reload function)

1

16

S

Q

WDF1

R

Notes 1: Timer 1 count start synchronous circuit is set

WRST instruction

(Note 3)

by the valid edge of P1

bits 1 (I1 ) and 2 (I1 ) of register I1.

3/INT pin selected by

1

2

2: Count source is stopped by clearing to “0.”

3: When the WRST instruction is executed at

WDF1 flag = “1,” WDF1 flag is cleared to “0”

and the next instruction is skipped.

S

R

Reset signal

WEF

DWDT instruction

+

WRST instruction

(Note 4)

When the WRST instruction is executed at

WDF1 flag = “0,” skip is not executed.

4: When the DWDT and WRST instructions are

executed continuously, WEF flag is cleared to

“0” and reset by watchdog timer is not executed.

D

WDF2

Q

Watchdog

reset signal

T

R

Reset signal

Fig. 22 Timers structure

25

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 10 Timer control registers

Timer control register W1

Prescaler control bit

at reset : 00002

Stop (state initialized)

Operating

at RAM back-up : 00002

R/W

0

1

0

1

0

1

0

1

W13

W12

W11

W10

Instruction clock divided by 4

Instruction clock divided by 16

Stop (state retained)

Prescaler dividing ratio selection bit

Timer 1 control bit

Operating

Count start synchronous circuit not selected

Count start synchronous circuit selected

Timer 1 count start synchronous circuit

control bit

Timer control register W2

Timer 2 control bit

at reset : 00002

at RAM back-up : state retained

R/W

0

Stop (state retained)

W23

W22

1

0

1

Operating

Count auto-stop circuit not selected

Count auto-stop circuit selected

Timer 1 count auto-stop circuit selection

bit (Note 2)

W21

Count source

W20

W21

W20

0

1

Timer 1 underflow signal

Prescaler output (ORCLK)

CNTR input

0

1

0

1

Timer 2 count source selection bits

System clock

Timer control register W6

Not used

at reset : 00002

at RAM back-up : state retained

R/W

0

W63

W62

W61

W60

This bit has no function, but read/write is enabled.

1

0

1

0

1

0

1

Not used

Timer 1 underflow signal divided by 2 output

Timer 2 underflow signal divided by 2 output

P12(I/O)/CNTR input (Note 3)

CNTR output selection bit

P12/CNTR function selection bit

P12 (input)/CNTR input/output (Note 3)

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: This function is valid only when the timer 1 count start synchronization circuit is selected.

3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.

(1) Timer control registers

(2) Prescaler

• Timer control register W1

Prescaler is a frequency divider. Its frequency dividing ratio can be

selected. The count source of prescaler is the instruction clock.

Use the bit 2 of register W1 to select the prescaler dividing ratio

and the bit 3 to start and stop its operation. Prescaler is initialized,

and the output signal (ORCLK) stops when the bit 3 of register W1

is cleared to “0.”

Register W1 controls the count operation of timer 1, the selection

of count start synchronous circuit, and the frequency dividing ra-

tio and count operation of prescaler. Set the contents of this

register through register A with the TW1A instruction. The TAW1

instruction can be used to transfer the contents of register W1 to

register A.

• Timer control register W2

Register W2 controls the selection of timer 1 count auto-stop cir-

cuit, and the count operation and count source of timer 2. Set the

contents of this register through register A with the TW2A instruc-

tion. The TAW2 instruction can be used to transfer the contents

of register W2 to register A.

• Timer control register W6

Register W6 controls the P12/CNTR pin function and the selec-

tion of CNTR output. Set the contents of this register through

register A with the TW6A instruction. The TAW6 instruction can

be used to transfer the contents of register W6 to register A..

26

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(3) Timer 1 (interrupt function)

(5) Timer interrupt request flags (T1F, T2F)

Each timer interrupt request flag is set to “1” when each timer

underflows. The state of these flags can be examined with the skip

instructions (SNZT1, SNZT2).

Timer 1 is an 8-bit binary down counter with the timer 1 reload reg-

ister (R1). Data can be set simultaneously in timer 1 and the reload

register (R1) with the T1AB instruction. Stop counting and then ex-

ecute the T1AB instruction to set data to timer 1. Data can be

written to reload register (R1) with the TR1AB instruction.

When writing data to reload register R1 with the TR1AB instruction,

the downcount after the underflow is started from the setting value

of reload register R1.

Use the interrupt control register V1 to select an interrupt or a skip

instruction.

An interrupt request flag is cleared to “0” when an interrupt occurs

or when the next instruction is skipped with a skip instruction.

Timer 1 starts counting after the following process;

➀ set data in timer 1, and

(6) Count start synchronization circuit (timer 1)

Timer 1 has the count start synchronous circuit which synchronizes

the input of INT pin, and can start the timer count operation.

Timer 1 count start synchronous circuit function is selected by set-

ting the bit 0 of register W1 to “1.” The control by INT pin input can

be performed by setting the bit 0 of register I1 to “1.”

The count start synchronous circuit is set by level change (“H”→“L”

or “L”→“H”) of INT pin input. This valid waveform is selected by bits

1 (I11) and 2 (I12) of register I1 as follows;

➀ set the bit 1 of register W1 to “1.”

However, INT pin input can be used as the start trigger for timer 1

count operation by setting the bit 0 of register W1 to “1.”

Also, in this time, the auto-stop function by timer 1 underflow can

be performed by setting the bit 2 of register W2 to “1.”

When a value set is n, timer 1 divides the count source signal by n

+ 1 (n = 0 to 255).

Once count is started, when timer 1 underflows (the next count

pulse is input after the contents of timer 1 becomes “0”), the timer

1 interrupt request flag (T1F) is set to “1,” new data is loaded from

reload register R1, and count continues (auto-reload function).

Data can be read from timer 1 with the TAB1 instruction. When

reading the data, stop the counter and then execute the TAB1 in-

struction.

• I11 = “0”: Synchronized with one-sided edge (falling or rising)

• I11 = “1”: Synchronized with both edges (both falling and rising)

When register I11=“0” (synchronized with the one-sided edge), the ris-

ing or falling waveform can be selected by the bit 2 of register I1;

• I12 = “0”: Falling waveform

• I12 = “1”: Rising waveform

When timer 1 count start synchronous circuit is used, the count

start synchronous circuit is set, the count source is input to each

timer by inputting valid waveform to INT pin. Once set, the count

start synchronous circuit is cleared by clearing the bit I10 to “0” or

reset.

(4) Timer 2 (interrupt function)

Timer 2 is an 8-bit binary down counter with the timer 2 reload reg-

ister (R2). Data can be set simultaneously in timer 2 and the reload

register (R2) with the T2AB instruction. Stop counting and then ex-

ecute the T2AB instruction to set data to timer 2.

Timer 2 starts counting after the following process;

➀ set data in timer 2,

However, when the count auto-stop circuit is selected (register W22

= “1”), the count start synchronous circuit is cleared (auto-stop) at

the timer 1 underflow.

➀ select the count source with the bits 0 and 1 of register W2, and

➀ set the bit 3 of register W2 to “1.”

(7) Count auto-stop circuit (timer 1)

Timer 1 has the count auto-stop circuit which is used to stop timer

1 automatically by the timer 1 underflow when the count start syn-

chronous circuit is used.

When a value set is n, timer 2 divides the count source signal by n

+ 1 (n = 0 to 255).

Once count is started, when timer 2 underflows (the next count

pulse is input after the contents of timer 2 becomes “0”), the timer

2 interrupt request flag (T2F) is set to “1,” new data is loaded from

reload register R2, and count continues (auto-reload function).

Data can be read from timer 2 with the TAB2 instruction. When

reading the data, stop the counter and then execute the TAB2 in-

struction.

The count auto-stop cicuit is valid by setting the bit 2 of register W2

to “1”. It is cleared by the timer 1 underflow and the count source to

timer 1 is stopped.

This function is valid only when the timer 1 count start synchronous

circuit is selected.

27

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(8) Timer input/output pin (P12/CNTR pin)

CNTR pin is used to input the timer 2 count source and output the

timer 1 and timer 2 underflow signal divided by 2.

(9) Precautions

Note the following for the use of timers.

• Prescaler

The P12/CNTR pin function can be selected by bit 0 of register W6.

The CNTR output signal can be selected by bit 1 of register W6.

When the CNTR input is selected for timer 2 count source, timer 2

counts the falling waveform of CNTR input.

Stop the prescaler operation to change its frequency dividing ra-

tio.

• Count source

Stop timer 1 or 2 counting to change its count source.

• Reading the count value

Stop timer 1 or 2 counting and then execute the TAB1 or TAB2

instruction to read its data.

• Writing to the timer

Stop timer 1 or 2 counting and then execute the T1AB or T2AB

instruction to write its data.

• Writing to reload register R1

When writing data to reload register R1 while timer 1 is operat-

ing, avoid a timing when timer 1 underflows.

CNTR input

(Note)

Timer 2 count

0316

0216

0116

0016

FF16

FE16

Timer 2 interrupt

request flag

(T2F)

Note: This is an example when “FF16” is set to timer 2 reload register R2L.

Fig. 23 Count timing diagram at CNTR input

28

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

Watchdog timer provides a method to reset the system when a pro-

gram run-away occurs. Watchdog timer consists of timer

WDT(16-bit binary counter), watchdog timer enable flag (WEF),

and watchdog timer flags (WDF1, WDF2).

When the WEF flag is set to “1” after system is released from reset,

the watchdog timer function is valid.

When the DWDT instruction and the WRST instruction are ex-

ecuted continuously, the WEF flag is cleared to “0” and the

watchdog timer function is invalid.

The timer WDT downcounts the instruction clocks as the count

source from “FFFF16” after system is released from reset.

After the count is started, when the timer WDT underflow occurs

(after the count value of timer WDT reaches “FFFF16,” the next

count pulse is input), the WDF1 flag is set to “1.”

However, in order to set the WEF flag to “1” again once it has

cleared to “0”, execute system reset.

The WRST instruction has the skip function. When the WRST in-

struction is executed while the WDF1 flag is “1”, the WDF1 flag is

cleared to “0” and the next instruction is skipped.

If the WRST instruction is never executed until the timer WDT un-

derflow occurs (until timer WDT counts 65534), WDF2 flag is set to

“1,” and the RESET pin outputs “L” level to reset the microcom-

puter.

When the WRST instruction is executed while the WDF1 flag is “0”,

the next instruction is not skipped.

The skip function of the WRST instruction can be used even when

the watchdog timer function is invalid.

Execute the WRST instruction at each period of 65534 machine

cycle or less by software when using watchdog timer to keep the

microcomputer operating normally.

FFFF16

Value of 16-bit timer (WDT)

000016

➀

WDF1 flag

65534 count

(Note)

➀

WDF2 flag

RESET pin output

➀ WRST instruction

executed

➀ Reset

released

➀ System reset

(skip executed)

➀ After system is released from reset (= after program is started), timer WDT starts count down.

➀ When timer WDT underflow occurs, WDF1 flag is set to “1.”

➀ When the WRST instruction is executed, WDF1 flag is cleared to “0,” the next instruction is skipped.

➀ When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the

watchdog reset signal is output.

➀ The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is

executed.

Note: The number of count is equal to the number of cycle because the count source of watchdog timer

is the instruction clock.

Fig. 24 Watchdog timer function

29

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

When the watchdog timer is used, clear the WDF1 flag at the pe-

riod of 65534 machine cycles or less with the WRST instruction.

When the watchdog timer is not used, execute the DWDT instruc-

tion and the WRST instruction continuously (refer to Figure 25).

The watchdog timer is not stopped with only the DWDT instruction.

The contents of WDF1 flag and timer WDT are initialized at the

RAM back-up mode.

WRST

; WDF1 flag cleared

DWDT

WRST

; Watchdog timer function enabled/disabled

; WEF and WDF1 flags cleared

When using the watchdog timer and the RAM back-up mode, ini-

tialize the WDF1 flag with the WRST instruction just before the

microcomputer enters the RAM back-up state (refer to Figure 26)

The watchdog timer function is valid after system is returned from

the RAM back-up. When not using the watchdog timer function, ex-

ecute the DWDT instruction and the WRST instruction continuously

every system is returned from the RAM back-up, and stop the

watchdog timer function.

Fig. 25 Program example to start/stop watchdog timer

WRST

NOP

DI

; WDF1 flag cleared

; Interrupt disabled

EPOF

POF

↓

; POF instruction enabled

Oscillation stop (RAM back-up mode)

Fig. 26 Program example to enter the RAM back-up mode

when using the watchdog timer

30

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

A-D CONVERTER

Table 11 A-D converter characteristics

Parameter

Conversion format

Resolution

Characteristics

Successive comparison method

10 bits

The 4501 Group has a built-in A-D conversion circuit that performs

conversion by 10-bit successive comparison method. Table 11

shows the characteristics of this A-D converter. This A-D converter

can also be used as an 8-bit comparator to compare analog volt-

ages input from the analog input pin with preset values.

Relative accuracy

Linearity error: ±2LSB

Non-linearity error: ±0.9LSB

Conversion speed

Analog input pin

46.5 µs (High-speed mode at 4.0 MHz

oscillation frequency)

2

Register B (4)

Register A (4)

4

8

4

8

4

IAP2

(P2 , P2

TAQ1

TQ1A

0

1

)

2

OP2A

(P2 , P2

Q13 Q12 Q11 Q10

0

1

TALA

TABAD

TADAB

Instruction clock

1/6

2

Q1

3

0

1

ADF

(1)

A-D

interrupt

A-D control circuit

P2

0

/AIN0

/AIN1

1

Comparator

Successive comparison

register (AD) (10)

0

1

Q1

3

Q1

3

8

10

1

0

1

DAC

0

1

operation

signal

Q1

3

8

DAC

8

DA converter

(Note 1)

VDD

VSS

Comparator register (8)

(Note 2)

Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage.

2: Writing/reading data to the comparator register is possible only in the comparator mode (Q1 =1).

The value of the comparator register is retained even when the mode is switched to the A-D conversion

mode (Q1 =0) because it is separated from the successive comparison register (AD). Also, the resolution

in the comparator mode is 8 bits because the comparator register consists of 8 bits.

3

Fig. 27 A-D conversion circuit structure

31

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 12 A-D control registers

A-D control register Q1

at reset : 00002

at RAM back-up : state retained

R/W

A-D conversion mode

Comparator mode

0

A-D operation mode selection bit

Not used

Q13

Q12

1

0

1

This bit has no function, but read/write is enabled.

Q11 Q10

Selected pins

Q11

Q10

0

1

0

1

0

1

AIN0

Analog input pin selection bits

AIN1

Not available

Note: “R” represents read enabled, and “W” represents write enabled.

(1) Operating at A-D conversion mode

The A-D conversion mode is set by setting the bit 3 of register Q1 to “0.”

(6) Operation description

A-D conversion is started with the A-D conversion start instruction

(ADST). The internal operation during A-D conversion is as follows:

(2) Successive comparison register AD

Register AD stores the A-D conversion result of an analog input in

10-bit digital data format. The contents of the high-order 8 bits of

this register can be stored in register B and register A with the

TABAD instruction. The contents of the low-order 2 bits of this reg-

ister can be stored into the high-order 2 bits of register A with the

TALA instruction. However, do not execute these instructions dur-

ing A-D conversion.

➀ When the A-D conversion starts, the register AD is cleared to

“00016.”

➀ Next, the topmost bit of the register AD is set to “1,” and the

comparison voltage Vref is compared with the analog input volt-

age VIN.

➀ When the comparison result is Vref < VIN, the topmost bit of the

register AD remains set to “1.” When the comparison result is

Vref > VIN, it is cleared to “0.”

When the contents of register AD is n, the logic value of the com-

parison voltage Vref generated from the built-in DA converter can

be obtained with the reference voltage VDD by the following for-

mula:

The 4501 Group repeats this operation to the lowermost bit of the

register AD to convert an analog value to a digital value. A-D con-

version stops after 62 machine cycles (46.5 µs when f(XIN) = 4.0

MHz in high-speed mode) from the start, and the conversion result

is stored in the register AD. An A-D interrupt activated condition is

satisfied and the ADF flag is set to “1” as soon as A-D conversion

completes (Figure 28).

Logic value of comparison voltage Vref

VDD

Vref =

➀ n

1024

n: The value of register AD (n = 0 to 1023)

(3) A-D conversion completion flag (ADF)

A-D conversion completion flag (ADF) is set to “1” when A-D con-

version completes. The state of ADF flag can be examined with the

skip instruction (SNZAD). Use the interrupt control register V2 to

select the interrupt or the skip instruction.

The ADF flag is cleared to “0” when the interrupt occurs or when

the next instruction is skipped with the skip instruction.

(4) A-D conversion start instruction (ADST)

A-D conversion starts when the ADST instruction is executed. The

conversion result is automatically stored in the register AD.

(5) A-D control register Q1

Register Q1 is used to select the operation mode and one of ana-

log input pins.

32

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 13 Change of successive comparison register AD during A-D conversion

Comparison voltage (Vref) value

VDD

At starting conversion

1st comparison

Change of successive comparison register AD

-------------

-----

1

0

1

0

1

0

-------------

2

-------------

VDD

2

VDD

4

-----

➀1

2nd comparison

3rd comparison

±

-------------

VDD

2

VDD

4

VDD

8

-----

➀2

±

-------------

A-D conversion result

After 10th comparison

completes

VDD

2

VDD

-------------

-----

➀1

➀2

➀3

➀8

➀9

➀A

1024

-------------

➀1: 1st comparison result

➀3: 3rd comparison result

➀9: 9th comparison result

➀2: 2nd comparison result

➀8: 8th comparison result

➀A: 10th comparison result

(7) A-D conversion timing chart

Figure 28 shows the A-D conversion timing chart.

ADST instruction

62 machine cycles

A-D conversion

completion flag (ADF)

DAC operation signal

Fig. 28 A-D conversion timing chart

(8) How to use A-D conversion

How to use A-D conversion is explained using as example in which

the analog input from P21/AIN1 pin is A-D converted, and the high-

order 4 bits of the converted data are stored in address M(Z, X, Y)

= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),

and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.

The A-D interrupt is not used in this example.

(Bit 3)

(Bit 0)

A-D control register Q1

0

1

A^IN1pin selected

➀ Select the AIN1 pin function and A-D conversion mode with the

register Q1 (refer to Figure 29).

A-D conversion mode

➀ Execute the ADST instruction and start A-D conversion.

➀ Examine the state of ADF flag with the SNZAD instruction to de-

termine the end of A-D conversion.

Fig. 29 Setting registers

➀ Transfer the low-order 2 bits of converted data to the high-order

2 bits of register A (TALA instruction).

➀ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).

➀ Transfer the high-order 8 bits of converted data to registers A

and B (TABAD instruction).

➀ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).

➀ Transfer the contents of register B to register A, and then, store

into M(Z, X, Y) = (0, 0, 0).

33

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(9) Operation at comparator mode

The A-D converter is set to comparator mode by setting bit 3 of the

register Q1 to “1.”

(12) Comparator operation start instruction

(ADST instruction)

In comparator mode, executing ADST starts the comparator oper-

Below, the operation at comparator mode is described.

ating.

The comparator stops 8 machine cycles after it has started (6 µs at

f(XIN) = 4.0 MHz in high-speed mode). When the analog input volt-

age is lower than the comparison voltage, the ADF flag is set to “1.”

(10) Comparator register

In comparator mode, the built-in DA comparator is connected to the

8-bit comparator register as a register for setting comparison volt-

ages. The contents of register B is stored in the high-order 4 bits of

the comparator register and the contents of register A is stored in

the low-order 4 bits of the comparator register with the TADAB in-

struction.

(13) Notes for the use of A-D conversion 1

Note the following when using the analog input pins also for port

P2 function:

• Selection of analog input pins

When changing from A-D conversion mode to comparator mode,

the result of A-D conversion (register AD) is undefined.

However, because the comparator register is separated from regis-

ter AD, the value is retained even when changing from comparator

mode to A-D conversion mode. Note that the comparator register

can be written and read at only comparator mode.

Even when P20/AIN0, P21/AIN1 are set to pins for analog input,

they continue to function as port P2 input/output. Accordingly,

when any of them are used as I/O port and others are used as

analog input pins, make sure to set the outputs of pins that are

set for analog input to “1.” Also, the port input function of the pin

functions as an analog input is undefined.

If the value in the comparator register is n, the logic value of com-

parison voltage Vref generated by the built-in DA converter can be

determined from the following formula:

• TALA instruction

When the TALA instruction is executed, the low-order 2 bits of

register AD is transferred to the high-order 2 bits of register A, si-

multaneously, the low-order 2 bits of register A is “0.”

Logic value of comparison voltage Vref

(14) Notes for the use of A-D conversion 2

Do not change the operating mode (both A-D conversion mode and

comparator mode) of A-D converter with the bit 3 of register Q1

while the A-D converter is operating.

VDD

Vref =

➀ n

256

n: The value of register AD (n = 0 to 255)

When the operating mode of A-D converter is changed from the

comparator mode to A-D conversion mode with the bit 3 of register

Q1, note the following;

(11) Comparison result store flag (ADF)

In comparator mode, the ADF flag, which shows completion of A-D

conversion, stores the results of comparing the analog input volt-

age with the comparison voltage. When the analog input voltage is

lower than the comparison voltage, the ADF flag is set to “1.” The

state of ADF flag can be examined with the skip instruction

(SNZAD). Use the interrupt control register V2 to select the inter-

rupt or the skip instruction.

• Clear the bit 2 of register V2 to “0” to change the operating mode

of the A-D converter from the comparator mode to A-D conver-

sion mode with the bit 3 of register Q1.

• The A-D conversion completion flag (ADF) may be set when the

operating mode of the A-D converter is changed from the com-

parator mode to the A-D conversion mode. Accordingly, set a

value to the bit 3 of register Q1, and execute the SNZAD instruc-

tion to clear the ADF flag.

The ADF flag is cleared to “0” when the interrupt occurs or when

the next instruction is skipped with the skip instruction.

ADST instruction

8 machine cycles

Comparison result

store flag(ADF)

DAC operation signal

Comparator operation completed.

(The value of ADF is determined)

Fig. 30 Comparator operation timing chart

34

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(15) Definition of A-D converter accuracy

The A-D conversion accuracy is defined below (refer to Figure 31).

Vn: Analog input voltage when the output data changes from “n” to

“n+1” (n = 0 to 1022)

VFST–V0T

• Relative accuracy

• 1LSB at relative accuracy →

(V)

1022

➀ Zero transition voltage (V0T)

This means an analog input voltage when the actual A-D con-

version output data changes from “0” to “1.”

➀ Full-scale transition voltage (VFST)

VDD

• 1LSB at absolute accuracy →

(V)

1024

This means an analog input voltage when the actual A-D con-

version output data changes from “1023” to ”1022.”

➀ Linearity error

This means a deviation from the line between V0T and VFST of

a converted value between V0T and VFST.

➀ Differential non-linearity error

This means a deviation from the input potential difference re-

quired to change a converter value between V0T and VFST by 1

LSB at the relative accuracy.

• Absolute accuracy

This means a deviation from the ideal characteristics between 0

to VDD of actual A-D conversion characteristics.

Output data

Full-scale transition voltage (V^FST

)

1023

1022

b–a

a

Differential non-linearity error =

c

[LSB]

Linearity error =

[LSB]

b

a

n+1

n

Actual A-D conversion

characteristics

c

a: 1LSB by relative accuracy

b: Vⁿ⁺¹–V

c: Difference between ideal V

and actual V

n

Ideal line of A-D conversion

between V

0

–V1022

1

0

V

n

Vn+1

V

0

V1

V

1022

VDD

Analog voltage

Zero transition voltage (V0T

)

Fig. 31 Definition of A-D conversion accuracy

35

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

RESET FUNCTION

System reset is performed by applying “L” level to RESET pin for

1 machine cycle or more when the following condition is satisfied;

the value of supply voltage is the minimum value or more of the

recommended operating conditions.

Then when “H” level is applied to RESET pin, software starts from

address 0 in page 0.

f(XIN

)

RESET

Ring oscillator (internal oscillator)

is counted 5359 times.

Program starts

(address 0 in page 0)

Fig. 32 Reset release timing

Reset input

Ring oscillator (internal oscillator)

1 machine cycle or more

is counted 5359 times.

0.85VDD

Program starts

(address 0 in page 0)

RESET

0.3VDD

(Note)

Note: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.

Fig. 33 RESET pin input waveform and reset operation

36

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(1) Power-on reset

time exceeds 100 µs, connect a capacitor between the RESET pin

and VSS at the shortest distance, and input “L” level to RESET pin

until the value of supply voltage reaches the minimum operating

voltage.

Reset can be automatically performed at power on (power-on re-

set) by the built-in power-on reset circuit. When the built-in

power-on reset circuit is used, the time for the supply voltage to

rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising

100 µs or less

VDD (Note 3)

Pull-up transistor

Power-on reset circuit output

(Note 1)

(Note 2)

RESET pin

Internal reset signal

Power-on reset circuit

(Note 1)

Volgate drop detection circuit

Watchdog reset signal

Internal reset signal

WEF

Reset

state

Power-on

Reset released

This symbol represents a parasitic diode.

Notes 1:

2: Applied potential to RESET pin must be VDD or less.

3: Keep the value of supply voltage to the minimum value

or more of the recommended operating conditions.

Fig. 34 Power-on reset circuit example

Table 14 Port state at reset

State

Name

D0, D1

Function

High-impedance (Note 1)

D0, D1

High-impedance (Notes 1, 2)

D2/C, D3/K

D2, D3

P00, P01, P02, P03

P10, P11, P12/CNTR, P13/INT

P20/AIN0, P21/AIN1

P00–P03

P10–P13

P20, P21

Notes 1: Output latch is set to “1.”

2: Pull-up transistor is turned OFF.

37

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(2) Internal state at reset

Figure 35 shows internal state at reset (they are the same after sys-

tem is released from reset). The contents of timers, registers, flags

and RAM except shown in Figure 35 are undefined, so set the ini-

tial value to them.

• Program counter (PC) ..............................................................................0......0......0.......0......0...

Address 0 in page 0 is set to program counter.

0

• Interrupt enable flag (INTE)..................................................................................................

• Power down flag (P) .............................................................................................................

• External 0 interrupt request flag (EXF0) ..............................................................................

• Interrupt control register V1..................................................................................0.......0......0...

• Interrupt control register V2..................................................................................0.......0......0...

• Interrupt control register I1 ...................................................................................0.......0......0...

• Timer 1 interrupt request flag (T1F) .....................................................................................

• Timer 2 interrupt request flag (T2F) .....................................................................................

• Watchdog timer flags (WDF1, WDF2)..................................................................................

• Watchdog timer enable flag (WEF) ......................................................................................

• Timer control register W1 .....................................................................................0.......0......0...

• Timer control register W2 .....................................................................................0.......0......0...

• Timer control register W6 .....................................................................................0.......0......0...

• Clock control register MR .....................................................................................1.......1......0...

• Key-on wakeup control register K0 ......................................................................0.......0......0...

• Key-on wakeup control register K1 ......................................................................0.......0......0...

• Key-on wakeup control register K2 ......................................................................0.......0......0...

• Pull-up control register PU0 .................................................................................0.......0......0...

• Pull-up control register PU1 .................................................................................0.......0......0...

• Pull-up control register PU2 .................................................................................0.......0......0...

• A-D conversion completion flag (ADF) .................................................................................

• A-D control register Q1 .........................................................................................0.......0......0...

• Carry flag (CY) ......................................................................................................................

• Register A .............................................................................................................0.......0......0...

• Register B .............................................................................................................0.......0......0...

• Register D ....................................................................................................................➀......➀...

0

1

0

➀

0

➀

1

(Interrupt disabled)

(Prescaler and timer 1 stopped)

(Timer 2 stopped)

• Register E .................................................................................................➀......➀......➀.......➀......➀...

➀

• Register X .............................................................................................................0.......0......0...

• Register Y .............................................................................................................0.......0......0...

• Register Z ..........................................................................................................................➀...

• Stack pointer (SP) .......................................................................................................1......1...

• Oscillation clock .......................................................................... Ring oscillator (operating)

• Ceramic resonator circuit ..................................................................................... Operating

• RC oscillation circuit ...................................................................................................... Stop

“➀” represents undefined.

Fig. 35 Internal state at reset

38

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

VOLTAGE DROP DETECTION CIRCUIT

The built-in voltage drop detection circuit is designed to detect a

drop in voltage and to reset the microcomputer if the supply voltage

drops below a set value.

Q

S

R

EPOF instruction +POF2 instruction

(continuousu execution)

(Note 1)

Reset signal

Return input

V

DD

–

+

Voltage drop detection circuit

reset signal

(Note 2)

VRST

Voltage drop detection circuit

Notes 1: In the RAM back-up mode by the POF2 instruction,

the voltage drop detection circuit stops.

2: When the VDD (supply voltage) is VRST (detection voltage) or less,

the voltage drop detection circuit reset signal is output.

Fig. 36 Voltage drop detection reset circuit

V

DD

Note 3

VRST

(detection voltage)

Voltage drop detection

circuit reset signal

The microcomputer starts

operation after the ring

oscillator (internal oscillator) is

counted 5359 times.

RESET pin

Notes 1: After system is released from reset, the ring oscillator (internal oscillator)

is selected as the operation clock of the microcomputer.

2: Refer to the voltage drop detection circuit in the electrical characteristics

for the rating value of VRST (detection voltage).

3: The VRST (detection voltage) does not include hysteresis.

Fig. 37 Voltage drop detection circuit operation waveform

39

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

RAM BACK-UP MODE

Table 15 Functions and states retained at RAM back-up

The 4501 Group has the RAM back-up mode.

When the POF or POF2 instruction is executed continuously after

the EPOF instruction, system enters the RAM back-up state.

The POF or POF2 instruction is equal to the NOP instruction when

the EPOF instruction is not executed before the POF or POF2 in-

struction.

RAM back-up

Function

POF

POF2

Program counter (PC), registers A, B,

carry flag (CY), stack pointer (SP) (Note 2)

Contents of RAM

✕

O

Port level

As oscillation stops retaining RAM, the function of reset circuit and

states at RAM back-up mode, current dissipation can be reduced

without losing the contents of RAM.

O

Selected oscillation circuit

✕

O

✕

O

Timer control register W1

Timer control registers W2, W6

Clock control register MR

In the RAM back-up mode by the POF instruction, system enters

the RAM back-up mode and the voltage drop detection cicuit keeps

operating.

✕

O

✕

O

Interrupt control registers V1, V2

Interrupt control register I1

Timer 1 function

In the RAM back-up mode by the POF2 instruction, all internal

periperal functions stop.

✕

Table 15 shows the function and states retained at RAM back-up.

Figure 38 shows the state transition.

(Note 3) (Note 3)

Timer 2 function

✕

O

A-D conversion function

O (Note 5)

Voltage drop detection circuit

A-D control register Q1

(1) Identification of the start condition

O

Warm start (return from the RAM back-up state) or cold start (re-

turn from the normal reset state) can be identified by examining the

state of the power down flag (P) with the SNZP instruction.

O

Pull-up control registers PU0 to PU2

Key-on wakeup control registers K0 to K2

External 0 interrupt request flag (EXF0)

Timer 1 interrupt request flag (T1F)

Timer 2 interrupt request flag (T2F)

Watchdog timer flags (WDF1)

Watchdog timer enable flag (WEF)

16-bit timer (WDT)

O

✕

(2) Warm start condition

(Note 3) (Note 3)

When the external wakeup signal is input after the system enters

the RAM back-up state by executing the EPOF instruction and

POF or POF2 instruction continuously, the CPU starts executing

the program from address 0 in page 0. In this case, the P flag is

“1.”

✕ (Note 4) ✕ (Note 4)

✕

✕ (Note 4) ✕ (Note 4)

✕

A-D conversion completion flag (ADF)

Interrupt enable flag (INTE)

Notes 1:“O” represents that the function can be retained, and “✕” repre-

sents that the function is initialized.

(3) Cold start condition

The CPU starts executing the program from address 0 in page 0

Registers and flags other than the above are undefined at RAM

back-up, and set an initial value after returning.

when;

• reset pulse is input to RESET pin, or

• reset by watchdog timer is performed, or

• voltage drop detection circuit is detected by the voltage drop

In this case, the P flag is “0.”

2: The stack pointer (SP) points the level of the stack register and is

initialized to “7” at RAM back-up.

3: The state of the timer is undefined.

4: Initialize the watchdog timer with the WRST instruction, and then

execute the POF or POF2 instruction.

5: This function is operating in the RAM back-up mode. When the

voltage drop is detected, system reset occurs.

40

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(4) Return signal

• Pull-up control register PU0

An external wakeup signal is used to return from the RAM back-up

mode because the oscillation is stopped. Table 16 shows the return

condition for each return source.

Register PU0 controls the ON/OFF of the port P0 pull-up transis-

tor. Set the contents of this register through register A with the

TPU0A instruction.

• Pull-up control register PU1

(5) Control registers

Register PU1 controls the ON/OFF of the port P1 pull-up transis-

tor. Set the contents of this register through register A with the

TPU1A instruction.

• Key-on wakeup control register K0

Register K0 controls the port P0 key-on wakeup function. Set the

contents of this register through register A with the TK0A instruc-

tion. In addition, the TAK0 instruction can be used to transfer the

contents of register K0 to register A.

• Pull-up control register PU2

Register PU2 controls the ON/OFF of the ports P2, D2/C and D3/

K pull-up transistor. Set the contents of this register through reg-

ister A with the TPU2A instruction.

• Key-on wakeup control register K1

Register K1 controls the port P1 key-on wakeup function. Set the

contents of this register through register A with the TK1A instruc-

tion. In addition, the TAK1 instruction can be used to transfer the

contents of register K0 to register A.

• Interrupt control register I1

Register I1 controls the valid waveform of the external 0 inter-

rupt, the input control of INT pin and the return input level. Set

the contents of this register through register A with the TI1A in-

struction. In addition, the TAI1 instruction can be used to transfer

the contents of register I1 to register A.

• Key-on wakeup control register K2

Register K2 controls the ports P2, D2/C and D3/K key-on wakeup

function. Set the contents of this register through register A with

the TK2A instruction. In addition, the TAK2 instruction can be

used to transfer the contents of register K2 to register A.

Table 16 Return source and return condition

Remarks

Return source

Port P0

Return condition

The key-on wakeup function can be selected by one port unit. Set the port

using the key-on wakeup function to “H” level before going into the RAM

back-up state.

Return by an external “L” level in-

put.

Port P1 (Note)

Port P2

Ports D2/C, D3/K

Port P13/INT

(Note)

Return by an external “H” level or Select the return level (“L” level or “H” level) with the bit 2 of register I1 ac-

“L” level input. The return level cording to the external state before going into the RAM back-up state.

can be selected with the bit 2

(I12) of register I1.

When the return level is input, the

EXF0 flag is not set.

Note: When the bit 3 (K13) of register K1 is “0”, the key-on wakeup of the INT pin is valid (“H” or “L” level).

It is “1”, the key-on wakeup of port P13 is valid (“L” level).

41

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

B

D

E

POF instruction execution

POF2 instruction execution

Operating

RAM back-up

Operation source clock:

ceramic resonator

(Voltage drop detection

circuit is operating.)

(All functions of

microcomputer stop)

Key-on wakeup

(Stabilizing time b )

Ring oscillator: stop

(Stabilizing time b )

RC oscillation circuit: stop

CMCK instruction

execution (Note 3)

POF instruction execution

A

POF2 instruction execution

Operating

(Stabilizing

time a )

Voltage drop

detected

Operation source clock:

ring oscillator clock

Reset

Key-on wakeup

Ceramic resonator:

Key-on wakeup

(Stabilizing time a )

operating (Note 2)

RC oscillation circuit: stop

(Stabilizing time a )

CRCK instruction

execution (Note 3)

C

POF instruction execution

POF2 instruction execution

Operating

Operation source clock:

RC oscillation

Key-on wakeup

Ring oscillator: stop

(Stabilizing time c )

Ceramic resonator: stop

Operation source clock: stop

Stabilizing time a : Microcomputer starts its operation after counting the ring oscillator clock 5359 times by hardware.

Stabilizing time b : Microcomputer starts its operation after counting the f(XIN) 5359 times by hardware.

Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) 165 times by hardware.

Notes 1: Continuous execution of the EPOF instruction and the POF or POF2 instruction is required to go into

the RAM back-up state.

2: Through the ceramic resonator is operating, the ring oscillator clock is selected as the operation source clock.

3: The oscillator clock corresponding to each instruction is selected as the operation source clock,

and the ring oscillator is stopped.

Fig. 38 State transition

Power down flag P

POF or

EPOF instruction +

POF2

instruction

S

Q

Program start

R

Reset input

Yes

P = “1”

?

POF or

POF2

No

• • • • • • •

✕ Set source

EPOF instruction +

instruction

Warm start

Cold start

✕ Clear source^{• • • • • •}Reset input

Fig. 39 Set source and clear source of the P flag

Fig. 40 Start condition identified example using the SNZP in-

struction

42

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 17 Key-on wakeup control register

Key-on wakeup control register K0

at reset : 00002

at RAM back-up : state retained

R/W

Port P03 key-on wakeup

0

1

0

1

0

1

0

1

Key-on wakeup not used

K03

control bit

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Port P02 key-on wakeup

K02

control bit

Port P01 key-on wakeup

K01

control bit

Port P00 key-on wakeup

K00

control bit

Key-on wakeup control register K1

at reset : 00002

at RAM back-up : state retained

Port P13/INT key-on wakeup

0

1

0

1

0

1

0

1

P13 key-on wakeup not used/INT pin key-on wakeup used

P13 key-on wakeup used/INT pin key-on wakeup not used

Key-on wakeup not used

K13

control bit

Port P12/CNTR key-on wakeup

K12

control bit

Key-on wakeup used

Port P11 key-on wakeup

Key-on wakeup not used

K11

control bit

Key-on wakeup used

Port P10 key-on wakeup

Key-on wakeup not used

K10

control bit

Key-on wakeup used

Key-on wakeup control register K2

at reset : 00002

at RAM back-up : state retained

Port D3/K key-on wakeup

0

1

0

1

0

1

0

1

Key-on wakeup not used

K23

control bit

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Port D2/C key-on wakeup

K22

control bit

Port P21/AIN1 key-on wakeup

K21

control bit

Port P20/AIN0 key-on wakeup

K20

control bit

Note: “R” represents read enabled, and “W” represents write enabled.

43

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Table 18 Pull-up control register and interrupt control register

Pull-up control register PU0

at reset : 00002

at RAM back-up : state retained

W

Port P03 pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

PU03

PU02

PU01

PU00

Port P02 pull-up transistor

control bit

Port P01 pull-up transistor

control bit

Port P00 pull-up transistor

control bit

Pull-up control register PU1

at reset : 00002

at RAM back-up : state retained

W

Port P13/INT pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

PU13

PU12

PU11

PU10

Port P12/CNTR pull-up transistor

control bit

Port P11 pull-up transistor

control bit

Port P10 pull-up transistor

control bit

Pull-up control register PU2

at reset : 00002

at RAM back-up : state retained

W

Port D3/K pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

PU23

PU22

PU21

PU20

Port D2/C pull-up transistor

control bit

Port P21/AIN1 pull-up transistor

control bit

Port P20/AIN0 pull-up transistor

control bit

Interrupt control register I1

at reset : 00002

INT pin input disabled

INT pin input enabled

at RAM back-up : state retained

R/W

0

1

INT pin input control bit (Note 2)

I13

I12

Falling waveform (“L” level of INT pin is recognized with the SNZI0

0

1

Interrupt valid waveform for INT pin/

return level selection bit (Note 2)

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

0

1

0

1

I11

I10

INT pin edge detection circuit control bit

INT pin

timer 1 control enable bit

Enabled

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-

struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

performed with the SNZ0 instruction.

44

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

The system clock and the instruction clock are generated as the

source clock for operation by these circuits.

CLOCK CONTROL

The clock control circuit consists of the following circuits.

• Ring oscillator (internal oscillator)

• Ceramic oscillator

Figure 41 shows the structure of the clock control circuit.

The 4501 Group operates by the ring oscillator clock (f(RING))

which is the internal oscillator after system is released from reset.

Also, the ceramic resonator or the RC oscillation can be used for

the source oscillation (f(XIN)) of the 4501 Group. The CMCK in-

struction or CRCK instruction is executed to select the ceramic

resonator or RC oscillator, respectively.

• RC oscillation circuit

• Multi-plexer (clock selection circuit)

• Frequency divider

• Internal clock generating circuit

MR3, MR

2

Division circuit

divided by 8

divided by 4

divided by 2

System clock

Internal clock

generation circuit

(divided by 3)

11

10

01

00

Instruction clock

Counter

Ring oscillator

(internal oscillator)

(Note 1)

Multiplexer

Q

S

R

Program

start signal

Wait time (Note 2)

control circuit

RC oscillation circuit

CRCK instruction

Q

S

R

X

IN

Ceramic resonator

circuit

X

OUT

S

R

CMCK

instruction

RESET pin

Q

S

Key-on wakeup signal

R

POF or

EPOF instruction + POF2

instruction

Notes 1: System operates by the ring oscillator clock (f(RING)) until the CMCK or CRCK instruction

is executed after system is released from reset.

2: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation.

After the certain oscillation stabilizing wait time elapses, the program start signal is output.

This circuit operates when system is released from reset or returned from RAM back-up.

Fig. 41 Clock control circuit structure

45

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(1) Selection of source oscillation (f(XIN))

The ceramic resonator or RC oscillation can be used for the source

oscillation of the MCU.

Reset

Ring oscillator

operation

After system is released from reset, the MCU starts operation by

the clock output from the ring oscillator which is the internal oscilla-

tor.

When the ceramic resonator is used, execute the CMCK instruc-

tion. When the RC oscillation is used, execute the CRCK

instruction. The oscillation circuit by the CMCK or CRCK instruction

can be selected only at once. The oscillation circuit corresponding

to the first executed one of these two instructions is valid. Other os-

cillation circuit and the ring oscillator stop.

CMCK instruction

CRCK instruction

• RC oscillation valid

• Ring oscillator stop

• Ceramic resonator stop

• Ceramic resonator valid

• Ring oscillator stop

• RC oscillation stop

Execute the CMCK or the CRCK instruction in the initial setting rou-

tine of program (executing it in address 0 in page 0 is

recommended). Also, when the CMCK or the CRCK instruction is

not executed in program, the MCU operates by the ring oscillator.

Fig. 42 Switch to ceramic resonance/RC oscillation

4501

Do not use the CMCK instruction

and CRCK instruction in program.

*

(2) Ring oscillator operation

XIN

XOUT

When the MCU operates by the ring oscillator as the source oscil-

lation (f(XIN)) without using the ceramic resonator or the RC

oscillator, connect XIN pin to VSS and leave XOUT pin open (Figure

43).

The clock frequency of the ring oscillator depends on the supply

voltage and the operation temperature range.

Be careful that variable frequencies when designing application

products.

Fig. 43 Handling of XIN and XOUT when operating ring oscillator

4501

Execute the CMCK instruc-

*

(3) Ceramic resonator

tion in program.

When the ceramic resonator is used as the source oscillation

(f(XIN)), connect the ceramic resonator and the external circuit to

pins XIN and XOUT at the shortest distance. Then, execute the

CMCK instruction. A feedback resistor is built in between pins XIN

and XOUT (Figure 44).

X

IN

XOUT

Note: Externally connect a damping

resistor Rd depending on the

oscillation frequency.

Rd

(A feedback resistor is built-in.)

Use the resonator manu-

facturer’s recommended value

because constants such as ca-

pacitance depend on the

resonator.

CIN

COUT

(4) RC oscillation

When the RC oscillation is used as the source oscillation (f(XIN)),

connect the XIN pin to the external circuit of resistor R and the ca-

pacitor C at the shortest distance and leave XOUT pin open. Then,

execute the CRCK instruction (Figure 45).

Fig. 44 Ceramic resonator external circuit

The frequency is affected by a capacitor, a resistor and a micro-

computer. So, set the constants within the range of the frequency

limits.

4501

Execute the CRCK

instruction in program.

*

R

C

XIN

XOUT

Fig. 45 External RC oscillation circuit

46

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) External clock

When the external signal clock is used as the source oscillation

(f(XIN)), connect the XIN pin to the clock source and leave XOUT pin

open. Then, execute the CMCK instruction (Figure 46).

Be careful that the maximum value of the oscillation frequency

when using the external clock differs from the value when using the

ceramic resonator (refer to the recommended operating condition).

Also, note that the RAM back-up mode (POF and POF2 instruc-

tions) cannot be used when using the external clock.

Execute the CMCK

instruction in program.

*

4501

V

DD

X

IN

XOUT

V

SS

(6) Clock control register MR

External oscillation circuit

Register MR controls system clock. Set the contents of this register

through register A with the TMRA instruction. In addition, the TAMR

instruction can be used to transfer the contents of register MR to

register A.

Fig. 46 External clock input circuit

Table 19 Clock control register MR

Clock control register MR

at reset : 11002

MR3 MR2

at RAM back-up : 11002

System clock

R/W

MR3

MR2

0

1

0

1

0

1

f(XIN) (high-speed mode)

System clock selection bits

f(XIN)/2 (middle-speed mode)

f(XIN)/4 (low-speed mode)

f(XIN)/8 (default mode)

0

1

0

1

MR1

MR0

Not used

This bit has no function, but read/write is enabled.

Note : “R” represents read enabled, and “W” represents write enabled.

ROM ORDERING METHOD

Please submit the information described below when ordering

Mask ROM.

(1) Mask ROM Order Confirmation Form ..................................... 1

(2) Data to be written into mask ROM ............................... EPROM

(three sets containing the identical data)

(3) Mark Specification Form .......................................................... 1

47

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

LIST OF PRECAUTIONS

¹⁰Watchdog timer

• The watchdog timer function is valid after system is released

from reset. When not using the watchdog timer function, execute

the DWDT instruction and the WRST instruction continuously,

and clear the WEF flag to “0” to stop the watchdog timer function.

• The watchdog timer function is valid after system is returned from

the RAM back-up. When not using the watchdog timer function,

execute the DWDT instruction and the WRST instruction continu-

ously every system is returned from the RAM back-up, and stop

the watchdog timer function.

✕Noise and latch-up prevention

Connect a capacitor on the following condition to prevent noise

and latch-up;

• connect a bypass capacitor (approx. 0.1 µF) between pins VDD

and VSS at the shortest distance,

• equalize its wiring in width and length, and

• use relatively thick wire.

In the One Time PROM version, CNVSS pin is also used as VPP

pin. Accordingly, when using this pin, connect this pin to VSS

through a resistor about 5 kΩ (connect this resistor to CNVSS/

VPP pin as close as possible).

11

Multifunction

• The input/output of D2, D3, P12 and P13 can be used even when

C, K, INT and CNTR (input) are selected.

✕Register initial values 1

• The input of P12 can be used even when CNTR (output) is selected.

• The input/output of P20 and P21 can be used even when AIN0 and

AIN1 are selected.

The initial value of the following registers are undefined after sys-

tem is released from reset. After system is released from reset,

set initial values.

• Register Z (2 bits)

¹²Program counter

• Register D (3 bits)

Make sure that the PCH does not specify after the last page of

the built-in ROM.

• Register E (8 bits)

✕Register initial values 2

¹³POF and POF2 instructions

The initial value of the following registers are undefined at RAM

When the POF or POF2 instruction is executed continuously af-

ter the EPOF instruction, system enters the RAM back-up state.

Note that system cannot enter the RAM back-up state when ex-

ecuting only the POF or POF2 instruction.

back-up. After system is returned from RAM back-up, set initial

values.

• Register Z (2 bits)

• Register X (4 bits)

• Register Y (4 bits)

• Register D (3 bits)

• Register E (8 bits)

Be sure to disable interrupts by executing the DI instruction be-

fore executing the EPOF instruction and the POF or POF2

instruction continuously.

14

P13/INT pin

✕ Stack registers (SK^S) and stack pointer (SP)

Note [1] on bit 3 of register I1

Stack registers (SKs) are eight identical registers, so that subrou-

tines can be nested up to 8 levels. However, one of stack

registers is used respectively when using an interrupt service

routine and when executing a table reference instruction. Accord-

ingly, be careful not to over the stack when performing these

operations together.

When the input of the INT pin is controlled with the bit 3 of regis-

ter I1 in software, be careful about the following notes.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 3 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 47✕)

and then, change the bit 3 of register I1.

✕Prescaler

Stop the prescaler operation to change its frequency dividing ra-

tio.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

after executing at least one instruction (refer to Figure 47✕).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 47✕).

✕Timer count source

Stop timer 1 or 2 counting to change its count source.

✕ Reading the count value

LA

4

8

; (✕✕✕02)

Stop timer 1 or 2 counting and then execute the TAB1 or TAB2

instruction to read its data.

TV1A

LA

; The SNZ0 instruction is valid ...........✕

; (1✕✕✕2)

TI1A

NOP

SNZ0

; Control of INT pin input is changed

........................................................... ✕

; The SNZ0 instruction is executed

(EXF0 flag cleared)

✕Writing to the timer

Stop timer 1 or 2 counting and then execute the T1AB or T2AB

instruction to write its data.

NOP

........................................................... ✕

✕Writing to reload register R1

When writing data to reload register R1 while timer 1 is operat-

ing, avoid a timing when timer 1 underflows.

✕ : these bits are not used here.

Fig. 47 External 0 interrupt program example-1

48

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

15

Power-on reset

Note [2] on bit 3 of register I1

Reset can be automatically performed at power on (power-on re-

set) by the built-in power-on reset circuit. When the built-in

power-on reset circuit is used, the time for the supply voltage to

rise from 0 V to 2.0 V must be set to 100 µs or less. If the rising

time exceeds 100 µs, connect a capacitor between the RESET

pin and VSS at the shortest distance, and input “L” level to RE-

SET pin until the value of supply voltage reaches the minimum

operating voltage.

When the bit 3 of register I1 is cleared, the RAM back-up mode is

selected and the input of INT pin is disabled, be careful about the

following notes.

• When the key-on wakeup function of port P13 is not used (regis-

ter K13 = “0”), clear bits 2 and 3 of register I1 before system

enters to the RAM back-up mode. (refer to Figure 48✕).

¹⁶Clock control

LA

0

; (00✕✕2)

Execute the CMCK or the CRCK instruction in the initial setting

routine of program (executing it in addres 0 in page 0 is recom-

mended).

TI1A

DI

; Input of INT disabled........................✕

EPOF

POF

The oscillation circuit by the CMCK or CRCK instruction can be

selected only at once. The oscillation circuit corresponding to the

first executed one of these two instruction is valid. Other oscilla-

tion circuits and the ring oscillator stop.

; RAM back-up

✕ : these bits are not used here.

17

Ring oscillator

Fig. 48 External 0 interrupt program example-2

The clock frequency of the ring oscillator depends on the supply

voltage and the operation temperature range.

Note [3] on bit 2 of register I1

Be careful that variable frequencies when designing application

products.

When the interrupt valid waveform of the P13/INT pin is changed

with the bit 2 of register I1 in software, be careful about the fol-

lowing notes.

Also, the oscillation stabilize wait time after system is released

from reset is generated by the ring oscillator clock. When consid-

ering the oscillation stabilize wait time after system is released

from reset, be careful that the variable frequency of the ring oscil-

lator clock.

• Depending on the input state of the P13/INT pin, the external 0 in-

terrupt request flag (EXF0) may be set when the bit 2 of register

I1 is changed. In order to avoid the occurrence of an unexpected

interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 49✕)

and then, change the bit 2 of register I1.

¹⁸External clock

When the external signal clock is used as the source oscillation

(f(XIN)), note that the RAM back-up mode (POF and POF2 in-

structions) cannot be used.

In addition, execute the SNZ0 instruction to clear the EXF0 flag

after executing at least one instruction (refer to Figure 49✕).

Also, set the NOP instruction for the case when a skip is per-

formed with the SNZ0 instruction (refer to Figure 49✕).

LA

4

; (✕✕✕02)

TV1A

LA

; The SNZ0 instruction is valid ...........✕

12

TI1A

NOP

SNZ0

; Interrupt valid waveform is changed

........................................................... ✕

; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP

........................................................... ✕

✕ : these bits are not used here.

Fig. 49 External 0 interrupt program example-3

49

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

20

18

Notes for the use of A-D conversion 3

Notes for the use of A-D conversion 1

Note the following when using the analog input pins also for port

P2 function:

Each analog input pin is equipped with a capacitor which is used

to compare the analog voltage. Accordingly, when the analog

voltage is input from the circuit with high-impedance and, charge/

discharge noise is generated and the sufficient A-D accuracy

may not be obtained. Therefore, reduce the impedance or, con-

nect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure

51).

• Selection of analog input pins

Even when P20/AIN0 and P21/AIN1 are set to pins for analog in-

put, they continue to function as port P2 input/output.

Accordingly, when any of them are used as I/O port and others

are used as analog input pins, make sure to set the outputs of

pins that are set for analog input to “1.” Also, the port input func-

tion of the pin functions as an analog input is undefined.

• TALA instruction

When the overvoltage applied to the A-D conversion circuit may

occur, connect an external circuit in order to keep the voltage

within the rated range as shown the Figure 52. In addition, test

the application products sufficiently.

When the TALA instruction is executed, the low-order 2 bits of

register AD is transferred to the high-order 2 bits of register A, si-

multaneously, the low-order 2 bits of register A is “0.”

19

Notes for the use of A-D conversion 2

Do not change the operating mode (both A-D conversion mode

and comparator mode) of A-D converter with the bit 3 of register

Q1 while the A-D converter is operating.

Sensor

AIN

When the operating mode of A-D converter is changed from the

comparator mode to A-D conversion mode with the bit 3 of regis-

ter Q1, note the following;

Apply the voltage withiin the specifications

to an analog input pin.

• Clear the bit 2 of register V2 to “0” (refer to Figure 50➀) to

change the operating mode of the A-D converter from the com-

parator mode to A-D conversion mode with the bit 3 of register

Q1.

Fig. 51 Analog input external circuit example-1

• The A-D conversion completion flag (ADF) may be set when the

operating mode of the A-D converter is changed from the com-

parator mode to the A-D conversion mode. Accordingly, set a

value to the bit 3 of register Q1, and execute the SNZAD instruc-

tion to clear the ADF flag.

About 1kΩ

Sensor

AIN

LA

8

0

; (➀0➀➀2)

TV2A

LA

; The SNZAD instruction is valid ........➀

; (0➀➀➀2)

Fig. 52 Analog input external circuit example-2

TQ1A

; Operation mode of A-D converter is

changed from comparator mode to A-D

conversion mode.

SNZAD

NOP

➀ : these bits are not used here.

Fig. 50 External 0 interrupt program example-3

50

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

CONTROL REGISTERS

Interrupt control register V1

at reset : 00002

at RAM back-up : 00002

R/W

0

1

0

1

0

1

0

1

Interrupt disabled (SNZT2 instruction is valid)

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

Not used

V13

V12

V11

V10

Interrupt enabled (SNZT2 instruction is invalid) (Note 2)

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid) (Note 2)

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZ0 instruction is valid)

External 0 interrupt enable bit

Interrupt enabled (SNZ0 instruction is invalid) (Note 2)

Interrupt control register V2

Not used

at reset : 00002

at RAM back-up : 00002

R/W

0

1

0

1

0

1

0

1

V23

V22

V21

V20

This bit has no function, but read/write is enabled.

Interrupt disabled (SNZAD instruction is valid)

A-D interrupt enable bit

Not used

Interrupt enabled (SNZAD instruction is invalid) (Note 2)

This bit has no function, but read/write is enabled.

Not used

Interrupt control register I1

at reset : 00002

INT pin input disabled

INT pin input enabled

at RAM back-up : state retained

R/W

0

1

INT pin input control bit (Note 3)

I13

I12

Falling waveform (“L” level of INT pin is recognized with the SNZI0

0

1

Interrupt valid waveform for INT pin/

return level selection bit (Note 3)

instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

0

1

0

1

I11

I10

INT pin edge detection circuit control bit

INT pin

timer 1 control enable bit

Enabled

Clock control register MR

System clock selection bits

at reset : 11002

MR3 MR2

at RAM back-up : 11002

System clock

R/W

MR3

MR2

0

1

0

1

0

1

f(XIN) (high-speed mode)

f(XIN)/2 (middle-speed mode)

f(XIN)/4 (low-speed mode)

f(XIN)/8 (default mode)

0

1

0

1

MR1

MR0

Not used

This bit has no function, but read/write is enabled.

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: These instructions are equivalent to the NOP instruction.

3: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-

struction when the bit 0 (V10) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

performed with the SNZ0 instruction.

51

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Timer control register W1

Prescaler control bit

at reset : 00002

at RAM back-up : 00002

R/W

Stop (state initialized)

Operating

0

1

0

1

0

1

0

1

W13

W12

W11

W10

Instruction clock divided by 4

Instruction clock divided by 16

Stop (state retained)

Prescaler dividing ratio selection bit

Timer 1 control bit

Operating

Count start synchronous circuit not selected

Count start synchronous circuit selected

Timer 1 count start synchronous circuit

control bit

Timer control register W2

Timer 2 control bit

at reset : 00002

at RAM back-up : state retained

R/W

0

1

0

1

Stop (state retained)

W23

W22

Operating

Count auto-stop circuit not selected

Count auto-stop circuit selected

Timer 1 count auto-stop circuit selection

bit (Note 2)

W21

Count source

W20

W21

W20

0

1

Timer 1 underflow signal

Prescaler output (ORCLK)

CNTR input

0

1

0

1

Timer 2 count source selection bits

System clock

Timer control register W6

Not used

at reset : 00002

at RAM back-up : state retained

R/W

0

W63

W62

W61

W60

This bit has no function, but read/write is enabled.

1

0

1

0

1

0

1

Not used

Timer 1 underflow signal divided by 2 output

Timer 2 underflow signal divided by 2 output

P12(I/O)/CNTR input (Note 3)

CNTR output selection bit

P12/CNTR function selection bit

P12 (input)/CNTR input/output (Note 3)

A-D control register Q1

A-D operation mode selection bit

Not used

at reset : 00002

at RAM back-up : state retained

R/W

A-D conversion mode

Comparator mode

0

Q13

Q12

1

0

1

This bit has no function, but read/write is enabled.

Q11 Q10

Selected pins

Q11

Q10

0

1

0

1

0

1

AIN0

Analog input pin selection bits

AIN1

Not available

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: This function is valid only when the timer 1 count start synchronization circuit is selected.

3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.

52

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Key-on wakeup control register K0

at reset : 00002

at RAM back-up : state retained

R/W

Port P03 key-on wakeup

control bit

0

1

0

1

0

1

0

1

Key-on wakeup not used

K03

K02

K01

K00

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Port P02 key-on wakeup

control bit

Port P01 key-on wakeup

control bit

Port P00 key-on wakeup

control bit

Key-on wakeup control register K1

at reset : 00002

at RAM back-up : state retained

Port P13/INT key-on wakeup

control bit

0

1

0

1

0

1

0

1

P13 key-on wakeup not used/INT pin key-on wakeup used

P13 key-on wakeup used/INT pin key-on wakeup not used

Key-on wakeup not used

K13

K12

K11

K10

Port P12/CNTR key-on wakeup

control bit

Key-on wakeup used

Port P11 key-on wakeup

control bit

Key-on wakeup not used

Key-on wakeup used

Port P10 key-on wakeup

control bit

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup control register K2

at reset : 00002

at RAM back-up : state retained

Port D3/K key-on wakeup

control bit

0

1

0

1

0

1

0

1

Key-on wakeup not used

K23

K22

K21

K20

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Port D2/C key-on wakeup

control bit

Port P21/AIN1 key-on wakeup

control bit

Port P20/AIN0 key-on wakeup

control bit

Note: “R” represents read enabled, and “W” represents write enabled.

53

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Pull-up control register PU0

at reset : 00002

at RAM back-up : state retained

W

Port P03 pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

PU03

PU02

PU01

PU00

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Port P02 pull-up transistor

control bit

Port P01 pull-up transistor

control bit

Port P00 pull-up transistor

control bit

Pull-up control register PU1

at reset : 00002

at RAM back-up : state retained

W

Port P13/INT pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

PU13

PU12

PU11

PU10

Port P12/CNTR pull-up transistor

control bit

Port P11 pull-up transistor

control bit

Port P10 pull-up transistor

control bit

Pull-up control register PU2

at reset : 00002

at RAM back-up : state retained

W

Port D3/K pull-up transistor

control bit

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

PU23

PU22

PU21

PU20

Port D2/C pull-up transistor

control bit

Port P21/AIN1 pull-up transistor

control bit

Port P20/AIN0 pull-up transistor

control bit

Notes 1: “R” represents read enabled, and “W” represents write enabled.

54

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INSTRUCTIONS

The 4501 Group has the 111 instructions. Each instruction is de-

scribed as follows;

(1) Index list of instruction function

(2) Machine instructions (index by alphabet)

(3) Machine instructions (index by function)

(4) Instruction code table

SYMBOL

The symbols shown below are used in the following list of instruc-

tion function and the machine instructions.

Symbol

Contents

Symbol

WDF1

Contents

Watchdog timer flag

A

B

Register A (4 bits)

Register B (4 bits)

Register D (3 bits)

Register E (8 bits)

WEF

INTE

EXF0

P

Watchdog timer enable flag

Interrupt enable flag

DR

E

External 0 interrupt request flag

Power down flag

Q1

V1

V2

I1

A-D control register Q1 (4 bits)

Interrupt control register V1 (4 bits)

Interrupt control register V2 (4 bits)

Interrupt control register I1 (4 bits)

Timer control register W1 (4 bits)

Timer control register W2 (4 bits)

Timer control register W6 (4 bits)

Clock control register MR (4 bits)

Key-on wakeup control register K0 (4 bits)

Key-on wakeup control register K1 (4 bits)

Key-on wakeup control register K2 (4 bits)

Pull-up control register PU0 (4 bits)

Pull-up control register PU1 (4 bits)

Pull-up control register PU2 (4 bits)

Register X (4 bits)

ADF

A-D conversion completion flag

D

Port D (4 bits)

Port P0 (4 bits)

Port P1 (4 bits)

Port P2 (2 bits)

Port C (1 bit)

W1

W2

W6

MR

K0

K1

K2

PU0

PU1

PU2

X

P0

P1

P2

C

K

Port K (1 bit)

x

Hexadecimal variable

Hexadecimal constant

Binary notation of hexadecimal variable A

(same for others)

y

z

p

n

Y

Register Y (4 bits)

i

Register Z (2 bits)

Z

j

DP

Data pointer (10 bits)

A3A2A1A0

(It consists of registers X, Y, and Z)

Program counter (14 bits)

PC

PCH

PCL

SK

High-order 7 bits of program counter

Low-order 7 bits of program counter

Stack register (14 bits ✕ 8)

Stack pointer (3 bits)

←

Direction of data movement

↔

Data exchange between a register and memory

Decision of state shown before “?”

?

SP

( )

—

Contents of registers and memories

CY

R1

Carry flag

Negate, Flag unchanged after executing instruction

RAM address pointed by the data pointer

Label indicating address a6 a5 a4 a3 a2 a1 a0

in page p5 p4 p3 p2 p1 p0

Timer 1 reload register

M(DP)

a

R2

Timer 2 reload register

T1

Timer 1

p, a

Timer 2

T2

T1F

T2F

Timer 1 interrupt request flag

Timer 2 interrupt request flag

C

+

x

Hex. C + Hex. number x (also same for others)

Note :Some instructions of the 4501 Group has the skip function to unexecute the next described instruction. The 4501 Group just invalidates the next instruc-

tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip

is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

55

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INDEX LIST OF INSTRUCTION FUNCTION

Group-

ing

Mnemonic

Function

Page

Mnemonic

XAMI j

Function

(A) ← → (M(DP))

Page

ing

(A) ← (B)

(B) ← (A)

(A) ← (Y)

(Y) ← (A)

TAB

75, 88

87, 88

(X) ← (X)EXOR(j)

j = 0 to 15

TBA

TAY

81, 88

86, 88

82, 88

(Y) ← (Y) + 1

TMA j

(M(DP)) ← (A)

(X) ← (X)EXOR(j)

j = 0 to 15

83, 88

TYA

TEAB

(E7–E4) ← (B)

(E3–E0) ← (A)

LA n

(A) ← n

66, 90

76, 90

n = 0 to 15

TABE

(B) ← (E7–E4)

(A) ← (E3–E0)

76, 88

TABP p

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

TDA

TAD

(DR2–DR0) ← (A2–A0)

82, 88

77, 88

(PCH) ← p (Note)

(PCL) ← (DR2–DR0, A3–A0)

(B) ← (ROM(PC))7–4

(A) ← (ROM(PC))3–0

(PC) ← (SK(SP))

(A2–A0) ← (DR2–DR0)

(A3) ← 0

TAZ

(A1, A0) ← (Z1, Z0)

(A3, A2) ← 0

81, 88

(SP) ← (SP) – 1

AM

(A) ← (A) + (M(DP))

60, 90

TAX

(A) ← (X)

81, 88

79, 88

AMC

(A) ← (A) + (M(DP)) + (CY)

(CY) ← Carry

(A2–A0) ← (SP2–SP0)

(A3) ← 0

TASP

A n

(A) ← (A) + n

60, 90

LXY x, y

(X) ← x x = 0 to 15

(Y) ← y y = 0 to 15

66, 88

n = 0 to 15

AND

OR

(A) ← (A) AND (M(DP))

(A) ← (A) OR (M(DP))

(CY) ← 1

61, 90

68, 90

71, 90

69, 90

74, 90

63, 90

69, 90

(Z) ← z z = 0 to 3

(Y) ← (Y) + 1

LZ z

INY

66, 88

63, 88

78, 88

SC

DEY

TAM j

(Y) ← (Y) – 1

RC

(CY) ← 0

(A) ← (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

SZC

CMA

RAR

(CY) = 0 ?

(A) ← (A)

XAM j

(A) ← → (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

87, 88

→ CY → A3A2A1A0

XAMD j

(A) ← → (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

(Y) ← (Y) – 1

Note: p is 0 to 15 for M34501M2,

p is 0 to 31 for M34501M4/E4.

56

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group-

ing

Group-

ing

Mnemonic

Function

Page

Mnemonic

DI

Function

Page

71, 90

(INTE) ← 0

(INTE) ← 1

64, 94

SB j

(Mj(DP)) ← 1

j = 0 to 3

EI

64, 94

72, 94

RB j

(Mj(DP)) ← 0

69, 90

74, 90

j = 0 to 3

SNZ0

V10 = 0: (EXF0) = 1 ?

After skipping, (EXF0) ← 0

V10 = 1: SNZ0 = NOP

SZB j

(Mj(DP)) = 0 ?

j = 0 to 3

SNZI0

I12 = 1 : (INT) = “H” ?

I12 = 0 : (INT) = “L” ?

73, 94

SEAM

SEA n

(A) = (M(DP)) ?

72, 90

(A) = n ?

TAV1

TV1A

TAV2

TV2A

TAI1

(A) ← (V1)

(V1) ← (A)

(A) ← (V2)

(V2) ← (A)

(A) ← (I1)

79, 94

85, 94

80, 94

85, 94

77, 94

82, 94

80, 94

85, 94

80, 94

86, 94

80, 94

86, 94

75, 94

n = 0 to 15

B a

(PCL) ← a6–a0

61, 92

BL p, a

(PCH) ← p (Note)

(PCL) ← a6–a0

BLA p

BM a

(PCH) ← p (Note)

61, 92

62, 92

(PCL) ← (DR2–DR0, A3–A0)

TI1A

(I1) ← (A)

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← 2

TAW1

TW1A

TAW2

TW2A

TAW6

TW6A

TAB1

(A) ← (W1)

(W1) ← (A)

(A) ← (W2)

(W2) ← (A)

(A) ← (W6)

(W6) ← (A)

(PCL) ← a6–a0

BML p, a (SP) ← (SP) + 1

(SK(SP)) ← (PC)

62, 92

(PCH) ← p (Note)

(PCL) ← a6–a0

BMLA p

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p (Note)

(B) ← (T17–T14)

(A) ← (T13–T10)

(PCL) ← (DR2–DR0, A3–A0)

RTI

RT

(PC) ← (SK(SP))

(SP) ← (SP) – 1

70, 92

T1AB

(R17–R14) ← (B)

(T17–T14) ← (B)

(R13–R10) ← (A)

(T13–T10) ← (A)

75, 94

(PC) ← (SK(SP))

(SP) ← (SP) – 1

RTS

(PC) ← (SK(SP))

(SP) ← (SP) – 1

TAB2

T2AB

(B) ← (T27–T24)

(A) ← (T23–T20)

76, 94

75, 94

(R27–R24) ← (B)

(T27–T24) ← (B)

(R23–R20) ← (A)

(T23–T20) ← (A)

Note: p is 0 to 15 for M34501M2,

p is 0 to 31 for M34501M4/E4.

57

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group-

ing

Group-

ing

Mnemonic

Function

Page

Mnemonic

IAK

Function

Page

TR1AB

(R17–R14) ← (B)

85, 94

(A0) ← (K)

65, 96

(R13–R10) ← (A)

(A3–A1) ← 0

SNZT1

SNZT2

V12 = 0: (T1F) = 1 ?

73, 94

74, 94

OKA

(K) ← (A0)

(K0) ← (A)

(A) ← (K0)

(K1) ← (A)

(A) ← (K1)

(K2) ← (A)

(A) ← (K2)

(PU0) ← (A)

(PU1) ← (A)

(PU2) ← (A)

67, 96

82, 96

77, 96

83, 96

78, 96

83, 96

78, 96

84, 96

76, 98

After skipping, (T1F) ← 0

V12 = 1: SNZT1 = NOP

TK0A

TAK0

V13 = 0: (T2F) = 1 ?

After skipping, (T2F) ← 0

V13 = 1: SNZT2 = NOP

TK1A

TAK1

IAP0

OP0A

IAP1

OP1A

IAP2

(A) ← (P0)

(P0) ← (A)

(A) ← (P1)

(P1) ← (A)

65, 96

67, 96

65, 96

67, 96

65, 96

TK2A

TAK2

TPU0A

TPU1A

TPU2A

TABAD

(A1, A0) ← (P21, P20)

(A3, A2) ← 0

OP2A

CLD

RD

(P21, P20) ← (A1, A0)

(D) ← 1

68, 96

62, 96

70, 96

In A-D conversion mode (Q13 = 0),

(B) ← (AD9–AD6)

(A) ← (AD5–AD2)

(D(Y)) ← 0

In comparator mode (Q13 = 1),

(B) ← (AD7–AD4)

(Y) = 0 to 3

(A) ← (AD3–AD0)

SD

(D(Y)) ← 1

71, 96

74, 96

(A3, A2) ← (AD1, AD0)

(A1, A0) ← 0

(Y) = 0 to 3

TALA

78, 98

77, 98

SZD

(D(Y)) = 0 ?

(Y) = 0 to 3

(AD7–AD4) ← (B)

(AD3–AD0) ← (A)

TADAB

SCP

(C) ← 1

(C) ← 0

(C) = 1 ?

71, 96

69, 96

73, 96

(A) ← (Q1)

(Q1) ← (A)

TAQ1

TQ1A

ADST

79, 98

84, 98

60, 98

RCP

SNZCP

(ADF) ← 0

Q13 = 0: A-D conversion starting

Q13 = 1: Comparator operation

starting

V22 = 0: (ADF) = 1 ?

SNZAD

72, 98

After skipping, (ADF) ← 0

V22 = 1: SNZAD = NOP

58

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INDEX LIST OF INSTRUCTION FUNCTION (continued)

Group-

ing

Mnemonic

Function

Page

NOP

(PC) ← (PC) + 1

67, 100

POF

RAM back-up

68, 100

(Voltage drop detection circuit

valid)

POF2

EPOF

SNZP

DWDT

RAM back-up

68, 100

64, 100

73, 100

64, 100

POF, POF2 instructions valid

(P) = 1 ?

Stop of watchdog timer func-

tion enabled

(WDF1) = 1 ?

WRST

CMCK

86, 100

63, 100

After skipping, (WDF1) ← 0

Ceramic oscillation circuit

selected

CRCK

TAMR

TMRA

RC oscillation circuit selected

(A) ← (MR)

63, 100

79, 100

83, 100

(MR) ← (A)

59

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET)

A n (Add n and accumulator)

Instruction

D9

D0

n

Number of Number of Flag CY

Skip condition

Overflow = 0

words

cycles

code

0

1

0

n

0

2

0

6

9

0

n

16

2

1

–

Grouping:

Arithmetic operation

Operation:

(A) ← (A) + n

Description: Adds the value n in the immediate field to

register A, and stores a result in register A.

The contents of carry flag CY remains un-

changed.

n = 0 to 15

Skips the next instruction when there is no

overflow as the result of operation.

Executes the next instruction when there is

overflow as the result of operation.

ADST (A-D conversion STart)

Instruction

Flag CY

–

Skip condition

–

D9

D0

1

Number of Number of

words

cycles

code

1

0

1

0

1

F

A

B

1

Operation:

(ADF) ← 0

Q13 = 0: A-D conversion starting

Grouping:

A-D conversion operation

Description: Clears (0) to A-D conversion completion flag

ADF, and the A-D conversion at the A-D con-

version mode (Q13 = 0) or the comparator

operation at the comparator mode (Q13 = 1)

is started.

Q13 = 1: Comparator operation starting

(Q13 : bit 3 of A-D control register Q1)

AM (Add accumulator and Memory)

Instruction

Number of Flag CY

cycles

D9

D0

0

Number of

words

Skip condition

–

code

0

1

0

1

–

Operation:

(A) ← (A) + (M(DP))

Grouping:

Arithmetic operation

Description: Adds the contents of M(DP) to register A.

Stores the result in register A. The contents

of carry flag CY remains unchanged.

AMC (Add accumulator, Memory and Carry)

Instruction

D9

D0

1

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

0

1

0/1

Operation:

(A) ← (A) + (M(DP)) + (CY)

(CY) ← Carry

Grouping:

Arithmetic operation

Description: Adds the contents of M(DP) and carry flag

CY to register A. Stores the result in register

A and carry flag CY.

60

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

AND (logical AND between accumulator and memory)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

8

16

2

1

–

Grouping:

Arithmetic operation

Operation:

(A) ← (A) AND (M(DP))

Description: Takes the AND operation between the con-

tents of register A and the contents of

M(DP), and stores the result in register A.

B a (Branch to address a)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

8

+a

code

0

1

a6 a5 a4 a3 a2 a1 a0

1

a

16

2

1

Operation:

(PCL) ← a6 to a0

Grouping:

Branch operation

Description: Branch within a page : Branches to address

a in the identical page.

Note:

Specify the branch address within the page

including this instruction.

BL p, a (Branch Long to address a in page p)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

cycles

E

+p

words

code

0

1

0

1

p4 p3 p2 p1 p0

0

2

p

a

16

2

–

1

a6 a5 a4 a3 a2 a1 a0

a

Grouping:

Branch operation

Description: Branch out of a page : Branches to address

Operation:

(PCH) ← p

(PCL) ← a6 to a0

a in page p.

Note:

p is 0 to 15 for M34501M2, and p is 0 to 31

for M34501M4/E4.

BLA p (Branch Long to address (D) + (A) in page p)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

0

1

0

2

1

p

0

p

16

2

1

p4

p3 p2 p1 p0

Grouping:

Branch operation

Description: Branch out of a page : Branches to address

(DR2 DR1 DR0 A3 A2 A1 A0)2 specified by

registers D and A in page p.

Operation:

(PCH) ← p

(PCL) ← (DR2–DR0, A3–A0)

Note:

p is 0 to 15 for M34501M2 and p is 0 to 31

for M34501M4/E4.

61

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

BM a (Branch and Mark to address a in page 2)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

a6 a5 a4 a3 a2 a1 a0

1

a

16

2

1

–

Grouping:

Subroutine call operation

Operation:

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← 2

Description: Call the subroutine in page 2 : Calls the sub-

routine at address a in page 2.

Note:

Subroutine extending from page 2 to another

page can also be called with the BM instruc-

tion when it starts on page 2.

(PCL) ← a6–a0

Be careful not to over the stack because the

maximum level of subroutine nesting is 8.

BML p, a (Branch and Mark Long to address a in page p)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

cycles

C

+p

words

code

0

1

0

1

0

p4 p3 p2 p1 p0

0

2

p

a

16

2

1

a6 a5 a4 a3 a2 a1 a0

a

Grouping:

Subroutine call operation

Description: Call the subroutine : Calls the subroutine at

Operation:

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p

address a in page p.

Note:

p is 0 to 15 for M34501M2 and p is 0 to 31

for M34501M4/E4.

(PCL) ← a6–a0

Be careful not to over the stack because the

maximum level of subroutine nesting is 8.

BMLA p (Branch and Mark Long to address (D) + (A) in page p)

Number of Flag CY

cycles

Instruction

D9

D0

Number of

words

Skip condition

–

code

0

1

0

1

0

2

3

p

0

p

16

2

–

1

p4

p3 p2 p1 p0

Grouping:

Subroutine call operation

Description: Call the subroutine : Calls the subroutine at

address (DR2 DR1 DR0 A3 A2 A1 A0)2 speci-

fied by registers D and A in page p.

Operation:

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p

Note:

p is 0 to 15 for M34501M2 and p is 0 to 31

for M34501M4/E4.

(PCL) ← (DR2–DR0, A3–A0)

Be careful not to over the stack because the

maximum level of subroutine nesting is 8.

CLD (CLear port D)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

16

2

1

–

Operation:

(D) ← 1

Grouping:

Input/Output operation

Description: Sets (1) to port D.

62

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

CMA (CoMplement of Accumulator)

Instruction

D9

D0

0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

C

16

2

1

–

Operation:

(A) ← (A)

Grouping:

Arithmetic operation

Description: Stores the one’s complement for register A’s

contents in register A.

CMCK (Clock select: ceraMic oscillation ClocK)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

0

1

0

2

9

A

1

Operation:

Ceramic oscillation circuit selected

Grouping:

Other operation

Description: Selects the ceramic oscillation circuit and

stops the ring oscillator.

CRCK (Clock select: Rc oscillation ClocK)

Instruction

D9

D0

1

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

1

0

1

2

9

B

1

–

Operation:

RC oscillation circuit selected

Grouping:

Other operation

Description: Selects the RC oscillation circuit and stops

the ring oscillator.

DEY (DEcrement register Y)

Instruction

code

Number of Number of

words

Flag CY

–

Skip condition

(Y) = 15

D9

D0

1

cycles

0

1

0

1

0

1

7

1

Operation:

(Y) ← (Y) – 1

Grouping:

RAM addresses

Description: Subtracts 1 from the contents of register Y.

As a result of subtraction, when the contents

of register Y is 15, the next instruction is

skipped. When the contents of register Y is

not 15, the next instruction is executed.

63

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

DI (Disable Interrupt)

Instruction

D9

D0

0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

2

0

9

0

5

4

16

2

1

–

Operation:

(INTE) ← 0

Grouping:

Interrupt control operation

Description: Clears (0) to interrupt enable flag INTE, and

disables the interrupt.

Note:

Interrupt is disabled by executing the DI in-

struction after executing 1 machine cycle.

DWDT (Disable WatchDog Timer)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

0

cycles

code

1

0

1

0

1

0

C

1

Grouping:

Other operation

Operation:

Stop of watchdog timer function enabled

Description: Stops the watchdog timer function by the

WRST instruction after executing the DWDT

instruction.

EI (Enable Interrupt)

Instruction

Number of Flag CY

cycles

D9

D0

1

Number of

words

Skip condition

–

code

0

1

0

5

1

–

Operation:

(INTE) ← 1

Grouping:

Interrupt control operation

Description: Sets (1) to interrupt enable flag INTE, and

enables the interrupt.

Note:

Interrupt is enabled by executing the EI in-

struction after executing 1 machine cycle.

EPOF (Enable POF instruction)

Instruction

D9

D0

1

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

0

1

0

1

B

1

–

Grouping:

Other operation

Operation:

POF instruction, POF2 instruction valid

Description: Makes the immediate after POF or POF2 in-

struction valid by executing the EPOF

instruction.

64

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

IAK (Input Accumulator from port K)

Instruction

D9

D0

1

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

1

2

6

F

0

1

2

16

2

1

–

Operation:

(A0) ← (K)

Grouping:

Input/Output operation

(A3–A1) ← 0

Description: Transfers the contents of port K to the bit 0

(A0) of register A.

Note:

After this instruction is executed, “0” is

stored to the high-order 3 bits (A3–A1) of

register A.

IAP0 (Input Accumulator from port P0)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

0

cycles

code

1

0

1

0

1

Operation:

(A) ← (P0)

Grouping:

Input/Output operation

Description: Transfers the input of port P0 to register A.

IAP1 (Input Accumulator from port P1)

Instruction

D9

D0

1

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

1

–

Operation:

(A) ← (P1)

Grouping:

Input/Output operation

Description: Transfers the input of port P1 to register A.

IAP2 (Input Accumulator from port P2)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

0

cycles

code

1

0

1

0

1

Operation:

(A1, A0) ← (P21, P20)

(A3, A2) ← 0

Grouping:

Input/Output operation

Description: Transfers the input of port P2 to the low-or-

der 2 bits (A1, A0) of register A.

Note:

After this instruction is executed, “0” is

stored to the high-order 2 bits (A3, A2) of reg-

ister A.

65

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

INY (INcrement register Y)

Instruction

D9

D0

1

Number of Number of Flag CY

Skip condition

(Y) = 0

words

cycles

code

0

1

0

1

0

3

0

1

7

x

4

3

n

y

16

2

1

–

Operation:

(Y) ← (Y) + 1

Grouping:

RAM addresses

Description: Adds 1 to the contents of register Y. As a re-

sult of addition, when the contents of register

Y is 0, the next instruction is skipped. When

the contents of register Y is not 0, the next

instruction is executed.

LA n (Load n in Accumulator)

Instruction

Number of Number of

Flag CY

–

Skip condition

D9

D0

n

words

cycles

code

0

1

n

1

Continuous

description

Operation:

(A) ← n

n = 0 to 15

Grouping:

Arithmetic operation

Description: Loads the value n in the immediate field to

register A.

When the LA instructions are continuously

coded and executed, only the first LA in-

struction is executed and other LA

instructions coded continuously are skipped.

LXY x, y (Load register X and Y with x and y)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

code

1

x3 x2 x1 x0 y3 y2 y1 y0

1

–

Continuous

description

Operation:

(X) ← x x = 0 to 15

(Y) ← y y = 0 to 15

Grouping:

RAM addresses

Description: Loads the value x in the immediate field to

register X, and the value y in the immediate

field to register Y. When the LXY instructions

are continuously coded and executed, only

the first LXY instruction is executed and

other LXY instructions coded continuously

are skipped.

LZ z (Load register Z with z)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

8

+z

cycles

words

code

0

1

0

1

0

z1 z0

1

–

Grouping:

RAM addresses

Operation:

(Z) ← z z = 0 to 3

Description: Loads the value z in the immediate field to

register Z.

66

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

NOP (No OPeration)

Instruction

D9

D0

0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

2

0

1

2

0

F

0

1

16

2

1

–

Operation:

(PC) ← (PC) + 1

Grouping:

Other operation

Description: No operation; Adds 1 to program counter

value, and others remain unchanged.

OKA (Output port K from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

1

cycles

code

1

0

1

Operation:

(K) ← (A0)

Grouping:

Input/Output operation

Description: Outputs the contents of bit 0 (A0) of register

A to port K.

OP0A (Output port P0 from Accumulator)

Instruction

D9

D0

0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

1

–

Operation:

(P0) ← (A)

Grouping:

Input/Output operation

Description: Outputs the contents of register A to port P0.

OP1A (Output port P1 from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

1

cycles

code

1

0

1

0

1

Operation:

(P1) ← (A)

Grouping:

Input/Output operation

Description: Outputs the contents of register A to port P1.

67

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

OP2A (Output port P2 from Accumulator)

Instruction

D9

D0

0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

2

16

2

1

–

Operation:

(P21, P20) ← (A1, A0)

Grouping:

Input/Output operation

Description: Outputs the contents of the low-order 2 bits

(A1, A0) of register A to port P2.

OR (logical OR between accumulator and memory)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

0

1

0

1

0

1

9

2

1

Operation:

(A) ← (A) OR (M(DP))

Grouping:

Arithmetic operation

Description: Takes the OR operation between the con-

tents of register A and the contents of

M(DP), and stores the result in register A.

POF (Power OFf1)

Instruction

Number of Flag CY

cycles

D9

D0

0

Number of

words

Skip condition

–

code

0

1

0

2

1

–

Grouping:

Other operation

Operation:

RAM back-up

However, voltage drop detection circuit valid

Description: Puts the system in RAM back-up state by

executing the POF instruction after execut-

ing the EPOF instruction.

However, the voltage drop detection circuit

is valid.

If the EPOF instruction is not executed before

executing this instruction, this instruction is

equivalent to the NOP instruction.

Note:

POF2 (Power OFf2)

Instruction

D9

D0

0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

0

8

1

–

Grouping:

Other operation

Operation:

RAM back-up

Description: Puts the system in RAM back-up state by

executing the POF2 instruction after ex-

ecuting the EPOF instruction. Operations of

all functions are stopped.

Note:

If the EPOF instruction is not executed be-

fore executing this instruction, this

instruction is equivalent to the NOP instruc-

tion.

68

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

RAR (Rotate Accumulator Right)

Instruction

D9

D0

1

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

2

1

4

0

8

D

16

2

1

0/1

Operation:

→ CY → A3A2A1A0

Grouping:

Arithmetic operation

Description: Rotates 1 bit of the contents of register A in-

cluding the contents of carry flag CY to the

right.

RB j (Reset Bit)

Instruction

Flag CY

–

Skip condition

–

D9

D0

j

Number of Number of

words

cycles

C

code

0

1

0

j

+j

1

Operation:

(Mj(DP)) ← 0

Grouping:

Bit operation

j = 0 to 3

Description: Clears (0) the contents of bit j (bit specified

by the value j in the immediate field) of

M(DP).

RC (Reset Carry flag)

Instruction

D9

D0

0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

6

1

0

Operation:

(CY) ← 0

Grouping:

Arithmetic operation

Description: Clears (0) to carry flag CY.

RCP (Reset Port C)

Instruction

Flag CY

–

Skip condition

–

D9

D0

0

Number of Number of

words

cycles

code

1

0

1

0

C

1

Operation:

(C) ← 0

Grouping:

Input/Output operation

Description: Clears (0) to port C.

69

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

RD (Reset port D specified by register Y)

Instruction

D9

D0

0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

0

1

4

6

5

16

2

1

–

Operation:

(D(Y)) ← 0

However,

Grouping:

Input/Output operation

Description: Clears (0) to a bit of port D specified by register

Y.

(Y) = 0 to 3

Note:

Set 0 to 3 to register Y because port D is

four ports (D0–D3).

When values except above are set to regis-

ter Y, this instruction is equivalent to the

NOP instruction.

RT (ReTurn from subroutine)

Instruction

Number of Number of

Flag CY

–

Skip condition

–

D9

D0

0

words

cycles

code

0

1

0

1

2

Operation:

(PC) ← (SK(SP))

(SP) ← (SP) – 1

Grouping:

Return operation

Description: Returns from subroutine to the routine called

the subroutine.

RTI (ReTurn from Interrupt)

Instruction

Number of Flag CY

cycles

D9

D0

0

Number of

words

Skip condition

–

code

0

1

0

1

–

Operation:

(PC) ← (SK(SP))

(SP) ← (SP) – 1

Grouping:

Return operation

Description: Returns from interrupt service routine to

main routine.

Returns each value of data pointer (X, Y, Z),

carry flag, skip status, NOP mode status by

the continuous description of the LA/LXY in-

struction, register A and register B to the

states just before interrupt.

RTS (ReTurn from subroutine and Skip)

Instruction

D9

D0

1

Number of Number of Flag CY

Skip condition

words

cycles

code

0

1

0

1

2

–

Skip at uncondition

Grouping:

Return operation

Operation:

(PC) ← (SK(SP))

(SP) ← (SP) – 1

Description: Returns from subroutine to the routine called

the subroutine, and skips the next instruction

at uncondition.

70

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SB j (Set Bit)

Instruction

D9

D0

j

Number of Number of Flag CY

Skip condition

–

words

cycles

C

code

0

1

0

1

0

1

0

1

j

0

2

0

5

0

8

1

+j

16

2

1

–

Operation:

(Mj(DP)) ← 0

Grouping:

Bit operation

j = 0 to 3

Description: Sets (1) the contents of bit j (bit specified by

the value j in the immediate field) of M(DP).

SC (Set Carry flag)

Instruction

Number of Number of

Flag CY

1

Skip condition

–

D9

D0

1

words

cycles

code

0

1

0

7

D

5

1

Operation:

(CY) ← 1

Grouping:

Arithmetic operation

Description: Sets (1) to carry flag CY.

SCP (Set Port C)

Instruction

D9

D0

1

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

–

Operation:

(C) ← 1

Grouping:

Input/Output operation

Description: Sets (1) to port C.

SD (Set port D specified by register Y)

Instruction

Number of Number of

Flag CY

Skip condition

–

D9

D0

1

words

cycles

code

0

1

0

1

–

Grouping:

Input/Output operation

Operation:

(D(Y)) ← 1

Description: Sets (1) to a bit of port D specified by register Y.

(Y) = 0 to 3

Note:

Set 0 to 3 to register Y because port D is

four ports (D0–D3).

When values except above are set to regis-

ter Y, this instruction is equivalent to the

NOP instruction.

71

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SEA n (Skip Equal, Accumulator with immediate data n)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

(A) = n

words

cycles

code

0

1

0

1

0

n

1

n

0

n

1

0

2

7

5

n

16

2

–

0

n

Grouping:

Comparison operation

Description: Skips the next instruction when the contents

of register A is equal to the value n in the im-

mediate field.

Operation:

(A) = n ?

n = 0 to 15

Executes the next instruction when the con-

tents of register A is not equal to the value n

in the immediate field.

SEAM (Skip Equal, Accumulator with Memory)

Number of Number of

Flag CY

–

Skip condition

(A) = (M(DP))

Instruction

D9

D0

words

cycles

code

0

1

0

1

0

2

6

16

2

1

Operation:

(A) = (M(DP)) ?

Grouping:

Comparison operation

Description: Skips the next instruction when the contents

of register A is equal to the contents of

M(DP).

Executes the next instruction when the con-

tents of register A is not equal to the

contents of M(DP).

SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)

Number of Flag CY

cycles

Instruction

D9

D0

Number of

words

Skip condition

code

0

1

0

3

8

16

2

1

–

V10 = 0: (EXF0) = 1

Operation:

V10 = 0: (EXF0) = 1 ?

Grouping:

Interrupt operation

After skipping, (EXF0) ← 0

Description: When V10 = 0 : Skips the next instruction

when external 0 interrupt request flag EXF0

is “1.” After skipping, clears (0) to the EXF0

flag. When the EXF0 flag is “0,” executes the

next instruction.

V10 = 1: SNZ0 = NOP

(V10 : bit 0 of the interrupt control register V1)

When V10 = 1 : This instruction is equivalent

to the NOP instruction.

SNZAD (Skip if Non Zero condition of A-D conversion completion flag)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

words

cycles

code

1

0

1

0

1

2

8

7

16

2

1

–

V22 = 0: (ADF) = 1

Operation:

V22 = 0: (ADF) = 1 ?

Grouping:

A-D conversion operation

After skipping, (ADF) ← 0

Description: When V22 = 0 : Skips the next instruction

when A-D conversion completion flag ADF is

“1.” After skipping, clears (0) to the ADF flag.

When the ADF flag is “0,” executes the next

instruction.

V22 = 1: SNZAD = NOP

(V22 : bit 2 of the interrupt control register V2)

When V22 = 1 : This instruction is equivalent

to the NOP instruction.

72

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SNZCP (Skip if Non Zero condition of Port C)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

(C) = 1

words

cycles

code

1

0

1

0

1

0

1

2

8

9

16

2

1

–

Operation:

(C) = 1 ?

Grouping:

Input/Output operation

Description: Skips the next instruction when the contents

of port C is “1.”

Executes the next instruction when the con-

tents of port C is “0.”

SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)

Number of Number of

Flag CY

–

Skip condition

Instruction

D9

D0

words

cycles

code

0

1

0

1

0

3

A

16

2

1

I12 = 0 : (INT) = “L”

I12 = 1 : (INT) = “H”

Grouping:

Interrupt operation

Operation:

I12 = 0 : (INT) = “L” ?

I12 = 1 : (INT) = “H” ?

Description: When I12 = 0 : Skips the next instruction

when the level of INT pin is “L.” Executes the

next instruction when the level of INT pin is

“H.”

(I12 : bit 2 of the interrupt control register I1)

When I12 = 1 : Skips the next instruction

when the level of INT pin is “H.” Executes

the next instruction when the level of INT pin

is “L.”

SNZP (Skip if Non Zero condition of Power down flag)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

(P) = 1

words

cycles

code

0

1

0

3

16

2

1

–

Operation:

(P) = 1 ?

Grouping:

Other operation

Description: Skips the next instruction when the P flag is

“1”.

After skipping, the P flag remains un-

changed.

Executes the next instruction when the P

flag is “0.”

SNZT1 (Skip if Non Zero condition of Timer 1 inerrupt request flag)

Number of Number of

Flag CY

–

Skip condition

Instruction

D9

D0

words

cycles

code

1

0

1

0

2

8

0

16

2

1

V12 = 0: (T1F) = 1

Operation:

V12 = 0: (T1F) = 1 ?

Grouping:

Timer operation

After skipping, (T1F) ← 0

Description: When V12 = 0 : Skips the next instruction

when timer 1 interrupt request flag T1F is

“1.” After skipping, clears (0) to the T1F flag.

When the T1F flag is “0,” executes the next

instruction.

V12 = 1: SNZT1 = NOP

(V12 = bit 2 of interrupt control register V1)

When V12 = 1 : This instruction is equivalent

to the NOP instruction.

73

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

SNZT2 (Skip if Non Zero condition of Timer 2 inerrupt request flag)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

words

cycles

code

1

0

1

0

1

2

0

8

2

1

16

2

1

–

V13 = 0: (T2F) = 1

Operation:

V13 = 0: (T2F) = 1 ?

Grouping:

Timer operation

After skipping, (T2F) ← 0

Description: When V13 = 0 : Skips the next instruction

when timer 2 interrupt request flag T2F is

“1.” After skipping, clears (0) to the T2F flag.

When the T2F flag is “0,” executes the next

instruction.

V13 = 1: SNZT2 = NOP

(V13 = bit 3 of interrupt control register V1)

When V13 = 1 : This instruction is equivalent

to the NOP instruction.

SZB j (Skip if Zero, Bit)

Instruction

Flag CY

–

Skip condition

D9

D0

j

Number of Number of

words

cycles

code

0

1

0

j

1

(Mj(DP)) = 0

j = 0 to 3

Operation:

(Mj(DP)) = 0 ?

j = 0 to 3

Grouping:

Bit operation

Description: Skips the next instruction when the contents

of bit j (bit specified by the value j in the im-

mediate field) of M(DP) is “0.”

Executes the next instruction when the con-

tents of bit j of M(DP) is “1.”

SZC (Skip if Zero, Carry flag)

Instruction

Number of Flag CY

cycles

D9

D0

1

Number of

words

Skip condition

(CY) = 0

code

0

1

0

1

F

1

–

Operation:

(CY) = 0 ?

Grouping:

Arithmetic operation

Description: Skips the next instruction when the contents

of carry flag CY is “0.”

After skipping, the CY flag remains un-

changed.

Executes the next instruction when the con-

tents of the CY flag is “1.“

SZD (Skip if Zero, port D specified by register Y)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

words

cycles

code

0

1

0

1

0

1

0

2

4

16

2

–

(D(Y)) = 0

(Y) = 0 to 3

0

1

B

Grouping:

Input/Output operation

Operation:

(D(Y)) = 0 ?

(Y) = 0 to 3

Description: Skips the next instruction when a bit of port D

specified by register Y is “0.” Executes the

next instruction when the bit is “1.”

Note:

Set 0 to 3 to register Y because port D is

four ports (D0–D3). When values except

above are set to register Y, this instruction is

equivalent to the NOP instruction.

74

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

2

3

0

16

2

1

–

Grouping:

Timer operation

Operation:

(T17–T14) ← (B)

(R17–R14) ← (B)

(T13–T10) ← (A)

(R13–R10) ← (A)

Description: Transfers the contents of register B to the

high-order 4 bits of timer 1 and timer 1 re-

load register R1. Transfers the contents of

register A to the low-order 4 bits of timer 1

and timer 1 reload register R1.

T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

1

0

1

0

1

2

3

1

16

2

1

Grouping:

Timer operation

Operation:

(T27–T24) ← (B)

(R27–R24) ← (B)

(T23–T20) ← (A)

(R23–R20) ← (A)

Description: Transfers the contents of register B to the

high-order 4 bits of timer 2 and timer 2 re-

load register R2. Transfers the contents of

register A to the low-order 4 bits of timer 2

and timer 2 reload register R2.

TAB (Transfer data to Accumulator from register B)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

E

16

2

1

–

Operation:

(A) ← (B)

Grouping:

Other operation

Description: Transfers the contents of register B to regis-

ter A.

TAB1 (Transfer data to Accumulator and register B from timer 1)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

1

0

1

0

2

7

0

16

2

1

Operation:

(B) ← (T17–T14)

(A) ← (T13–T10)

Grouping:

Timer operation

Description: Transfers the high-order 4 bits (T17–T14) of

timer 1 to register B.

Transfers the low-order 4 bits (T13–T10) of

timer 1 to register A.

75

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAB2 (Transfer data to Accumulator and register B from timer 2)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

2

7

1

16

2

1

–

Operation:

(B) ← (T27–T24)

(A) ← (T23–T20)

Grouping:

Timer operation

Description: Transfers the high-order 4 bits (T27–T24) of

timer 2 to register B.

Transfers the low-order 4 bits (T23–T20) of

timer 2 to register A.

TABAD (Transfer data to Accumulator and register B from register AD)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

1

0

1

0

1

2

7

9

16

2

1

Grouping:

A-D conversion operation

Operation:

In A-D conversion mode (Q13 = 0),

Description: In the A-D conversion mode (Q1

fers the high-order 4 bits (AD

register AD to register B, and the middle-order

4 bits (AD –AD ) of register AD to register A.

In the comparator mode (Q1 = 1), transfers

the middle-order 4 bits (AD –AD ) of register

AD to register B, and the low-order 4 bits

(AD –AD ) of register AD to register A.

3

= 0), trans-

(B) ← (AD9–AD6)

9

–AD ) of

6

(A) ← (AD5–AD2)

In comparator mode (Q13 = 1),

(B) ← (AD7–AD4)

5

2

3

(A) ← (AD3–AD0)

7

4

(Q13 : bit 3 of A-D control register Q1)

3

0

TABE (Transfer data to Accumulator and register B from register E)

Number of Flag CY

cycles

Instruction

D9

D0

Number of

words

Skip condition

–

code

0

1

0

1

0

1

0

2

A

16

2

1

–

Operation:

(B) ← (E7–E4)

(A) ← (E3–E0)

Grouping:

Register to register transfer

Description: Transfers the high-order 4 bits (E7–E4) of

register E to register B, and low-order 4 bits

of register E to register A.

TABP p (Transfer data to Accumulator and register B from Program memory in page p)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

8

+p

code

0

1

0

p4 p3 p2 p1 p0

0

p

16

2

1

3

–

Grouping:

Arithmetic operation

Operation:

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p

Description: Transfers bits 7 to 4 to register B and bits 3 to

0 to register A. These bits 7 to 0 are the ROM

pattern in ad-dress (DR

2 DR1 DR0 A3 A2 A1

(PCL) ← (DR2–DR0, A3–A0)

(B) ← (ROM(PC))7–4

(A) ← (ROM(PC))3–0

(PC) ← (SK(SP))

A0)2

specified by registers A and D in page p.

Note:

p is 0 to 15 for M34501M2, and p is 0 to 31

for M34501M4/E4.

When this instruction is executed, be careful

not to over the stack because 1 stage of

stack register is used.

(SP) ← (SP) – 1

76

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAD (Transfer data to Accumulator from register D)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

0

5

1

16

2

1

–

Operation:

(A2–A0) ← (DR2–DR0)

(A3) ← 0

Grouping:

Register to register transfer

Description: Transfers the contents of register D to the

low-order 3 bits (A2–A0) of register A.

Note:

When this instruction is executed, “0” is

stored to the bit 3 (A3) of register A.

TADAB (Transfer data to register AD from Accumulator from register B)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

1

0

1

0

1

2

3

5

9

3

6

16

2

1

Grouping:

A-D conversion operation

Operation:

(AD7–AD4) ← (B)

(AD3–AD0) ← (A)

Description: In the A-D conversion mode (Q13 = 0), this

instruction is equivalent to the NOP instruc-

tion.

In the comparator mode (Q13 = 1), transfers

the contents of register B to the high-order 4

bits (AD7–AD4) of comparator register, and

the contents of register A to the low-order 4

bits (AD3–AD0) of comparator register.

(Q13 = bit 3 of A-D control register Q1)

TAI1 (Transfer data to Accumulator from register I1)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

1

2

1

–

Operation:

(A) ← (I1)

Grouping:

Interrupt operation

Description: Transfers the contents of interrupt control

register I1 to register A.

TAK0 (Transfer data to Accumulator from register K0)

Instruction

Number of Number of

Flag CY

–

Skip condition

–

D9

D0

words

cycles

code

1

0

1

0

1

0

1

0

2

1

Operation:

(A) ← (K0)

Grouping:

Input/Output operation

Description: Transfers the contents of key-on wakeup

control register K0 to register A.

77

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAK1 (Transfer data to Accumulator from register K1)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

1

2

5

4

C

9

A

9

j

16

2

1

–

Grouping:

Input/Output operation

Operation:

(A) ← (K1)

Description: Transfers the contents of key-on wakeup

control register K1 to register A.

TAK2 (Transfer data to Accumulator from register K2)

Instruction

Flag CY

–

Skip condition

–

D9

D0

Number of Number of

words

cycles

code

1

0

1

0

1

0

1

0

2

1

Operation:

(A) ← (K2)

Grouping:

Input/Output operation

Description: Transfers the contents of key-on wakeup

control register K2 to register A.

TALA (Transfer data to Accumulator from register LA)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

–

code

1

0

1

0

1

0

1

2

1

–

Operation:

(A3, A2) ← (AD1, AD0)

(A1, A0) ← 0

Grouping:

A-D conversion operation

Description: Transfers the low-order 2 bits (AD1, AD0) of

register AD to the high-order 2 bits (A3, A2)

of register A.

Note:

After this instruction is executed, “0” is

stored to the low-order 2 bits (A1, A0) of

register A.

TAM j (Transfer data to Accumulator from Memory)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

j

2

1

–

Operation:

(A) ← (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

Grouping:

RAM to register transfer

Description: After transferring the contents of M(DP) to

register A, an exclusive OR operation is per-

formed between register X and the value j in

the immediate field, and stores the result in

register X.

78

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAMR (Transfer data to Accumulator from register MR)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

1

0

2

5

2

4

0

4

16

2

1

–

Grouping:

Other operation

Operation:

(A) ← (MR)

Description: Transfers the contents of clock control reg-

ister MR to register A.

TAQ1 (Transfer data to Accumulator from register Q1)

Instruction

Flag CY

–

Skip condition

–

D9

D0

Number of Number of

words

cycles

code

1

0

1

0

1

0

2

4

2

1

Operation:

(A) ← (Q1)

Grouping:

A-D conversion operation

Description: Transfers the contents of A-D control regis-

ter Q1 to register A.

TASP (Transfer data to Accumulator from Stack Pointer)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

0

1

0

5

2

1

–

Operation:

(A2–A0) ← (SP2–SP0)

(A3) ← 0

Grouping:

Register to register transfer

Description: Transfers the contents of stack pointer (SP)

to the low-order 3 bits (A2–A0) of register A.

Note:

After this instruction is executed, “0” is

stored to the bit 3 (A3) of register A.

TAV1 (Transfer data to Accumulator from register V1)

Instruction

Flag CY

–

Skip condition

–

D9

D0

Number of Number of

words

cycles

code

0

1

0

1

0

1

0

5

2

1

Operation:

(A) ← (V1)

Grouping:

Interrupt operation

Description: Transfers the contents of interrupt control

register V1 to register A.

79

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAV2 (Transfer data to Accumulator from register V2)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

0

1

0

5

16

2

1

–

Operation:

(A) ← (V2)

Grouping:

Interrupt operation

Description: Transfers the contents of interrupt control

register V2 to register A.

TAW1 (Transfer data to Accumulator from register W1)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

0

1

2

4

B

C

0

2

1

Operation:

(A) ← (W1)

Grouping:

Timer operation

Description: Transfers the contents of timer control reg-

ister W1 to register A.

TAW2 (Transfer data to Accumulator from register W2)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

–

code

1

0

1

0

1

0

2

4

2

1

–

Operation:

(A) ← (W2)

Grouping:

Timer operation

Description: Transfers the contents of timer control regis-

ter W2 to register A.

TAW6 (Transfer data to Accumulator from register W6)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

1

0

2

5

2

1

–

Operation:

(A) ← (W6)

Grouping:

Timer operation

Description: Transfers the contents of timer control regis-

ter W6 to register A.

80

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TAX (Transfer data to Accumulator from register X)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

0

5

2

16

2

1

–

Grouping:

Register to register transfer

Operation:

(A) ← (X)

Description: Transfers the contents of register X to reg-

ister A.

TAY (Transfer data to Accumulator from register Y)

Instruction

Flag CY

–

Skip condition

–

D9

D0

Number of Number of

words

cycles

code

0

1

0

1

F

2

1

Operation:

(A) ← (Y)

Grouping:

Register to register transfer

Description: Transfers the contents of register Y to regis-

ter A.

TAZ (Transfer data to Accumulator from register Z)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

0

1

0

1

0

1

0

5

3

2

1

–

Operation:

(A1, A0) ← (Z1, Z0)

(A3, A2) ← 0

Grouping:

Register to register transfer

Description: Transfers the contents of register Z to the

low-order 2 bits (A1, A0) of register A.

Note:

After this instruction is executed, “0” is

stored to the high-order 2 bits (A3, A2) of

register A.

TBA (Transfer data to register B from Accumulator)

Instruction

Flag CY

–

Skip condition

–

D9

D0

Number of Number of

words

cycles

code

0

1

0

E

2

1

Operation:

(B) ← (A)

Grouping:

Register to register transfer

Description: Transfers the contents of register A to regis-

ter B.

81

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TDA (Transfer data to register D from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

1

0

1

0

2

9

16

2

1

–

Operation:

(DR2–DR0) ← (A2–A0)

Grouping:

Register to register transfer

Description: Transfers the contents of the low-order 3

bits (A2–A0) of register A to register D.

TEAB (Transfer data to register E from Accumulator and register B)

Number of Number of

Flag CY

–

Skip condition

–

Instruction

D9

D0

words

cycles

code

0

1

0

1

0

1

A

16

2

1

Operation:

(E7–E4) ← (B)

(E3–E0) ← (A)

Grouping:

Register to register transfer

Description: Transfers the contents of register B to the

high-order 4 bits (E3–E0) of register E, and

the contents of register A to the low-order 4

bits (E3–E0) of register E.

TI1A (Transfer data to register I1 from Accumulator)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

–

code

1

0

1

0

1

2

7

2

1

–

Operation:

(I1) ← (A)

Grouping:

Interrupt operation

Description: Transfers the contents of register A to inter-

rupt control register I1.

TK0A (Transfer data to register K0 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

2

B

2

1

–

Operation:

(K0) ← (A)

Grouping:

Input/Output operation

Description: Transfers the contents of register A to key-on

wakeup control register K0.

82

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TK1A (Transfer data to register K1 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

2

1

4

16

2

1

–

Operation:

(K1) ← (A)

Grouping:

Input/Output operation

Description: Transfers the contents of register A to key-

on wakeup control register K1.

TK2A (Transfer data to register K2 from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

0

1

2

1

5

2

1

Grouping:

Input/Output operation

Operation:

(K2) ← (A)

Description: Transfers the contents of register A to key-

on wakeup control register K2.

TMA j (Transfer data to Memory from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

1

j

2

B

j

2

1

–

Operation:

(M(DP)) ← (A)

(X) ← (X)EXOR(j)

j = 0 to 15

Grouping:

RAM to register transfer

Description: After transferring the contents of register A to

M(DP), an exclusive OR operation is per-

formed between register X and the value j in

the immediate field, and stores the result in

register X.

TMRA (Transfer data to register MR from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

0

2

1

6

2

1

Operation:

(MR) ← (A)

Grouping:

Other operation

Description: Transfers the contents of register A to clock

control register MR.

83

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TPU0A (Transfer data to register PU0 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

0

1

2

D

E

F

4

16

2

1

–

Operation:

(PU0) ← (A)

Grouping:

Input/Output operation

Description: Transfers the contents of register A to pull-

up control register PU0.

TPU1A (Transfer data to register PU1 from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

0

2

1

Operation:

(PU1) ← (A)

Grouping:

Input/Output operation

Description: Transfers the contents of register A to pull-

up control register PU1.

TPU2A (Transfer data to register PU2 from Accumulator)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

–

code

1

0

1

0

1

2

1

–

Operation:

(PU2) ← (A)

Grouping:

Input/Output operation

Description: Transfers the contents of register A to pull-up

control register PU2.

TQ1A (Transfer data to register Q1 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

words

Skip condition

–

cycles

code

1

0

1

0

2

0

2

1

–

Operation:

(Q1) ← (A)

Grouping:

A-D conversion operation

Description: Transfers the contents of register A to A-D

control register Q1.

84

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TR1AB (Transfer data to register R1 from Accumulator and register B)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

2

3

F

16

2

1

–

Operation:

(R17–R14) ← (B)

(R13–R10) ← (A)

Grouping:

Timer operation

Description: Transfers the contents of register B to the

high-order 4 bits (R17–R14) of reload regis-

ter R1, and the contents of register A to the

low-order 4 bits (R13–R10) of reload regis-

ter R1.

TV1A (Transfer data to register V1 from Accumulator)

Instruction

Number of Number of

Flag CY

–

Skip condition

–

D9

D0

words

cycles

code

0

1

0

F

2

1

Grouping:

Interrupt operation

Operation:

(V1) ← (A)

Description: Transfers the contents of register A to inter-

rupt control register V1.

TV2A (Transfer data to register V2 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

0

1

0

E

2

1

–

Grouping:

Interrupt operation

Operation:

(V2) ← (A)

Description: Transfers the contents of register A to inter-

rupt control register V2.

TW1A (Transfer data to register W1 from Accumulator)

Instruction

Number of Number of

Flag CY

–

Skip condition

–

D9

D0

words

cycles

code

1

0

1

0

2

0

E

2

1

Operation:

(W1) ← (A)

Grouping:

Timer operation

Description: Transfers the contents of register A to timer

control register W1.

85

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

TW2A (Transfer data to register W2 from Accumulator)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

2

0

F

3

C

0

16

2

1

–

Operation:

(W2) ← (A)

Grouping:

Timer operation

Description: Transfers the contents of register A to timer

control register W2.

TW6A (Transfer data to register W6 from Accumulator)

Instruction

Number of Number of

words

Flag CY

–

Skip condition

–

D9

D0

cycles

code

1

0

1

0

1

2

0

2

1

0

A

2

1

Operation:

(W6) ← (A)

Grouping:

Timer operation

Description: Transfers the contents of register A to timer

control register W6.

TYA (Transfer data to register Y from Accumulator)

Instruction

Number of Flag CY

cycles

D9

D0

Number of

words

Skip condition

–

code

0

1

0

2

1

–

Operation:

(Y) ← (A)

Grouping:

Register to register transfer

Description: Transfers the contents of register A to regis-

ter Y.

WRST (Watchdog timer ReSeT)

Instruction

D9

D0

0

Number of Number of Flag CY

words

Skip condition

(WDF1) = 1

cycles

code

1

0

1

0

1

0

2

1

–

Operation:

(WDF1) = 1 ?

After skipping, (WDF1) ← 0

Grouping:

Other operation

Description: Skips the next instruction when watchdog

timer flag WDF1 is “1.” After skipping, clears

(0) to the WDF1 flag. When the WDF1 flag

is “0,” executes the next instruction. Also,

stops the watchdog timer function when ex-

ecuting the WRST instruction immediately

after the DWDT instruction.

86

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)

XAM j (eXchange Accumulator and Memory data)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

–

words

cycles

code

1

0

1

0

1

j

2

D

j

16

2

1

–

Operation:

(A) ←→ (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

Grouping:

RAM to register transfer

Description: After exchanging the contents of M(DP)

with the contents of register A, an exclusive

OR operation is performed between regis-

ter X and the value j in the immediate field,

and stores the result in register X.

XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)

Number of Number of

Flag CY

Skip condition

(Y) = 15

Instruction

D9

D0

words

cycles

code

1

0

1

j

2

F

j

16

2

1

–

Grouping:

RAM to register transfer

Operation:

(A) ←→ (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

Description: After exchanging the contents of M(DP)

with the contents of register A, an exclusive

OR operation is performed between regis-

ter X and the value j in the immediate field,

and stores the result in register X.

(Y) ← (Y) – 1

Subtracts 1 from the contents of register Y.

As a result of subtraction, when the con-

tents of register Y is 15, the next instruction

is skipped. When the contents of register Y

is not 15, the next instruction is executed.

XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)

Instruction

D9

D0

Number of Number of Flag CY

Skip condition

(Y) = 0

words

cycles

code

1

0

1

0

j

2

E

j

16

2

1

–

Grouping:

RAM to register transfer

Operation:

(A) ←→ (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

Description: After exchanging the contents of M(DP)

with the contents of register A, an exclusive

OR operation is performed between regis-

ter X and the value j in the immediate field,

and stores the result in register X.

(Y) ← (Y) + 1

Adds 1 to the contents of register Y. As a re-

sult of addition, when the contents of register

Y is 0, the next instruction is skipped. when

the contents of register Y is not 0, the next

instruction is executed.

Instruction

code

D9

D0

Number of Number of

words

cycles

Flag CY

Skip condition

16

2

87

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY TYPES)

Instruction code

Parameter

Function

Mnemonic

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

TAB

TBA

TAY

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

E

1

(A) ← (B)

(B) ← (A)

(A) ← (Y)

(Y) ← (A)

0

E

F

C

A

TYA

TEAB

(E7–E4) ← (B)

(E3–E0) ← (A)

TABE

0

1

0

1

0

1

0

2

A

1

(B) ← (E7–E4)

(A) ← (E3–E0)

TDA

TAD

0

1

0

1

0

1

0

2

5

9

1

(DR2–DR0) ← (A2–A0)

(A2–A0) ← (DR2–DR0)

(A3) ← 0

TAZ

0

1

0

1

0

1

0

5

3

1

(A1, A0) ← (Z1, Z0)

(A3, A2) ← 0

TAX

0

1

0

1

0

1

0

5

2

0

1

(A) ← (X)

TASP

(A2–A0) ← (SP2–SP0)

(A3) ← 0

LXY x, y

1

x3 x2 x1 x0 y3 y2 y1 y0

3

x

y

1

(X) ← x x = 0 to 15

(Y) ← y y = 0 to 15

LZ z

INY

0

1

0

1

0

1

z1 z0

0

4

1

8

+z

1

(Z) ← z z = 0 to 3

(Y) ← (Y) + 1

1

3

7

DEY

(Y) ← (Y) – 1

TAM j

1

0

1

0

1

0

1

j

2

C j

D j

1

(A) ← (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

XAM j

XAMD j

(A) ← → (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

F

j

(A) ← → (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

(Y) ← (Y) – 1

XAMI j

TMA j

1

0

1

0

1

0

1

j

2

E j

1

(A) ← → (M(DP))

(X) ← (X)EXOR(j)

j = 0 to 15

(Y) ← (Y) + 1

B j

(M(DP)) ← (A)

(X) ← (X)EXOR(j)

j = 0 to 15

88

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Datailed description

–

Transfers the contents of register B to register A.

Transfers the contents of register A to register B.

Transfers the contents of register Y to register A.

Transfers the contents of register A to register Y.

Transfers the contents of register B to the high-order 4 bits (E3–E0) of register E, and the contents of regis-

ter A to the low-order 4 bits (E3–E0) of register E.

–

Transfers the high-order 4 bits (E7–E4) of register E to register B, and low-order 4 bits of register E to regis-

ter A.

–

Transfers the contents of the low-order 3 bits (A2–A0) of register A to register D.

Transfers the contents of register D to the low-order 3 bits (A2–A0) of register A.

–

Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.

–

Transfers the contents of register X to register A.

Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2–A0) of register A.

Continuous

description

–

Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.

When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed

and other LXY instructions coded continuously are skipped.

–

Loads the value z in the immediate field to register Z.

(Y) = 0

(Y) = 15

Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-

struction is skipped. When the contents of register Y is not 0, the next instruction is executed.

Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,

the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.

–

After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg-

ister X and the value j in the immediate field, and stores the result in register X.

After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-

formed between register X and the value j in the immediate field, and stores the result in register X.

(Y) = 15

After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-

formed between register X and the value j in the immediate field, and stores the result in register X.

Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,

the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.

(Y) = 0

–

After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per-

formed between register X and the value j in the immediate field, and stores the result in register X.

Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next in-

struction is skipped. when the contents of register Y is not 0, the next instruction is executed.

–

After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg-

ister X and the value j in the immediate field, and stores the result in register X.

89

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Parameter

Function

Mnemonic

LA n

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

(A) ← n

n = 0 to 15

0

1

0

1

0

1

n

0

7

n

1

3

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p (Note)

TABP p

p4 p3 p2 p1 p0

0

8

p

+p

(PCL) ← (DR2–DR0, A3–A0)

(B) ← (ROM(PC))7–4

(A) ← (ROM(PC))3–0

(PC) ← (SK(SP))

(SP) ← (SP) – 1

(A) ← (A) + (M(DP))

AM

0

1

0

1

0

1

n

0

n

1

n

0

1

n

0

6

A

B

n

1

(A) ← (A) + (M(DP)) +(CY)

(CY) ← Carry

AMC

A n

(A) ← (A) + n

n = 0 to 15

(A) ← (A) AND (M(DP))

(A) ← (A) OR (M(DP))

AND

OR

0

1

0

1

0

1

8

9

1

(CY) ← 1

SC

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

7

1

(CY) ← 0

RC

6

(CY) = 0 ?

SZC

CMA

RAR

F

C

D

(A) ← (A)

→ CY → A3A2A1A0

(Mj(DP)) ← 1

j = 0 to 3

SB j

0

1

0

1

0

1

0

1

0

j

0

5

4

2

C

+j

1

(Mj(DP)) ← 0

j = 0 to 3

RB j

SZB j

C

+j

(Mj(DP)) = 0 ?

j = 0 to 3

j

(A) = (M(DP)) ?

SEAM

SEA n

0

1

0

1

0

2

6

1

2

1

2

(A) = n ?

n = 0 to 15

0

1

0

1

0

n

1

n

0

n

1

n

0

2

7

5

n

Note :p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4.

90

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Datailed description

Continuous

description

–

Loads the value n in the immediate field to register A.

When the LA instructions are continuously coded and executed, only the first LA instruction is executed and

other LA instructions coded continuously are skipped.

–

Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad-

dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p.

When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.

–

Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re-

mains unchanged.

–

0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.

Overflow = 0

–

Adds the value n in the immediate field to register A, and stores a result in register A.

The contents of carry flag CY remains unchanged.

Skips the next instruction when there is no overflow as the result of operation.

Executes the next instruction when there is overflow as the result of operation.

–

Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re-

sult in register A.

Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result

in register A.

–

1

0

–

Sets (1) to carry flag CY.

–

Clears (0) to carry flag CY.

(CY) = 0

Skips the next instruction when the contents of carry flag CY is “0.”

Stores the one’s complement for register A’s contents in register A.

–

0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.

–

Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).

(Mj(DP)) = 0

j = 0 to 3

Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of

M(DP) is “0.”

Executes the next instruction when the contents of bit j of M(DP) is “1.”

(A) = (M(DP))

(A) = n

–

Skips the next instruction when the contents of register A is equal to the contents of M(DP).

Executes the next instruction when the contents of register A is not equal to the contents of M(DP).

Skips the next instruction when the contents of register A is equal to the value n in the immediate field.

Executes the next instruction when the contents of register A is not equal to the value n in the immediate

field.

91

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (continued)

Instruction code

Parameter

Function

Mnemonic

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

B a

0

1

0

1

0

a6 a5 a4 a3 a2 a1 a0

1

0

2

8

+a

a

1

2

1

2

(PCL) ← a6–a0

BL p, a

1

p4 p3 p2 p1 p0

E p

+p

(PCH) ← p (Note)

(PCL) ← a6–a0

a6 a5 a4 a3 a2 a1 a0

a

BLA p

0

1

0

1

0

2

1

p

0

p

2

1

2

1

2

(PCH) ← p (Note)

(PCL) ← (DR2–DR0, A3–A0)

p4

p3 p2 p1 p0

BM a

0

1

0

a6 a5 a4 a3 a2 a1 a0

1

a

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← 2

(PCL) ← a6–a0

BML p, a

0

1

0

1

0

1

0

p4 p3 p2 p1 p0

0

2

C p

+p

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p (Note)

(PCL) ← a6–a0

a6 a5 a4 a3 a2 a1 a0

a

BMLA p

0

1

0

1

0

1

0

2

3

p

0

p

2

(SP) ← (SP) + 1

(SK(SP)) ← (PC)

(PCH) ← p (Note)

p4

p3 p2 p1 p0

(PCL) ← (DR2–DR0,A3–A0)

RTI

RT

0

1

0

1

0

1

0

4

6

4

5

1

2

(PC) ← (SK(SP))

(SP) ← (SP) – 1

(PC) ← (SK(SP))

(SP) ← (SP) – 1

RTS

(PC) ← (SK(SP))

(SP) ← (SP) – 1

Note :p is 0 to 15 for M34501M2, p is 0 to 31 for M34501M4/E4.

92

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Datailed description

Branch within a page : Branches to address a in the identical page.

Branch out of a page : Branches to address a in page p.

–

Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p.

–

Call the subroutine in page 2 : Calls the subroutine at address a in page 2.

Call the subroutine : Calls the subroutine at address a in page p.

Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D

and A in page p.

–

Returns from interrupt service routine to main routine.

Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de-

scription of the LA/LXY instruction, register A and register B to the states just before interrupt.

–

Returns from subroutine to the routine called the subroutine.

–

Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.

Skip at uncondition

93

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Parameter

Function

Mnemonic

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

DI

0

1

0

1

0

1

0

1

0

3

4

5

8

1

(INTE) ← 0

(INTE) ← 1

EI

SNZ0

V10 = 0: (EXF0) = 1 ?

After skipping, (EXF0) ← 0

V10 = 1: SNZ0 = NOP

SNZI0

0

1

0

1

0

3

A

1

I12 = 0 : (INT) = “L” ?

I12 = 1 : (INT) = “H” ?

TAV1

TV1A

TAV2

TV2A

TAI1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

5

3

5

3

5

1

4

0

4

0

5

1

7

4

F

5

E

3

7

B

E

C

F

0

3

0

1

(A) ← (V1)

(V1) ← (A)

(A) ← (V2)

(V2) ← (A)

(A) ← (I1)

TI1A

(I1) ← (A)

TAW1

TW1A

TAW2

TW2A

TAW6

TW6A

TAB1

(A) ← (W1)

(W1) ← (A)

(A) ← (W2)

(W2) ← (A)

(A) ← (W6)

(W6) ← (A)

(B) ← (T17–T14)

(A) ← (T13–T10)

T1AB

1

0

1

0

2

3

0

1

(T17–T14) ← (B)

(R17–R14) ← (B)

(T13–T10) ← (A)

(R13–R10) ← (A)

TAB2

T2AB

1

0

1

0

1

0

1

2

7

3

1

(B) ← (T27–T24)

(A) ← (T23–T20)

(T27–T24) ← (B)

(R27–R24) ← (B)

(T23–T20) ← (A)

(R23–R20) ← (A)

TR1AB

SNZT1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

3

8

F

0

1

(R17–R14) ← (B)

(R13–R10) ← (A)

V12 = 0: (T1F) = 1 ?

After skipping, (T1F) ← 0

V12 = 1: SNZT1 = NOP

SNZT2

1

0

1

0

1

2

8

1

V13 = 0: (T2F) = 1 ?

After skipping, (T2F) ← 0

V13 = 1: SNZT2 = NOP

94

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Datailed description

–

Clears (0) to interrupt enable flag INTE, and disables the interrupt.

Sets (1) to interrupt enable flag INTE, and enables the interrupt.

–

V10 = 0: (EXF0) = 1

When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,

clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.

When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register

V1)

(INT) = “L”

However, I12 = 0

–

When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when

the level of INT pin is “H.”

(INT) = “H”

However, I12 = 1

When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when

the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)

–

Transfers the contents of interrupt control register V1 to register A.

Transfers the contents of register A to interrupt control register V1.

Transfers the contents of interrupt control register V2 to register A.

Transfers the contents of register A to interrupt control register V2.

Transfers the contents of interrupt control register I1 to register A.

Transfers the contents of register A to interrupt control register I1.

Transfers the contents of timer control register W1 to register A.

Transfers the contents of register A to timer control register W1.

Transfers the contents of timer control register W2 to register A.

Transfers the contents of register A to timer control register W2.

Transfers the contents of timer control register W6 to register A.

Transfers the contents of register A to timer control register W6.

Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.

Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.

–

Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Trans-

fers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.

–

Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.

Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.

Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Trans-

fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.

–

Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the con-

tents of register A to the low-order 4 bits (R13–R10) of reload register R1.

V12 = 0: (T1F) = 1

When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping,

clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction.

When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)

V13 = 0: (T2F) =1

–

When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping,

clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction.

When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)

95

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Parameter

Function

Mnemonic

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

IAP0

OP0A

IAP1

OP1A

IAP2

1

0

1

0

1

0

1

0

1

0

1

0

2

6

2

6

2

6

0

1

2

1

(A) ← (P0)

(P0) ← (A)

(A) ← (P1)

(P1) ← (A)

(A1, A0) ← (P21, P20)

(A3, A2) ← 0

OP2A

CLD

RD

1

0

1

0

1

0

1

0

1

0

2

0

2

1

2

1

4

1

(P21, P20) ← (A1, A0)

(D) ← 1

(D(Y)) ← 0

(Y) = 0 to 3

SD

0

1

0

1

0

1

0

1

5

1

2

1

2

(D(Y)) ← 1

(Y) = 0 to 3

SZD

0

1

0

1

0

1

0

1

0

2

4

(D(Y)) = 0 ?

(Y) = 0 to 3

B

SCP

1

0

1

0

1

0

1

0

1

2

8

D

C

9

1

(C) ← 1

(C) ← 0

(C) = 1?

RCP

SNZCP

IAK

1

0

1

0

1

2

6

F

1

(A0) ← (K)

(A3–A1) ← 0

OKA

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

1

5

1

5

1

5

2

F

B

6

1

(K) ← (A0)

(K0) ← (A)

(A) ← (K0)

(K1) ← (A)

(A) ← (K1)

(K2) ← (A)

(A) ← (K2)

(PU0) ← (A)

(PU1) ← (A)

(PU2) ← (A)

TK0A

TAK0

TK1A

TAK1

TK2A

TAK2

TPU0A

TPU1A

TPU2A

4

9

5

A

D

E

F

96

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

Datailed description

–

Transfers the input of port P0 to register A.

Outputs the contents of register A to port P0.

Transfers the input of port P1 to register A.

Outputs the contents of register A to port P1.

Transfers the input of port P2 to the low-order 2 bits (A1, A0) of register A.

–

Outputs the contents of the low-order 2 bits (A1, A0) of register A to port P2.

Sets (1) to port D.

Clears (0) to a bit of port D specified by register Y.

–

Sets (1) to a bit of port D specified by register Y.

(D(Y)) = 0 ?

(Y) = 0 to 3

Skips the next instruction when a bit of port D specified by register Y is “0.” Executes the next instruction

when a bit of port D specified by register Y is “1.”

–

Sets (1) to port C.

Clears (0) to port C.

(C) = 1

Skips the next instruction when the contents of port C is “1.”

Executes the next instruction when the contents of port C is “0.”

–

Transfers the contents of port K to the bit 0 (A0) of register A.

–

Outputs the contents of bit 0 (A0) of register A to port K.

Transfers the contents of register A to key-on wakeup control register K0.

Transfers the contents of key-on wakeup control register K0 to register A.

Transfers the contents of register A to key-on wakeup control register K1.

Transfers the contents of key-on wakeup control register K1 to register A.

Transfers the contents of register A to key-on wakeup control register K2.

Transfers the contents of key-on wakeup control register K2 to register A.

Transfers the contents of register A to pull-up control register PU0.

Transfers the contents of register A to pull-up control register PU1.

Transfers the contents of register A to pull-up control register PU2.

97

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)

Instruction code

Parameter

Function

Mnemonic

TABAD

Hexadecimal

notation

Type of

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

instructions

1

0

1

0

1

2

7

9

1

In A-D conversion mode (Q13 = 0),

(B) ← (AD9–AD6)

(A) ← (AD5–AD2)

In comparator mode (Q13 = 1),

(B) ← (AD7–AD4)

(A) ← (AD3–AD0)

TALA

1

0

1

0

1

0

1

0

1

2

4

3

9

1

(A3, A2) ← (AD1, AD0)

(A1, A0) ← 0

TADAB

(AD7–AD4) ← (B)

(AD3–AD0) ← (A)

TAQ1

TQ1A

ADST

1

0

1

0

1

0

1

0

1

0

1

2

4

0

9

4

F

1

(A) ← (Q1)

(Q1) ← (A)

(ADF) ← 0

Q13 = 0: A-D conversion starting

Q13 = 1: Comparator operation starting

SNZAD

1

0

1

0

1

2

8

7

1

V22 = 0: (ADF) = 1 ?

After skipping, (ADF) ← 0

V22 = 1: SNZAD = NOP

NOP

POF

0

1

0

2

1

(PC) ← (PC) + 1

RAM back-up

However, voltage drop detection circuit is valid

POF2

0

1

0

8

1

RAM back-up

EPOF

SNZP

0

1

0

1

0

1

0

1

0

5

0

B

3

1

POF or POF2 instruction valid

(P) = 1 ?

DWDT

WRST

1

0

1

0

1

0

1

0

1

0

2

9

C

1

Stop of watchdog timer function enabled

A 0

(WDF1) = 1,

after skipping,

(WDF1) ← 0

CMCK

CRCK

TAMR

TMRA

1

0

1

0

1

0

1

0

1

0

1

0

2

9

5

1

A

B

2

6

1

Ceramic resonator selected

RC oscillation selected

(A) ← (MR)

(MR) ← (A)

98

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Skip condition

–

Datailed description

–

In the A-D conversion mode (Q13 = 0), transfers the high-order 4 bits (AD9–AD6) of register AD to register

B, and the middle-order 4 bits (AD5–AD2) of register AD to register A.

In the comparator mode (Q13 = 1), transfers the middle-order 4 bits (AD7–AD4) of register AD to register B,

and the low-order 4 bits (AD3–AD0) of register AD to register A.

(Q13: bit 3 of A-D control register Q1)

–

Transfers the low-order 2 bits (AD1, AD0) of register AD to the high-order 2 bits (AD3, AD2) of register A.

In the A-D conversion mode (Q13 = 0), this instruction is equivalent to the NOP instruction.

In the comparator mode (Q13 = 1), transfers the contents of register B to the high-order 4 bits (AD7–AD4) of

comparator register, and the contents of register A to the low-order 4 bits (AD3–AD0) of comparator register.

(Q13 = bit 3 of A-D control register Q1)

–

Transfers the contents of A-D control register Q1 to register A.

Transfers the contents of register A to A-D control register Q1.

Clears (0) to A-D conversion completion flag ADF, and the A-D conversion at the A-D conversion mode (Q13

= 0) or the comparator operation at the comparator mode (Q13 = 1) is started.

(Q13 = bit 3 of A-D control register Q1)

V22 = 0: (ADF) = 1

–

When V22 = 0 : Skips the next instruction when A-D conversion completion flag ADF is “1.” After skipping,

clears (0) to the ADF flag. When the ADF flag is “0,” executes the next instruction.

When V22 = 1 : This instruction is equivalent to the NOP instruction. (V22: bit 2 of interrupt control register V2)

–

No operation; Adds 1 to program counter value, and others remain unchanged.

Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruc-

tion. However, the voltage drop detection circuit is valid.

–

Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction.

Operations of all functions are stopped.

–

Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.

(P) = 1

Skips the next instruction when the P flag is “1”.

After skipping, the P flag remains unchanged.

Executes the next instruction when the P flag is “0.”

–

Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.

(WDF1) = 1

Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears (0) to the WDF1 flag.

When the WDF1 flag is “0,” executes the next instruction. Also, stops the watchdog timer function when ex-

ecuting the WRST instruction immediately after the DWDT instruction.

–

Selects the ceramic oscillation circuit and stops the ring oscillator.

Selects the RC oscillation circuit and stops the ring oscillator.

Transfers the contents of clock control register MR to register A.

Transfers the contents of register A to clock control register MR.

99

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INSTRUCTION CODE TABLE

010000 011000

001100

0C

D9–D4 000000000001000010000011000100000101000110 000111001000001001001010001011

001101001110 001111

010111 011111

Hex.

00

01

02

03

04

–

05

06

07

08

09

0A

–

0B

–

0D

0E

0F 10–17 18–1F

D3–D0

0000

notation

SZB

0

A

0

LA TABP TABP

16*

LA TABP TABP

17*

LA TABP TABP

18*

LA TABP TABP

19*

LA TABP TABP

20*

LA TABP TABP

21*

LA TABP TABP

22*

LA TABP TABP

23*

LA TABP TABP

24*

LA TABP TABP

25*

LA TABP TABP

10 10 26*

LA TABP TABP

11 11 27*

LA TABP TABP

12 12 28*

LA TABP TABP

13 13 29*

LA TABP TABP

14 14 30*

LA TABP TABP

15 15 31*

0

NOP BLA

BMLA

TASP

TAD

TAX

TAZ

BML BML* BL

BL*

BM

B

0

SZB

1

A

1

0001

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

–

CLD

–

1

SZB

2

A

2

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

POF

–

2

SZB

3

A

3

SNZP INY

–

3

A

4

SZD

SEAn

SEAM

–

DI

EI

RD

SD

–

RT TAV1

RTS TAV2

4

A

5

–

5

A

6

RC

–

RTI

–

6

A

7

SC DEY

–

SNZ0

–

7

LZ

0

A

8

–

POF2 AND

–

8

LZ

1

A

9

TDA

TABE

–

OR

AM TEAB

AMC

TYA CMA

RAR

TBA TAB

TAY

–

9

LZ

2

A

10

SNZI0

–

LZ

3

A

11

–

EPOF

RB

0

SB

0

A

12

–

RB

1

SB

1

A

13

–

RB

2

SB

2

A

14

–

TV2A

TV1A

RB

3

SB

3

A

15

SZC

–

The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order

4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal representa-

tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is

shown. Do not use code marked “–.”

The codes for the second word of a two-word instruction are described below.

The second word

• * cannot be used in the M34501M2-XXXFP.

BL

10 0aaa aaaa

10 0p00 pppp

00 0111 nnnn

00 0010 1011

BML

BLA

BMLA

SEA

SZD

100

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INSTRUCTION CODE TABLE (continued)

110000

101100

2C

D9–D4 100000100001100010100011100100100101100110 100111101000101001101010101011

101101101110 101111

111111

2F 30–3F

Hex.

20

–

21

22

23

24

25

TAW6 IAP0 TAB1 SNZT1

IAP1 TAB2 SNZT2

26

27

28

29

2A

2B

2D

2E

D3–D0

0000

notation

TMA

0

TAM XAM XAMI XAMD

0

LXY

0

–

OP0A T1AB

OP1A T2AB

–

WRST

0

TMA

1

TAM XAM XAMI XAMD

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

–

0001

1

TMA

2

TAM XAM XAMI XAMD

2

–

OP2A

–

TAMR IAP2

–

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2

TMA

3

TAM XAM XAMI XAMD

3

–

TW6A

–

TAI1

–

3

TMA TAM XAM XAMI XAMD

TQ1A TK1A

–

TAQ1

–

4

TMA TAM XAM XAMI XAMD

–

TK2A

–

TAK0

–

5

TMA

6

TAM XAM XAMI XAMD

6

–

TMRA

–

SNZAD

–

6

TMA

7

TAM XAM XAMI XAMD

7

–

TI1A

–

7

TMA

8

TAM XAM XAMI XAMD

8

–

8

TMA

9

TAM XAM XAMI XAMD

9

–

TADAB TALA TAK1

–

TABADSNZCP

–

9

TMA TAM XAM XAMI XAMD

10

10 10 10 10

TMA TAM XAM XAMI XAMD

11

TMA TAM XAM XAMI XAMD

–

TAK2

–

CMCK

CRCK

–

TK0A

TAW1

–

11

12

11

12

11

12

–

TAW2

–

RCP DWDT

12

TAM XAM XAMI XAMD

13 13 13 13

TAM XAM XAMI XAMD

14 14 14 14

TAM XAM XAMI XAMD

15 15 15 15

TMA

13

TPU0A

TPU1A

–

SCP

–

TMA

14

TW1A

–

TMA

15

TW2A OKA TPU2ATR1AB

IAK

ADST

The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-

order 4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal

representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of

each instruction is shown. Do not use code marked “–.”

The codes for the second word of a two-word instruction are described below.

The second word

BL

10 0aaa aaaa

10 0p00 pppp

00 0111 nnnn

00 0010 1011

BML

BLA

BMLA

SEA

SZD

101

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RAINGS

Parameter

Symbol

VDD

VI

Conditions

Ratings

–0.3 to 6.5

Unit

V

Supply voltage

Input voltage P0, P1, P2, D2/C, D3/K, RESET, XIN

Input voltage D0, D1

–0.3 to VDD+0.3

–0.3 to 13.0

–0.3 to VDD+0.3

–0.3 to 13.0

–0.3 to VDD+0.3

300

V

VI

V

Input voltage AIN0–AIN1

VI

V

Output voltage P0, P1, P2, D2/C, D3/K, RESET

Output voltage D0, D1

VO

V

Output transistors in cut-off state

Ta = 25 °C

VO

V

Output voltage XOUT

V

VO

Power dissipation

mW

°C

Pd

–20 to 85

Operating temperature range

Storage temperature range

Topr

Tstg

–40 to 125

102

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

RECOMMENDED OPERATING CONDITIONS 1 (Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted)

Limits

Symbol

VDD

Parameter

Supply voltage

Conditions

f(XIN) ≤ 4.4 MHz

Unit

V

Min.

2.7

Typ.

Max.

5.5

High-speed mode

(Note 1)

Middle-speed mode

Low-speed mode

Default mode

V

1.8 (Note 2)

VRAM

RAM back-up voltage

(at RAM back-up mode with the POF2

instruction)

V

0

VSS

VIH

Supply voltage

0.8VDD

0.85VDD

VDD

12

“H” level input voltage

P0, P1, P2, D2, D3, XIN

D0, D1

VDD

0.2VDD

0.16VDD

0.3VDD

0.15VDD

10

RESET

VDD = 4.0 to 5.5 V 0.5VDD

C, K

VDD = 2.7 to 5.5 V 0.7VDD

0.85VDD

VIH

VIL

“H” level input voltage

“L” level input voltage

CNTR, INT

P0, P1, P2, D0–D3, XIN

C, K

0

V

0

RESET

0

CNTR, INT

P2, RESET

mA

VDD = 5.0 V

IOL(peak) “L” level peak output current

40

D0, D1

24

D2/C, D3/K

P0, P1

24

5.0

IOL(avg)

“L” level average output current

P2, RESET (Note 3)

D0, D1 (Note 3)

D2/C, D3/K (Note 3)

P0, P1 (Note 3)

P2, D, RESET

P0, P1

30

15

12

80

ΣIOL(avg) “L” level total average current

80

Notes 1: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less.

2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (system enters into the reset state when the value is

VRST or less). In the RAM back-up mode with the POF2 instruction, the voltage drop detection circuit stops.

3: The average output current (IOH, IOL) is the average value during 100 ms.

External clock input (ceramic resonator selected)

RST (Note)

Ceramic resonator and high-speed mode selected

VRST (Note)

V

f [MHz]

4.4

f [MHz]

3.2

Recommended operating

condition

Recommended operating

condition

VDD[V]

2.7

4.2

5.5

2.7

4.2

5.5

Note: It shows the electrical characteristics range of detected voltage

for voltage drop detection circuit.

System reset occurs when the supply voltage is under

the detected voltage for voltage drop detection circuit.

103

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

RECOMMENDED OPERATING CONDITIONS 2 (Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted)

Limits

Symbol

f(XIN)

Parameter

Unit

Conditions

Typ.

Max.

4.4

Min.

Oscillation frequency

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

MHz

(with a ceramic resonator/

RC oscillation) (Note)

MHz

%

f(XIN)

Oscillation frequency

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

3.2

(with a ceramic resonator selected,

external clock input)

∆ f(XIN)

Oscillation frequency

VDD = 5.0 V ±10 %,

±17

(at RC oscillation, error value of

exteranal R, C not included)

Note: use 30 pF capacitor and vary external R

Ta = 25 °C, –20 to 85 °C

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

Hz

s

f(CNTR) Timer external input frequency

f(XIN)/6

f(XIN)/12

f(XIN)/24

f(XIN)/48

tw(CNTR) Timer external input period

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

3/f(XIN)

6/f(XIN)

(“H” and “L” pulse width)

12/f(XIN

24/f(XIN

)

µs

TPON

Valid supply voltage rising time for

power-on reset circuit

VDD = 0 → 2.0 V

100

Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.

104

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Ta = –20 °C to 85 °C, VDD = 2.7 to 5.5 V, unless otherwise noted)

Limits

Typ. Max.

2.0

Symbol

Parameter

Test conditions

Unit

V

Min.

VDD = 5.0 V

VI = VDD

IOL = 12 mA

VOL

“L” level output voltage P0, P1

IOL = 4.0 mA

IOL = 5.0 mA

IOL = 1.0 mA

IOL = 30 mA

IOL = 10 mA

IOL = 15 mA

IOL = 5.0 mA

0.9

VOL

IIH

“L” level output voltage P2, RESET

“L” level output voltage D0, D1

2.0

V

0.6

2.0

0.9

2.0

V

“L” level output voltage D2/C, D3/K

0.9

1.0

µA

“H” level input current

P0, P1, P2, D2/C, D3/K, RESET

“H” level input current D0, D1

“L” level input current P0, P1, P2

“L” level input current

VI = 12 V

µA

IIH

IIL

1.0

VI = 0 V P0, P1, P2 No pull-up

VI = 0 V, D2/C, D3/K, No pull-up

–1.0

D0, D1, D2/C, D3/K

VDD = 5.0 V

1.7

1.3

1.1

1.0

50

5.0

3.9

3.3

3.0

100

mA

IDD

Supply current at active mode

(Notes 1, 2)

High-speed mode

f(XIN) = 4.0 MHz

VDD = 5.0 V

Middle-speed mode

Low-speed mode

Default mode

µA

at RAM back-up mode

(POF instruction execution)

at RAM back-up mode

(POF2 instruction execution)

Ta = 25 °C

0.1

60

1.0

10

VDD = 5.0 V

VDD = 3.0 V

6.0

150

VI = 0 V, VDD = 5.0 V

kΩ

RPU

Pull-up resistor value

30

P0, P1, P2, D2/C, D3/K, RESET

Hysteresis INT, CNTR

VDD = 5.0 V

0.25

1.2

V

VT+ – VT–

VT+ – VT– Hysteresis RESET

f(RING)

Ring oscillator clock frequency (Note 3)

2.0

3.0

MHz

1.0

Notes 1: The operation current of the voltage drop detection circuit is included.

2: When the A-D converter is used, the A-D operation current (IADD) is included.

3: When system operates by the ring oscillator, the system clock frequency is the ring oscillator clock divided by the dividing ratio selected with register

MR.

105

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

A-D CONVERTER RECOMMENDED OPERATING CONDITIONS

(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)

Limits

Typ.

Unit

V

Symbol

VDD

Parameter

Supply voltage

Conditions

Max.

5.5

Min.

2.7 (Note)

3.0

Ta = 25 °C

Ta = –20 °C to 85 °C

5.5

V

VIA

Analog input voltage

Oscillation frequency

VDD+2LSB

0

MHz

f(XIN)

VDD = VRST to 5.5 V High-speed mode

Middle-speed mode

0.1

0.2

Low-speed mode

0.4

Default mode

0.8

Note: System is in the reset state when the value is the detection voltage of the voltage drop detection circuit or less.

A-D CONVERTER CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted)

Limits

Typ.

Unit

Symbol

Parameter

Test conditions

Max.

10

Min.

–

Resolution

bits

Ta = 25 °C, VDD = VRST to 5.5 V

Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V

Ta = 25 °C, VDD = VRST to 5.5 V

Ta = –25 °C to 85 °C, VDD = 3.0 V to 5.5 V

VDD = 5.12 V

Linearity error

±2.0

LSB

–

Differential non-linearity error

±0.9

mV

mA

µs

V0T

Zero transition voltage

20

5125

0.3

30

5135

0.9

46.5

93.0

186

372

8

10

VDD = 5.12 V

VFST

IADD

TCONV

Full-scale transition voltage

A–D operating current (Note 1)

A-D conversion time

5115

VDD = 5.0 V

f(XIN) = 0.4 MHz to 4.0 MHz

High-speed mode

Middle-speed mode

Low-speed mode

f(XIN) = 4.0 MHz

Default mode

bits

mV

µs

Comparator mode

VDD = 5.12 V

–

Comparator resolution

Comparator error (Note 2)

Comparator comparison time

±20

6.0

12

f(XIN) = 4.0 MHz

High-speed mode

Middle-speed mode

Low-speed mode

Default mode

24

48

Notes 1: When the A-D converter is used, the IADD is included to IDD.

2: As for the error from the logic value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison

voltage Vref which is generated by the built-in DA converter can be obtained by the following formula.

Logic value of comparison voltage Vref

VDD

Vref =

✕ n

256

n = Value of register AD (n = 0 to 255)

106

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS

(Ta = –20 °C to 85 °C, unless otherwise noted)

Limits

Unit

Symbol

VRST

Parameter

Test conditions

Min.

2.7

Typ.

Max.

4.2

V

Detection voltage (Note 1)

Ta = 25 °C

3.3

3.5

50

3.7

Operation current of voltage RAM back-up mode

drop detection circuit

VDD = 5.0 V

100

µA

IRST

(POF instruction execution) (Note 2)

Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs while the supply voltage (VDD) is falling.

2: The voltage drop detection circuit is operating in the RAM back-up with the POF instruction (It stops in the RAM back-up with the POF2 instruction).

BASIC TIMING DIAGRAM

Machine cycle

Mi

Mi+1

Pin name

Parameter

Clock

XIN : high-speed mode

(System clock = f(XIN))

X

IN : middle-speed mode

(System clock = f(XIN)/2)

X

IN : low-speed mode

(System clock = f(XIN)/4)

X

IN : default mode

(System clock = f(XIN)/8)

D

0

, D

1

, D

2

/C, D

3

/K

Port D output

Port D input

D

0, D

1

, D

2/C, D

3/K

Port P0, P1, P2

output

P0

P1

P2

0

–P0

–P1

, P2

3

1

Port P0, P1, P2

input

P0

P1

P2

0

–P0

–P1

, P2

3

1

Timer output

Timer input

CNTR

Interrupt input

INT

107

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

BUILT-IN PROM VERSION

In addition to the mask ROM versions, the 4501 Group has the

One Time PROM versions whose PROMs can only be written to

and not be erased.

The built-in PROM version has functions similar to those of the

mask ROM versions, but it has PROM mode that enables writing to

built-in PROM.

Table 20 shows the product of built-in PROM version. Figure 52

shows the pin configurations of built-in PROM versions.

The One Time PROM version has pin-compatibility with the mask

ROM version.

Table 20 Product of built-in PROM version

PROM size

(✕ 10 bits)

4096 words

RAM size

(✕ 4 bits)

256 words

Package

20P2N-A

Product

M34501E4FP

ROM type

One Time PROM [shipped in blank]

(1) PROM mode

The 4501 Group has a PROM mode in addition to a normal opera-

tion mode. It has a function to serially input/output the command

codes, addresses, and data required for operation (e.g., read and

program) on the built-in PROM using only a few pins. This mode

can be selected by setting pins SDA (serial data input/output),

SCLK (serial clock input), PGM to “H” after connecting wires as

shown in Figure 54 and powering on the VDD pin, and then apply-

ing 12 V to the VPP pin.

Writing with PROM programmer

Screening (Leave at 150 °C for 40 hours) (Note)

Verify test with PROM programmer

Function test in target device

In the PROM mode, three types of software commands (read, pro-

gram, and program verify) can be used. Clock-synchronous serial

I/O is used, beginning from the LSB (LSB first).

Use the special-perpose serial programmer when performing serial

read/program.

As for the serial programmer for the Mitsubishi single-chip micro-

computer (serial programmer and control software), refer to the

“Mitsubishi Microcomputer Development Support Tools” Hompage

(http://www.tool-spt.mesc.co.jp/index_e.htm).

Since the screening temperature is higher

than storage temperature, never expose the

microcomputer to 150 °C exceeding 100

hours.

Note:

(2) Notes on handling

✕A high-voltage is used for writing. Take care that overvoltage is

not applied. Take care especially at turning on the power.

✕For the One Time PROM version shipped in blank, Mitsubishi

Electric corp. does not perform PROM writing test and screening

in the assembly process and following processes. In order to im-

prove reliability after writing, performing writing and test

according to the flow shown in Figure 53 before using is recom-

mended (Products shipped in blank: PROM contents is not

written in factory when shipped).

Fig. 53 Flow of writing and test of the product shipped in blank

108

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PIN CONFIGURATION (TOP VIEW)

P0

P1

0

1

2

3

0

1

2

3

1

2

20

19

18

17

16

15

V

DD

SS

V

DD

SS

IN

OUT

V

3

X

4

X

5

V

PP

CNVSS

RESET

6

7

14 P1

/CNTR

/INT

P2

1

/AIN1

/AIN0

S

CLK

V

DD

8

13

12

11

P1

SDA

PGM

P2

0

9

D

0

1

D

3

/K

10

D

2

/C

Outline 20P2N-A

Fig. 54 Pin configuration of built-in PROM version

109

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PACKAGE OUTLINE

20P2N-A

Plastic 20pin 300mil SOP

EIAJ Package Code

SOP20-P-300-1.27

JEDEC Code

Weight(g)

0.26

Lead Material

Cu Alloy

e

b2

–

20

11

Recommended Mount Pad

Dimension in Millimeters

Symbol

Min

–

0

Nom

–

Max

2.1

0.2

–

0.5

0.25

12.7

5.4

–

F

1

10

A

1

2

0.1

1.8

0.4

0.2

12.6

5.3

1.27

7.8

0.6

1.25

0.585

–

D

G

b

0.35

0.18

12.5

5.2

–

7.5

0.4

–

c

D

E

e

A2

A1

b

x

M

HE

8.1

0.8

–

e

L

y

L

1

z

–

Z

1

0.735

0.25

0.1

8°

x

y

–

c

0°

b

e

2

–

1.27

0.76

7.62

–

z

1

Z

1

Detail G

Detail F

I2

110

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN

Keep safety first in your circuit designs!

•

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to

personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable

material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

•

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Printed in Japan (ROD) II

New publication, effective June. 2001.

Specifications subject to change without notice.

REVISION DESCRIPTION LIST

4501 GROUP DATA SHEET

Rev.

date

Revision Description

No.

1.0 First Edition

000711

000726

1.1 Page 5:

Input/Output ports; Description of AIN0–AIN3 added.

Page 25: Fig.18 to Fig. 20; Description of “✕” revised.

Page 33: (2) Successive comparison register AD;

this instruction (error) → these instructions (correct)

Page 42: Table 16; Return condition of port P13/INT revised

bit 1 (error) → bit 2 (correct), EXF1 (error) → EXF0 (correct)

Pages 49 to 51: Fig. 46 to Fig. 49; Description of “✕” revised.

Page 73: SEAM; Instruction code 0000010110 (error) → 0000100110 (correct)

Page 80: Description AD3, AD2 (error) → A3, A2 (correct)

Page 88: WRST;

Operation: (WDF) ← 1? (error) → (WDF1) = 1? (correct)

Description:

Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears

(0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction.......

Page 91: Description of DEY; “Subtracts 1 from the contents of register Y.” added.

Page 93: Description of SEAM and description of SEA n are exchanged.

Page 100: WRST;

(WDF1) ← 0,

after skipping,

(WDF1) ← 1

(error)

(WDF1) = 1,

after skipping,

(WDF1) ← 0

(correct)

→

Page 101: WRST;

Skip condition: (WDF) = 1 (error) → (WDF1) = 1 (correct)

Description:

Skips the next instruction when watchdog timer flag WDF1 is “1.” After skipping, clears

(0) to the WDF1 flag. When the WDF1 flag is “0,” executes the next instruction.......

Page 110: (1) PROM mode; 12.5 V (error) → 12 V (correct)

Fig. 52; title revised

1.2 Pages 3, 4, 22 : Character fonts errors revised

000905

(1/2)

REVISION DESCRIPTION LIST

4501 GROUP DATA SHEET

Rev.

No.

2.0 The 4501/4502 Group data sheet is separated.

Rev.

date

Revision Description

010620

Page 9: Port block diagram (3); Block diagram of P12/CNTR pin revised.

Page 25: Fig. 22 Timers structure; Block diagram of P12/CNTR pin revised.

Page 28: (9) Precautions → (8) Precautions

(8) Timer input/output pin (P12/CNTR pin) added.

Fig. 23 added.

Page 29: WATCHDOG TIMER revised all.

Page 30: Fig. 24 → Fig. 25, Fig. 25 → Fig. 26

Fig. 26 NOP instruction added

Page 39: Fig. 37 Note 3 added.

Page 61: BL p, a, BLA p instructions revised.

Page 62: BML p, a, BMLA p instructions revised.

Page 76: TABP p instruction revised.

Page 90: TABP p instruction revised.

Page 92: BL p, a, BLA p, BML p, a, BMLA p instructions revised.

Page 100: BL, BML, BLA, BMLA instructions; The second word revised.

Page 101: BL, BML, BLA, BMLA instructions; The second word revised.

Page 102: ABSOLUTE MAXIMUM RATINGS; VDD –0.3 to 6.0 → –0.3 to 6.5

Page 103: RECOMMENDED OPERATING CONDITIONS 1;

VRST → 2.7

Note 1 revised.

Operating condition map added.

Page 104: RECOMMENDED OPERATING CONDITIONS 2; VRST → 2.7

Page 105: ELECTRICAL CHARACTERISTICS; VRST → 2.7

Page 106: A-D CONVERTER RECOMMENDED OPERATING CONDITIONS;

VDD (Ta = 25 °C) Min. VRST → 2.7, Note added

(2/2)


型号：	M34501E4FP
厂家：	Mitsubishi Group
描述：	SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 单片4位微机的CMOS 计算机
文件：	总113页 (文件大小：1236K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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