M37481E8FP [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M37481E8FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总97页 (文件大小：1068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
PIN CONFIGURATION
The 7480/7481 group is the single-chip microcomputer adopting
the silicon gate CMOS process. In addition to its simple instruction
set, the ROM, RAM, and I/O addresses are placed in the same
memory space.
Having built-in serial I/O, A-D converter, and watchdog timer, this
single-chip microcomputer is useful for control of automobiles, of-
fice automation equipment and home electric appliances.
The 7480/7481 group includes multiple types which differ in the
memory type, size, and package.
1
2
3
4
5
6
32
31
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
1
0
P17/SRDY
P1
P1
P1
6
5
4
/SCLK
30
29
28
/TX
D
/RX
D
P1
P1
3
2
/T
1
0
1
0
FEATURES
27
26
25
24
23
22
21
20
19
18
17
/T
●Number of basic machine language instructions ..................... 71
●Minimum instruction execution time ...................................0.5 µs
(at 8 MHz clock input oscillation frequency)
7
8
P1
P1
9
P2
3
2
1
0
/IN
/IN
/IN
/IN
3
2
1
0
/CNTR
/CNTR
1
0
●Memory size ROM ........................................... 4 K to 16 K bytes
RAM ............................................ 128 to 448 bytes
●Programmable I/O ports .................................... 18 (7480 group)
10
P2
P2
P2
11
12
13
14
15
16
(P0, P1, P4, P5)
●Input ports ............................................................ 8 (7480 group)
(P2, P3) 12 (7481 group)
24 (7481 group)
V
REF
IN
OUT
SS
/INT
/INT
1
0
X
●Built-in programmable pull-up transistors (P0, P1)
●Built-in clamp diodes............................................ 2 (7480 group)
X
RESET
V
V
CC
(P4, P5)
8 (7481 group)
●Interrupt ................................................... 14 sources, 13 vectors
●Timer X, Y..................................................................... 16-bit ✕ 2
●Timer 1, 2 ....................................................................... 8-bit ✕ 2
●Serial I/O ....................... 8-bit x 1 (UART or clock-synchronized)
●A-D converter ............................ 8-bit x 4 channels (7480 group)
8-bit x 8 channels (7481 group)
Outline 32P4B
●Built-in watchdog timer
●Power source voltage ................................................ 2.7 to 4.5 V
(at [2.2 VCC-2] MHz clock input oscillation frequency)
4.5 to 5.5 V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
7
6
5
4
3
2
1
0
1
0
3
2
1
0
P1
7
/SRDY
P1
P1
P1
6/SCLK
(at 8 MHz clock input oscillation frequency)
5
4
/T
XD
●Power dissipation .............................................................. 35 mW
(at 8 MHz clock input oscillation frequency and 5 V power
source voltage)
/RX
D
P1
3
2
/T
1
0
1
0
P1
/T
P1
P1
APPLICATIONS
Automobiles, office automation equipment, home electric appli-
ances, etc.
P2
3
2
1
0
/IN
/IN
/IN
/IN
3
2
1
0
/CNTR
/CNTR
1
0
10
11
12
13
14
P2
P2
P2
V
REF
IN
OUT
SS
/INT
1
0
X
/INT
X
15
16
RESET
V
VCC
Outline 32P2W-A
Fig. 1 Pin configuration (top view)
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
P5
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P4
P4
P3
P3
P3
P3
2
7
6
5
4
3
2
1
0
P5
3
P17/SRDY
P1
P1
P1
6
5
4
/SCLK
4
5
/TX
D
/R
X
D
P0
P0
P0
P0
P5
4
5
6
7
2
22
34
35
36
37
38
39
40
41
42
43
44
P3
0/INT0
6
P1
P1
3
2
/T
1
0
1
0
21
RESET
P5
P5
7
/T
20
19
1
0
8
P1
P1
9
M37481MX-XXXFP
M37481MXT-XXXFP
M37481E8-XXXFP
M37481E8T-XXXFP
18
17
16
15
14
13
12
V
V
CC
SS
10
P2
7
6
5
4
/IN
/IN
/IN
/IN
7
6
5
4
3
2
1
0
3
2
VSS
11
12
13
14
15
16
17
18
19
20
21
P2
P2
P2
P2
P2
P2
P2
AVSS
P5
3
1
0
3
2
1
0
/CNTR
1
0
P1
7
/SRDY
/SCLK
X
X
V
OUT
IN
/CNTR
P1
6
3
2
1
0
/IN
/IN
/IN
/IN
REF
P1
5
/T
X
X
D
D
P20/IN0
P1
4
/R
/INT
1
0
/INT
V
REF
IN
OUT
SS
RESET
X
P5
P5
1
0
X
V
VCC
Outline 42P4B
42S1B-A
Outline 44P6N-A
Fig. 2 Pin configuration (top view)
2
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7480/7481 GROUP PRODUCT LIST
Table 1. 7480/7481 group product list
Product model name
ROM (bytes)
4096
RAM (bytes)
128
I/O port
Package
32P4B
Remarks
M37480M2T-XXXSP
M37480M2T-XXXFP
M37480M4-XXXSP
M37480M4-XXXFP
M37480M4T-XXXSP
M37480M4T-XXXFP
M37480M8-XXXSP
M37480M8-XXXFP
M37480M8T-XXXSP
M37480M8T-XXXFP
M37480E8SP
Mask ROM version*
32P2W-A
32P4B
Mask ROM version
Mask ROM version*
Mask ROM version
Mask ROM version*
32P2W-A
32P4B
8192
256
32P2W-A
32P4B
18 I/O ports
32P2W-A
32P4B
8 input ports
(including 4 analog
input ports)
32P2W-A
32P4B
One time PROM version
(shipped in blank)
16384
448
M37480E8FP
32P2W-A
32P4B
M37480E8-XXXSP
M37480E8-XXXFP
M37480E8T-XXXSP
M37480E8T-XXXFP
M37481M2T-XXXSP
M37481M2T-XXXFP
M37481M4-XXXSP
M37481M4-XXXFP
M37481M4T-XXXSP
M37481M4T-XXXFP
M37481M8-XXXSP
M37481M8-XXXFP
M37481M8T-XXXSP
M37481M8T-XXXFP
M37481E8SP
One time PROM version
One time PROM version*
Mask ROM version*
Mask ROM version
32P2W-A
32P4B
32P2W-A
42P4B
4096
8192
128
256
44P6N-A
42P4B
44P6N-A
42P4B
Mask ROM version*
Mask ROM version
44P6N-A
42P4B
24 I/O ports
44P6N-A
42P4B
12 input ports
(including 8 analog
input ports)
Mask ROM version*
44P6N-A
42P4B
One time PROM version
(shipped in blank)
16384
448
M37481E8FP
44P6N-A
42P4B
M37481E8-XXXSP
M37481E8-XXXFP
M37481E8T-XXXSP
M37481E8T-XXXFP
M37481E8SS
One time PROM version
44P6N-A
42P4B
One time PROM version*
Built-in EPROM version
44P6N-A
42S1B-A
*: Extended operating temperature range version
3
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7480/7481 GROUP ROM/RAM DEVELOPMENT SCHEDULE
ROM size
(bytes)
M37481E8SS
M37480M8T/E8T-XXXSP/FP
M37481M8T/E8T-XXXSP/FP
16K
M37480M8/E8-XXXSP/FP
M37481M8/E8-XXXSP/FP
12K
M37480M4-XXXSP/FP
M37480M4T-XXXSP/FP
M37481M4-XXXSP/FP
M37481M4T-XXXSP/FP
8K
4K
M37480M2T-XXXSP/FP
M37481M2T-XXXSP/FP
: Being developed
: Being planned
0
128
256
384
448
RAM size
(bytes)
Note: Regarding the models being developed and planned, the development schedule may be reviewed. In case of the models be-
ing planned, the development of them may be stopped.
Fig. 3 ROM/RAM development schedule
4
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM
Fig. 4 Function block diagram (1)
5
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 5 Function block diagram (2)
6
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 6 Function block diagram (3)
7
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONS OF 7480/7481 GROUP
Table 2. Functions of 7480/7481 group
Functions
Parameter
M37480M4/M8/E8-XXXSP/FP
M37480M2T/M4T/M8T/E8T-XXXSP/FP
M37481M4/M8/E8-XXXSP/FP
M37481M2T/M4T/M8T/E8T-XXXSP/FP
Number of basic instructions
Instruction execution time
Clock input oscillation frequency
M8/E8
71 (740 family 69 basic instructions + 2 multiplication/division instructions)
0.5µs (Minimum instructions, at 8 MHz clock input oscillation frequency)
8 MHz (max.)
16384 bytes
8192 bytes
4096 bytes
448 bytes
ROM
M4
M2
Memory size
M8/E8
M4
RAM
256 bytes
M2
128 bytes
I/O
8 bits ✕ 2
P0, P1
P2
Input
Input
I/O
4 bits ✕ 1
8 bits ✕ 1
I/O port
4 bits ✕ 1
P3
2 bits ✕ 1
4 bits ✕ 1
4 bits ✕ 1
P4
I/O
—————
P5
I/O withstand voltage
Output current
5 V
I/O characteristics
–5 to 10 mA (P0, P1: CMOS tri-states), 10 mA (P4, P5: N channel)
Serial I/O
Timers
8 bits ✕ 1
16-bit timer x 2, 8-bit timer x 2
M8/E8
M4
192 max.
Subroutine nesting
Interrupt
96 max.
64 max.
M2
5 external interrupts, 8 internal interrupts, 1 software interrupt
8 bits ✕ 4 analog inputs
8 bits ✕ 8 analog inputs
A-D converter (successive comparison method)
(in common with P2)
(in common with P2)
Built-in circuit with feedback resistor (with external ceramic oscillator)
Built-in circuit
Clock generating circuit
Watchdog timer
2.7 to 4.5 V (at f(XIN) = (2.2VCC – 2) MHz)
4.5 to 5.5 V (at f(XIN)=8 MHz)
Power source voltage
35 mW (standard, at 8 MHz clock input oscillation frequency)
–20 to 85 °C (–40 to 85 °C for extended operating temperature range version)
CMOS silicon gate
Power dissipation
Operating temperature range
Device structure
Package
32-pin SDIP/32-pin SOP
42-pin SDIP/44-pin OFP
8
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 3. Pin description
Input/
output
Pin
Name
Functions
Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS.
VCC, VSS
AVSS
Power source
Analog power
source input
Ground level input pin for A-D converter. Apply the same voltage as Vss. (This
pin is for 44P6N-A package only.)
Reference voltage
input
Reference voltage input pin for A-D converter. (When the A-D converter is not
used, connect it to VCC.)
VREF
_____
RESET
Input
Input
Input
Reset input
Reset input pin active “L”.
These are I/O pins for the internal clock generating circuit of the main clock. To
control the generating frequency, an external ceramic is connected between
the XIN and XOUT pins. If an external clock is used, the clock source should be
connected to the XIN pin, and the XOUT pin should be left open. The feedback
resistor is connected between XIN and XOUT.
XIN
Clock input
XOUT
Clock output
I/O port P0
Output
I/O
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistors can be connected in
units of 1 bit, and a key-on wake-up function is provided.
P00 – P07
P10 – P17
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistors can be connected in
units of 4 bits. P12 and P13 are in common with timer output pins T0 and T1.
I/O port P1
I/O
P14, P15, P16 and P17 are in common with serial I/O pins RXD, TXD, SCLK and
____
SRDY, respectively.
8-bit input port. (Only 4 bits of P20 to P23 for the 7480 group) or analog input
pins IN0 to IN7 (IN0 to IN3 for the 7480 group).
Input
P20 – P27
P30 – P33
Input port P2
Input port P3
4-bit input port. P30 and P31 can be configured to serve as external interrupt
input pins INT0 and INT1.
Input
I/O
4-bit I/O port. (2 bits of P40 and P41 for the 7480 group). The output structure
is N-channel open drain output, having a built-in clamp diode. P40 and P41 can
be configured to serve as timer I/O pins CNTR0 and CNTR1.
P40 – P43
P50 – P53
I/O port P4
I/O port P5
4-bit I/O port. (This port is not included in the 7480 group.) The output structure
is N-channel open drain output, having built-in clamp diodes.
I/O
9
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7480/7481 group uses the standard 740 family CPU. Refer to
the table of 740 family addressing modes and machine instruc-
tions or the MELPS 740 programming manual for details on the
instruction set.
CPU Mode Register
The stack page selection bit is assigned to the CPU mode regis-
ter. This register is allocated at address 00FB16.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions are not available.
2. The MUL and DIV instructions are available.
3. The WIT instruction is available. (Note)
4. The STP instruction is available. (Note)
Note: When using these instructions, refer to the corresponding
chapter “STP and WIT instruction control” below.
b7
b0
CPU mode register (CPUM: address 00FB16)
Not used.
These bits must always be set to “0”.
Stack page selection bit (Note)
0
:
Page 0
1
:
Page 1
Watchdog timer L count source selection bit
0
:
f(XIN)/8
1
:
f(XIN)/16
Not used (undefined at read)
System clock division proportion selection bit
0
: f = f(XIN)/2 (high-speed mode)
1
: f = f(XIN)/8 (medium-speed mode)
Not used (undefined at read)
Note : In the models of RAM size under 192 bytes, set this bit to “0”.
Fig. 7 Structure of CPU mode register
10
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Interrupt Vector Area
Memory
The interrupt vector area is used for storing vector addresses
when an interrupt is generated or at reset.
• Zero Page
• SFR Area
This SFR area is provided in the zero page and contains the reg-
isters for controlling I/O ports and timers.
• RAM
This area can be accessed with 2 words when the zero page ad-
dressing mode is used.
RAM is used for data storage and for calling subroutines, as well
as for a stack area for interrupts.
• Special Page
This area can be accessed with 2 words when the special page
addressing mode is used.
• ROM
ROM is used for storing user programs and interrupt vectors.
000016
RAM (128 bytes) for
M37480M2,
M37481M2
RAM (192 bytes) for
M37480M4,
M37480M8/E8,
M37481M4,
M37481M8/E8
007F16
008016
00BF16
00C016
00FF16
010016
Zero
page
SFR area
RAM (64 bytes) for
M37480M4,
M37481M4
RAM (256 bytes) for
M37480M8/E8,
M37481M8/E8
013F16
01FF16
Not used
C00016
E00016
F00016
FF0016
ROM (16384 bytes) for
M37480M8/E8,
M37481M8/E8
ROM (8192 bytes) for
M37480M4,
M37481M4
ROM (4096 bytes) for
M37480M2,
Special
page
M37481M2
FFE416
FFFF16
Interrupt vector area
Fig. 8 Memory map
11
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Transmit/receive buffer register (TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
Port P0 (P0)
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C916
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Bus collision detection control register (BUSARBCON)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5) (Note)
Port P5 direction register (P5D) (Note)
Watchdog timer H (WDTH)
Port P0 pull-up control register (P0PCON)
Port P1 pull-up control register (P1PCON)
Port P4P5 input control register (P4P5CON)
00F016 Timer X low-order (TXL)
00F116 Timer X high-order (TXH)
00F216 Timer Y low-order (TYL)
00F316 Timer Y high-order (TYH)
00F416 Timer 1 (T1)
Edge polarity selection register (EG)
00F516 Timer 2 (T2)
00F616 Timer X mode register (TXM)
00F716 Timer Y mode register (TYM)
00F816 Timer XY control register (TXYCON)
00F916 Timer 1 mode register (T1M)
00FA16 Timer 2 mode register (T2M)
00FB16 CPU mode register (CPUM)
00FC16 Interrupt request register 1 (IREQ1)
00FD16 Interrupt request register 2 (IREQ2)
00FE16 Interrupt control register 1 (ICON1)
00FF16 Interrupt control register 2 (ICON2)
A-D control register (ADCON)
A-D conversion register (AD)
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
STP instruction operation control register (STPCON)
Fig. 9 SFR (Special Function Register) memory map
Note: This port is not allocated in the 7480 group.
12
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Pull-up Control Registers]
I/O Ports
Ports P0 and P1 are provided with a programmable pull-up tran-
sistor. When “1” is written to the pull-up control register and the
direction register is in the input mode, the pull-up transistor turns
on, and the port is pulled up.
[Direction Registers]
The I/O ports have direction registers which determine the input/
output direction of each pin in units of bit. When a bit of the direc-
tion register is set to “1”, the corresponding pin becomes an output
port. When the bit is cleared to “0”, it becomes an input port.
If data is read from a pin configured as output, the value of the
port latch is read rather than the value of this pin.
A pin configured as input becomes floating and its value can be
read. If data is written to a pin, it is written to the port latch, but the
pin remains floating.
■Notes on Use for STP Instruction
When the 7480/7481 group is executing an STP instruction, apply
0 V or the same voltage as Vcc to the following pins.
If an intermediate voltage is applied to these pins, a through-cur-
rent flows to the input gates and the power current increases.
P4, P5, P3, P16, P14
[Port P4P5 Input Control Register]
When ports P42, P43 and P5 of the 7481 group are selected for in-
put, clear the corresponding direction register to “0” and set “1” to
the corresponding bit of the port P4P5 input control register.
Ports P42, P43 and P5 are not included in the 7480 group. Fix
each bit of the port P4P5 input control register to “0”.
b7
b0
Port P0 pull-up control register
(P0PCON : address 00D016
)
P0
P0
P0
P0
0
1
2
3
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
pull-up control bit
b7
b0
Port P4P5 input control register
(P4P5CON : address 00D216
)
P0
P0
P0
P0
4
5
6
7
P42, P43 input control bit
P5 input control bit
(For the 7480 group) Set this bit to “0”.
(For the 7481 group) Set this bit to “1”.
0 : Pull-up transistor OFF
1 : Pull-up transistor ON
Not used (“0” at read)
b7
b0
Port P1 pull-up control register
Fig. 11 Structure of port P4P5 input control register
(P1PCON : address 00D116
)
P13
– P1
0
pull-up control bit
P17
– P14 pull-up control bit
Not used (undefined at read)
0 : Pull-up transistor OFF
1 : Pull-up transistor ON
Fig. 10 Structure of pull-up control register
13
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0
Pull-up control
register
Tr1
Direction register
Data bus
Port latch
Port P0
Interrupt control circuit
Ports P1
0
– P1
3
Pull-up control
register
Data bus
Tr2
T2M
1
Direction register
Data bus
Port latch
Port P1
3
T1
Tr3
T1M
1
Direction register
Data bus
Port latch
Port P1
2
T0
Tr4
Direction register
Data bus
Port latch
Port P1
1
Tr5
Direction register
Data bus
Port latch
Port P1
0
Tr1 to Tr5 are pull-up transistors.
Fig. 12 Block diagram of ports (1)
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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Ports P14 – P17
SIOE
SIOM
SRDY
Tr6
Direction register
Data bus
Port latch
Port P1
7
S
RDY
SCS
SIOE
SIOM
SIOE
Tr7
Direction register
Data bus
Port latch
Port P1
6
S
CLK input
S
CLK output
SIOE
TE
Tr8
Direction register
Data bus
Port latch
Port P1
5
TXD
SIOE
RE
Tr9
Direction register
Data bus
Data bus
Port latch
Port P1
4
RXD
Pull-up control
register
Tr6 to Tr9 are pull-up transistors.
Fig. 13 Block diagram of ports (2)
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P2
Data bus
Port P2
Multi-
plexer
A-D conversion
circuit
Port P3
Data bus
INT , INT
Port P3
0
1
Port P40, P41
“001”
“100”
“101”
Timer X,Y
operating
mode bits “110”
Direction register
Data bus
Port latch
Port P40, P41
CNTR
0
,
Timer output
CNTR
1
input
Port P4
2
, P43, P5
0
, P51, P5
2
, P5
3
Direction register
Data bus
Port latch
Port P42, P43, P50, P51, P52, P53
Port P4 P5 input control register
(For the 7480 group) Set this bit to “0”.
(For the 7481 group) Set this bit to “1”.
Fig. 14 Block diagram of ports (3)
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MITSUBISHI MICROCOMPUTERS
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(2) Interrupt Operation
When an interrupt request is accepted:
Interrupts
Interrupts are vectored interrupts, and they can be caused by 14
different sources: 5 external sources, 8 internal sources, and 1
software source.
1. The contents of the program counter and the processor status
register are automatically pushed into the stack.
2. The interrupt disable flag is set and the interrupt request bit is
cleared.
(1) Interrupt Control
All interrupts, except the BRK instruction interrupt, have an inter-
rupt request bit and an interrupt enable bit. Additionally, a global
interrupt disable flag affects them.
3. The interrupt jump destination address is read into the program
counter.
■Notes
When the interrupt enable bit and the interrupt request bit are set
to "1" and the interrupt disable flag is set to "0", an interrupt is ac-
cepted.
• When the active edge of an external interrupt (INT0, INT1,
CNTR0, CNTR1) is set, the interrupt request bit may also be set.
Therefore, disable the external interrupt and set the edge polar-
ity selection register. Then clear the interrupt request bit and
accept the external interrupt.
The interrupt request bits can be cleared by the program but can-
not be set. The interrupt enable bit can be set and cleared by the
program.
• Input a trigger width over 250 ns to the INT0/INT1 pin.
The reset and BRK instruction interrupt can never be disabled.
Other interrupts are disabled when the interrupt disable flag is set.
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MITSUBISHI MICROCOMPUTERS
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Table 4. Interrupt vector addresses and priority
Vector address (Note 1)
High-order Low-order
Prior-
ity
Interrupt source
Interrupt request generating conditions
Remarks
RESET (Note 2)
INT0
1
2
FFFF16
FFFD16
FFFE16
FFFC16
At reset
Non-maskable
At detection of either rising edge or falling External interrupt
edge of INT0 input
(active edge programmable)
At detection of either rising edge or falling External interrupt
INT1
edge of INT1 input
(active edge programmable)
3
FFFB16
FFFA16
At input “L” to port P0 in key-on wake-up Validity after execution of
Key-on wake-up
CNTR0
mode
STP/WIT instruction
At detection of either rising edge or falling External interrupt
edge of CNTR0 input
4
5
FFF916
FFF716
FFF816
FFF616
(active edge programmable)
At detection of either rising edge or falling External interrupt
edge of CNTR1 input
CNTR1
(active edge programmable)
6
7
FFF516
FFF316
FFF116
FFEF16
FFED16
FFF416
FFF216
FFF016
FFEE16
FFEC16
Timer X
At timer X underflow
Timer Y
At timer Y underflow
8
Timer 1
At timer 1 underflow
9
Timer 2
At timer 2 underflow
10
Serial I/O reception
At completion of serial I/O data reception
At completion of serial I/O transfer shift or
when transmission buffer is empty
11
FFEB16
FFEA16
Serial I/O transmission
Bus arbitration
A-D conversion
12
13
FFE916
FFE716
FFE816
FFE616
At detection of bus collision
At completion of A-D conversion
Non-maskable software
interrupt
BRK instruction
14
FFE516
FFE416
At execution of BRK instruction
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : RESET is mentioned in the table because its operation is the same as an interrupt.
Interrupt request bit
Interrupt enable bit
Interrupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 15 Interrupt control diagram
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MITSUBISHI MICROCOMPUTERS
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b7
b0
Edge polarity selection register (EG : address 00D416)
INT0 selection bit
0 : Falling edge
1 : Rising edge
INT1 selection bit
0 : Falling edge
1 : Rising edge
CNTR0 edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” level output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” level output.
: Interrupt, rising edge active.
CNTR1 edge selection bit
0 : In event count mode, count rising edge.
: In pulse output mode, start at “H” level output.
: In pulse cycle measurement mode, measure a period from falling edge to falling edge.
: In pulse width measurement mode, measure an “H” period.
: In programmable one-shot output mode, generate one-shot “H” pulse after start at “L” level output.
: Interrupt, falling edge active.
1 : In event count mode, count falling edge.
: In pulse output mode, start at “L” output.
: In pulse cycle measurement mode, measure a period from rising edge to rising edge.
: In pulse width measurement mode, measure an “L” period.
: In programmable one-shot output mode, generate one-shot “L” pulse after start at “H” output.
: Interrupt rising edge active.
Not used (undefined at read)
INT1 source selection bit at STP or WIT
0 : P31/INT1
1 : P00 – P07 “L” level (for key-on wake-up)
Not used (undefined at read)
b7
b0
b7
b0
Interrupt request register 1 (IREQ1: address 00FC16)
Timer X interrupt request bit
Interrupt control register 1 (ICON1: address 00FE16)
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt enable bit
Timer 2 interrupt request bit
Serial I/O receive interrupt enable bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt enable bit
Serial I/O transmit interrupt request bit
Bus arbitration interrupt enable bit
Bus arbitration interrupt request bit
A-D conversion completion interrupt enable bit
A-D conversion completion interrupt request bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : No interrupt request
1 : Interrupt requested
b7
b0
b7
b0
Interrupt control register 2 (ICON2: address 00FF16)
Interrupt request register 2 (IREQ2: address 00FD16)
INT0 interrupt enable bit
INT1 interrupt enable bit
CNTR0 interrupt enable bit
INT0 interrupt request bit
INT1 interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
CNTR1 interrupt enable bit
0 : Interrupt disable
0
: No interrupt request
1 : Interrupt enable
1
: Interrupt request
Not used (undefined at read)
0 : Interrupt disabled
1 : Interrupt enabled
Not used (undefined at read)
0 : No interrupt request
1 : Interrupt requested
Fig. 16 Structure of registers related to interrupts
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MITSUBISHI MICROCOMPUTERS
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the latch only. At the next underflow reloading, the timer value is
changed.
Timers
The 7480/7481 group has two 16-bit timers (timer X and timer Y),
and two 8-bit timers (timer 1 and timer 2).
➁ Event Count Mode
● Mode Selection
All the timers are of a count-down type. When the timer reaches
“FF16” or “000016”, an underflow occurs at the next count pulse
and the corresponding timer latch is reloaded into the timer and
the count is continued. When a timer underflows, the interrupt re-
quest bit corresponding to this timer is set to “1”.
Select the timer event count mode. This mode is selected by in-
putting from the CNTR0 pin for timer X or from the CNTR1 pin
for timer Y (setting “11” in b7 and b6 of TXM or “11” in b7 and b6
of TYM). The count operation active edge is selected by setting
in the CNTR0 edge selection bit (b2) or the CNTR1 edge selec-
tion bit (b3) of EG. At “0”, the rising edge is counted.
At “1”, the falling edge is counted.
At reading and setting the timer value to a 16-bit timer, be sure to
read and set both high-order byte and low-order byte.
At reading the count value from a 16-bit timer, read the high-order
byte and the low-order byte in this order. At setting the count value
in a 16-bit timer, set the low-order byte and the high-order byte in
this order.
● Interrupt
The underflow interrupt is the same as the timer mode.
● Explanation of Operation
This operation is the same as that of the timer mode. In this
mode, set the port in common with the CNTR0/CNTR1 pin as an
input port.
The 16-bit timer cannot operate normally at reading during set op-
eration or at setting during read operation.
● Timer X, Timer Y
Figure 19 shows a timing diagram in the timer event count
mode.
Both timer X and timer Y are 16-bit timers independent from
each other. They can select 7 operating modes by setting the
mode registers. The registers related to timer X and timer Y are
shown below. In the following, abbreviations will be used as
register names.
(2) Pulse Output Mode
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “001”.
• Timer XY control register (TXYCON: address 00F816)
• Port P4 direction register (P4D: address 00C916)
• Timer X low-order (TXL: address 00F016)
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
• Timer X high-order (TXH: address 00F116)
• Timer Y low-order (TYL: address 00F216)
• Timer Y high-order (TYH: address 00F316)
• Timer X mode register (TXM: address 00F616)
• Timer Y mode register (TYM: address 00F716)
• Edge polarity selection register (EG: address 00D416)
• Interrupt request register 1 (IREQ1: address 00FC16)
• Interrupt request register 2 (IREQ2: address 00FD16)
• Interrupt control register 1 (ICON1: address 00FE16)
• Interrupt control register 2 (ICON2: address 00FF16)
For register structures, refer to each register structural diagram.
In the following, each mode will be described.
(1) Timer Mode/Event Count Mode
➀Timer Mode
● Mode Selection
This mode is selected by setting “000” in the timer X operating
mode bits (b2b1b0) of TXM and the timer Y operating mode bits
(b2b1b0) of TYM.
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
When a timer underflows, the timer X interrupt request bit (b0)
or timer Y interrupt request bit (b1) of IREQ1 is set to “1”.
● Explanation of Operation
After reset release, the timer X stop control bit (b0) or timer Y
stop control bit (b1) of TXYCON is “1”, and the timer stops.
In the timer stop status, usually the timer value is set by writing
the latch and timer at the same time. Timer operation is started
by setting “0” in b0 or b1 of TXYCON.
When the timer reaches “000016”, an underflow occurs at the
next count pulse, the corresponding timer latch is reloaded into
the timer, and the count is continued. To change the timer value
during count operation, the latch value is changed by writing to
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MITSUBISHI MICROCOMPUTERS
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the timer value provided before the start of measurement.
Figure 21 shows a timing diagram in the pulse cycle measurement
mode.
● Interrupt
The timer underflow interrupt is the same as the timer event
count mode.
● Explanation of Operation
(4) Pulse Width Measurement Mode
This operation is the same as the timer event count mode ex-
cept that a timer outputs a pulse from the CNTR0/CNTR1 pin in
which the polarity of output level is inverted at each timer
underflow. When the CNTR0 edge selection bit (b2) or CNTR1
edge selection bit (b3) of EG is “0”, the output of the CNTR0/
CNTR1 pin is started with an “H” level output. When b2 or b3 of
EG is “1”, the output of this pin is started with an “L” level. In this
mode, set the port in common with the CNTR0/CNTR1 pin as an
output port.
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “011”.
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
The underflow interrupt is the same as the timer event count
mode. Set b2 or b3 of IREQ2 to “1” as soon as pulse width
measurement is completed.
■Note
● Explanation of Operation
While a timer operation stops
While a timer operation stops
The output level of the CNTR0/CNTR1 pin is initialized to the value
set in the CNTR0 edge selection bit or CNTR1 edge selection bit
by writing to the timer.
Select a timer count source. Next, select a pulse width to be
measured. A timer counts a period from a falling edge to a rising
edge of the CNTR0/CNTR1 pin input (“L” period) when b2 or b3
of EG is “1”. A timer counts a period from a rising edge to a fall-
ing edge of the CNTR0/CNTR1 pin input (“H” period) when b2 or
b3 of EG is set to “0”.
While a timer operation is enabled
The output level of the CNTR0/CNTR1 pin is inverted by changing
the CNTR0 edge selection bit or CNTR1 edge selection bit.
Figure 20 shows a timing diagram in the pulse output mode.
While a timer operation is enabled
At setting b0 and b1 of TXYCON to “0”, a timer starts to mea-
sure a pulse width, and starts to count down from the count
value provided before measurement. When the active edge is
detected at measurement completion, 1’s complement of the
timer value is set in the timer latch. When the active edge is de-
tected at measurement completion or measurement start,
“FFFF16” is set in the timer. When a timer underflows, a timer X
or timer Y interrupt occurs, and “FFFF16” is set in the timer.
A measurement value is held until the next measurement is
completed. In this mode, set the port in common with the
CNTR0/CNTR1 pin as an input port.
(3) Pulse Cycle Measurement Mode
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “010”.
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
The underflow interrupt is the same as the timer event count
mode. Set b2 or b3 of IREQ2 to “1” as soon as the pulse cycle
measurement is completed.
● Explanation of Operation
While a timer operation stops
Select a timer count source. Next, select a pulse cycle to be
measured. When b2 or b3 of EG is “0”, a timer counts a period
from a falling edge to a falling edge of the CNTR0/CNTR1 pin in-
put.
When b2 or b3 of EG is “1”, a timer counts a period from a ris-
ing edge to a rising edge of the CNRT0/CNTR1 pin input.
While a timer operation is enabled
At setting b0 and b1 of TXYCON to “0”, a timer starts to mea-
sure the pulse cycle, and starts to count down from the count
value provided before measurement. When an active edge is
detected at measurement completion or measurement start, 1's
complement of the timer value is set to the timer latch and
“FFFF16” is set in the timer.
When a timer underflows, a timer X or timer Y interrupt occurs,
and “FFFF16” is set in the timer. A measurement value is held
until the next measurement is completed. In this mode, set the
port in common with the CNTR0/CNTR1 pin as an input port.
■Note
The timer value cannot be read in this mode. A timer value can be
set while a timer operation stops (no measurement).
Since the timer latch of this mode becomes read only, do not per-
form a write operation during measurement.
The timer is set to “FFFF16” only when the timer underflows or the
active edge of pulse cycle measurement is detected.
Accordingly, the timer value at a start of measurement depends on
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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
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■Note
(b2, b3 of EG = “0”)
The timer value cannot be read in this mode. A timer value can be
set while a timer operation stops (not under pulse width measure-
ment).
While a timer operation stops
The output level of the CNTR0/CNTR1 pin is initialized to “L” at
mode selection. Set the one-shot width in TXH, TXL, TYH and
TYL. While a timer operation stops, a trigger (input signal of
INT0/INT1 pin) cannot occur.
Since the timer latch of this mode becomes read only, do not per-
form a write operation during measurement.
The timer is set to “FFFF16” only when a timer underflows or when
the active edge of pulse width measurement is detected.
Accordingly, the timer value at a start of measurement depends on
the timer value provided before the start of measurement.
Figure 22 shows a timing diagram in the pulse width measurement
mode.
While a timer operation is enabled
At detecting a trigger, a timer outputs “H” from the CNTR0/
CNTR1 pin, and outputs “L” at a timer underflow.
➁In Case of One-shot Output “L”
(b2, b3 of EG = “1”)
While a timer operation stops
The output level of the CNTR0/CNTR1 pin is initialized to “H” at
mode selection. Set the one-shot width in TXH, TXL, TYH and
TYL. While a timer operation stops, a trigger (input signal of the
INT0/INT1 pin) cannot occur.
(5) Programmable Waveform Generation Mode
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “100”.
While a timer operation is enabled
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
The underflow interrupt is the same as the timer event count
mode. The INT0 interrupt request bit (b0) or INT1 interrupt re-
quest bit (b1) of IREQ2 is set to “1” by detecting an active edge
of the INT pin.
At the detection of a trigger, a timer outputs “L” from the CNTR0/
CNTR1 pin and outputs “H” at a timer underflow.
In this mode, set the port in common with the CNTR0/CNTR1
pin as an output port.
■Note
● Input a trigger width over 250 ns to the INT0/INT1 pin.
● If the value of the CNTR0 edge selection bit or CNTR1 edge se-
lection bit is changed while one-shot output is enabled or
one-shot output occurs, the output level from the CNTR0/
CNTR1 pin changes.
● Explanation of Operation
This operation is the same as that of the timer event count
mode, except that a timer outputs the level of the value set in
the output level latch (b4) of TXM or TYM from the CNTR0/
CNTR1 pin each time the timer underflows. After the timer
underflows, if the values of the output level latch and timer latch
are changed, the timer can output an optional waveform from
the CNTR0/CNTR1 pin. In this mode, set the port in common
with the CNTR0/CNTR1 pin as an output port.
In this mode, if the trigger selection bit of TXM or TYM is set to
“1” and the count stop control bit of TXYCON is set to “0” (count
operation), a timer can be started concurrently with the occur-
rence of a trigger (input signal of INT0/INT1 pin).
A timer starting trigger is set in the INT0 edge selection bit (b0)
or INT1 edge selection bit (b1) of EG. At “0”, the falling edge is
active. At “1”, the rising edge is active. When the count stop
control bit is “1” (count status), a timer is not started at the oc-
currence of a trigger.
Figure 24 shows a timing diagram in the programmable one-
shot output mode.
Figure 23 shows a timing diagram in the programmable wave-
form generation mode.
(6) Programmable One-Shot Output Mode
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “101”.
● Count Source Selection
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
The underflow interrupt is the same as the timer event count
mode. One-shot output trigger is set in the INT0 edge selection
bit (b0) or INT1 edge selection bit (b1) of EG. At “0”, the falling
edge is active. At “1”, the rising edge is active. The INT0 inter-
rupt request bit (b0) or INT1 interrupt request bit (b1) of IREQ2
is set to “1” by detecting an active edge of the INT pin.
● Explanation of Operation
➀In case of One-shot Output “H”
22
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
same time.
(7) PWM Mode
At writing only to the timer latch, when the write timing for the
timer latch is almost equal to the underflow timing, the value
that is set in the timer may not be constant.
● Mode Selection
This mode is selected by setting b2, b1 and b0 of TXM or TYM
to “110”.
● Count Source Selection
● Read Control for Timer X/Timer Y
The count source is f(XIN)/2, f(XIN)/8 or f(XIN)/16.
● Interrupt
At the rising edge of the CNTR0/CNTR1 output, set the timer X
interrupt request bit (b0) or timer Y interrupt request bit (b1) of
IREQ1 to “1”.
When the pulse cycle measurement mode or pulse width mea-
surement mode is selected, the timer value cannot be read out.
In the other modes, the timer value can be read regardless of
count operation and count stop. However, the timer latch value
cannot be read out.
● Explanation of Operation
In the case of timer X, the PWM waveform is output from the
CNTR0 pin. In the case of timer Y, the PWM waveform is output
from the CNTR1 pin.
The PWM waveform “H” period is determined by the setting
value n (n=0 to 255) of TXH or TYH. The “L” period is deter-
mined by the setting value m (m=0 to 255) of TXL or TYL.
The PWM cycle is as follows:
● Note on CNTR0, CNTR1, INT0, INT1 Interrupt Polarity Selection
When the CNTR0/CNTR1 edge selection bit or INT0/INT1 inter-
rupt edge selection bit is set, this affects the respective interrupt
polarity.
PWM cycle = (n + m) ✕ ts
n
PWM output duty =
(n + m)
ts: Timer X/timer Y count source cycle
While a timer operation stops
The timer value is set in TXL, TXH, TYL and TYH by writing to
the timer and timer latch at the same time. The output of the
CNTR0/CNTR1 pin is initialized to “H” by setting this timer value.
While a timer operation is enabled
When b1 and b0 of TXYCON are set to “0”, “H” is output during
the period of the setting value of TXH or TYH. After that, “L” is
output during the period of the setting value of TXL or TYL.
Then, these operations will be repeated. The PWM output sub-
sequent to an underflow can be changed by setting the timer
value in TXL, TXH, TYL, TYH by writing only to the timer latch.
In this mode, set the port in common with the CNTR0/CNTR1
pin as an output port.
■Note
● When the PWM “H” period is set to “0016”, the PWM output is
always “L” level.
● When the PWM “L” period is set to “0016”, the PWM output is al-
ways “H” level.
● When the PWM “H” period is set to “0016” and the “L” period is
set to “0016”, the PWM output is always “L” level.
● When at least one of the PWM “H” period and “L” period is set
to “0016”, a timer X interrupt request/timer Y interrupt request
does not occur.
● When the timer latch is set at “0016”, the timer counts down, so
its value is not constant.
Figure 25 shows a timing diagram in the PWM mode.
■Note on All Modes
● Write Control for Timer X, Timer Y
Timer X and timer Y can select either writing to both timer latch
and timer or writing only to the timer latch by b3 of TXM or TYM.
At writing only to the timer latch, a value is set in the timer latch
by writing the value in the timer X/timer Y address, so the timer
is updated at the next underflow. After reset release, writing to
both the timer latch and timer is selected.
At this status, when a value is written in the timer X/timer Y ad-
dress, the value is set in both the timer and timer latch at the
23
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Programmable
one-shot
output mode
CNTR0 edge
selection bit
“1”
Data bus
“1”
Programmable one-shot
output circuit
P30/INT0
“0”
INT0 edge selection bit
“0”
PWM mode
Programmable one-shot
output mode
PWM generating circuit
INT0 interrupt
request
PWM mode
Programmable waveform
generation mode
Output level latch
D
Q
Pulse output
mode
T
CNTR0 edge
selection bit
“0”
S
Q
“001”
“100”
“101”
“110”
Timer X
operating mode bits
T
Q
Pulse output mode
“1”
P40
latch
P40 direction
register
Timer X (low-order) latch Timer X (high-order) latch
Timer X (low-order) Timer X (high-order)
Timer X
interrupt request
Pulse width measurement mode
Pulse cycle measurement mode
CNTR0 edge
Edge detecting circuit
selection bit
“1”
CNTR0 interrupt
request
Timer X count source
selection bit
P40/CNTR0
f(XIN)/2
f(XIN)/8
“0”
f(XIN)/16
Programmable waveform generation mode
Timer X trigger selection bit
“0”
“1”
Timer X stop control bit
D
T
Q
Programmable
one-shot
output mode
CNTR1 edge
selection bit
“1”
“1”
Programmable one-shot
output circuit
P31/INT1
“0”
INT1 edge selection bit
“0”
PWM mode
Programmable one-shot
output mode
PWM generating circuit
INT1 interrupt
request
PWM mode
Programmable waveform
generation mode
Output level latch
D
T
Q
Pulse output
mode
CNTR1 edge
selection bit
“0”
S
Q
“001”
“100”
“101”
T
Q
Pulse output mode
“1”
“110”
P41
latch
Timer Y
operating mode bits
P41 direction
register
Timer Y (low-order) latch Timer Y (high-order) latch
Timer Y (low-order) Timer Y (high-order)
Timer Y
interrupt request
Pulse width measurement mode
Pulse cycle measurement mode
CNTR1 edge
Edge detecting circuit
selection bit
CNTR1 interrupt
request
“1”
Timer Y count source
selection bit
P41/CNTR1
f(XIN)/2
f(XIN)/8
“0”
f(XIN)/16
Programmable waveform generation mode
Timer Y trigger selection bit
“0”
“1”
Timer Y stop control bit
D
T
Q
Fig. 17 Block diagram of timer X and timer Y
24
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer X mode register (TXM : address 00F616
)
Timer Y mode register (TYM : address 00F716)
Timer Y operating mode bits
b2 b1 b0
Timer X operating mode bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Timer event count mode
1 : Pulse output mode
0 : Pulse cycle measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform generation mode
1 : Programmable one-shot output mode
0 : PWM mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Timer event count mode
1 : Pulse output mode
0 : Pulse cycle measurement mode
1 : Pulse width measurement mode
0 : Programmable waveform generation mode
1 : Programmable one-shot output mode
0 : PWM mode
1 : Not used
1 : Not used
Timer X write control bit
Timer Y write control bit
0 : Writing to both latch and timer
1 : Writing to latch only
0 : Writing to both latch and timer
1 : Writing to latch only
Output level latch
0 : “L” output
1 : “H” output
Output level latch
0 : “L” output
1 : “H” output
Timer Y trigger selection bit
Timer X trigger selection bit
0 : Timer Y free run in programmable waveform
generation mode
0 : Timer X free run in programmable waveform generation
mode
1 : Trigger occurrence (input signal of INT 1 pin) and timer
1 : Trigger occurrence (input signal of INT
0 pin) and timer
Y start in programmable waveform generation mode.
X start in programmable waveform generation mode.
Timer X count source selection bits
b7 b6
Timer Y count source selection bits
b7 b6
0
0
1
1
0 : f(XIN)/2
1 : f(XIN)/8
0 : f(XIN)/16
1 : Input from CNTR
0
0
1
1
0 : f(XIN)/2
1 : f(XIN)/8
0 : f(XIN)/16
1 : Input from CNTR1 pin
0
pin
b7
b0
Timer XY control register (TXYCON : address 00F816
)
Timer X stop control bit
0 : Count operation
1 : Count stop
Timer Y stop control bit
0 : Count operation
1 : Count stop
Not used (all “0” at read)
Fig. 18 Structure of timer X/timer Y mode register and timer XY control register
25
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FFFF16
TL
000016
TR
TR
TR
TL : Value set in timer latch
TR : Timer interrupt request
Fig. 19 Timing diagram in timer mode/event count mode
FFFF16
TL
000016
TR
TR
TR
TR
Output waveform from
CNTR0/CNTR1 pin
CNTR
CNTR
TL : Value set in timer latch
TR : Timer interrupt request
CNTR : CNTR
0/CNTR1 interrupt request
(CNTR polarity selection bit “0” : falling edge active)
Fig. 20 Timing diagram in pulse output mode
26
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
T3
T2
T1
FFFF16
TR
FFFF16+T1
TR
T2
T3
FFFF16
Input signal from
CNTR /CNTR pin
0
1
CNTR CNTR
CNTR
CNTR
CNTR
TR : Timer interrupt request
CNTR: CNTR /CNTR interrupt request
0/CNTR1 interrupt polarity is active at rising edge.
0
1
Fig. 21 Timing diagram in pulse cycle measurement mode (at “rising edge interval” measurement)
000016
T3
T2
T1
FFFF16
TR
FFFF16+T2
T3
T1
Input signal from
CNTR /CNTR pin
0
1
CNTR
interrupt polarity is active at rising edge, and pulse L width is measured.
TR : Timer interrupt request
CNTR : CNTR /CNTR interrupt request
CNTR
CNTR
CNTR0/CNTR1
0
1
Fig. 22 Timing diagram in pulse width measurement mode (at “L section” measurement)
27
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FFFF16
T3
L
T2
T1
000016
TR TR
T1
TR
TR
T3
T2
L
Input signal from
INT /INT pin
0
1
Output waveform
from CNTR /CNTR1 pin
0
CNTR
L : Initial value of TL , TL
TR : Timer interrupt request
CNTR : CNTR /CNTR interrupt request
(CNTR polarity selection bit “0” : falling edge active)
CNTR
H
L
0
1
Fig. 23 Timing diagram in programmable waveform generation mode (when trigger selection bit = “1”)
FFFF16
L
000016
TR
TR
TR
Input signal from
INT /INT pin
0
1
L
L
L
Output waveform
from CNTR
CNTR pin
0/
1
CNTR
CNTR
CNTR
L : One-shot pulse width
TR : Timer interrupt request
CNTR : CNTR
0/CNTR1 interrupt request
(CNTR polarity selection bit “0” : falling edge active)
Fig. 24 Timing diagram in programmable one-shot output mode
28
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer X/timer Y
count source
Timer X/timer Y
PWM output
n
✕t s
m✕t s
(n+m)
CNTR
✕t s
TR
TR
CNTR : CNTR0/CNTR1 interrupt request
(CNTR polarity selection bit “0” : falling edge active)
TR : Timer interrupt
Note : A PWM waveform with duty n/(n+m) and cycle (n+m) ✕ ts is output.
• TXH/TYH setting value: n= 0 – 255
• TXL/TYL setting value: m = 0 – 255
• Timer X/timer Y count source cycle: ts
• n+m = 0 – 510
Fig. 25 Timing diagram in PWM mode
29
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Timers 1 and 2
Timer 1 and timer 2 are the 8-bit timers. They can select the fol-
lowing 2 modes by setting timer 1 mode register and timer 2 mode
register.
(1) Timer Mode
The frequency of f(XIN)/8, f(XIN)/64, f(XIN)/128 or f(XIN)/256 is
counted.
• Timer mode
• Programmable waveform generation mode
When the count source is changed, set it again as the timer value
may go wrong.
(2) Programmable Waveform Generation Mode
This operation is the same as the timer mode, except that a timer
outputs the level of the value set in the output level latch of the
timer 1 mode register/timer 2 mode register from the T0 or T1 pin
each time a timer underflows.
After the timer underflows, the timer can output an optional wave-
form from the T0 or T1 pin if the values of the output level latch and
timer latch are changed.
In this mode, set the port in common with the T0/T1 pin as an out-
put port.
Data bus
8
Timer count source
selection bits
TL
8
Timer interrupt
request bit
“00”
“01”
“10”
“11”
Count stop
control bit
f(XIN)/8
f(XIN)/64
f(XIN)/128
f(XIN)/256
T
T
Output
level latch
8
Timer mode register
D
T
0, T
1
output
Q
8
Data bus
Fig. 26 Block diagram of timer 1, timer 2
b7
b0
Timer 1 mode register (T1M : address 00F916
Timer 2 mode register (T2M : address 00FA16
)
)
Timer stop control bit
0 : Count operation
1 : Count stop
Timer operation mode bit
0 : Timer mode
1 : Programmable waveform generation mode
Not used (“0” at read)
Output level latch
0 : “L” output
1 : “H” output
Not used (“0” at read)
Timer count source selection bits
b7 b6
0
0
1
1
0 : f(XIN)/8
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
Fig. 27 Structure of timer 1/timer 2 mode register
30
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
the serial I/O mode selection bit of the serial I/O control register
(address 00E216) to “1”.
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation when serial I/O is in opera-
tion.
In the clock synchronous serial I/O, the transmitter-side microcom-
puter and the receiver-side microcomputer must use the same
clock for serial I/O operation. If an internal clock is used as oper-
ating clock, a transfer is started by a write signal to the transmit/
receive buffer register.
(1) Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode can be selected by setting
Data bus
Address 00E216
Serial I/O control register
Address 00E016
Receive buffer register
P16
P14
Receive buffer full flag (RBF)
Receive interrupt request (RI)
RXD
Receive shift register
Shift clock
Receive
enable bit
(RE)
Clock control circuit
S
CLK
Serial I/O enable bit
(SIOE)
Serial I/O synchronous
BRG count source
selection bit (CSS)
Frequency division
clock selection
bit (SCS)
ratio 1/(n+1)
X
IN
1/4
Baud rate generator
1/4
S
RDY output enable
1/4
Address 00E416
bit (SRDY)
Falling edge
detection
Clock control circuit
S
RDY
F/F
Transmit enable
bit (TE)
Transmit shift register shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit shift register
T
XD
Transmit interrupt source
selection bit (TIC)
Transmit buffer register
Transmit buffer empty flag (TBE)
P15
P17
Address 00E016
Serial I/O status register
Address 00E116
Data bus
Fig. 28 Block diagram of clock synchronous serial I/O
Transmit/receive shift clock,
1/8 – 1/8192 of internal clock, or
external clock
Serial output TxD
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Serial input RxD
D0
Receive enable signal SRDY
Write signal to receive/
transmit buffer register
(address 00E016)
TBE = 1
TSC = 0
RBF = 1
TSC = 1
TBE = 0
Overrun error (OE) detection
Notes 1 : The transmit interrupt (TI) can be selected to be generated either when the transmit buffer is empty (TBE = 1) or after the
transmit shift operation is completed (TSC = 1) by using the transmit interrupt source selection bit (TIC) of the serial I/O control
register.
2 : If data is written to the transmit buffer register when TSC = 0, the transmit clock is generated continuously, and serial data is
output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig. 29 Operation of clock synchronous serial I/O function
31
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Each of the transmit and receive registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the trans-
mit buffer register and receive data is read from the receive buffer
register. These buffer registers can also hold the next data to be
transmitted and receive 2-byte receive data in succession.
The UART mode can be selected by clearing the serial I/O mode
selection bit of the serial I/O control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identi-
cal.
Data bus
Address 00E216
Serial I/O control register
P1
4
RXD
Receive enable bit (RE)
Address 00E016
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST detection
OE
7-bit
8-bit
Character length
UART control register
SP detection
selection bit (CHAS)
1/16
PE FE
Clock control circuit
Address 00E316
Serial I/O synchronous clock
selection bit (SCS)
Serial I/O enable bit (SIOE)
Serial I/O synchronous clock selection bit (SCS)
BRG count source
selection bit (CSS)
S
CLK
Frequency division ratio 1/(n+1)
X
IN
1/4
Baud rate generator
1/4
Address 00E416
1/16
ST/SP/PA generation
Transmit enable bit (TE)
Transmit shift register shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit shift register
TXD
Transmit interrupt
source selection bit (TIC)
Character length
selection bit
(CHAS)
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 00E116
P16 P15
Transmit buffer register
Address 00E016
Data bus
Fig. 30 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer register
write signal
TBE=0
TSC=0
TBE=1
TBE=0
*
TBE=1
TSC=1
SP
Serial output TxD
ST
D
D
0
ST
D
0
D1
D
1
SP
1 start bit
✽
Generated at 2nd bit in 2
stop bit mode
7/8 data bit
1/0 parity bit
1/2 stop bit
Receive buffer register
read signal
RBF=0
RBF=1
SP
RBF=1
SP
Serial input RxD
ST
0
D0
D
1
ST
D1
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception).
2 : The transmit interrupt (TI) can be selected to be generated when either TBE=1 or TSC=1, depending on the setting of
the transmit interrupt source selection bit of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
Fig. 31 Operation of UART serial I/O function
32
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O Control Register] SIOCON
The serial I/O control register consists of 8 control bits for control
of the serial I/O.
b7
b0
Serial I/O status register SIOSTS
(address 00E116
)
Transmit buffer empty flag (TBE)
0 : Buffer full
1 : Buffer empty
[UART Control Register] UARTCON
Receive buffer full flag (RBF)
The UART control register is a 4-bit control register which is valid
when UART is selected. This 4-bit control register sets a data for-
mat for serial data transfer.
0 : Buffer empty
1 : Buffer full
Transmit shift register shift completion flag (TSC)
0 : Transmit shift in progress
1 : Transmit shift completed
Overrun error flag (OE)
0 : No error
1 : Overrun error
Parity error flag (PE)
0 : No error
[Serial I/O Status Register] SIOSTS
This is a 7-bit read-only register consisting of flags that indicate
the serial I/O operating status and different error flags. The 3 bits
of bit 4 to bit 6 are valid only in the UART mode.
The receive buffer full flag is cleared to “0” when the receive buffer
register is read.
1 : Parity error
Framing error flag (FE)
0 : No error
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set.
1 : Framing error
Summing error flag (SE)
0 : (OE)U(PE)U(FE)=0
1 : (OE)U(PE)U(FE)=1
Writing to the serial I/O status register clears all the error flags
(OE, PE, FE, SE).
All the bits of this register are initialized to “0” at reset.
However, if the transmit enable bit of the serial I/O control register
is set to “1”, bit 2 and bit 0 become “1”.
Not used (“1” at read)
b7
b0
Serial I/O control register SIOCON
(address 00E216
)
BRG count source selection bit (CSS)
0 : f(XIN)/4
1 : f(XIN)/16
[Transmit Buffer Register/Receive Buffer Register] TB/RG
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is a
write-only type and the receive buffer register is a read-only type.
If a character bit length is 7 bits, the MSB of the receive data
stored in the receive buffer is “0”.
Serial I/O synchronous clock selection bit (SCS)
0 : BRG output/4 (when clock synchronous
serial I/O is selected)
BRG output/16 (when UART is selected)
1 : External clock input (when clock synchronous
serial I/O is selected)
External clock input/16 (when UART is selected
RDY output enable bit (SRDY)
)
S
0 : P1
1 : P1
7
7
pin operates as ordinary I/O pin.
pin operates as SRDY output pin.
[Baud Rate Generator] BRG
Transmit interrupt source selection bit (TIC)
The baud rate generator determines a baud rate for serial transfer.
The baud rate generator, being an 8-bit counter with a reload reg-
ister, divides the frequency of the count source by 1/(n+1), where
n is the value written to the baud rate generator.
0 : Interrupt when transmit buffer is empty.
1 :Interrupt when transmit shift operation is completed.
Transmit enable bit (TE)
0 : Transmit disabled
1 : Transmit enabled
Receive enable bit (RE)
0 : Receive disabled
1 : Receive enabled
Serial I/O mode selection bit (SIOM)
0 : Asynchronous serial I/O (UART)
1 : Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0 : Serial I/O disabled (P1
I/O ports)
4
to P17: ordinary
1 : Serial I/O enabled (P1
4
to P1 : serial
7
I/O function pins)
b7
b0
UART control register UARTCON
(address 00E316
)
Character length selection bit (CHAS)
0 : 8-bit
1 : 7-bit
Parity enable bit (PARE)
0 : Parity disabled
1 : Parity enabled
Parity selection bit (PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit (STPS)
0 : 1 stop bit
1 : 2 stop bits
Not used (“1” at read)
Fig. 32 Structure of serial I/O related registers (SIOSTS,
UARTCON, SIOCON)
33
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bus Arbitration Interrupt
The 7480/7481 group is provided with a built-in bus arbitration in-
terrupt as a function for bus conflict system communication.
At such bus conflict system communication, as shown in Figure
33, if transmit data cannot be transmitted to the LAN data bus due
to a transmit data collision, the data collision can be detected by
the bus arbitration interrupt.
LAN data bus
TxD
Interface
driver/
7480/7481
group
serial I/O
receiver
RxD
Fig. 33 Example of bus conflict system communication
34
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A transmit data collision is detected between LSB and MSB of
transmit data in the clock synchronous serial I/O mode or between
the start bit and stop bit of transmit data in the UART mode. Bus
collision detection can be performed by both the internal clock and
the external clock.
A block diagram is shown in Figure 34. A timing diagram is shown
in Figure 35. A bus collision detection control register is shown in
Figure 36.
Bus Collision Detection
The 7480/7481 group can detect a bus collision by setting the bus
collision detection enable bit to “1”.
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD is
compared with the receive pin RxD in synchronization with a rising
edge of transmit shift clock. If they do not coincide with each other,
a bus arbitration interrupt request occurs (bus collision detection).
TXD
RXD
Q
D
Bus arbitration interrupt
request
Shift clock
Bus collision detection
enable bit
TE
Fig. 34 Block diagram of bus arbitration interrupt circuit
Transmit shift clock
Transmit pin TxD
Receive pin RxD
Bus arbitration interrupt
generation
Data collision
Fig. 35 Timing diagram of bus arbitration interrupt
b0
b7
Bus collision detection control register
(BUSARBCON address 00E5 16
)
Bus collision detection enable bit
0 : Collision detection disabled
1 : Collision detection enabled
Not used (“0” at read)
Fig. 36 Structure of bus collision detection control register
35
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Application Example
Priority Control at Simplified SAEJ1850
At simplified SAEJ1850 communication, when multiple units start
to transmit data at the same time, priority control is exerted.
On the LAN data bus, the “H” level has priority over the “L” level.
When an “H” level collides with an “L” level, the LAN data bus sta-
tus goes to the “H” level.
For example, when unit A outputs “H” and unit B outputs “L” at the
same time in Figure 37, the LAN data bus goes to “H”. Accord-
ingly, unit A takes priority of control and continues its transmission,
and unit B stops its transmission immediately.
In this way, the 7480/7481 group exerts priority control for each bit
and finally allows only the highest-priority unit to transmit data.
BUS+
BUS-
LAN data bus
Unit
A
Unit
B
Continue to transmit
Unit A
Stop transmitting
Unit B
LAN data bus
Data collision
Fig. 37 Priority control at simplified SAEJ1850
36
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
Next, the procedure for executing A-D conversion will be ex-
plained below. First, set values in bit 2 to bit 0 of the A-D control
register and select pins to be A-D converted.
For A-D conversion, the 8-bit successive comparison method is
used. Figure 38 shows a block diagram of A-D conversion. Con-
version is automatically performed once started by the program.
There are 8 analog input pins that are in common with P27 to P20
of port P2 (4 pins of P23 to P20 in the 7480 group).
Next, clear the A-D conversion completion bit to “0”. With this write
operation, A-D conversion is started. The A-D conversion is com-
pleted after the lapse of 50 machine cycles (12.5 µs at f(XIN)= 8
MHz), and the A-D conversion completion bit is set to “1”. The A-D
conversion interrupt request bit is also set to “1”. Conversion re-
sults are stored in the A-D conversion register.
Pin inputs to be A-D converted are selected by bit 2 to bit 0 of the
A-D control register (address 00D916). Bit 3 of the A-D control reg-
ister is an A-D conversion completion bit. This bit is “0” during A-D
conversion and “1” after completion of it. Accordingly, it is possible
by checking this bit to know whether A-D conversion is completed
or not. Figure 39 shows the relationship between the contents of
the A-D control register and input pins to be selected.
The A-D conversion register (address 00DA16) stores conversion
results, so it is possible to know them by reading the contents of
this register.
Data bus
b0
b4
A-D control register
(address 00D916
)
A-D conversion
completion
interrupt request
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/IN
/IN
/IN
/IN
/IN
/IN
/IN
/IN
0
1
2
3
4
5
6
7
A-D control circuit
A-D conversion register
Comparator
(address 00DA16
)
Switch tree
Ladder resistor
V
SS (Note 1)
V
REF
Notes 1 : AVSS for the 44P6N package of the 7481 group.
2 : The 7480 group is not provided with P2 /IN to P27/IN7.
4
4
Fig. 38 Block diagram of A-D converter circuit
37
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
A-D control register ADCON
(address 00D916)
Analog input pin selection bits
000 : P20/IN0
001 : P21/IN1
010 : P22/IN2
011 : P23/IN3
100 : P24/IN4
(Note)
101 : P25/IN5
110 : P26/IN6
111 : P27/IN7
A-D conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF connection selection bit
0:Disconnect between VREF pin and ladder resistor
1:Connect between VREF pin and ladder resistor
Not used (undefined at read)
Note : Do not perform setting in the 7480 group.
Fig. 39 Structure of A-D control register
38
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
up. After that, the 7480/7481 group runs the program from the re-
set vector address. It is programmed that the watchdog timer H
can be set before bit 7 of the watchdog timer H is cleared to “0”. If
the watchdog timer H is never written, the watchdog timer does
not function. When the STP instruction is executed, the clock
stops and the watchdog timer also stops. The count is restarted as
soon as the stop mode is released. (Note) On the other hand, the
watchdog timer does not stop after execution of the WIT instruc-
tion.
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of a 7-bit watchdog timer L and an 8-
bit watchdog timer H.
● Initial Value of Watchdog Timer
By a reset or writing to the watchdog timer H, the watchdog timer
H is set to “FF16” and the watchdog timer L is set to “7F16”. Any in-
struction that permits generating a write signal can be used; for
example, STA, LDM, CLB, etc. Write data has no significance, so
the above values are set regardless of that data.
The timing from writing to the watchdog timer H to clearing bit 7 of
the watchdog timer H to “0” is shown below. (f(XIN)=8 MHz)
• When bit 3 of the CPU mode register is “0”............. 16.384 ms
• When bit 3 of the CPU mode register is “1”............ 32.768 ms
● Operation of Watchdog Timer
The watchdog timer stops at reset, and writing a value in the
watchdog timer H causes it to start to count down. When bit 7 of
the watchdog timer H becomes “0”, an internal reset occurs.
The reset status is released as soon as the release reset time is
Note: Since the watchdog timer still counts for the stop release
waiting time (about 2048 cycles of XIN), bit 7 of the watch-
dog timer H should not be cleared to “0” in this period.
Data bus
Write “7F16” to the
watchdog timer register
Write “FF16” to the
watchdog timer register
“0”
“1”
1/8
Watchdog timer L (7)
Watchdog timer H (8)
f(XIN
)
1/16
bit7
Watchdog timer L count
source selection bit
Reset circuit
Internal reset
RESET
Fig. 40 Block diagram of watchdog timer
39
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The STP and WIT instructions can be set as enable/disable only
by writing to the STP instruction operation control register twice
successively so as not to stop the oscillation clock even if a write
data error is caused by program runaway. Figure 41 shows a
structure of the STP instruction operation control register.
STP/WIT Instruction Control
The STP instruction and the WIT instruction can be enabled or
disabled selectively by using the STP instruction operation control
register. To cope with a program runaway after reset, the STP in-
struction and the WIT instruction are disabled in the initial status.
b7
b0
STP instruction operation control register
(STPCON: address 00DE 16
)
STP instruction and WIT instruction enable/disable selection bit (Note)
0 : STP/WIT instruction enabled
1 : STP/WIT instruction disabled
Not used (“0” at read)
Note : The STP instruction and the WIT instruction are disabled in the initial status. When using these
instructions, set bit 0 of the STP instruction operation control register to “1”, then set this bit to “0”.
(Writing twice successively)
When not using the STP and WIT instructions, set this bit to “1” either once or twice.
Fig. 41 Structure of STP instruction operation control register
If an interrupt is received while the same data is written twice,
Explanation of STP Instruction Operation
Control Register
there is a possibility that the write instruction in the interrupt rou-
tine may be executed. For this reason, rewriting is required after
interrupt disable. Figure 42 shows a reference example of data re-
writing.
The STP instruction operation control register will be enabled by
writing data to the same address twice successively. If data is not
written in continuous form, the written data is not valid but the pre-
vious value is held.
●STP/WIT instruction enable
●STP/WIT instruction disable
•
•
•
•
•
•
SEI
SEI
Interrupt
disable in
Interrupt
disable in
LDM #01H, 0DEH
LDM #01H, 0DEH
LDM #00H, 0DEH
this period
LDM #01H, 0DEH
this period
CLI
CLI
•
•
•
•
•
•
Use only in interrupt enable status
Use only in interrupt enable status
Fig. 42 Reference example of data rewriting
40
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
matrix of active “L” with port P0 as an input port is constructed, a
recovery can be made to the normal operating status by pressing
a key.
Recovery From Power-down Status By Key
Input Interrupt
(Key-on wake-up)
“Key-on wake-up” is one way of recovery from a power-down sta-
tus by using the STP or WIT instruction.
If an “L” level voltage is input to any pin of port P0 when bit 5 of
the edge polarity selection register is “1”, an interrupt occurs, and
a recovery can be made to the normal operating state. If a key
The key input interrupt is in common with the INT1 interrupt. When
bit 5 of the edge polarity selection register is set to “1”, the key in-
put interrupt function is selected. If this bit is set to “1” except in
the power-down status, both INT1 and key-on wake-up are invali-
dated.
P41/CNTR1
Port P4
1
data read circuit
interrupt request signal
CNTR
1
EG3
P40/CNTR0
Port P4
0
data read circuit
interrupt request signal
CNTR
0
EG2
P3
P3
0
1
/INT
/INT
0
1
Port P3
0
data read circuit
interrupt request signal
INT
0
EG
0
Port P31 data read circuit
EG1
EG
5
INT1 interrupt request signal
CPU stop status signal
Pull-up control
register
P0
7
Direction register
Pull-up control
register
P0
P0
1
0
Direction register
Port P0 data read circuit
Pull-up control
register
Direction register
Fig. 43 Block diagram of interrupt input/key-on wake-up circuit
41
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The 7480/7481 group is provided with a built-in oscillation circuit.
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. Use the manufacturer's recommended
values for constants such as capacitance, which will differ de-
pending on each resonator. The 7480/7481 group has a built-in
feedback resistor between the XIN and XOUT pins, so an external
resistor can be omitted.
XIN
XOUT
Rd
● Frequency Control
(1) High-speed Mode
CIN
COUT
The frequency applied to the clock input pin XIN divided by 2 is
used as the internal clock φ. This mode is set after reset release.
(2) Medium-speed Mode
The frequency applied to the clock input pin XIN divided by 8 is
used as the internal clock φ.
Fig. 44 External circuit of ceramic resonator
● Oscillation Frequency
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and the oscillator stops. At this time, timer 1 is set to
“FF16,” and f(XIN)/8 is forcibly connected to the count source of
timer 1. Accordingly, set the timer 1 interrupt enable bit to the dis-
able status (“0”) before execution of the STP instruction.
When a reset or an external interrupt is accepted, oscillation is re-
started, but the internal clock φ is supplied to the CPU after timer
1 underflows. This is because when an external resonator is used,
some time is required until a start of oscillation.
X
IN
XOUT
Open
(2) Wait Mode
V
CC
SS
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. But, the oscillator does not stop. When a reset or inter-
rupt is accepted, the stop status is released. The microcomputer
can execute any instruction immediately, because the oscillator
does not stop.
External oscillation
circuit
V
Duty ratio 50%
Fig. 45 External clock input circuit
42
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
XOUT
Timer 1
1/2
1/4
1/4
CM
6
“1”
Internal clock
“0”
Q S
R
S Q
Reset
STP instruction
WIT
instruction
STP
instruction
R
Reset
Interrupt disable flag
Interrupt request
Fig. 46 Block diagram of clock generating circuit
43
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
The microcomputer is put into a reset status by holding the
_____
Power ON
RESET pin at the “L” level for 2µs or more when the power source
voltage is 2.7 to 5.5 V and XIN is in stable oscillation.
_____
RESET
VCC
Power source
voltage
0V
(Note)
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFF16 as high-order address and the con-
tents of address FFFE16 as low-order address.
Reset input
voltage
0V
0.12VCC
Note that the reset input voltage should be 0.32 V or less when
the power source voltage passes 2.7 V.
Note : Reset release voltage VCC = 2.7 V
Power source
voltage
detecting circuit
RESET
VCC
Fig. 47 Reset circuit diagram
X
IN
φ
RESET
Internal reset
Address
?
?
?
?
ADH,L
FFFE16 FFFF16
Reset address from
the vector table
Data
?
?
?
?
AD
L
ADH
SYNC
Notes 1 : The frequency relation between f(XIN) and φ is f(XIN)=2·f(φ).
2 : The mark “?” means that the address is changeable depending
on the previous state.
X
IN 2048 clock cycle
Fig. 48 Reset sequence
44
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Address
0016
0016
( 1 ) Port P0 direction register (P0D)
(C116
(C316
(C916
)
)
)
• • •
• • •
• • •
• • •
• • •
• • •
( 2 ) Port P1 direction register (P1D)
( 3 ) Port P4 direction register (P4D)
0 0 0 0
0 0 0 0
( 4 ) Port P5 direction register (P5D)
(CB16)
0016
( 5 ) Port P0 pull-up control register (P0PCON)
( 6 ) Port P1 pull-up control register (P1PCON)
( 7 ) Port P4P5 input control register (P4P5CON)
( 8 ) Edge polarity selection register (EG)
( 9 ) A-D control register (ADCON)
(D016
(D116
(D216
(D416
(D916
)
)
0 0
0016
)
)
)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
0
0 0 0 0
0 1 0 0 0
(10) STP instruction operation control register (STPCON)
(11) Serial I/O status register (SIOSTS)
(12) Serial I/O control register (SIOCON)
(13) UART control register (UARTCON)
(DE16)
1
0 0 0 0 0 0 0
(E116
(E216
(E316
)
1 0
0 0 0 0 0 0
0016
)
)
)
1
1
1 1 0 0 0 0
0016
(14) Bus collision detection control register (BUSARBCON) (E516
FF16
FF16
FF16
FF16
FF16
FF16
0016
0016
(15) Watchdog timer H (WDTH)
(16) Timer X low-order (TXL)
(EF16)
(F016
(F116
(F216
(F316
(F416
)
(17) Timer X high-order (TXH)
)
)
)
)
(18) Timer Y low-order (TYL)
(19) Timer Y high-order (TYH)
(20) Timer 1 (T1)
(21) Timer X mode register (TXM)
(22) Timer Y mode register (TYM)
(23) Timer XY control register (TXYCON)
(24) Timer 1 mode register (T1M)
(25) Timer 2 mode register (T2M)
(26) CPU mode register (CPUM)
(27) Interrupt request register 1 (IREQ1)
(28) Interrupt request register 2 (IREQ2)
(29) Interrupt control register 1 (ICON1)
(30) Interrupt control register 2 (ICON2)
(F6 16)
(F716
(F816
(F916
)
)
)
1 1
0 0 0 0 0 0
0016
0016
(FA16
(FB16
)
)
0
0 0 0 0
0016
(FC16
(FD16
)
)
0 0 0 0
0016
(FE16
(FF16
)
)
0 0 0 0
Contents of address FFFF16
Contents of address FFFE16
1
(31) Program counter (PC
(PC
(32) Processor status register (PS)
H)
L
)
: At reset release, the read value is undefined.
Note : Some kinds of microcomputers do not use some of these bits. Refer to the structure of each register.
Fig. 49 Internal state of microcomputer at reset
45
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUILT-IN PROGRAMMABLE ROM VERSIONS
M37480E8-XXXSP/FP, M37480E8T-XXXSP/FP, M37481E8-XXXSP/FP, M37481E8T-XXXSP/FP,
M37481E8SS
PIN DESCRIPTION
Table 5. Pin description
Input/
output
Pin
Mode
Name
Function
VCC, VSS
AVSS
(Note 1)
Single-chip/
EPROM
Power source
Apply a voltage of 2.7 to 5.5 V to VCC and 0 V to VSS and AVSS.
Reference power
input
Single-chip
Input
Reference voltage input pin for A-D converter.
__
VREF
EPROM
Input
Input
Input
Mode input
Reset input
Reset input
Used as CE input pin.
Single-chip
EPROM
_____
RESET
Reset input pin.
Connect to VSS.
These are I/O pins of internal clock generating circuit for the main
clock. To control generating frequency, an external ceramic resona-
tor is connected between XIN and XOUT pins. If an external clock is
used, the clock oscillation source should be connected to the XIN
pin, and the XOUT pin should be left open. Feedback resistor is con-
nected between XIN and XOUT.
Single-chip/
EPROM
XIN
Clock input
Input
Single-chip/
EPROM
XOUT
Clock output
Output
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, a pull-up transistor can be con-
nected in units of 1 bit, and a key-on wake-up function is provided.
Single-chip
EPROM
I/O
I/O
I/O port P0
P00 – P07
P10 – P17
Data I/O D0 – D7
Data 8-bit (D0 to D7) I/O pins
8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, a pull-up transistor can be con-
nected in units of 4 bits. P12 and P13 are in common with timer
Single-chip
I/O
I/O port P1
output pins T0 and T1. P14, P15, P16 and P17 are in common with
____
serial I/O pins RxD, TxD, SCLK and SRDY.
Address input
A4 – A10
EPROM
Input
Input
Input
Input
P11 to P17 are address (A4 to A10) input pins. Leave P10 open.
8-bit input port. This port is in common with analog input pins IN0 to
IN7 (IN0 to IN3 for the 7480 group).
Single-chip
EPROM
Input port P2
P20 – P27
(Note 2)
P20 to P23 are address (A0 to A3) input pins. Leave P24 to P27
open.
Address input
A0 – A3
4-bit input port. P30 and P31 are in common with external interrupt
input pins INT0 and INT1.
Single-chip
Input port P3
__
P30 – P33
P30 and P31 are address (A11, A12) input pins. P32 is used for OE
input. P33 is VPP input. Apply VPP in the program and program
verify modes.
Address input
A11, A12, mode
input, VPP input
EPROM
Input
4-bit I/O port. The output structure is N-channel open drain output,
having built-in clamp diode. P40 and P41 are in common with timer
input pins CNTR0 and CNTR1.
Single-chip
EPROM
I/O
I/O port P4
P40 – P43
(Note 3)
P40 and P41 are address (A13, A14) input pins. Leave P42 and P43
open.
Address input
A13, A14
Input
4-bit I/O port. The output structure is N-channel open drain output,
having a built-in clamp diode.
Single-chip
EPROM
I/O
I/O port P5
P50 – P53
(Note 4)
Input
Leave these pins open.
Input port P5
Notes 1 : This is a dedicated pin for the 44P6N-A package in the 7481 group.
2 : Only 4 bits of P20 to P23 (IN0 to IN3) for the 7480 group.
3 : Only 2 bits of P40 and P41 for the 7480 group.
4 : This is a dedicated pin for the 7481 group.
46
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6. Correspondence between pins in EPROM mode
EPROM MODE
The built-in programmable ROM has the EPROM mode in addition
_____
M37480E8, M37481E8
M5M27C256K
to its normal operation modes. When the RESET level becomes
“L”, the chip automatically enters the EPROM mode. Table 6
shows a list of correspondence between pins and Figure 50 to Fig-
ure 52 show pin connection diagrams. In this status, each of ports
P0, P11 to P17, P20 to P23, P3, P40, P41 and VREF are used for
the PROM (equivalent to M5M27C256K). In this mode, the built-in
PROM can be written to or read from using these pins in the same
way as with the M5M27C256K. The clock should be connected to
XIN and XOUT pins.
VCC
VPP
VSS
VCC
P33
VSS
VCC
VPP
VSS
Ports P11 – P17,
P20 – P23, P30,
P31, P40, P41
Address input
A0 – A14
Data I/O
__
Port P0
VREF
P32
D0 – D7
__
CE
CE
__
__
OE
OE
1
42
P5
P0
P0
P0
P0
P0
P0
P0
P0
P4
P4
P4
P4
P3
P3
P3
P3
2
7
6
5
4
3
2
1
0
3
2
P5
3
2
3
4
5
6
7
8
9
41
40
A
10
D
D
7
6
P17/SRDY
A
9
8
P1
P1
P1
6
5
4
/SCLK
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A
/TX
D
D
D
5
4
A
A
A
A
7
6
5
4
/RX
D
D
3
P1
P1
3
2
/T
1
0
1
0
D
D
D
2
1
0
/T
P1
P1
10
11
12
13
14
15
16
17
18
19
20
21
P2
7
6
5
4
/IN
/IN
/IN
/IN
7
6
5
4
3
2
1
0
P2
P2
P2
P2
P2
P2
P2
A
A
14
13
1
0
3
2
1
0
/CNTR
/CNTR
1
0
V
PP
A
A
A
A
3
2
1
3
2
1
0
/IN
/IN
/IN
/IN
OE
A
A
12
11
/INT
/INT
1
0
0
CE
V
REF
IN
OUT
SS
RESET
X
P5
P5
1
VSS
X
0
V
SS
V
CC
V
V
CC
Outline 42P4B
42S1B-A (M37481E8SS)
: PROM pin (equivalent to M5M27C256K)
Fig. 50 Pin connection in EPROM mode (1)
47
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
22
34
35
D
D
4
5
A
11
P0
4
P3
RESET
0/INT0
21
20
19
P0
P0
P0
5
36
37
38
39
D
6
P5
P5
1
0
6
7
VSS
D
7
V
V
CC
SS
18
17
16
15
P5
2
V
V
CC
SS
M37481E8-XXXFP
M37481E8T-XXXFP
VSS
VSS
AVSS
40
41
P5
3
A10
P1
P1
P1
7
6
5
/SRDY
X
OUT
IN
A
9
8
7
14
13
12
42
43
/SCLK
X
A
V
REF
/TX
D
CE
44
A
P1
4
/RXD
A
0
P20/IN0
Outline 44P6N-A
: PROM pin (equivalent to M5M27C256K)
Fig. 51 Pin connection in EPROM mode (2)
1
32
31
A
10
P0
7
6
5
4
3
2
1
0
1
0
3
2
1
0
D
D
7
6
P17/SRDY
2
3
A
9
P1
P1
P1
6
5
4
/SCLK
P0
P0
P0
P0
P0
P0
P0
P4
P4
P3
P3
P3
P3
D
D
D
D
D
D
5
4
30
29
28
27
26
A
A
A
A
A
8
7
/TX
D
4
5
/RX
D
6
5
4
3
2
1
0
P1
P1
3
2
/T
1
0
1
0
6
/T
7
P1
P1
8
25
24
23
22
9
A
A
A
A
3
2
A
A
14
13
P2
3
2
1
0
/IN
/IN
/IN
/IN
3
2
1
0
/CNTR
/CNTR
1
0
10
P2
P2
P2
V
PP
1
0
11
12
13
14
15
21
20
19
18
OE
A
A
12
11
CE
V
REF
IN
OUT
SS
/INT
/INT
1
0
X
X
RESET
V
SS
V
16
17
V
CC
V
CC
V
SS
Outline 32P4B
32P2W-A
: PROM pin (equivalent to M5M27C256K)
Fig. 52 Pin connection in EPROM mode (3)
48
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION OF PROM VERSION
Reading
NOTES ON HANDLING
(1) Sunlight and fluorescent light contain wavelengths capable of
erasing data. For use in the read mode, be sure to cover the
transparent window with a seal. (Ceramic package type)
(2) We can supply the seal with which the transparent window is
covered. Be careful not to allow the seal to contact the micro-
computer lead pins. (Ceramic package type)
__
__
To read the PROM, set the CE and OE pins to “L” level, and set
the address signal (A0 to A14). The stored contents will appear to
__
__
data I/O pins (D0 to D7). When the CE and OE pins are set to “H”
level, the data I/O pins will be put into a floating status.
(3) Before erasing, clean the transparent glass. If the glass is
smeared with greasy hands or paste, ultraviolet light transmis-
sion will be prevented, having a negative effect on erasing
characteristics. (Ceramic package type)
Writing
__
To write to the PROM, apply “H” to the OE pin and VPP to the VPP
pin to set the program mode. Select addresses to be written to
with address input pins (A0 to A14) and give write data to the data
(4) Since a high voltage is used for writing data, care should be
taken not to apply an overvoltage when turning on the power
source.
input pins (D0 to D7) in 8-bit parallel form. In this status, when the
__
CE pin becomes “L”, writing will be started.
(5) For the programmable microcomputers (one-time program-
mable version, version shipped in blank), Mitsubishi does not
perform PROM write testing and screening in the assembly
process and subsequent processes. To improve reliability after
writing, perform writing and testing according to the following
operation flow before use.
Notes on Writing
When using a PROM programmer, specify the address range to
address 400016 to address 7FFF16.
When data is written between address 000016 and address
7FFF16, fill addresses 000016 to 3FFF16 with “FF16”.
Erasing
Data can be erased only on the ceramic package with window
M37481E8SS. To erase data on this chip, use an ultraviolet light
source with a 2537 Angstrom wave length. The minimum radiation
power required for erasing is 15W·s/cm2.
Writing with PROM programmer
Screening (Leave at 150°C
for 40 hours.) (Note)
Verify test with
PROM programmer
Function check in target device
The screening temperature is up to 150°C.
Never expose to 150°C exceeding 100 hours.
The M37480E8SP/FP, M37481E8SP/FP and
M37481E8SS are not T versions (mountable on
vehicles), so it is impossible to mount them on
vehicles.
Note :
The M37481E8SS is for user program
evaluation, so it is impossible to mount it on
vehicles or on user’s mass-production real
machines.
Fig. 53 Writing and testing for one-time programmable version
49
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O SIGNALS IN EACH MODE
Table 7. I/O signals in each mode
Pin
__
__
CE
OE
VPP
VCC
Data I/O
Mode
Read-out
VIL
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIH
VCC
VCC
VPP
VPP
VPP
VCC
VCC
VCC
VCC
VCC
Output
Floating
Input
Output disable
Programming
Programming verify
Program disable
Output
Floating
Note : VIL and VIH denote an “L” input voltage and an “H” input voltage, respectively.
50
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ADDRESSING MODES
DATA REQUIRED FOR MASK ORDERING
Please submit the following data when placing mask orders.
(1) Mask ROM confirmation form
The 7480/7481 group has strong accessability, because it has 17
kinds of addressing modes. For details, refer to the 740 family ad-
dressing modes.
(2) Mark specification form
(3) ROM data.......................................................... EPROM 3 sets
MACHINE-LANGUAGE INSTRUCTIONS
The 7480/7481 group has 71 machine-language instructions. For
details, refer to the 740 family machine-language instruction list.
DATA REQUIRED FOR ROM WRITING
ORDERING
Please submit the following data when placing ROM writing or-
ders.
(1) ROM writing confirmation form
(2) Mark specification form
NOTES ON PROGRAMMING
(1) The frequency division ratio of the timer is 1/(n+1).
n: Timer setting value
However, n = 0 – 255 (for timer 1, timer 2)
n = 0 – 65535 (timer X, timer Y)
(3) ROM data.......................................................... EPROM 3 sets
(2) The contents of the interrupt request bits can be changed by
software, but the values will not change immediately after be-
ing overwritten.
After changing the value of the interrupt request bits, execute
at least one instruction before executing a the BBC or BBS in-
struction.
(3) To calculate in decimal notation, set the decimal mode flag (D)
to “1”. After executing the ADC or SBC instruction, execute
another instruction before executing the SEC, CLC, or CLD in-
struction.
(4) A NOP instruction should be executed after every PLP instruc-
tion.
(5) Do not execute the STP instruction during A-D conversion.
(6) Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instructions.
The execution of these instructions does not change the con-
tents of the processor status register.
51
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP
ABSOLUTE MAXIMUM RATINGS (7480 Group)
Table 8. Absolute maximum ratings
Symbol
Parameter
Power source voltage
Input voltage
Condition
All voltages are measured on the basis
of the VSS pin.
Rated value
–0.3 to 7
Unit
V
VCC
VI
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
1000 (Note 1)
V
Output voltage
VO
Pd
Output transistors are cut off.
Ta = 25 °C
V
Power dissipation
mW
°C
°C
Operating temperature range
Storage temperature
Topr
Tstg
–20 to 85 (Note 2)
–40 to 150 (Note 3)
Notes 1 : 500 mW for 32P2W-A package type.
2 : –40 to 85 °C for extended operating temperature range version.
3 : –65 to 150 °C for extended operating temperature range version.
RECOMMENDED OPERATING CONDITIONS (7480 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C (Note 1) unless otherwise specified)
Table 9. Recommended operating conditions
Standard values
Symbol
Parameter
Unit
Min.
2.7
Typ.
Max.
f(XIN) = (2.2VCC – 2) MHz
f(XIN) = 8 MHz
3
5
0
4.5
5.5
V
V
VCC
Power source voltage
Power source voltage
4.5
VSS
VIH
VIH
V
“H” input voltage P00 – P07, P10 – P17
“H” input voltage P20 – P23
0.8 VCC
VCC
VCC
V
0.7 VCC
V
0.8 VCC
VCC
V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VIH
VIH
“H” input voltage P30 – P33
0.9 VCC
VCC
V
0.8 VCC
VCC
V
“H” input voltage P40 – P41 (Note 4)
0.9 VCC
VCC
V
_____
VIH
VIL
VIL
“H” input voltage XIN, RESET
0.8 VCC
VCC
V
“L” input voltage P00 – P07, P10 – P17
“L” input voltage P20 – P23
0
0
0
0
0
0
0
0
0.2 VCC
0.25 VCC
0.4 VCC
0.3 VCC
0.4 VCC
0.3 VCC
0.16 VCC
0.12 VCC
1
V
V
V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VIL
VIL
“L” input voltage P30 – P33
“L” input voltage P40 – P41
V
V
V
VIL
“L” input voltage XIN
_____
V
VIL
“L” input voltage RESET
V
II
Input current P40 – P41 (Note 4) VI > VCC
“H” sum output current P00 – P07
“H” sum output current P10 – P17
“L” sum output current P00 – P07, P40 – P41
“L” sum output current P10 – P17
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
– 30
– 30
60
60
“H” peak output current P00 – P07, P10 – P17
– 10
“L” peak output current P00 – P07, P10 – P17, P40 – P41
“H” average output current P00 – P07, P10 – P17 (Note 2)
“L” average output current P00 – P07, P10 – P17, P40 – P41 (Note 2)
20
– 5
10
52
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9. Recommended operating conditions (cont.)
Standard values
Unit
Symbol
Parameter
Min.
Typ.
Max.
Timer input frequency CNTR0 (P40),
CNTR1 (P41) (Note 3)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
1
f(CNTR)
MHz
kHz
2
Clock synchronous
250
Serial I/O clock input
frequency SCLK (P16)
(Note 3)
serial I/O mode
500
f(SCLK)
1
UART mode
MHz
MHz
2
2.2VCC – 2
8
f(XIN)
Clock input oscillation frequency (Note 3)
Notes 1 : –40 to 85 °C for extended operating temperature range version.
2 : The average output currents IOH(avg) and IOL(avg) are the average values during 100 ms.
3 : The clock input oscillation frequency is at 50 % duty ratio.
4 : When applying a voltage through a resistor as shown in the figure 54, VI > VCC may be accepted if the current is 1 mA or less.
The clamp diode of the 7480/7481 group is designed for a level
shift of DC signal unlike ordinary switching diodes. Do not apply
sudden stress, such as rush current, directly to the diode.
VI
Notes on Countermeasures for Noise and
I
Latch-up (7480 Group)
(1) Connect a bypass capacitor (0.1µF) across the VCC pin and
the VSS pin with the shortest possible wiring, using a relatively
thick wire.
Port P4
(2) Connect a bypass capacitor (0.01 µF) across the VREF pin and
the VSS pin with the shortest possible wiring, using a relatively
thick wire.
(3) In the oscillation circuit, connect across the XIN and XOUT pins
with the shortest possible wiring. Connect the GND and VSS
pins of the oscillation circuit with the shortest possible wiring,
using a relatively thick wire.
Fig. 54 Note on use of port P4
(4) In the case of the P33/VPP pin of the built-in programmable
ROM version, connect an approximately 5 kΩ resistor to the
P33/VPP pin the shortest possible in series.
Notes on Clamp Diode (7480 Group)
(1) Total input current
The current of port P4 through the clamp diode can be drawn
up to 1.0 mA per port. When a current that cannot be con-
sumed by microcomputer is sent to the clamp diode, this may
raise the power source pin voltage of the microcomputer.
The system power circuit must be designed so that the power
source voltage of the microcomputer may be stabilized within
standard values.
(2) Maximum input voltage
If the input voltage of a signal connected to port P4 is beyond
VCC + 0.3 V, the input waveform should have a delay exceed-
ing 2 µs/V from the moment that this waveform goes over the
voltage.
For using a CR circuit for delay, calculate a proper delay value
by the following expression:
dt
t
–6
=
≥ 2 ✕ 10 (s/V)
dv
0.6 ✕ VIN
where VIN = Maximum input voltage amplitude margin and
t = C ✕ R.
53
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP
ELECTRICAL CHARACTERISTICS (7480 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C (Note 1) unless otherwise specified)
Table 10. Electrical characteristics
Standard values
Typ.
Symbol
Parameter
“H” output voltage
Test conditions
VCC = 5 V, IOH = –5 mA
Unit
V
Min.
Max.
3
VOH
P00 – P07, P10 – P17
“L” output voltage
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
2
2
VOL
V
P00 – P07, P10 – P17, P40 – P41 VCC = 3 V, IOL = 3 mA
1
Hysteresis P00 – P07,
VCC = 5 V
0.5
0.3
0.5
0.3
0.5
0.3
VT + – VT–
VT + – VT–
VT + – VT–
IIH
V
P30 – P33, P40 – P41 (Note 2)
VCC = 3 V
VCC = 5 V
VCC = 3 V
When used as SCLK, RxD
input
Hysteresis P16/SCLK, P14/RXD
V
_____
VCC = 5 V
Hysteresis RESET
V
VCC = 3 V
VCC = 5 V
VCC = 3 V
“H” input current
VI = VCC without pull-up
transistor
5
3
µ
µ
µ
µ
µ
A
A
A
A
A
P00 – P07, P10 – P17
“H” input current
VI = VCC = 5 V
VI = VCC = 3 V
VI = VCC when analog
input is not selected
VI = VCC
5
IIH
P30 – P33, P40 – P41
3
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
5
IIH
“H” input current P20 – P23
3
_____
5
IIH
“H” input current RESET, XIN
(XIN at stop)
3
VI = 0 V without pull-up
transistor
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
“L” input current
IIL
P00 – P07, P10 – P17
VI = 0 V with pull-up
transistor (Note 3)
–0.25
–0.08
–0.5
mA
–0.18
“L” input current
IIL
IIL
IIL
VI = 0 V
µ
µ
µ
A
A
A
P30 – P33, P40 – P41
VI = 0 V when analog input
is not selected
VI = 0 V
“L” input current P20 – P23
_____
“L” input current RESET, XIN
(XIN at stop)
Notes 1 : –40 to 85 °C for extended operating temperature range version.
2 : At using P0 for key-on wake-up function.
3 : Can be indicated in resistance value as shown below:
When VCC = 5 V: 5 kΩ (min.), 10 kΩ (typ.), 20 kΩ (max.).
When VCC = 3 V: 8.6 kΩ (min.), 16.7 kΩ (typ.), 37.5 kΩ (max.).
54
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP
Table 10. Electrical characteristics (cont.)
Standard values
Typ.
Symbol
Parameter
Test conditions
At clock stop mode
Unit
Min.
2
Max.
VRAM
RAM retention voltage
V
A-D conversion
not executed
3.5
4
7
8
mA
In high-speed mode,
f(XIN) = 4 MHz,
VCC = 5 V
A-D conversion
in progress
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A-D conversion
not executed
1.8
2
3.6
4
In high-speed mode,
f(XIN) = 4 MHz,
VCC = 3 V
A-D conversion
in progress
A-D conversion
not executed
7
14
15
3.5
4
In high-speed mode,
f(XIN) = 8 MHz,
VCC = 5 V
A-D conversion
in progress
7.5
1.75
2
A-D conversion
not executed
In medium-speed
mode, f(XIN) = 4 MHz,
VCC = 5 V
A-D conversion
in progress
A-D conversion
not executed
0.9
1
1.8
2
In medium-speed
mode, f(XIN) = 4 MHz,
VCC = 3 V
A-D conversion
in progress
ICC
Power source current
A-D conversion
not executed
In medium-speed
mode, f(XIN) = 8 MHz,
VCC = 5 V
3.5
3.75
1
7
A-D conversion
in progress
7.5
2
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
Ta = 25 °C
Ta = 85 °C
In high-speed mode,
f(XIN) = 4 MHz
0.5
2
1
mA
mA
In high-speed mode,
f(XIN) = 8 MHz
4
0.9
0.45
1.8
0.1
1
1.8
0.9
3.6
1
In medium-speed
mode, f(XIN) = 4 MHz
In medium-speed
mode, f(XIN) = 8 MHz
µA
µA
f(XIN) = 0
VCC = 5 V
10
55
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37480M4/M8/E8-XXXSP/FP, M37480M2T/M4T/M8T/E8T-XXXSP/FP
A-D CONVERSION CHARACTERISTICS (7480 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C (Note) unless otherwise specified)
Table 11. A-D conversion characteristics
Standard values
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
8
——
——
Resolution
bits
Absolute accuracy (except
quantization error)
VCC = VREF = 5.0 V
±2
LSB
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
VCC = 2.7 to 4.0 V
25
12.5
VCC
VCC
100
TCONV
Conversion time
µs
V
2
0.5 VCC
12
VVREF
Reference voltage
VCC = 4.0 to 5.5 V
RLADDER
VIA
Ladder resistance
35
kΩ
V
Analog input voltage
Reference input current
0
VREF
416
IVREF
VREF = 5.0 V
50
143
µA
Note: –40 to 85 °C for extended operating temperature range version.
56
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS
ABSOLUTE MAXIMUM RATINGS (7481 Group)
Table 12. Absolute maximum ratings
Symbol
Parameter
Power source voltage
Input voltage
Condition
All voltages are measured on the basis
of the VSS pin.
Rated value
–0.3 to 7
Unit
V
VCC
VI
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
1000 (Note 1)
V
Output voltage
VO
Pd
Output transistors are cut off.
Ta = 25 °C
V
Power dissipation
mW
°C
°C
Operating temperature range
Storage temperature
Topr
Tstg
–20 to 85 (Note 2)
–40 to 150 (Note 3)
Notes 1 : 500 mW for 44P6N-A package type.
2 : –40 to 85 °C for extended operating temperature range version.
3 : –65 to 150 °C for extended operating temperature range version.
RECOMMENDED OPERATING CONDITIONS (7481 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C (Note 1) unless otherwise specified)
Table 13. Recommended operating conditions
Standard values
Symbol
Parameter
Unit
Min.
2.7
Typ.
Max.
f(XIN) = (2.2VCC – 2) MHz
f(XIN) = 8 MHz
3
5
0
4.5
5.5
V
V
VCC
Power source voltage
Power source voltage
4.5
VSS
VIH
VIH
V
“H” input voltage P00 – P07, P10 – P17
“H” input voltage P20 – P27
0.8 VCC
VCC
VCC
V
0.7 VCC
V
0.8 VCC
VCC
V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VIH
VIH
“H” input voltage P30 – P33
VCC
V
0.9 VCC
VCC
V
0.8 VCC
“H” input voltage P40 – P43, P50 – P53 (Note 4)
VCC
V
0.9 VCC
_____
VIH
VIL
VIL
“H” input voltage XIN, RESET
VCC
V
0.8 VCC
“L” input voltage P00 – P07, P10 – P17
“L” input voltage P20 – P27
0.2 VCC
0.25 VCC
0.4 VCC
0.3 VCC
0.4 VCC
0.3 VCC
0.16 VCC
0.12 VCC
1
V
0
0
0
0
0
0
0
0
V
V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
VCC = 2.7 to 4.5 V
VIL
VIL
“L” input voltage P30 – P33
V
V
“L” input voltage P40 – P43, P50 – P53
V
VIL
“L” input voltage XIN
_____
V
VIL
“L” input voltage RESET
V
II
Input current P40 – P43, P50 – P53 (Note 4) VI > VCC
“H” sum output current P00 – P07
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOH(sum)
IOH(sum)
IOL(sum)
IOL(sum)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–30
“H” sum output current P10 – P17
–30
“L" sum output current P00 – P07, P40 – P43, P50 – P52
“L” sum output current P10 – P17, P53
60
60
“H” peak output current P00 – P07, P10 – P17
“L” peak output current P00 – P07, P10 – P17, P40 – P43, P50 – P53
“H” average output current P00 – P07, P10 – P17 (Note 2)
–10
20
–5
“L” average output current P00 – P07, P10 – P17, P40 – P43, P50 – P53 (Note 2)
10
57
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 13. Recommended operating conditions (cont.)
Standard values
Unit
Symbol
Parameter
Min.
Typ.
Max.
Timer input frequency CNTR0 (P40),
CNTR1 (P41) (Note 3)
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
f(XIN) = 4 MHz
f(XIN) = 8 MHz
VCC = 2.7 to 4.5 V
VCC = 4.5 to 5.5 V
1
f(CNTR)
MHz
kHz
2
Clock synchronous
250
Serial I/O clock input
frequency SCLK (P16)
(Note 3)
serial I/O mode
500
f(SCLK)
1
UART mode
MHz
MHz
2
2.2VCC – 2
8
f(XIN)
Clock input oscillation frequency (Note 3)
Notes 1 : –40 to 85 °C for extended operating temperature range version.
2 : The average output currents IOH(avg) and IOL(avg) are the average values during 100 ms.
3 : The clock input oscillation frequency is at 50 % duty ratio.
4 : When applying a voltage through a resistor as shown in the figure 55, VI > VCC may be accepted if the current is 1 mA or less.
The clamp diode of the 7480/7481 group is designed for a level
shift of DC signal unlike ordinary switching diodes. Do not apply
sudden stress, such as rush current, directly to the diode.
VI
Notes on Countermeasures for Noise and
I
Latch-up (7481 Group)
(1) Connect a bypass capacitor (0.1µF) across the VCC pin and
the VSS pin with the shortest possible wiring, using a relatively
thick wire.
Port P4, P5
(2) Connect a bypass capacitor (0.01 µF) across the VREF pin and
the VSS pin with the shortest possible wiring, using a relatively
thick wire.
(3) In the oscillation circuit, connect across the XIN and XOUT pins
with the shortest possible wiring. Connect the GND and VSS
pins of the oscillation circuit with the shortest possible wiring,
using a relatively thick wire.
Fig. 55 Notes on use of ports P4 and P5
(4) In the case of the P33/VPP pin of the built-in programmable
ROM version, connect an approximately 5 kΩ resistor to the
P33/VPP pin the shortest possible in series.
Notes on Clamp Diode (7481 Group)
(1) Total input current
The current of ports P4 and P5 through the clamp diode can
be drawn up to 1.0 mA per port. When a current that cannot be
consumed by microcomputer is sent flow to the clamp diode,
this may raise the power source pin voltage of the microcom-
puter.
The system power circuit must be designed so that the power
source voltage of the microcomputer may be stabilized within
the standard values.
(2) Maximum input voltage
If the input voltage of a signal connected to ports P4 and P5 is
beyond VCC + 0.3 V, the input waveform should have a delay
exceeding 2 µs/V from the moment that this waveform goes
over the voltage.
For using a CR circuit for delay, calculate a proper delay value
by the following expression:
dt
t
–6
=
≥ 2 ✕ 10 (s/V)
dv
0.6 ✕ VIN
where VIN = Maximum input voltage amplitude margin and
t = C ✕ R.
58
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS
ELECTRICAL CHARACTERISTICS (7481 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C (Note 1) unless otherwise specified)
Table 14. Electrical characteristics
Standard values
Typ.
Symbol
Parameter
“H” output voltage
Test conditions
VCC = 5 V, IOH = –5 mA
Unit
V
Min.
Max.
3
VOH
P00 – P07, P10 – P17
VCC = 3 V, IOH = –1.5 mA
VCC = 5 V, IOL = 10 mA
VCC = 3 V, IOL = 3 mA
VCC = 5 V
2
“L” output voltage P00 – P07,
P10 – P17, P40 – P43, P50 – P53
Hysteresis P00 – P07, (Note 2)
P30 – P33, P40 – P43, P50 – P53
2
VOL
V
1
0.5
0.3
0.5
0.3
0.5
0.3
VT + – VT–
V
VCC = 3 V
When used as SCLK, RxD
input
VCC = 5 V
VCC = 3 V
VT + – VT–
Hysteresis P16/SCLK, P14/RXD
V
_____
VCC = 5 V
VT + – VT–
Hysteresis RESET
V
VCC = 3 V
“H” input current
VI = VCC without pull-up
transistor
VCC = 5 V
VCC = 3 V
5
3
IIH
IIH
IIH
IIH
µ
µ
µ
µ
µ
A
A
A
A
A
P00 – P07, P10 – P17
“H” input current
VI = VCC = 5 V
VI = VCC = 3 V
VI = VCC when analog
input is not selected
VI = VCC
5
P30 – P33, P40 – P43, P50 – P53
3
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
5
“H” input current P20 – P27
3
_____
5
“H” input current RESET, XIN
(XIN at stop)
3
VI = 0 V without pull-up
transistor
–5
–3
–1.0
–0.35
–5
–3
–5
–3
–5
–3
“L” input current P00 – P07,
P10 – P17
IIL
VI = 0 V with pull-up
transistor (Note 3)
–0.25
–0.08
–0.5
mA
–0.18
“L” input current P30 – P33,
P40 – P43, P50 – P53
IIL
IIL
IIL
VI = 0 V
µ
µ
µ
A
A
A
VI = 0 V when analog input
is not selected
VI = 0 V
“L” input current P20 – P27
_____
“L” input current RESET, XIN
(XIN at stop)
Notes 1 : –40 to 85 °C for extended operating temperature range version.
2 : Using P0 for key-on wake-up function.
3 : Can be indicated in resistance value as shown below:
When VCC = 5 V: 5 kΩ (min.), 10 kΩ (typ.), 20 kΩ (max.).
When VCC = 3 V: 8.6 kΩ (min.), 16.7 kΩ (typ.), 37.5 kΩ (max.).
59
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS
Table 14. Electrical characteristics (cont.)
Standard values
Typ.
Symbol
Parameter
Test conditions
At clock stop mode
Unit
Min.
2
Max.
VRAM
RAM retention voltage
V
A-D conversion
not executed
3.5
4
7
8
mA
In high-speed mode,
f(XIN) = 4 MHz,
VCC = 5 V
A-D conversion
in progress
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A-D conversion
not executed
1.8
2
3.6
4
In high-speed mode,
f(XIN) = 4 MHz,
VCC = 3 V
A-D conversion
in progress
A-D conversion
not executed
7
14
15
3.5
4
In high-speed mode,
f(XIN) = 8 MHz,
VCC = 5 V
A-D conversion
in progress
7.5
1.75
2
A-D conversion
not executed
In medium-speed
mode, f(XIN) = 4 MHz,
VCC = 5 V
A-D conversion
in progress
A-D conversion
not executed
0.9
1
1.8
2
In medium-speed
mode, f(XIN) = 4 MHz,
VCC = 3 V
A-D conversion
in progress
ICC
Power source current
A-D conversion
not executed
In medium-speed
mode, f(XIN) = 8 MHz,
VCC = 5 V
3.5
3.75
1
7
A-D conversion
in progress
7.5
2
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
Ta = 25 °C
Ta = 85 °C
In high-speed mode,
f(XIN) = 4 MHz
0.5
2
1
mA
mA
In high-speed mode,
f(XIN) = 8 MHz
4
0.9
0.45
1.8
0.1
1
1.8
0.9
3.6
1
In medium-speed
mode, f(XIN) = 4 MHz
In medium-speed
mode, f(XIN) = 8 MHz
µA
µA
f(XIN) = 0
VCC = 5 V
10
60
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37481M4/M8/E8-XXXSP/FP, M37481M2T/M4T/M8T/E8T-XXXSP/FP, M37481E8SS
A-D CONVERSION CHARACTERISTICS (7481 Group)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C (Note) unless otherwise specified)
Table 15. A-D conversion characteristics
Standard values
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
8
——
——
Resolution
bits
Absolute accuracy (except
quantization error)
VCC = VREF = 5.0 V
±2
LSB
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
VCC = 2.7 to 4.0 V
25
12.5
VCC
VCC
100
TCONV
Conversion time
µs
V
2
0.5 VCC
12
VVREF
Reference voltage
VCC = 4.0 to 5.5 V
RLADDER
VIA
Ladder resistance
35
kΩ
V
Analog input voltage
Reference input current
0
VREF
416
IVREF
VREF = 5.0 V
50
143
µA
Note: –40 to 85 °C for extended operating temperature range version.
61
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
MASK ROM CONFIRMATION FORM
GZZ-SH09-84B<56A0>
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480M2T-XXXSP
M37480M2T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M2T–’
‘M37480M2T-’
‘M37480M2T–’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M2T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M2T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
62
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-84B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M2T–’
✽= $8000
.BYTE ‘M37480M2T–’
✽= $0000
.BYTE ‘M37480M2T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (32P4B for M37480M2T-XXXSP, 32P2W-A for M37480M2T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
63
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-85B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480M4-XXXSP
M37480M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M4-’
Area for ASCII
codes of the name
of the product
‘M37480M4–’
‘M37480M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
64
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-85B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M4–’
✽= $8000
.BYTE ‘M37480M4–’
✽= $0000
.BYTE ‘M37480M4–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (32P4B for M37480M4-XXXSP, 32P2W-A for M37480M4-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
65
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-86B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480M4T-XXXSP
M37480M4T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M4T–’
‘M37480M4T-’
‘M37480M4T–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M4T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M4T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
66
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-86B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37480M4T–’
✽= $8000
.BYTE ‘M37480M4T–’
✽= $0000
.BYTE ‘M37480M4T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (32P4B for M37480M4T-XXXSP, 32P2W-A for M37480M4T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
67
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-87B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480M8-XXXSP
M37480M8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M8–’
‘M37480M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
68
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-87B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480M8-’
✽= $0000
.BYTE ‘M37480M8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (32P4B for M37480M8-XXXSP, 32P2W-A for M37480M8-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
69
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-88B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480M8T-XXXSP
M37480M8T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480M8T–’
‘M37480M8T–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480M8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480M8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
70
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-88B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480M8T-’
✽= $0000
.BYTE ‘M37480M8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (32P4B for M37480M8T-XXXSP, 32P2W-A for M37480M8T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
71
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-78B<56A0>
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481M2T-XXXSP
M37481M2T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M2T–’
‘M37481M2T-’
‘M37481M2T–’
000F16
001016
000F16
001016
000F16
001016
2FFF16
300016
6FFF16
700016
EFFF16
F00016
ROM (4K)
ROM (4K)
ROM (4K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M2T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M2T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘2’ = 3216
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
72
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-78B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M2T–’
✽= $8000
.BYTE ‘M37481M2T–’
✽= $0000
.BYTE ‘M37481M2T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (42P4B for M37481M2T-XXXSP, 44P6N-A for M37481M2T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
73
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-79B<56A0>
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481M4-XXXSP
M37481M4-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M4-’
Area for ASCII
codes of the name
of the product
‘M37481M4–’
‘M37481M4–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M4–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M4–’ are listed on the right. The
addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
74
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-79B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M4–’
✽= $8000
.BYTE ‘M37481M4–’
✽= $0000
.BYTE ‘M37481M4–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (42P4B for M37481M4-XXXSP, 44P6N-A for M37481M4-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
75
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-80B<56A0>
Date:
740 FAMILY MASK ROM CONFIRMATION FORM
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481M4T-XXXSP
M37481M4T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27128
27256
27512
EPROM address
000016
EPROM address
EPROM address
000016
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M4T–’
‘M37481M4T-’
‘M37481M4T–’
000F16
001016
000F16
001016
000F16
001016
1FFF16
200016
5FFF16
600016
DFFF16
E00016
ROM (8K)
ROM (8K)
ROM (8K)
3FFF16
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
000016
000116
000216
000316
000416
000516
000616
000716
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M4T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M4T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘4’ = 3416
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
76
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-80B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program.
EPROM type
27128
27256
27512
✽= $C000
.BYTE ‘M37481M4T–’
✽= $8000
.BYTE ‘M37481M4T–’
✽= $0000
.BYTE ‘M37481M4T–’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (42P4B for M37481M4T-XXXSP, 44P6N-A for M37481M4T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
77
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-81B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481M8-XXXSP
M37481M8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M8–’
‘M37481M8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
78
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-81B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481M8-’
✽= $0000
.BYTE ‘M37481M8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (42P4B for M37481M8-XXXSP, 44P6N-A for M37481M8-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
79
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-82B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
Date:
Section head Supervisor
SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP
MITSUBISHI ELECTRIC
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We
shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data.
Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481M8T-XXXSP
M37481M8T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481M8T–’
‘M37481M8T–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481M8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481M8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘M’ = 4D16
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
80
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mask ROM number
GZZ-SH09-82B<56A0>
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481M8T-’
✽= $0000
.BYTE ‘M37481M8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing
is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark
specification form (42P4B for M37481M8T-XXXSP, 44P6N-A for M37481M8T-XXXFP) and attach to the mask ROM
confirmation form.
❈ 3. Comments
81
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
ROM PROGRAMMING CONFIRMATION FORM
GZZ-SH09-91B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480E8-XXXSP
M37480E8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
Area for ASCII
codes of the name
of the product
‘M37480E8–’
codes of the name
of the product
‘M37480E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
82
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-91B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480E8-’
✽= $0000
.BYTE ‘M37480E8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8-XXXSP or the
32P2W-A Mark Specification Form for the M37480E8-XXXFP.
❈ 3. Comments
83
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-92B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37480E8T-XXXSP
M37480E8T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37480E8T–’
‘M37480E8T–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37480E8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37480E8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘0’ = 3016
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
84
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-92B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37480E8T-’
✽= $0000
.BYTE ‘M37480E8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8T-XXXSP or the
32P2W-A Mark Specification Form for the M37480E8T-XXXFP.
❈ 3. Comments
85
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-89B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481E8-XXXSP
M37481E8-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
Area for ASCII
codes of the name
of the product
‘M37481E8–’
codes of the name
of the product
‘M37481E8–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481E8–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481E8–’ are listed on the right. The
addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
86
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-89B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481E8-’
✽= $0000
.BYTE ‘M37481E8-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8-XXXSP or the
44P6N-A Mark Specification Form for the M37481E8-XXXFP.
❈ 3. Comments
87
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-90B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Date:
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Submitted by
Supervisor
TEL
(
Company
name
)
Customer
❈
Date
issued
Date:
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern (Check @ in the appropriate box).
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on
this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Microcomputer name :
M37481E8T-XXXSP
M37481E8T-XXXFP
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27256
27512
EPROM address
000016
EPROM address
000016
Area for ASCII
codes of the name
of the product
Area for ASCII
codes of the name
of the product
‘M37481E8T–’
‘M37481E8T–’
000F16
001016
000F16
001016
3FFF16
400016
BFFF16
C00016
ROM (16K)
ROM (16K)
7FFF16
FFFF16
(1) Set “FF16” in the shaded area.
Address
Address
(2) Write the ASCII codes that indicates the name of the
product ‘M37481E8T–’ to addresses 000016 to 000F16.
ASCII codes ‘M37481E8T–’ are listed on the right.
The addresses and data are in hexadecimal notation.
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘7’ = 3716
‘4’ = 3416
‘8’ = 3816
‘1’ = 3116
‘E’ = 4516
‘8’ = 3816
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘ T ’ = 5416
‘ – ’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
88
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM number
GZZ-SH09-90B<56A0>
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP
MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file :
EPROM type
27256
27512
✽= $8000
.BYTE ‘M37481E8T-’
✽= $0000
.BYTE ‘M37481E8T-’
The pseudo-command
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form,
the ROM processing is disabled. Write the data correctly.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP
package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8T-XXXSP or the
44P6N-A Mark Specification Form for the M37481E8T-XXXFP.
❈ 3. Comments
89
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
32P2W–A
32P4B
90
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42P4B
44P6N–A
91
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MARK SPECIFICATION FORM
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
92
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
32P2W (32-PIN SOP) MARK SPECIFICATION FORM
93
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
94
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
44P6N (44-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special
mark (if needed).
A. Standard Mitsubishi Mark
#
@
#
@
Mitsubishi lot
number (6-digit)
Mitsubishi IC catalog name
$
!
q
!1
B. Customer’s Parts Number + Mitsubishi Catalog Name
# @
Customer’s parts number
Note : The fonts and size of characters are standard
Mitsubishi type.
#
@
Mitsubishi IC catalog name and Mitsubishi lot number
Note4 : If the Mitsubishi logo
the box below.
is not required, check
$
!
Mitsubishi logo is not required.
q
!1
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard
Mitsubishi type.
3 : Customer’s parts number can be up to 7 characters :
Only 0 ~ 9, A ~ Z,+,–,
⁄
, (, ), &, ©, (period), and
•
,
(comma) are usable.
Note1 : If the special mark is to be printed, indicate the
desired layout of the mark in the left figure. The
layout will be duplicated as close as possible.
Mitsubishi lot number (6-digit ) and mask ROM
number (3-digit) are always marked.
C. Special Mark Required
#
@
#
@
2 : If the customer’s trade mark logo must be used
in the special mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean
font original (ideally logo drawing) must be sub-
mitted.
$
!
Special logo required
q
!1
The standard Mitsubishi font is used for all characters ex-
cept for a logo.
95
MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1997 MITSUBISHI ELECTRIC CORP.
KI-9711 Printed in Japan (ROD)
II
New publication, effective Nov. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
7480/7481 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
971130
(1/1)
相关型号：
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