M37510M6 概述
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单片8位CMOS微机
M37510M6 数据手册
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PDF下载MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●2 Clock generating circuit
DESCRIPTION
(Connect to external ceramic resonator or quartz-crystal.)
●Power source voltage
The 7510 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
In high-speed mode .................................................. 4.0 to 5.5 V
In middle-speed mode............................................... 2.5 to 5.5 V
In low-speed mode .................................................... 2.5 to 5.5 V
●Power dissipation
This microcomputer is equipped with added functions such as a
dot matrix type LCD controller/driver built in a contrast controller
and UART.
In high-speed mode ..........................................................32 mW
(at 8.0 MHz oscillation frequency)
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ........................... 0.5 µs
(at 8.0 MHz oscillation frequency)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency and 3.0 V power source voltage)
In wait mode ........................................................................ 9 µW
(at 32 kHz oscillation frequency and 3.0 V power source voltage)
●Operating temperature range.................................. –20 to +85°C
●RAM for LCD display .................................................... 160 bytes
●Programmable input/output ports ............................................ 41
●Interrupts ................................................. 15 sources, 15 vectors
(includes key-on wake up)
APPLICATION
●Timers ........................................................... 8-bit ✕ 3, 16-bit ✕ 2
●Serial I/O ...................... 8-bit ✕ 2 (UART or clock-synchronized)
●LCD controller/driver Bias ........................................ 1/4, 1/5 bias
Duty ratio ......................1/8, 1/11, 1/16 duty
Cellular radio telephones, business telephones, facsimiles, and
other portable equipment that need a large capacity of LCD dis-
play.
Common output ...................................... 16
Segment output ...................................... 80
Built-in an LCD contrast controller
(capable of 32-step contrast adjustment)
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
133
88
NC
NC
134
87
NC
SEG65
NC
NC
135
86
136
85
SEG64
NC
137
84
SEG63
SEG62
NC
NC
138
83
139
82
SEG61
SEG60
P11
P12
140
81
141
80
SEG59
P13
142
79
SEG58
SEG57
P14
P15
143
78
144
77
SEG56
SEG55
P16
P17
145
76
146
75
SEG54
SEG53
SEG52
P20
P21
P22
147
74
148
73
149
72
SEG51
SEG50
P23
P24
150
71
151
70
SEG49
SEG48
P25
P26
152
69
153
68
SEG47
P27
154
67
SEG46
SEG45
VSS
XOUT
M37510M6-XXXFP
155
66
156
65
SEG44
SEG43
XIN
P50/XCOUT
157
64
158
63
SEG42
P51/XCIN
159
62
SEG41
SEG40
RESET
P40/INT0
160
61
161
60
SEG39
SEG38
P41/INT1
P42/CNTR0
162
59
163
58
SEG37
SEG36
SEG35
P43/CNTR1
P44/RXD1
P45/TXD1
164
57
165
56
166
55
SEG34
SEG33
P46/SCLK1
P47/SRDY1
167
54
168
53
SEG32
SEG31
NC
NC
169
52
170
51
SEG30
NC
171
50
SEG29
SEG28
NC
NC
172
49
173
48
SEG27
SEG26
NC
VSS
174
47
175
46
NC
NC
176
45
NC
NC
Package type : 176P6D-A
176-pin plastic-molded QFP
NC : No connect
2
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key-on wake up
3
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Function
Function except a port function
VCC, VSS
RESET
XIN
Power source
Reset input
Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS (in high-speed mode).
Reset input pin for active “L”.
Input and output pins for the main clock generating circuit. Connect a ceramic resonator or
quartz-crystal oscillator between the XIN and XOUT pins to set the oscillating frequency. If an ex-
ternal clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
Clock input
XOUT
Clock output
LCD voltage source
VLCD
This pin is used as voltage supply input for LCD driver. Input VLCD ≤ VCC voltage.
When the LCD is operated at 1/5 bias, leave these pins open. When the LCD is operated at 1/4
bias, connect these pins externally.
VL2, VL3
LCD bias control pin
Common output
COM0–
COM15
LCD common output pins.
LCD segment output pins.
SEG0–
SEG79
Segment output
An 8-bit I/O port. The output structure of this port is CMOS 3-state, and the input levels are
CMOS compatible. The port direction register allows each pin to be individually programmed as
either input or output.
P00–P07
P10–P17
P20–P27
I/O port P0
I/O port P1
I/O port P2
Key input (Key-on wake-up) interrupt input pins.
P30/RXD2,
P31/TXD2,
P32/ SCLK2,
P33/SRDY2
Serial I/O2 function pins
I/O port P3
P34–P37
P40/INT0
P41/INT1
Input port P4
A 1-bit CMOS level input port.
External interrupt input pins
A 7-bit I/O port with the same function as port
P0.
Timer X, Timer Y function pins
External interrupt input pins
P42/CNTR0,
P43/CNTR1
I/O port P4
The port direction register allows each pin to
be individually programmed as either input or
output.
P44/RXD1,
P45/TXD1,
P46/ SCLK1,
P47/SRDY1
Serial I/O1 function pins
A 2-bit I/O port with the same function as port
P0.
I/O pins for the internal sub clock generating
circuit. Connect an oscillator.
P50/XCOUT,
P51/XCIN
I/O port P5
The port direction register allows each pin to
be individually programmed as either input or
output.
4
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M37510
M
6
XXX
FP
Package type
FP: 176P6D-A package
FS: 160D0 package
ROM number
Omitted in some types.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
RAM size
512 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
Currently supported products are listed below.
As of May 1996
Product name
M37510M6-XXXFP
M37510E6-XXXFP
M37510E6FP
(P) ROM size (bytes)
24K
RAM size (bytes)
512
Package
Remarks
Mask ROM version
176P6D-A One Time PROM version
One Time PROM version (blank)
M37510E6FS
EPROM version
160D0
5
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CPU MODE REGISTER
CENTRAL PROCESSING UNIT (CPU)
The 7510 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction are not available for use.
The STP, WIT, MUL, and DIV instruction can be used.
b7
b0
CPU mode register (CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 : Do not use
0 : Do not use
1 : Do not use
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
XCOUT drivability selection bit
0 : Low drive
1 : High drive
Port XC selection bit
0 : I/O port
1 : XCIN, XCOUT
Main clock (XIN-XOUT) stop bit
0 : Operating
1 : Stopped
Main clock division ratio selection bit
0 : XIN/2 (high-speed mode)
1 : XIN/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN-XOUT selected (middle/high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
Fig. 1 Structure of CPU mode register
6
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Interrupt Vector Area
Special Function Register (SFR) Area
The Special Function Register area contains registers which con-
trol functions such as I/O ports and timers, and is located in the
zero page area.
The interrupt vector area contains reset and interrupt vectors.
Zero Page
This dedicated zero page addressing mode enables access to this
area with only 2 bytes.
RAM
RAM is used for data storage as well for stack area.
Special Page
This dedicated special page addressing mode enables access to
ROM
this area with only 2 bytes.
The first 128 bytes and the last two bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
000016
SFR area
004016
LCD display RAM area✽
Zero page
00DF16
RAM area
Type name
Address XXXX16
023F16
010016
M37510M6-XXXFP
RAM
034016
LCD display RAM area✽
03DF16
XXXX16
Not used
YYYY16
Reserved ROM area
ROM area
(common ROM area, 128 bytes)
Type name
Address YYYY16
A00016
Address ZZZZ16
A08016
ZZZZ16
M37510M6-XXXFP
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
✽ LCD display RAM area can reside at either zero page (addresses 004016 to 00DF16) or third page (addresses 034016 to 03DF16) by software.
The third page is selected after reset.
Fig. 2 Memory map diagram
7
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
002016 Timer X (low) (TXL)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
002116 Timer X (high) (TXH)
002216 Timer Y (low) (TYL)
002316 Timer Y (high) (TYH)
002416 Timer 1 (T1)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
002516 Timer 2 (T2)
002616 Timer 3 (T3)
000716 Port P3 direction register (P3D)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
002716 Timer X mode register (TXM)
002816 Timer Y mode register (TYM)
002916 Timer 123 mode register (T123M)
002A16
000B16 Port P5 direction register (P5D)
000C16 Port P0 pull-up control register (PULLP0)
000D16 Port P1 pull-up control register (PULLP1)
000E16 Port P2 pull-up control register (PULLP2)
000F16 Port P3 pull-up control register (PULLP3)
001016 Port P4 pull-up control register (PULLP4)
001116 Port P5 pull-up control register (PULLP5)
001216
002B16
002C16
002D16
002E16
002F16
003016 Transmit/receive buffer register 2 (TB2/RB2)
003116 Serial I/O2 status register (SIO2STS)
003216 Serial I/O2 control register (SIO2CON)
003316 UART2 control register (UART2CON)
003416 Baud rate generator 2 (BRG2)
003516
001316
001416
001516
001616
003616
001716
003716 LCD contrast control register (LC)
003816
001816 Transmit/receive buffer register 1 (TB1/RB1)
001916 Serial I/O1 status register (SIO1STS)
001A16 Serial I/O1 control register (SIO1CON)
001B16 UART1 control register (UART1CON)
001C16 Baud rate generator 1 (BRG1)
001D16
003916 LCD mode register (LM)
003A16 Interrupt edge selection register (INTEDGE)
003B16 CPU mode register (CPUM)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001E16
001F16
Fig. 3 Memory map of special function register (SFR)
8
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
When “0” is written to the pull-up control register, the pull up on the
pin is disabled. When “1” is written to the pull-up control register,
the pull-up on the pin is enabled.
Direction Registers
The 7510 group has 41 programmable I/O pins arranged in six I/O
ports (ports P0 to P5). The I/O ports have direction registers which
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input or output.
After reset, all the pull-up control registers are initialized to “0016”,
disabling all the internal pull-ups.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
b7
b0
Port Pi pull-up control register
(PULLPi : addresses 000C16 to 001116)
If data is read from a pin which is set for output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating and can read the value of the pin itself. If a pin
set to input is written to, only the port output latch is written to and
the pin remains floating.
Pi0 pull-up
Pi1 pull-up
Pi2 pull-up
Pi3 pull-up
Pi4 pull-up
Pi5 pull-up
Pi6 pull-up
Pi7 pull-up
0 : Disabled
1 : Enabled
Port Pull-up Control Registers
The 7510 group is equipped with internal pull-ups that can be en-
abled by software. Each I/O port of ports P0–P5 has an port Pi (i=
0 to 5) pull-up control register (addresses 000C16 to 001116). Each
bit of the pull-up control register controls a corresponding bit of the
port. The value written to each individual bit determines whether
the pull-up of the corresponding pin is either enabled or disabled.
i = 0 to 5
Fig. 4 Structure of port Pi pull-up control register
Pin
Name
Input/Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
Non-Port Function
Related SFRs
Ref. No.
(1)
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
P00–P07
Port P0
P10–P17
P20–P27
Port P1
Port P2
(1)
(2)
Key-on wake up
interrupt input
Interrupt control
register 2
(3)
(4)
(5)
(6)
(1)
(7)
(8)
(9)
(8)
(3)
(4)
(5)
(6)
Serial I/O2 control
register
P30/RXD2,
P31/TXD2,
P32/ SCLK2,
P33/SRDY2
P34–P37
CMOS compatible
input level
Serial I/O2
function I/O
Input/output,
individual bits
Serial I/O2 status register
UART control register 2
Port P3
CMOS 3-state output
P40/INT0
P41/INT1
P42/CNTR0,
P43/CNTR1
P44/RXD1,
P45/TXD1,
P46/ SCLK1,
P47/SRDY1
P50/XCOUT,
P51/XCIN
COM0–
Input
CMOS compatible input level
External interrupt
input
Timer X function I/O
Timer Y function I/O
Timer X mode register
Timer Y mode register
CMOS compatible
input level
Input/output,
individual bits
Port P4
Serial I/O1 control
register
CMOS 3-state output
Serial I/O1
function I/O
Serial I/O1 status register
UART1 control register
CMOS compatible input level
Input/output,
individual bits
Sub-clock generat-
ing circuit I/O
Port P5
Common
Segment
(1)
CPU mode register
LCD mode register
CMOS 3-state output
Output
Output
LCD common output
LCD segment output
COM15
SEG0–
SEG79
Notes 1: For details of how to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
9
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0, P1, P34 to P37, P5
(2) Port P2
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Key-on wake up input
(4) Port P31, P45
(3) Port P30, P44
Pull-up control
Serial I/O enable bit
Receive enable bit
Pull-up control
P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Serial I/O input
Serial I/O output
(6) Port P33, P47
(5) Port P32, P46
Pull-up control
Serial I/O synchronous
clock selection bit
Pull-up control
Serial I/O enable bit
Serial I/O
mode selection bit
Serial I/O enable bit
RDY output enable bit
Serial I/O mode selection bit
Serial I/O enable bit
S
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial clock output
Serial ready output
External clock input
Fig. 5 Port block diagram (1)
10
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8) Port P41, P43
(7) Port P40
Pull-up control
Direction
register
Data bus
Port latch
Data bus
INT0 interrupt input
INT1 interrupt input
CNTR1 interrupt input
(9) Port P42
Pull-up control
Direction
register
Data bus
Port latch
Pulse output mode
Timer output
CNTR0 interrupt input
Fig. 6 Port block diagram (2)
11
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Operation
A total of 15 sources can generate interrupts: 5 external, 9 inter-
When an interrupt is received, the program counter and processor
status register are automatically pushed onto the stack. The inter-
rupt disable flag is set to inhibit other interrupts from interfering.
The corresponding interrupt request bit is cleared and the interrupt
jump destination address is read from the vector table into the pro-
gram counter.
nal, and 1 software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt is generated if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Notes on Use
When the active edge of an external interrupt (INT0, INT1, CNTR0,
or CNTR1) is changed, the corresponding interrupt request bit
may also be set. Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and BRK instruction can not be disabled with any flag or
bit.
(3) Clear interrupt request which is selected to “0”.
(4) Enable the external interrupt which is selected.
The I flag disables all interrupts except for the BRK instruction in-
terrupt and the reset.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 1 Interrupt vector addresses and priority
Vector addresses (Note 1)
Interrupt request
Remarks
Interrupt source
Priority
generating conditions
High
Low
FFFD16
FFFC16
Reset (Note 2)
INT0
1
2
At reset
Non-maskable
At detection of either rising or External interrupt (active edge
falling edge of INT0 input
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
selectable)
At detection of either rising or
falling edge of INT1 input
External interrupt (active edge
selectable)
INT1
3
4
At end of serial I/O1 data re-
ception
Serial I/O1
reception
Valid when serial I/O1 is se-
lected
At end of serial I/O1 transfer
shift or when transmission
buffer is empty
Serial I/O1
transmission
Valid when serial I/O1 is se-
lected
5
FFF516
FFF416
Timer X
Timer Y
Timer 2
Timer 3
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
Serial I/O2
reception
At end of serial I/O2 data re- Valid when serial I/O2 is se-
10
11
12
FFEB16
FFE916
FFE716
FFEA16
FFE816
FFE616
ception
lected
At end of serial I/O2 transfer
shift or when transmission
buffer is empty
Serial I/O2
transmission
Valid when serial I/O2 is se-
lected
At detection of either rising or
falling edge of CNTR0 input
External interrupt (active edge
selectable)
CNTR0
At detection of either rising or
falling edge of CNTR1 input
External interrupt (active edge
selectable)
13
14
FFE516
FFE316
FFE416
FFE216
CNTR1
Timer 1
At timer 1 underflow
At falling of conjunction of in-
put logic level for port P2 (at
input)
External interrupt (valid when
an “L” level is applied)
Key-on wake up
BRK instruction
15
16
FFE116
FFDD16
FFE016
FFDC16
Non-maskable software inter-
rupt
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
12
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 7 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
0
1
active edge selection bit
active edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16
Interrupt request register 2
(IREQ2 : address 003D16)
)
INT
INT
0
1
interrupt request bit
interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
Timer 1 interrupt request bit
Timer Y interrupt request bit
Timer 2 interrupt request bit
Key-on wake up interrupt request bit
Not used (return “0” when read)
Timer 3 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
1
Timer 1 interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Key-on wake up interrupt enable bit
Not used (returns “0” when read)
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 8 Structure of interrupt-related registers
13
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
The 7510 group has five built-in timers: timer X, timer Y, timer 1,
timer 2, and timer 3. Timer X and timer Y are 16-bit timers,
whereas timer 1, timer 2, and timer 3 are 8-bit timers.
XCIN
1/32
Internal system
clock selection bit
“1”
XIN
1/16
“0”
Timer X stop control bit
“00”
Timer X write control bit
Timer XH latch (8)
CNTR0 active edge
selection bit
Timer XL latch (8)
Timer XL (8)
Timer X operation mode bit
“01”
“11”
P42/CNTR0
“0”
Timer XH (8)
Timer X interrupt request
CNTR0 interrupt request
“10”
“1”
Pulse output mode
“0”
S
Q
Q
T
CNTR0 active “1”
edge selection bit
P42 direction register
Pulse output mode
P42 latch
Pulse width continuously
measurement mode
Rising edge detector
Falling edge detector
Period
measurement mode
Timer Y
stop
control bit
“00”
“01”
“11”
Timer YL latch (8)
Timer YL (8)
Timer YH latch (8)
Timer YH (8)
P43/CNTR1
“0”
“1”
Timer Y interrupt request
Timer Y operation mode bit
“10”
Timer Y operation mode bit
“11”
CNTR1 active edge
selection bit
CNTR1 interrupt request
“00”
“01”
“10”
Timer 2 write control bit
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
“0”
“1”
Timer 2 interrupt request
Timer 1 interrupt request
“1”
Timer 1 count source selection bit
“0”
Timer 2 count source
selection bit
Timer 3 latch (8)
Timer 3 (8)
“0”
“1”
Timer 3 interrupt request
Timer 3 count source
selection bit
Fig. 9 Block diagram of Timer
14
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
responding to that timer is set to “1”.
If the value is written in latch only, unexpected value may be set in
the high-order counter when the writing in high-order latch and the
underflow of timer X are performed at the same timing.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Note on CNTR0 Interrupt Active Edge
Selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
selection bit.
Timer X
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write by setting the timer X
mode register.
b7
b0
Timer X mode register
(TXM : address 002716
)
Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16, if the selected system
clock φ is f(XCIN)/2).
Timer X write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Pulse output mode
Not used (Always write “0” )
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode, set
the corresponding port P42 direction register to output mode.
Event counter mode
Timer X operation mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR0 active edge selection bit
The timer counts signals input through the CNTR0 pin. Except for
this, the operation in event counter mode is the same as in timer
mode.
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for CNTR0 interrupt
Pulse width measurement mode
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
The count source is f(XIN)/16 (or f(XCIN)/16, if the selected system
clock φ is f(XCIN)/2). If CNTR0 active edge selection bit is “0”, the
timer counts while the input signal of CNTR0 pin is at “H”. If it is
“1”, the timer counts while the input signal of CNTR0 pin is at “L”.
Rising edge active for CNTR
0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
Fig. 10 Structure of timer X mode register
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
15
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
b7
b0
Timer Y is a 16-bit timer that can be selected in one of four modes.
Timer Y mode register
(TYM : address 002816)
Timer mode
The timer counts f(XIN)/16 (or f(XCIN)/16, if the selected system
clock φ is f(XCIN)/2).
Not used (return “0” when read)
Timer Y operation mode bits
b5 b4
Period measurement mode
0
0
1
1
0 : Timer mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except
for the above-mentioned, the operation in period measurement
mode is the same as in timer mode.
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge selection bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
1 : Count at falling edge in event counter mode
Measure the rising edge to rising edge
period in period measurement mode
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt.
Rising edge active for CNTR1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
Event counter mode
The timer counts signals input through the CNTR1 pin. Except for
this, the operation in event counter mode is the same as in timer
mode.
Fig. 11 Structure of timer Y mode register
Pulse width HL continuously measurement mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
Note on CNTR1 Interrupt Active Edge
Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
selection bit. However, in pulse width HL continuously measure-
ment mode, CNTR1 interrupt request is generated at both rising
and falling edges of CNTR1 pin input signal regardless of the set-
ting of CNTR1 active edge selection bit.
16
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1,Timer 2,Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer.
b7
b0
Timer 123 mode register
(T123M : address 002916)
Not used (Always write “0” )
Timer 2 write control bit
0 : Write data in latch and timer
1 : Write data in latch only
Therefore, rewrite the value of timer whenever the count source is
changed.
Timer 2 count source selection bit
0 : Timer 1 output
1 : XIN/16
Timer 2 Write Control
(or XCIN/16 when system clock φ = XCIN/2)
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
Timer 3 count source selection bit
0 : Timer 1 output
1 : XCIN/32
Timer 1 count source selection bit
0 : XIN/16
(or XCIN/16 when system clock φ = XCIN/2)
1 : XCIN/32
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
Not used (return “0” when read)
Note on Timer 1 to Timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer. If the count source of timer 2 or timer 3 is
connected to timer 1 output, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Fig. 12 Structure of timer 123 mode register
Therefore, set the value of timer in the order of timer 1 , timer 2
and timer 3 after the count source selection of timer 1 to 3.
17
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
but the two buffers have the same address in memory.
Since the shift register cannot be written to or read from directly,
transmit data is written to the transmit buffer, and receive data is
read from the receive buffer. The transmit buffer can also hold the
next data to be transmitted, and the receive buffer can hold a char-
acter while the next character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer,
Data bus
Address
001816
003016
Address 001A16
Serial I/O control register
003216
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Receive buffer
Character length selection bit
7 bits
ST detector
P44/RXD1
P30/RXD2
Receive shift register
1/16
8 bits
UART control register
PE FE
SP detector
Clock control circuit
Address 001B16
003316
Serial I/O synchronous clock selection bit
P46/SCLK1
P32/SCLK2
BRG count source selection bit
1/4
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16 003416
f(XIN)
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit shift register
P45/TXD1
P31/TXD2
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address
Transmit buffer empty flag (TBE)
Serial I/O status register
Address 001916 003116
001816 003016
Data bus
Contents in
are for serial I/O2.
Fig. 15 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE = 0
TBE = 0
D1
TSC = 0
TBE = 1
✽
TBE = 1
TSC = 1
ST
D0
SP
ST
D0
D1
SP
Serial output TXD
1 start bit
✽Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit(s)
Receive buffer read signal
RBF = 0
RBF = 1
SP
RBF = 1
SP
ST
D0
D1
ST
D0
D1
Serial input RXD
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Fig. 16 Operation of UART serial I/O function
19
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Control Register
SIO1CON (001A16), SIO2CON (003216)
The serial I/O control register consists of eight control bits for the
serial I/O function.
UART Control Register
UART1CON (001B16), UART2CON (003316)
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD1 (P31/
TXD2) pin.
Serial I/O Status Register
SIO1STS (001916), SIO2STS (003116)
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. Writing to the serial I/O status reg-
ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6,
respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the serial I/O control register) also clears all the status flags, in-
cluding the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift completion flag (bit 2) and
the transmit buffer empty flag (bit 0) become “1”.
Transmit Buffer Register/Receive Buffer Register
TB1/RB1 (001816), TB2/RB2 (003016)
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only.
If a character bit length is 7 bits, the MSB of data stored in the re-
ceive buffer register is “0”.
Baud Rate Generator
BRG1 (001C16), BRG2 (003416)
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n+1), where n is the value written to the baud rate generator.
20
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O control register
Serial I/O status register
(SIO1STS : address 001916)
(SIO1CON : address 001A16)
(SIO2STS : address 003116)
(SIO2CON : address 003216)
Transmit buffer empty flag (TBE)
0 : Buffer full
BRG count source selection bit (CSS)
0 : f(XIN)
1 : Buffer empty
1 : f(XIN) divided by 4
Receive buffer full flag (RBF)
0 : Buffer empty
1 : Buffer full
Serial I/O synchronous clock selection bit (SCS)
0 : BRG output divided by 4 when clock
synchronous serial I/O is selected,
BRG output divided by 16 when UART
is selected.
Transmit shift completion flag (TSC)
0 : Transmit shift in progress
1 : Transmit shift completed
1 : External clock input when clock synchronous
serial I/O is selected, external clock input
divided by 16 when UART is selected.
Overrun error flag (OE)
0 : No error
1 : Overrun error
SRDY output enable bit (SRDY)
0 : P47 P33 pin operates as ordinary I/O pin
1 : P47 P33 pin operates as SRDY output pin
Parity error flag (PE)
0 : No error
1 : Parity error
Transmit interrupt source selection bit (TIC)
0 : Interrupt when transmit buffer has emptied
1 : Interrupt when transmit shift operation
is completed
Framing error flag (FE)
0 : No error
1 : Framing error
Transmit enable bit (TE)
0 : Transmit disabled
1 : Transmit enabled
Summing error flag (SE)
0 : (OE) U (PE) U (FE) = 0
1 : (OE) U (PE) U (FE) = 1
Receive enable bit (RE)
0 : Receive disabled
1 : Receive enabled
Not used (returns “1” when read)
Serial I/O mode selection bit (SIOM)
0 : Asynchronous serial I/O (UART)
1 : Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0 : Serial I/O disabled
(pins P44 to P47 P30 to P33
operate as ordinary I/O pins)
1 : Serial I/O enabled
(pins P44 to P47 P30 to P33
operate as serial I/O pins)
b7
b0
UART control register
(UART1CON : address 001B16)
(UART2CON : address 003316)
Character length selection bit (CHAS)
0 : 8 bits
1 : 7 bits
Parity enable bit (PARE)
0 : Parity checking disabled
1 : Parity checking enabled
Parity selection bit (PARS)
0 : Even parity
1 : Odd parity
Stop bit length selection bit (STPS)
0 : 1 stop bit
1 : 2 stop bits
P45/TXD1 P-channel output disable bit (POFF)
P31/TXD2 P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Not used (return “1” when read)
Contents in
are for serial I/O2.
Fig. 17 Structure of serial I/O control registers
21
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD CONTROLLER/DRIVER
The 7510 group has a built-in Liquid Crystal Display (LCD) control-
ler/driver consisting of the following.
●A 160-byte LCD display RAM
●Segment drivers
●A timing controller
●An LCD mode register
●An LCD contrast control register
●An LCD contrast controller
A maximum of eighty segment output pins (SEG0–SEG79) and six-
teen common output pins (COM0–COM15) can be used to control
an external LCD display controller.
●Common drivers
●A timing generator
●A built-in bias resistor
Fig. 18 Block diagram of LCD controller/driver
22
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Maximum number of display pixels for each duty ratio
LCD Controller/Driver Function
The controller/driver reads the display data, performs bias and
duty ratio control, and outputs the correct LCD timing signals on
the segment and common pins according to the data in LCD dis-
play RAM.
Duty ratio
1/8
Maximum number of display pixels
8 ✕ 80 dots
(16 characters (5 ✕ 7 dots/1 character) + cursor) ✕ 1 line
11 ✕ 80 dots
(16 characters (5 ✕ 10 dots/1 character) + cursor) ✕ 1 line
1/11
1/16
LCD Mode Register
LM (003916)
16 ✕ 80 dots
(16 characters (5 ✕ 7 dots/1 character) + cursor) ✕ 2 line
The LCD mode register is an 8-bit register. This register is used to
match the characteristics of the controller/driver to the LCD panel
used.
Note: Prior to executing an STP instruction, the LCD must be disabled by
clearing the bit 3 of the LCD mode register to “0”.
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
b1 b0
0
0
1
1
0 : 1/8 duty (pins COM
1 : 1/8 duty (pins COM
0 : 1/11 duty (pins COM
1 : 1/16 duty (pins COM
0
8
– COM
– COM15
7)
)
0
0
– COM10
– COM15
)
)
LCD display RAM address selection bit
0 : Third page
1 : Zero page
LCD enable bit
0 : Turn off
1 : Turn on
LCD drive timing selection bit
0 : Type-A
1 : Type-B
LCDCK division ratio selection bits
b6 b5
0
0
1
1
0 : Clock input
1 : Clock input/2
0 : Clock input/4
1 : Clock input/8
LCDCK count source selection bit
0 : f(XIN) /1024
1 : f(XCIN) /16
Fig. 19 Structure of LCD mode register
23
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
RAM can not be used. After reset, the LCD display RAM is set to
third page.
The 7510 group has LCD display RAM apart from user RAM at
addresses 004016 to 043F16. The LCD display RAM consists of
160 bytes. The memory space for the LCD display RAM can be
selected as zero page addresses 004016 to 00DF16 or third page
addresses 034016 to 03DF16, by setting the LCD display RAM ad-
dress selection bit.
Writing “1” to a bit of the LCD display RAM activates the corre-
sponding pixel on the LCD panel and writing “0” to the bit turns the
pixel off.
Note: The data of user RAM at the same addresses with the LCD display
RAM (addresses 004016 to 00DF16 or 034016 to 03DF16) is retained.
Therefore, user RAM can be used effectively by switching the LCD
display RAM address.
When the LCD display RAM is at zero page, the addresses 004016
to 00DF16 of user RAM can not be used. When the LCD display
RAM is at third page, the addresses 034016 to 03DF16 of user
COM0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0 LSB
0
0
0
0
0
0
0 MSB
0 LSB
1
1
0
0
0
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
0 MSB
LCD display RAM map
Fig. 20 LCD display RAM map and example of a display pattern for 1/16 duty operation
24
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bias Control and Time Division Control
The LCD controller/driver has built-in bias resistor and supports 1/
4 bias or 1/5 bias. The bias setting is made by either floating pins
VL2 and VL3 (1/5 bias) or shorting them together externally (1/4
bias). The number of common pins driven is determined by the
duty ratio selected. Bits 0 and 1 of the LCD mode register are
used to set the duty ratio.
When the contrast controller is used, it becomes possible to apply
32 steps of voltage to VL5 from 1/2 VLCD through VLCD. Conse-
quently, 32 steps of contrast adjustment by the software becomes
possible.
Note: Supply power to the contrast controller from an external source
through the VLCD pin.
Also, when bit 7 of the LCD contrast control register is set to “0”,
VLCD pin is coupled directly to VL5 (the contrast controller and VL5
become separated). In this case, perform contrast adjustment using
an external circuit.
Table 3 Time division control
Duty ratio selection bit
Duty
Common pins used
ratio
Bit 1
Bit 0
b7
b0
0
0
1
1
0
1
0
1
COM0–COM7
COM8–COM15
COM0–COM10
COM0–COM15
1/8
LCD contrast control register
(LC : address 003716
)
1/11
1/16
VLCD level selection bit
Not used (returns “0” when read)
Note: For all duty ratios, the unused common pins output the non-select
LCD contrast control enable bit
0 : Built-in LCD contrast
controller is not used
waveform.
1 : Built-in LCD contrast
controller is used.
Contrast Controller
The contrast controller is a circuit generating 32 steps of voltages
using the voltage applied to the VLCD pin as the reference voltage.
The voltage generated varies depending on the values given to bit
0–bit 4 with the LCD contrast control register. When bit 7 of the
LCD contrast control register is set to “1”, the voltage generated by
the contrast controller is applied to VL5. Given below is the relation
between the values set to bit 0–bit 4 of LCD contrast control regis-
ter and the voltages applied to VL5.
Fig. 22 Structure of LCD contrast control register
LCD Drive Timing
The LCD controller/driver supports both type-A and type-B drive
timing.
The desired type is selected by setting the LCD drive timing selec-
tion bit (bit 4 of the LCD mode register).
Voltage applied to VL5
If the LCD drive timing selection bit is set to “0”, type-A is selected,
and if this bit is set to “1”, type-B is selected. After reset, type-A is
selected for the drive timing.
= Voltage applied to the VLCD pin ✕ (n+33)/64
Where:
The frame frequency can be determined by the following equation:
n = Value set to bit 0–bit 4 of the LCD contrast control register (in
decimal values)
LCDCK count source frequency
Frame frequency =
LCDCK division ratio ✕ duty ratio
Variable
resistance
for
brightness
control
Contrast
Contrast
controller
Variable resistance
controller
for
brightness control
V
LCD
V
LCD
“1”
“1”
LCD contrast control enable bit
LCD contrast control enable bit
“0”
“0”
V
V
V
V
V
L5
L4
L3
L2
L1
VL5
VL4
VL3
VL2
VL1
R
R
R
R
R
R
R
R
R
R
V
L3
L2
V
V
L3
L2
Open
V
External
connection
1/5 bias
1/4 bias
Fig. 21 Example of circuit at 1/5 and 1/4 bias
25
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCDCK
1 frame
VL5
VL4
VL3
VL2
VL1
VSS
COM7
VL5
VL4
VL3
VL2
VL1
VSS
COM6
VL5
VL4
VL3
VL2
VL1
VSS
SEG0
VL5
VL4
VL3
VL2
VL1
VSS
VL1
VL2
VL3
VL4
VL5
SEG0 – COM7
ON
OFF
ON
OFF
VL5
VL4
VL3
VL2
VL1
VSS
VL1
VL2
VL3
VL4
VL5
SEG0 – COM6
OFF
OFF
Fig. 23 1/8 duty, 1/5 bias, type-A LCD wave diagram
26
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCDCK
1 frame
1 frame
V
V
V
V
V
V
L5
L4
L3
L2
L1
SS
COM
COM
7
V
V
V
V
V
V
L5
L4
L3
L2
L1
SS
6
V
V
V
V
V
V
L5
L4
L3
L2
L1
SS
SEG
0
V
V
V
V
V
V
V
V
V
V
V
L5
L4
L3
L2
L1
SS
L1
L2
L3
L4
L5
SEG0 – COM7
ON
OFF
ON
OFF
ON
OFF
V
V
V
V
V
V
V
V
V
V
V
L5
L4
L3
L2
L1
SS
L1
L2
L3
L4
L5
SEG0 – COM6
OFF
OFF
OFF
Fig. 24 1/8 duty, 1/5 bias, type-B LCD wave diagram
27
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
KEY-ON WAKE UP
This interrupt is generated by applying “L” level to any pin of port
P2 and the microcomputer is returned to the normal operating
state. If a key matrix is connected to port P20 to P23 as shown in
Figure 25, the microcomputer can be returned to a normal state by
pressing any one of the keys.
The 7510 group contains a key-on wake up interrupt function. The
key-on wake up interrupt function is one way of returning from a
power down state caused by the STP or WIT instruction.
Port P2x (X = 0 to 7)
“L” level output
PULLP2 register
bit 7
Port P2
direction register
bit 7 = “1”
✽
✽
✽
✽
✽
✽
✽
✽
✽ ✽
Key-on wake up input interrupt request
Port P27
latch
P27 output
P26 output
P25 output
PULLP2 register
bit 6
Port P2
direction register
bit 6 = “1”
✽ ✽
Port P26
latch
PULLP2 register
bit 5
Port P2
direction register
bit 5 = “1”
✽ ✽
Port P25
latch
PULLP2 register
bit 4
Port P2
direction register
bit 4 = “1”
✽ ✽
Port P24
latch
P24 output
PULLP2 register
bit 3
Port P2
direction register
bit 3 = “0”
Port P2 input
read circuit
✽ ✽
Port P23
latch
P23 input
PULLP2 register
bit 2
Port P2
direction register
bit 2 = “0”
✽ ✽
Port P22
latch
P22 input
P21 input
P20 input
PULLP2 register
bit 1
Port P2
direction register
bit 1 = “0”
✽ ✽
Port P21
latch
PULLP2 register
bit 0
Port P2
direction register
bit 0 = “0”
✽ ✽
Port P20
latch
✽
P-channel transistor for pull-up
✽ ✽ CMOS output buffer
Fig. 25 Block diagram of port P2, and example of wired at used key-on wake up
28
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at “L” level
for 2 µs or more. Then RESET pin is returned to “H” level (the
power source voltage should be between 2.5 V and 5.5 V, and XIN
oscillation width is stable), reset is released. In order to give the
XIN clock time to stabilize, internal operation does not begin until
after about 8000 XIN clock cycles are complete. After the reset is
completed, the program starts from the address contained in ad-
dress FFFD16 (high-order) and address FFFC16 (low-order).
Make sure that the reset input voltage is less than 0.5 V for VCC of
3.0 V at f(XIN) = 8.0 MHz.
Address
Register contents
(1) Port P0 direction register
(2) Port P1 direction register
(3) Port P2 direction register
(4) Port P3 direction register
(5) Port P4 direction register
(6) Port P5 direction register
(7) Port P0 pull-up control register
(8) Port P1 pull-up control register
(9) Port P2 pull-up control register
(10) Port P3 pull-up control register
(11) Port P4 pull-up control register
(12) Port P5 pull-up control register
(13) Serial I/O1 status register
(14) Serial I/O1 control register
(15) UART1 control register
(16) Timer X (low)
000116
000316
000516
000716
000916
000B16
000C16
000D16
000E16
000F16
001016
001116
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
003116
003216
003316
003716
003916
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
Poweron
3.0V
Power source
voltage 0V
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0016
Reset input
voltage 0V
0.5V
0
0
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
(17) Timer X (high)
V
CC
(18) Timer Y (low)
1
(19) Timer Y (high)
5
4
(20) Timer 1
RESET
(21) Timer 2
M51953AL
(22) Timer 3
0.1µF
(23) Timer X mode register
(24) Timer Y mode register
(25) Timer 123 mode register
(26) Serial I/O2 status register
(27) Serial I/O2 control register
(28) UART2 control register
(29) LCD contrast control register
(30) LCD mode register
3
V
SS
1
1
0
1
0
1
0
0
0
0
0
0
0
0
7510 group
f(XIN) = 8.0MHz
0016
0
0
Fig. 26 Example of reset circuit
0016
0016
0016
(31) Interrupt edge selection register 003A16
(32) CPU mode register
003B16
003C16
003D16
003E16
003F16
(PS)
0
1
0
0
1
1
0
0
(33) Interrupt request register 1
(34) Interrupt request register 2
(35) Interrupt control register 1
(36) Interrupt control register 2
(37) Processor status register
(38) Program counter
0016
0016
0016
0016
✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
Contents of address
FFFD16
(PCH)
(PCL)
Contents of address
FFFC16
Note :The contents of all other registers and RAM are undefined after
reset, so they must be initialized by software.
✕ : Undefined
Fig. 27 Internal status of microcomputer after reset
29
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
φ
RESET
Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Reset address from
vector table
?
?
?
?
AD
L
ADH
Data
SYNC
Notes 1 : f(XIN) and f(φ) are in the relationship : f(XIN) = 8.f(φ)
2 : A question mark (?) indicates an undefined status that depens on the previous status.
about 8000
clock cycles
Fig. 28 Reset sequence
30
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 7510 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
Stop mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level. Timer 1 is set to “FF16” and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1, and the output
of timer 1 is connected to timer 2. The bits of the timer 123 mode
register are cleared to “0” except for bit 4.
The timer 1 and timer 2 interrupt enable bits must be set to dis-
abled (“0”), so a program must set these bits before executing a
STP instruction. Oscillation restarts at reset or when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU until timer 2 underflows. This allows time for the clock circuit
oscillation to stabilize.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O port. The pull-
up resistor of XCIN and XCOUT pins must be made invalid to use
the XCIN oscillating circuit.
Frequency Control
Middle-speed mode
Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. XIN and XCIN are the same state with that before the ex-
ecution of the WIT instruction. The internal clock restarts if a reset
occurs or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
High-speed mode
The internal clock φ is half the frequency of XIN.
Low-speed mode
The internal clock φ is half the frequency of XCIN.
Note: If you switch the mode between middle/high-speed and low-speed,
both of XIN and XCIN oscillation must be stabilized. The sufficient
time is required for the XCIN oscillation to stabilize, especially imme-
diately after power-on and at returning from stop mode. The mode
must be switched on condition that f(XIN) > 3f(XCIN).
Low-power consumption mode
X
CIN
XCOUT
X
IN
XOUT
In low-speed mode, a low-power consumption operation can be
entered by stopping the main clock XIN. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted, the program must allow enough time for oscillation to
stabilize.
R
f
R
d
C
CIN
C
COUT
C
IN
COUT
In low-power consumption mode, the XCIN-XCOUT drive perfor-
mance can be reduced, allowing lower power consumption (8 µA
or less with XCIN = 32 kHz). To reduce the XCIN-XCOUT drive per-
formance, clear bit 3 of the CPU mode register to “0”. At reset or
when the STP instruction is executed, this bit is set to “1” and
strong drive is selected to help the oscillation to start.
Fig. 29 Ceramic resonator circuit
XCIN
XCOUT
XIN
XOUT
Open
Open
External oscillator
External oscillator
or pulse
2.5V
V
CC
SS
VSS
V
Fig. 30 External clock input circuit
31
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
“1”
“0”
Port XC selection bit
1/32
Timer 1 count
source selection
bit
“1”
Timer 2 count
source selection
bit
Internal system clock selection bit
XIN
XOUT
(Note 1)
Low-speed mode
“0”
Timer 1
1/2
Middle/High-speed mode
1/4
1/2
Timer 2
“0”
“1”
Main clock division ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
S
Q
Q
S
R
WIT
R
STP instruction
STP instruction
instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port XC selection bit to “1”.
Fig. 31 System clock generating circuit block diagram
32
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (φ =1MHz)
High-speed mode (φ = 4.0MHz)
CM
“1”
6
6
6
CM
CM
CM
CM
7
6
5
4
= 0 (8.0MHz selected)
= 1 (Middle-speed)
= 0 (XIN oscillating)
= 0 (32kHz stopped)
CM
CM
CM
CM
7
6
5
4
= 0 (8.0MHz selected)
= 0 (High-speed)
= 0 (XIN oscillating)
“0”
= 0 (32kHz stopped)
CM
“1”
4
6
CM
4
6
“0”
“0”
“0”
“1”
“0”
CM
“1”
CM
“1”
Middle-speed mode (φ =1MHz)
High-speed mode (φ = 4.0MHz)
CM
“1”
CM
CM
CM
CM
7
6
5
4
= 0 (8.0MHz selected)
= 1 (Middle-speed)
= 0 (XIN oscillating)
= 1 (32kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 0 (8.0MHz selected)
= 0 (High-speed)
= 0 (XIN oscillating)
= 1 (32kHz oscillating)
“0”
Low-speed mode (φ =16kHz)
Low-speed mode (φ = 16kHz)
CM
“1”
CM
CM
CM
CM
7
6
5
4
= 1 (32kHz selected)
= 1 (Middle-speed)
= 0 (XIN oscillating)
= 1 (32kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 1 (32kHz selected)
= 0 (High-speed)
= 0 (XIN oscillating)
“0”
b7
b0
CPU mode register
= 1 (32kHz oscillating)
(CPUM : address 003B16
)
CM
0 : I/O port
1 : XCIN, XCOUT
CM : Main clock (XIN-XOUT) stop bit
0 : Operating
1 : Stopped
4 : Port XC selection bit
CM
“1”
5
6
CM
5
6
“0”
“0”
“0”
“1”
“0”
5
CM
“1”
CM
“1”
CM6 : Main clock division ratio selection bit
0 : XIN/2 (high-speed mode)
1 : XIN/8 (middle-speed mode)
Low power consumption mode (φ =16kHz)
Low power consumption mode (φ =16kHz)
CM
6
CM
CM
CM
CM
7
6
5
4
= 1 (32kHz selected)
= 1 (Middle-speed)
= 1 (XIN stopped)
CM
CM
CM
CM
7
6
5
4
= 1 (32kHz selected)
= 0 (High-speed)
= 1 (XIN stopped)
= 1 (32kHz oscillating)
CM7 : Internal system clock selection bit
“1”
“0”
0 : XIN-XOUT selected
(middle/high-speed mode)
1 : XCIN-XCOUT selected
(low-speed mode)
= 1 (32kHz oscillating)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The main clock must be oscillated (CM : 1→0) before the switching from the low-speed mode to middle/high-speed mode (CM 7 : 1→0).
5
3 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode
is ended.
Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 2ms is automatically generated by timer 1 and timer 2 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25s is automatically generated by timer 1 and timer 2 in low-speed mode.
6 : The example assumes that 8.0MHz is being applied to the XIN pin and 32kHz to the XCIN pin φ indicates the internal clock.
Fig. 32 State transitions of system clock
33
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal operation mode (D) flag because of their effect on calcu-
lations.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The contents of the interrupt request bits do not change immedi-
ately after they have been written.
After writing to an interrupt request register, execute at least one
instruction before performing a BBC or BBS instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
In high-speed mode, the frequency of the internal clock φ is half of
the XIN frequency.
Decimal Calculations
To calculate in decimal notation, set the decimal operation mode
flag (D) to “1”, then execute the ADC or the SBC instruction. Only
the ADC and the SBC instruction yield proper decimal results. Af-
ter executing the ADC or SBC instruction, execute at least one
instruction before executing the SEC, the CLC, or the CLD instruc-
tion.
In middle-speed mode, the frequency of the internal clock φ is one
eighth the XIN frequency.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flag are invalid. The carry flag can be used to indicate
whether a carry or borrow has occurred.
3. Data to be written to ROM, in EPROM form (three identical
copies)
Initialize the carry flag before each calculation. Clear the carry flag
before the ADC instruction and set the flag before the SBC in-
struction.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flag do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
●the data transfer instruction (LDA, etc.)
●the operation instruction when the index X mode flag (T) is “1”
●the addressing mode which uses the value of a direction register
as an index
●the bit-test instruction (BBC or BBS, etc.) to a direction register
●the read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
34
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROM Programming Method
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter.
Set the address of PROM programmer in the user ROM area.
Package
Name of Programming Adapter
PCA4738F-176A
176P6D-A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 33 is recommended to verify programming.
Programming with PROM Programmer
Screening (Caution)
(150°C for 40 hours)
Verification with PROM Programmer
Functional check in target device
Caution : The screening temperature is far higher than
the storage temperature. Never expose to
150°C exceeding 100 hours.
Fig. 33 Programming and testing of One Time PROM version
35
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power source voltage
Conditions
Retings
Unit
V
VCC
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51
Input voltage P40
VI
–0.3 to VCC+0.3
V
VI
VI
VI
–0.3 to 13
V
V
V
Input voltage VLCD
All voltage are based on VSS.
Output transistors are cut off.
–0.3 to VCC+0.3
–0.3 to VCC+0.3
Input voltage RESET, XIN, XCIN
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51, XOUT
Output voltage SEG0–SEG79, COM0–COM15
Output voltage XCOUT
VO
–0.3 to VCC+0.3
V
VO
VO
Pd
–0.3 to VLCD
–0.3 to VCC
300
V
V
Power dissipation
mW
°C
°C
Ta = 25°C
Topr
Tstg
Operating temperature
–20 to 85
–40 to 125
Storage temperature
RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
4.0
3.0
2.5
Typ.
5.0
5.0
5.0
Max.
5.5
High-speed mode f(φ) ≥ 2.5 MHz
V
V
5.5
VCC
Power source voltage
Middle-speed mode 1.0 MHz ≤ f(φ) < 2.5 MHz
Low-speed mode f(φ) ≤ 650 kHz
5.5
V
VCC
VLCD
Power source voltage for LCD driver
Power source voltage
V
0
VSS
V
0.8VCC
0.8VCC
VCC
VCC
2.5
VIH
“H” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50, P51
“H” input voltage RESET, XIN
V
VIH
V
VIH
“H” input voltage XCIN
V
0
0
0
VIL
“L” input voltage P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50, P51
“L” input voltage RESET, XIN
V
0.2VCC
VIL
V
0.2VCC
0.4
VIL
“L” input voltage XCIN
V
–80
80
ΣIOH(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOL(avg)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
f(CNTR0)
f(CNTR1)
f(XIN)
“H” total peak output current (Note 1) P0
“L” total peak output current P0 –P0 , P1
“H” total average output current P0 –P0 , P1
“L” total average output current P0 , P1
“H” peak output current (Note 2) P0 , P1
“L” peak output current P0 –P0 , P1 , P2
“H” average output current (Note 3) P0 , P1
“L” average output current P0 –P0 , P1 –P1 , P2
0
–P0
–P1
–P1
–P1
–P1
–P2
–P1
–P2
7
, P1
, P2
, P2
, P2
, P2
, P3
, P2
, P3
0
–P1
–P2
–P2
–P2
–P2
–P3
–P2
–P3
7
, P2
, P3
, P3
, P3
, P3
, P4
, P3
, P4
0
–P2
–P3
–P3
–P3
–P3
–P4
–P3
–P4
7
, P3
, P4
, P4
, P4
, P4
, P5
, P4
, P5
0
–P3
–P4
–P4
–P4
–P4
, P5
–P4
, P5
7
, P4
, P5
, P5
1
–P4
7
, P5
, P5
, P5
0
, P5
1
mA
mA
mA
mA
mA
mA
mA
mA
0
7
0
7
0
7
0
7
1
7
0
1
–40
40
0
7
0
7
0
7
0
7
1
7
0
1
0
–P0
7
0
7
0
7
0
7
1
7
, P5
0
, P5
1
–10
10
0
–P0
7
0
7
0
7
0
7
1
7
, P50, P51
0
7
0
–P1
7
0
7
0
7
1
7
0
1
–5
0
–P0
7
0
7
0
7
0
7
1
7, P50, P51
5
0
7
0
7
0
7
0
7
1
7
0
1
2.6
Timer X, Timer Y input frequency (at 50% duty)
MHz
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
MHz
kHz
8.0
50
f(XCIN)
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: The oscillating frequency has a 50% duty cycle.
5: In low-speed mode, the sub-clock input oscillation frequency must be used on condition that f(XCIN) < f(XIN)/3.
36
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
VOH
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Max.
2.0
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51
VCC–2.0
“L” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51
VOL
IOL = 10 mA
V
0.4
0.5
0.5
VT+–VT–
VT+–VT–
VT+–VT–
Hysteresis INT0, INT1, CNTR0, CNTR1
Hysteresis SCLK1, SCLK2, RXD1, RXD2
Hysteresis RESET
V
V
V
“H” input current P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51
5.0
5.0
IIH
µA
IIH
IIH
IIH
“H” input current RESET, P40
VI = VCC
µA
µA
µA
4.0
2.0
“H” input current XIN
VI = VCC
“H” input current XCIN
VI = 2.5 V
VI = 0 V
–5.0
µA
µA
µA
Pull-ups “off”
VCC = 5 V, VI = 0 V
Pull-ups “on”
VCC = 3 V, VI = 0 V
Pull-ups “on”
VI = VSS
“L” input current P00–P07, P10–P17, P20–P27,
P30–P37, P41–P47, P50, P51
–30
–6
–70
–25
–140
IIL
–45
IIL
“L” input current RESET, P40
µA
µA
µA
V
–5.0
IIL
“L” input current XIN
VI = VSS
–4.0
–2.0
IIL
“L” input current XCIN
VI = VSS
VRAM
Rbias
RCOM5
RCOM4
RCOM1
RCOM0
RSEG5
RSEG3
RSEG2
RSEG0
RAM hold voltage
With clock stopped
2.0
5.5
LCD bias resistance (Note)
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
mA
mA
3
COM on-resistance with VL5 output from COM
COM on-resistance with VL4 output from COM
COM on-resistance with VL1 output from COM
COM on-resistance with VL0 output from COM
SEG on-resistance with VL5 output from SEG
SEG on-resistance with VL3 output from SEG
SEG on-resistance with VL2 output from SEG
SEG on-resistance with VL0 output from SEG
IO = –0.1 mA
IO = ±0.1 mA
IO = ±0.1 mA
IO = 0.1 mA
IO = –0.1 mA
IO = ±0.1 mA
IO = ±0.1 mA
IO = 0.1 mA
0.5
4.5
4.5
0.5
0.5
6.5
6.5
0.5
13
In high-speed mode, VCC = 5 V
f(XIN) = 8.0 MHz
f(XIN) = 5.0 MHz
6.4
4.0
Output transistors are isolated.
In low-speed mode, VCC = 3 V
f(XIN) = stopped
8.0
µA
µA
f(XCIN) = 32 kHz
20
Low-power consumption mode
Output transistors are isolated.
In low-speed mode, VCC = 3 V
f(XIN) = stopped
ICC
Power source current
f(XCIN) = 32 kHz (in wait mode)
Low-power consumption mode
Output transistors are isolated.
All oscillation are stopped.
(in stop mode)
4.5
0.1
9.0
µA
µA
Ta = 25°C
Ta = 85°C
1.0
10
Output transistors are isolated.
Note: This is the value of bias resistance for one stage.
37
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD CONTRAST CONTROLLER CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
5
–
–
–
Resolution
Accuracy
Iinearity
Bits
%
2.0
LSB
V
±0.5
VLCD
VCCH
Maximum output voltage (Note)
VCC = 5.0 V, VLCD = VCC
4.9
Note: When the value in the LCD contrast control register (address 003716) is “9F16”.
38
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External clock input cycle time
125
50
twH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
twL(XIN)
50
tc(CNTR)
200
80
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input “H” pulse width
INT0, INT1 input “H” pulse width
80
twL(CNTR)
twL(INT)
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “L” pulse width
80
80
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
800
800
370
370
370
370
220
220
100
100
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD1–SCLK1)
tsu(RXD2–SCLK2)
th(SCLK1–RXD1)
th(SCLK2–RXD2)
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Note: When f(φ) = 4 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 4 MHz and bit 6 of address
001A16 or 003216 is “0” (clock asynchronous).
TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External clock input cycle time
500
200
200
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
200
twH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input “H” pulse width
INT0, INT1 input “H” pulse width
twL(CNTR)
twL(INT)
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “L” pulse width
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O1 input set up time
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD1–SCLK1)
tsu(RXD2–SCLK2)
th(SCLK1–RXD1)
th(SCLK2–RXD2)
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
Note: When f(φ) = 1 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 1 MHz and bit 6 of address
001A16 or 003216 is “0” (clock asynchronous).
39
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
/2–30
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1–TXD1)
td(SCLK2–TXD2)
tv(SCLK1–TXD1)
tv(SCLK2–TXD2)
tr(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 1)
Serial I/O1 clock output rise time
Serial I/O1 clock output fall time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(SCLK1)
tc(SCLK2)
tc(SCLK1)
tc(SCLK2)
/2–30
/2–30
/2–30
140
140
–30
–30
CL = 100 pF
30
30
30
30
30
30
tf(SCLK1)
tr(SCLK2)
Serial I/O2 clock output rise time
Serial I/O2 clock output fall time
tf(SCLK2)
tr(CMOS)
CMOS output rise time (Note 2)
10
10
tf(CMOS)
CMOS output fall time (Note 2)
Notes 1: When bit 4 of the UART control register (address 001B16 or 003316) is “0”.
2: XOUT pin is excluded.
1kΩ
Measurement output pin
Measurement output pin
100pF
100pF
CMOS output
N-channel open-drain output
Fig. 34 Circuit for measuring output switching characteristics (1)
Fig. 35 Circuit for measuring output switching characteristics (2)
Note: When bit 4 of the UART contronl register (address 001B16 or 003316)
is “1” (N-channel open-drain output), and bit 7 of the serial I/O con-
trol register (address 001A16 or 003216) is “1”.
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
/2–50
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1–TXD1)
td(SCLK2–TXD2)
tv(SCLK1–TXD1)
tv(SCLK2–TXD2)
tr(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 1)
Serial I/O1 clock output rise time
Serial I/O1 clock output fall time
tc(SCLK1)
tc(SCLK2)
tc(SCLK1)
tc(SCLK2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/2–50
/2–50
/2–50
350
350
–30
–30
CL = 100 pF
50
50
50
50
50
50
tf(SCLK1)
tr(SCLK2)
Serial I/O2 clock output rise time
Serial I/O2 clock output fall time
tf(SCLK2)
tr(CMOS)
CMOS output rise time (Note 2)
20
20
tf(CMOS)
CMOS output fall time (Note 2)
Notes 1: When bit 4 of the UART control register (address 001B16 or 003316) is “0”.
2: XOUT pin excluded.
40
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tc(CNTR)
twH(CNTR)
twL(CNTR)
0.8VCC
CNTR0, CNTR1
0.2VCC
twH(INT)
twL(INT)
0.8VCC
INT0, INT1
0.2VCC
tw(RESET)
0.8VCC
RESET
0.2VCC
tc(XIN)
twH(XIN)
twL(XIN)
0.8VCC
XIN
0.2VCC
tc(SCLK1), tc(SCLK2)
tf
tr
twL(SCLK1), twL(SCLK2)
twH(SCLK1), twH(SCLK2)
SCLK1
SCLK2
0.8VCC
0.2VCC
tsu(RXD1 – SCLK1)
tsu(RXD2 – SCLK2)
th(SCLK1 – RXD1), th(SCLK2 – RXD2)
RXD1
RXD2
0.8VCC
0.2VCC
tv(SCLK1 – TXD1),
tv(SCLK2 – TXD2)
td(SCLK1 – TXD1), td(SCLK2 – TXD2)
TXD1
TXD2
41
REVISION DESCRIPTION LIST
7510 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980110
(1/1)
MITSUBISHI MICROCOMPUTERS
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 1998.
Specifications subject to change without notice.
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