M37542M2V-XXXGP [MITSUBISHI]
Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32;
| 型号： | M37542M2V-XXXGP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 微控制器 |
| 文件： | 总68页 (文件大小：1191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
APPLICATION
Office automation equipment, factory automation equipment,
DESCRIPTION
The 7542 Group is the 8-bit microcomputer based on the 740 fam-
home electric appliances, consumer electronics, car, etc.
ily core technology.
The 7542 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A-D converter, and is useful for control of home electric appli-
ances and office automation equipment.
FEATURES
• Basic machine-language instructions ...................................... 71
•
The minimum instruction execution time .. 0.25 µs (Target Spec.)
(at 8 MHz oscillation frequency, double-speed mode for the
shortest instruction)
• Memory size ROM............................................ 8 K to 32 K bytes
RAM ........................................... 384 to 1024 bytes
• Programmable I/O ports ....................... 29 (25 in 32-pin version)
• Interrupts ................................................. 18 sources, 16 vectors
• Timers ............................................................................. 8-bit ✕ 2
...................................................................................... 16-bit ✕ 2
• Output compare............................................................ 4-channel
• Input capture ................................................................ 2-channel
• Serial I/O...................... 8-bit ✕ 2 (UART or Clock-synchronized)
• A-D converter ............................................... 10-bit ✕ 8 channels
.................................................... (6 channels for 32-pin version)
• Clock generating circuit............................................. Built-in type
(low-power dissipation by a ring oscillator)
(connected to external ceramic resonator or quartz-crystal
oscillator permitting RC oscillation)
• Watchdog timer ............................................................ 16-bit ✕ 1
• Power source voltage
X
IN oscillation frequency at ceramic oscillation, in double-speed mode
At 8 MHz ................................................................................TBD
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
At 4 MHz .................................................................... 2.4 to 5.5 V
At 2 MHz .................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz .................................................................... 4.0 to 5.5 V
At 2 MHz .................................................................... 2.4 to 5.5 V
At 1 MHz .................................................................... 2.2 to 5.5 V
• Power dissipation ..................................................................TBD
• Operating temperature range................................... –20 to 85 °C
(–40 to 85 °C for extended operating temperature version)
(–40 to 125 °C for extended operating temperature 125 °C ver-
sion (Note))
Note: In this version, the operating temperature range and total time are
limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
23 22
24
21 20 19 18 17
P07(LED07)/SRDY2
P10/RXD1/CAP0
P11/TXD1
16
25
26
27
28
29
30
31
32
P34(LED14)
P33(LED13)/INT1
P32(LED12)/CMP3
P31(LED11)/CMP2
P30(LED10)/CAP1
VSS
XOUT
XIN
15
14
13
P12/SCLK1
P13/SRDY1
P14/CNTR0
P20/AN0
M37542M4-XXXGP
12
11
10
9
P21/AN1
1
2
3
4
5
6
7
8
Package type: 32P6U-A
Fig. 1 Pin configuration (32P6U-A type)
P1
2
/SCLK1
1
2
3
4
5
6
7
36
P1
1
/T
/R
X
D
D
1
P13
/SRDY1
35
P1
P0
P0
P0
P0
P0
0
7
6
X
1
/CAP
0
P1
4
/CNTR
0
0
1
2
3
34
33
32
31
(LED07)/SRDY2
(LED06)/SCLK
(LED05)/TxD
(LED04)/RxD
(LED03)/TXOUT
P2
P2
P2
P2
0
1
2
3
/AN
/AN
/AN
/AN
2
5
4
3
2
2
30
29
8
P0
2
(LED02)/CMP
1
P2
4
/AN
4
28
27
26
25
9
P0
P0
1
0
(LED01)/CMP
0
P2
P2
5
6
/AN
/AN
5
6
(LED00)/CAP
0
10
11
12
13
14
15
P3
P3
P3
P3
P3
P3
P3
P3
7
(LED17)/INT
0
P27
/AN
REF
7
V
6
(LED16)/INT
1
24
23
RESET
CNVSS
Vcc
5
4
3
2
1
(LED15
)
)
(LED14
22
21
20
19
(LED13)/INT
1
16
17
18
X
IN
OUT
SS
(LED12)/CMP
(LED11)/CMP
3
2
X
V
0
(LED10)/CAP
1
Package type: 36P2R-A
Fig. 2 Pin configuration (36P2R-A type)
2
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P1
P1
P1 /CNTR
2
/SCLK1
32
1
P1
1
/T
X
D
1
3
/SRDY1
31
30
2
3
4
P1
P0
0
7
/R
XD1/CAP0
4
0
(LED07)/SRDY2
29
28
P2
0
1
2
/AN
0
1
2
P0
P0
P0
P0
6
(LED06)/SCLK
(LED05)/TxD
(LED04)/RxD
(LED03)/TXOUT
2
5
P2
P2
P2
P2
/AN
/AN
/AN
/AN
5
2
6
7
8
27
26
25
4
2
3
4
3
4
3
P0
P0
P0
2
(LED02)/CMP
(LED01)/CMP
1
24
23
9
P2
5
/AN
5
1
0
0
VREF
10
(LED00)/CAP
0
11
12
22
21
P3
7
(LED17)/INT
0
RESET
CNVSS
P34
(LED14
)
13
20
19
18
V
CC
IN
OUT
P33
(LED13)/INT
(LED12)/CMP
1
X
14
P3
P3
P3
2
3
2
15
X
1
0
(LED11)/CMP
16
17
V
SS
(LED10)/CAP
1
Package type: 32P4B
Fig. 3 Pin configuration (32P4B-A type)
P1
4
/CNTR
0
1
2
42
P1
3
/SRDY1
/SCLK1
/T
/R
41
40
NC
NC
P1
P1
P1
2
1
0
3
4
X
D
D
1
P2
P2
0
/AN
0
39
38
X
1
/CAP
0
1
/AN
1
5
P07
(LED07)/SRDY2
(LED06)/SCLK2
37
NC
6
P06
7
36
35
P0
5
(LED05)/TxD
(LED04)/RxD
(LED03)/TXOUT
2
P2
2
/AN
2
3
8
P04
2
P23
/AN
9
34
33
32
31
P0
P0
P0
3
P2
P2
P2
4
/AN
/AN
/AN
4
10
11
5
5
2
(LED02)/CMP
1
1
(LED01)/CMP
0
6
7
6
7
P0
0
(LED00)/CAP
0
12
13
14
15
16
17
18
19
P2
/AN
30
29
NC
NC
NC
REF
P3
P3
P3
P3
P3
P3
7
(LED17)/INT
(LED16)/INT
0
1
28
27
26
25
V
6
5
4
3
2
RESET
CNVSS
Vcc
(LED15
(LED14
)
)
(LED13)/INT
1
24
23
(LED12)/CMP
3
2
X
IN
OUT
SS
X
20
21
P3
P3
1
(LED11)/CMP
22
0
(LED10)/CAP
1
V
Outline 42S1M
Fig. 4 Pin configuration (42S1M type)
3
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
K e y - o n w a k e u p
Fig. 5 Functional block diagram (32P6U package)
4
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
K e y - o n w a k e u p
Fig. 6 Functional block diagram (36P2R package)
5
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
K e y - o n w a k e u p
Fig. 7 Functional block diagram (32P4B package)
6
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
Name
Function
Function expect a port function
Power source
(Note 1)
•Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
VREF
Analog refer- •Reference voltage input pin for A-D converter.
ence voltage
CNVss
RESET
XIN
CNVss
•Chip operating mode control pin, which is always connected to Vss.
Reset input
Clock input
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit.
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•
XOUT
Clock output
•
When the ring oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open.
• Key-input
(key-on
•8-bit I/O port.
P00(LED00)/CAP0 I/O port P0
P01(LED01)/CMP0
P02(LED02)/CMP1
P03(LED03)/TXOUT
P04(LED04)/RxD2
• Capture function pin
• Compare function pin
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
wake up
interrupt
input) pin
• Timer X function pin
• Serial I/O2 function pin
P05(LED05)/TxD2
P06(LED06)/SCLK2
P07(LED07)/SRDY2
•
High drive capacity for LED drive port can be selected by program.
•5-bit I/O port
P10/RxD1/CAP0
I/O port P1
• Serial I/O1 function pin
• Capture function pin
• Serial I/O1 function pin
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
P11/TxD1
•CMOS compatible input level
P12/SCLK1
P13/SRDY1
P14/CNTR0
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12 and P13
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
• Timer X function pin
P20/AN0–P27/AN7 I/O port P2
• Input pins for A-D converter
(Note 2)
•CMOS 3-state output structure
•8-bit I/O port
P30(LED10)/CAP1 I/O port P3
P31(LED11)/CMP2 (Note 3)
P32(LED12)/CMP3
P33(LED13)/INT1
• Capture function pin
• Compare function pin
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be
switched for P36 and P37).
• Interrupt input pin
• Interrupt input pin
P34(LED14)
•CMOS 3-state output structure
P35(LED15)
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
P36(LED16)/INT1
P37(LED17)/INT0
•
High drive capacity for LED drive port can be selected by program.
Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port.
3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.
7
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Memory size
Mitsubishi plans to expand the 7542 group as follow:
Flash memory size ......................................................... 32 K bytes
Mask ROM size ................................................... 8 K to 16 K bytes
RAM size ............................................................ 384 to 1024 bytes
Memory type
Support for Mask ROM version, Flash memory version, and Emu-
lator MCU .
Package
32P4B .................................................. 32-pin plastic molded SDIP
32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP
36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP
42S1M....................................42-pin shrink ceramic PIGGY BACK
ROM size
(bytes)
M37542F8V **
M37542F8T **
32K
**
M37542F8
**
M37542M4V
**
**
16K
M37542M4T
M37542M4
M37542M2V **
**
**
8K
M37542M2T
M37542M2
RAM size
(bytes)
0
384
512
1024
**: Under development
Note: Products under development•••the development schedule and
specification may be revised without notice.
Fig. 8 Memory expansion plan
8
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Currently supported products are listed below.
Table 2 List of supported products
ROM size (bytes)
Product
RAM size
(bytes)
384
Package
Remarks
ROM size for User ()
32P4B
Mask ROM version
M37542M2-XXXSP
M37542M2-XXXFP
M37542M2T-XXXFP
M37542M2V-XXXFP
M37542M2-XXXGP
M37542M2T-XXXGP
M37542M2V-XXXGP
M37542M4-XXXSP
M37542M4-XXXFP
M37542M4T-XXXFP
M37542M4V-XXXFP
M37542M4-XXXGP
M37542M4T-XXXGP
M37542M4V-XXXGP
M37542F8SP
8192
36P2R-A
Mask ROM version
(8062)
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
32P6U-A
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
32P4B
16384
512
1024
1024
36P2R-A
Mask ROM version
(16254)
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
32P6U-A
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Flash memory version
32P4B
32768
36P2R-A
Flash memory version
M37542F8FP
(32638)
Flash memory version (extended operating temperature version)
Flash memory version (extended operating temperature 125 °C version)
Flash memory version
M37542F8TFP
M37542F8VFP
32P6U-A
42S1M
M37542F8GP
Flash memory version (extended operating temperature version)
Flash memory version (extended operating temperature 125 °C version)
Emulator MCU
M37542F8TGP
M37542F8VGP
M37542RSS
9
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Stack pointer (S)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing reg-
ister contents onto the stack and popping them from the stack are
shown in Fig. 9.
This instruction cannot be used while CPU operates by a ring os-
cillator.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Program counter (PC)
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
b7
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0
A
X
Accumulator
Index Register X
Y
Index Register Y
S
Stack Pointer
b15
PC
H
PC
L
Program Counter
Processor Status Register (PS)
N V T B D I Z C
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 9 740 Family CPU register structure
10
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S – 1)
Store Return Address
on Stack
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
Subroutine
M (S) (PCL)
(S) (S – 1)
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
M (S) (PS)
(S) (S – 1)
Interrupt
Service Routine
I Flag “0” to “1”
Execute RTS
(S) (S + 1)
Fetch the Jump Vector
Execute RTI
(S) (S + 1)
Restore Return
Address
Restore Contents of
Processor Status Register
(PCL) M (S)
(S) (S + 1)
(PCH) M (S)
(PS)
M (S)
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
Restore Return
Address
(PCH) M (S)
Note : The condition to enable the interrupt
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
11
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Processor status register (PS)
(5) Break flag (B)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data trans-
fers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory lo-
cation 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal ad-
dressing modes.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(7) Overflow flag (V)
(3) Interrupt disable flag (I)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location oper-
ated on by the BIT instruction is stored in the overflow flag.
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 4 Set and clear instructions of each bit of processor status register
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
N flag
Set instruction
–
–
–
–
–
–
Clear instruction
CLI
CLV
12
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit, etc..
This register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016
)
Processor mode bits (Note 1)
b1 b0
Switching method of CPU mode register
0
0
1
1
0
1
0
1
Single-chip mode
Switch the CPU mode register (CPUM) at the head of program af-
ter releasing Reset in the following method.
Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Ring oscillator oscillation control bit
0
1
: Ring oscillator oscillation enabled
: Ring oscillator oscillation stop
X
IN oscillation control bit
0
1
: Ceramic or RC oscillation enabled
: Ceramic or RC oscillation stop
Oscillation mode selection bit (Note 1)
0
1
: Ceramic oscillation
: RC oscillation
Clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
:
:
:
:
f(φ) = f(XIN)/2 (High-speed mode)
f(φ) = f(XIN)/8 (Middle-speed mode)
applied from ring oscillator
f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37542RSS”.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 11 Structure of CPU mode register
After releasing reset
Start with a built-in ring oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
Switch the oscillation mode
selection bit (bit 5 of CPUM)
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from a ring oscillator meets the requirement).
Wait by ring oscillator operation until
establishment of oscillator clock
Select 1/1, 1/2, 1/8 or ring oscillator.
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Fig. 12 Switching method of CPU mode register
13
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Zero page
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
Special page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
000016
SFR area
Zero page
004016
010016
RAM
RAM area
RAM capacity
(bytes)
address
XXXX16
XXXX16
384
512
1024
01BF16
023F16
043F16
Reserved area
044016
Not used
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
FF0016
ROM
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
Special page
FFDC16
8192
16384
32768
E00016
C00016
800016
E08016
C08016
808016
Interrupt vector area
FFFE16
Reserved ROM area
FFFF16
Fig. 13 Memory map diagram
14
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Capture mode register (CAPM)
Port P0 (P0)
000016
000116
000216
002016
002116
002216
Port P0 direction register (P0D)
Port P1 (P1)
Compare output mode register (CMOM)
Capture/compare status register (CCSR)
Compare interrupt source set register (CISR)
Timer A (low-order) (TAL)
Port P1 direction register (P1D)
000316
000416
000516
002316
002416
002516
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer A (high-order) (TAH)
000616
000716
000816
002616 Timer B (low-order) (TBL)
Port P3 direction register (P3D)
Reserved
Timer B (high-order) (TBH)
Prescaler 1 (PRE1)
002716
002816
002916
Timer 1 (T1)
000916 Reserved
Timer count source set register (TCSS)
Timer X mode register (TXM)
000A16
000B16
000C16
000D16
002A16
002B16
002C16
002D16
Interrupt source set register (INTSET)
Interrupt source discrimination register (INTDIS)
Capture register 0 (low-order) (CAP0L)
Prescaler X (PREX)
Timer X (TX)
Capture register 0 (high-order) (CAP0H)
Transmit 2 / Receive 2 buffer register (TB2/RB2)
Serial I/O2 status register (SIO2STS)
000E16
000F16
001016
001116
002E16
002F16
003016
003116
Capture register 1 (low-order) (CAP1L)
Capture register 1 (high-order) (CAP1H)
Compare register (low-order) (CMPL)
Compare register (high-order) (CMPH)
Serial I/O2 control register (SIO2CON)
UART2 control register (UART2CON)
Baud rate generator 2 (BRG2)
Reserved
001216 Capture/compare register R/W pointer (CCRP)
001316 Capture software trigger register (CSTR)
003216
003316
003416
003516
Compare register re-load register (CMPR)
001416
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
A-D conversion register (high-order) (ADH)
Port P0P3 drive capacity control register (DCCR)
001516
Pull-up control register (PULL)
001616
001716
001816
001916
003616
003716
003816
003916
Ring oscillation division ratio selection register (RODR)
MISRG
Port P1P3 control register (P1P3C)
Transmit 1 /Receive 1 buffer register (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
001A16
001B16
001C16
003A16
003B16
003C16
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Timer A, B mode register (TABM)
001D16
003D16
003E16
003F16
001E16 Capture/compare port register (CCPR)
001F16
Interrupt control register 2 (ICON2)
Timer source selection register (TMSR)
Note : Do not access to the SFR area including nothing.
Fig. 14 Memory map of special function register (SFR)
15
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD
b7
b0
Port P0P3 drive capacity control register
(DCCR: address 001516, initial value: 0016
)
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an in-
put port.
Port P0 drive capacity bit
0
Ports P0
Ports P0
1
, P0
2
drive capacity bit
drive capacity bit
3–P0
7
Port P3
Ports P31, P3
Port P3 drive capacity bit
0
drive capacity bit
2
drive capacity bit
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
3
Ports P3
Ports P3
4
, P3
5
7
drive capacity bit
drive capacity bit
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
6, P3
0 : Low
1 : High
Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin version.
Accordingly, the following settings are required;
• Select P33 for the INT1 function.
Note: Number of LED drive port (drive capacity is HIGH) is 8-port.
Fig. 15 Structure of port P0P3 drive capacity control register
• Set direction registers of ports P26 and P27 to output.
• Set direction registers of ports P35 and P36 to output.
b7
b0
Pull-up control register
(PULL: address 001616, initial value: 0016
)
[Port P0P3 drive capacity control register] DCCR
By setting the Port P0P3 drive capacity control register (address
001516), the drive capacity of the N-channel output transistor for
the port P0 and port P3 can be selected.
P0
P0
P0
P3
P3
P3
P3
P3
0
1
3
0
1
3
4
6
pull-up control bit
, P0
2
7
pull-up control bit
pull-up control bit
–P0
pull-up control bit
, P3 pull-up control bit
pull-up control bit
[Pull-up control register] PULL
2
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
0 : Pull-up Off
1 : Pull-up On
, P3
, P3
5
7
pull-up control bit
pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P13, P36, and P37 by program.
Fig. 16 Structure of pull-up control register
b7
b0
Port P1P3 control register
(P1P3C: address 0017 16, initial value: 0016)
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P36/INT1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
Note: Keep setting the P36/INT1 input level selection bit
to “0” (initial value) for 32-pin version.
Fig. 17 Structure of port P1P3 control register
16
MITSUBISHI MICROCOMPUTERS
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Table 5 I/O port function table
Pin
Name
I/O format
Non-port function
SFRs related each pin
Diagram
No.
P00(LED00)/CAP0
I/O port P0 •CMOS compatible
input level (Note 1)
• Capture function input
• Key input interrupt
Capture/Compare port register
Interrupt edge selection register
Pull-up control register
(1)
•CMOS 3-state output
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
P01(LED01)/CMP0
P02(LED02)/CMP1
• Compare function output
• Key input interrupt
(2)
(3)
(4)
Port P0P3 drive capacity control register
Timer X mode register
P03(LED03)/TXOUT
P04(LED04)/RxD2
• Timer X function output
• Key input interrupt
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
• Serial I/O2 function input/output
• Key input interrupt
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
P05(LED05)/TxD2
P06(LED06)/SCLK2
(5)
(6)
Port P0P3 drive capacity control register
Serial I/O2 control register
Interrupt edge selection register
Pull-up control register
Port P0P3 drive capacity control register
Serial I/O2 control register
Pull-up control register
P07(LED07)/SRDY2
P10/RxD1/CAP0
(7)
(8)
Port P0P3 drive capacity control register
Serial I/O1 control register
Capture/Compare port register
Port P1P3 control register
Serial I/O1 control register
Serial I/O1 control register
Port P1P3 control register
Serial I/O1 control register
Port P1P3 control register
Timer X mode register
I/O port P1
• Serial I/O1 function input
• Capture function input
P11/TxD1
• Serial I/O1 function input/output
(9)
P12/SCLK1
(10)
P13/SRDY1
P14/CNTR0
(11)
(12)
(13)
(14)
• Timer X function input/output
• External interrupt input
• A-D conversion input
P20/AN0–P27/AN7 I/O port P2
A-D control register
(Note 2)
P30(LED10)/CAP1
I/O port P3
• Capture function input
• Compare function output
• External interrupt input
Capture/Compare port register
Pull-up control register
(Note 3)
Port P0P3 drive capacity control register
Capture/Compare port register
Pull-up control register
P31(LED11)/CMP2
P32(LED12)/CMP3
(15)
(16)
(17)
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
P33(LED13)/INT1
Port P0P3 drive capacity control register
Pull-up control register
P34(LED14)
P35(LED15)
Port P0P3 drive capacity control register
Interrupt edge selection register
Pull-up control register
P36(LED16)/INT1
P37(LED17)/INT0
• External interrupt input
(18)
(19)
Port P0P3 drive capacity control register
Port P1P3 control register
Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version.
3: P35 and P36/INT1 do not exist for the 32-pin version.
17
MITSUBISHI MICROCOMPUTERS
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(1) Port P0
0
(2) Ports P01, P0
2
Pull-up control
Pull-up control
Compare output control
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Drive capacity
control
Drive capacity
control
Capture 0 input
Capture 0 input control
Compare output
To key input interrupt
generating circuit
To key input interrupt
generating circuit
P0
0
key-on wakeup
selection bit
(3) Port P0
3
(4) Port P0
4
Pull-up control
Pull-up control
Serial I/O2 enable bit
P03/TXOUT output valid
Receive enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Drive capacity
control
Drive capacity
control
Timer output
Serial I/O2 input
To key input interrupt
generating circuit
To key input interrupt
generating circuit
P04 key-on wakeup
selection bit
(5) Port P0
5
(6) Port P06
P05/TxD2 P-channel output
Pull-up control
disable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 enable bit
Serial I/O2 enable bit
Transmit enable bit
Pull-up control
Direction
register
Serial I/O2 mode selection bit
Serial I/O2 enable bit
Direction
register
Data bus
Port latch
Drive capacity
control
Data bus
Port latch
Drive capacity
control
Serial I/O2 output
To key input interrupt
generating circuit
Serial I/O2 clock output
Serial I/O2 clock input
To key input interrupt
generating circuit
P0
6
key-on wakeup
selection bit
(7) Port P0
7
Serial I/O2 mode selection bit
Serial I/O2 enable bit
Pull-up control
S
RDY2 output enable bit
Direction
register
Data bus
Port latch
Drive capacity
control
Serial I/O2 ready output
To key input interrupt
generating circuit
Fig. 18 Block diagram of ports (1)
18
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(8) Port P1
0
(9) Port P1
1
Serial I/O1 enable bit
Receive enable bit
P1
1
/T
x
D
1
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
P10, P12, P13
input level
selection bit
Data bus
Port latch
Serial I/O1 input
Capture 0 input control
*
Capture 0 input
Serial I/O1 output
(11) Port P1
3
(10) Port P1
2
Serial I/O1 synchronous
Serial I/O1 mode selection bit
Serial I/O1 enable bit
clock selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Direction
register
Port latch
Data bus
P10, P12, P13
input level
Data bus
Port latch
selection bit
P10, P12, P13
input level
selection bit
Serial I/O1 ready output
Serial I/O1 clock output
*
Serial I/O1 clock input
*
(13) Ports P20–P27
(12) Port P1
4
Pulse output mode
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Timer output
A-D converter input
Analog input pin
selection bit
CNTR0 interrupt input
P10
, P1
2, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 19 Block diagram of ports (2)
19
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(15) Ports P31, P32
(14) Port P30
Pull-up control
Pull-up control
Compare output control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Drive capacity
control
Drive capacity
control
Capture 1 input
Capture 1 input control
Compare output
(16) Port P33
(17) Ports P34, P35
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Drive capacity
control
Drive capacity
control
INT1 input control
INT1 input
(18) Port P36
(19) Port P37
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Drive capacity
control
Drive capacity
control
P3 input level
selection bit
P3 input level
selection bit
INT1 input control
INT1 input
INT0 input
*
*
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
*
Fig. 20 Block diagram of ports (3)
20
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Interrupts
[Interrupt edge selection register] INTEDGE
Interrupts occur by 18 different sources : 6 external sources, 11 in-
The valid edge of external interrupt INT0 and INT1 can be selected
by the interrupt edge selection bit, respectively.
ternal sources and 1 software source.
For the external interrupt INT1, the external input pin P33/INT1 or
P36/INT1 can be selected by the INT1 input port selection bit.
However, since there is no P36/INT1 pin in the 32-pin version, se-
lect P33/INT1 pin. By the key-on wakeup selection bit, enable/
disable of a key-on wakeup of P00, P04, and P06 pins can be se-
lected, respectively.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the in-
terrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
ꢀꢀNotes on use
(1) When setting the followings, the interrupt request bit may be
set to “1”.
•When setting external interrupt active edge
Related register:
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt edge selection register (address 003A16)
Timer X mode register (address 002B16)
Capture mode register (address 002016)
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the interrupt edge select bit (active edge switch bit, trigger
mode bit).
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
(2) Use a LDM instruction to clear an interrupt discrimination bit.
LDM #$0n, $0Bn
[Interrupt source set register] INTSET
When two interrupt sources are assigned to the same interrupt
vector, the valid/invalid of each interrupt is set by this register.
When both two interrupt sources are set to be valid, which inter-
rupt request occurs is confirmed by the next interrupt source
discrimination bit.
Set the following values to “n”
“0”: an interrupt discrimination bit to clear
“1”: other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is
cleared;
LDM #00001110B and $0B.
[Interrupt source discrimination register] INTDIS
When two interrupt sources are assigned to the same interrupt
vector, which interrupt source occurs is confirmed by this register.
If an interrupt request of a key-on wakeup, UART1 bus collision
detection, A-D conversion or timer 1 occurs, an interrupt discrimi-
nation bit is set to “1” regardless of valid/invalid state by the
interrupt source set register.
However, when the interrupt valid bit of an interrupt source set
register is “0” (invalid), the interrupt request bit of an interrupt con-
trol register is not set to “1.”
Moreover, since an interrupt discrimination bit is not automatically
cleared to “0” by interrupt, please clear it by program.
An interrupt discrimination bit can be cleared to “0” by program but
not be set to “1.”
21
MITSUBISHI MICROCOMPUTERS
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Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
Interrupt source Priority
Interrupt request generating conditions
At reset input
Remarks
High-order Low-order
Reset (Note 2)
1
2
3
FFFD16
FFFB16
FFF916
FFFC16
FFFA16
FFF816
Non-maskable
Serial I/O1 receive
Serial I/O1 transmit
At completion of serial I/O1 data receive Valid only when serial I/O1 is selected
At completion of serial I/O1 transmit shift Valid only when serial I/O1 is selected
or when transmit buffer is empty
Serial I/O2 receive
Serial I/O2 transmit
4
5
FFF716
FFF516
FFF616
FFF416
At completion of serial I/O2 data receive Valid only when serial I/O2 is selected
At completion of serial I/O2 transmit shift Valid only when serial I/O2 is selected
or when transmit buffer is empty
INT0
INT1
6
7
8
FFF316
FFF116
FFEF16
FFF216
FFF016
FFEE16
At detection of either rising or falling edge External interrupt
of INT0 input
(active edge selectable)
At detection of either rising or falling edge External interrupt
of INT1 input
(active edge selectable)
Key-on wake-up/
UART1 bus
collision detection
(Note 3)
At falling of conjunction of input logical
level for port P0 (at input)
At detection of UART1 bus collision
detection
External interrupt (valid at falling, when
key-on wakeup interrupt is enabled)
When UART1 bus collision detection
interrupt is enabled.
CNTR0
9
FFED16
FFEB16
FFE916
FFEC16
FFEA16
FFE816
At detection of either rising or falling edge External interrupt
of CNTR0 input
(active edge selectable)
Capture 0
Capture 1
10
11
At detection of either rising or falling edge External interrupt
of Capture 0 input
(active edge selectable)
At detection of either rising or falling edge External interrupt
of Capture 1 input
(active edge selectable)
Compare
Timer X
12
13
14
15
16
FFE716
FFE516
FFE316
FFE116
FFDF16
FFE616
FFE416
FFE216
FFE016
FFDE16
At compare matched
At timer X underflow
At timer A underflow
At timer B underflow
At completion of A-D conversion
At timer 1 underflow
Compare interrupt source is selected.
Timer A
Timer B
A-D conversion/
Timer 1
When A-D conversion interrupt is enabled.
STP release timer underflow
(Note 4)
(When Timer 1 interrupt is enabled)
Non-maskable software interrupt
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of
these interrupts are discriminated by interrupt source discrimination register.
4: A-D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are dis-
criminated by interrupt source discrimination register.
22
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Key-on wakeup interrupt
discrimination bit
Key-on wakeup interrupt request
Key-on wakeup interrupt valid bit
Key-on wakeup/
UART1 bus collision
detection interrupt
request bit
UART1 bus
collision detection
interrupt
UART1 bus collision detection
interrupt request
discrimination bit
UART1 bus collision detection
interrupt valid bit
A-D conversion interrupt
discrimination bit
A-D conversion interrupt request
A-D conversion interrupt valid bit
A-D conversion/
Timer 1 interrupt
request bit
Timer 1 interrupt
discrimination bit
Timer 1 interrupt request
Timer 1 interrupt valid bit
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Note: For key-on wakeup, UART1 bus collision detection, A-D conversion and Timer 1 interrupt,
even if interrupt valid bit (000A16) is set “0: Invalid”,
interrupt discrimination bit (000B16) is set to “1: interrupt occurs”
when corresponding interrupt request occurs.
But corresponding interrupt request bit (003C16, 003D16) is not set to “1”.
Fig. 21 Interrupt control
23
MITSUBISHI MICROCOMPUTERS
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b7
b0
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016
Interrupt source set register
(INTSET: address 000A16, initial value: 0016
)
)
Key-on wakeup interrupt valid bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
UART1 bus collision detection
interrupt valid bit
A-D conversion interrupt valid bit
INT
INT
0
1
interrupt request bit
interrupt request bit
Timer 1 interrupt valid bit
Key-on wake up/UART1 bus collision detection
interrupt request bit
Not used (returns “0” when read)
0: Interrupt invalid
1: Interrupt valid
CNTR
0
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt source discrimination register
(INTDIS: address 000B16, initial value: 0016
b7
b0
Interrupt request register 2
)
(IREQ2 : address 003D16, initial value : 0016
)
Key-on wakeup interrupt discrimination bit
UART1 bus collision detection
interrupt discrimination bit
Capture 0 interrupt request bit
Capture 1 interrupt request bit
Compare interrupt request bit
Timer X interrupt request bit
Timer A interrupt request bit
Timer B interrupt request bit
A-D conversion interrupt discrimination bit
Timer 1 interrupt discrimination bit
Not used (returns “0” when read)
A-D conversion/Timer 1 interrupt request bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0: Interrupt does not occur
1: Interrupt occurs
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16, initial value: 0016
0 : No interrupt request issued
1 : Interrupt request issued
)
b7
b0
Interrupt control register 1
INT
0
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
interrupt edge selection bit
(ICON1 : address 003E16, initial value : 0016
)
INT
0 : Falling edge active
1 : Rising edge active
1 input port selection bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
INT
0 : P3
6
1 : P3
3
INT
INT
0
1
interrupt enable bit
interrupt enable bit
Not used (returns “0” when read)
P00
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
Key-on wake up/UART1 bus collision detection
interrupt enable bit
P0
4
6
CNTR
0
interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
b0
Interrupt control register 2
P0
b7
(ICON2 : address 003F16, initial value : 0016
)
Note: P36 does not exist for the 32-pin version.
Capture 0 interrupt enable bit
Capture 1 interrupt enable bit
Compare interrupt enable bit
Timer X interrupt enable bit
Timer A interrupt enable bit
Timer B interrupt enable bit
Accordingly, select P33 for the INT1 function.
A-D conversion/Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 22 Structure of Interrupt-related registers
24
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 21, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
Port P0
Direction register = “1”
7
Key input interrupt request
*
**
Port P0
7
latch
P0
7
output
output
Falling edge
detection
PULL register
bit 3 = “0”
Port P0
6
Direction register = “1”
*
**
Port P0
latch
6
P0
6
Falling edge
detection
Port P06 key-on wakeup
selection bit
PULL register
bit 3 = “0”
Port P0
Direction register = “1”
5
*
**
Port P0
5
latch
P0
5
output
output
Falling edge
detection
PULL register
bit 3 = “0”
Port P0
4
Direction register = “1”
*
**
Port P0
latch
4
P0
4
Falling edge
detection
Port P04 key-on wakeup
selection bit
PULL register
bit 2 = “1”
Port P0
3
Port P0
Direction register = “0”
Input read circuit
*
*
*
**
Port P0
3
2
1
0
latch
P0
3
input
input
input
input
Falling edge
detection
PULL register
bit 2 = “1”
Port P0
2
Direction register = “0”
**
Port P0
latch
P0
2
Falling edge
detection
PULL register
bit 1 = “1”
Port P0
1
Direction register = “0”
**
Port P0
latch
P0
P0
1
Falling edge
detection
PULL register
bit 0 = “1”
Port P0
0
Direction register = “0”
*
**
Port P0
latch
0
Falling edge
detection
Port P00 key-on wakeup
selection bit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 23 Connection example when using key input interrupt and port P0 block diagram
25
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀTimer X
Timers
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
The 7542 Group has 4 timers: timer 1, timer X, timer A and timer
B.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows.The value of timer X latch is set to Timer X when Timer
X underflows.
• Frequency divider for timer
When writing to Prescaler X (PREX) is executed, the value is writ-
ten to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
According to the clock division selection bits (b7 and b6) of CPU
mode register (003B16), the count source of frequency divider is
set as follows;
b7b6 = “00”(high-speed), “01”(middle-speed), “11”(double-speed): XIN
b7b6 = “10”(Ring oscillator): Ring oscillator
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
ꢀTimer 1
Timer X can can be selected in one of 4 operating modes by set-
ting the timer X operating mode bits of the timer X mode register.
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
(1) Timer mode
Prescaler 1 is an 8-bit prescaler and counts the signal which is the
oscillation frequency divided by 16.
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows.The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is writ-
ten to both the prescaler 1 latch and Prescaler 1.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)ꢀ(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-
ecuted, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal which is the oscillation frequency di-
vided by 16. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “0016”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count contin-
ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 ac-
tive edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
The contents of Timer 1 is decremented by 1 each time the under-
flow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The di-
vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)ꢀ(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direc-
tion registers to output mode.
Timer 1 cannot stop counting by software.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
26
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Pulse width measurement mode
b7
b0
Timer X mode register
(TXM : address 002B16, initial value: 0016
In the pulse width measurement mode, the pulse width of the sig-
nal input to P14/CNTR0 pin is measured.
)
Timer X operating mode bits
b1 b0
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR0 pin.
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
Timer X can stop counting by setting “1” to the timer X count stop
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR0 output)
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Not used (return “0” when read)
Note on Timer X is described below;
Fig. 24 Structure of timer X mode register
ꢀꢀNote on Timer X
b7
b0
Timer count source set register
(TCSS : address 002A16, initial value: 0016
(1) CNTR0 interrupt active edge selection-1
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
)
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (Note 1)
1 : Not available
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
Timer A count source selection bits
b4 b3 b2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
(2) CNTR0 interrupt active edge selection-2
According to the setting value of CNTR0 active edge switch bit,
the interrupt request bit may be set to “1”.
0 : Ring oscillator output (Note 2)
1 : Not available
Timer B count source selection bits
b7 b6 b5
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0 : Timer A underflow
1 : Not available
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the active edge switch bit.
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or ring oscillator.
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
Do not use it at RC oscillation.
2: Ring oscillator can be used when the ring oscillator is enabled by bit 3 of CPUM.
Fig. 25 Timer count source set register
27
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Prescaler 1 latch (8)
Prescaler 1 (8)
Timer 1 latch (8)
Timer 1 interrupt
request bit
Timer 1 (8)
Data bus
1/16
“00”
“01”
“11”
Clock
division ratio
selection bits
Frequency Timer X count
divider
source selection bits
X
IN
1/16
1/2
1/1
Prescaler X latch (8)
Timer X latch (8)
Timer X (8)
Ring
oscillator
Pulse width
measurement
mode
“10”
Timer mode
Pulse output mode
Timer X
Prescaler X (8)
interrupt
request bit
CNTR0 active
edge switch bit
Event
counter
mode
Timer X count stop bit
P14/CNTR0
“0”
CNTR
0
interrupt
request bit
“1”
CNTR0 active “1”
Q
Q
edge switch bit
Toggle flip-flop T
R
“0”
Port P1
latch
4
Writing to timer X latch
Pulse output mode
Port P1
4
direction
register
Pulse output mode
P03/TXOUT
Port P03 latch
P03/TXOUT output valid
Port P0
3
direction
register
Fig. 26 Block diagram of timer 1 and timer X
28
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀTimer A,B
ꢀ Notes on Timer A, B
Timer A and Timer B are 16-bit timers and counts the signal which
is the oscillation frequency selected by setting of the timer count
source set register (TCSS). Timer A and Timer B have the same
function except of the count source clock selection.
(1) Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped. Accordingly, in order to set the initial value for timer when
it is stopped, set “0: Write to latch and timer simultaneously” to
timer A (B) write control bit.
The count source clock of Timer A is selected from among 1/2,1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and ring oscillator
clock.
(2) Read/write of timer A
The count source clock of Timer B is selected from among 1/2, 1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and Timer A underflow.
Stop timer A to read/write its data when the system is in the follow-
ing state;
• CPU operation clock source: XIN oscillation
• Timer A count source: Ring oscillator output
Timer A (B) consists of the low-order of Timer A: TAL (Timer B:
TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A
(B) is decremented by 1 when each time of the count clock is in-
put. When the contents of Timer A (B) reach “000016”, an
underflow occurs at the next count clock, and the timer latch is re-
loaded into timer. When Timer A (B) underflows, the Timer A (B)
interrupt request bit is set to “1”.
(3) Read/write of timer B
Stop timer B to read/write its data when the system is in the fol-
lowing state;
• CPU operation clock source: XIN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: Ring oscillator output
Timer A (B) has the Timer A (B) latch to retain the load value. The
value of timer A (B) latch is set to Timer A (B) at the timing of Timer
A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) pro-
vided that the value of Timer A (B) is n.
When writing to both the low-order of Timer A (B) and the high or-
der of Timer A (B) is executed, writing to “latch only” or “latch and
timer” can be selected by the setting value of the timer A (B) write
control bit.
When reading from Timer A (B) register is executed, the count
value of Timer A (B) is read out.
Be sure to write to/read out the low-order of Timer A (B) and the
high-order of Timer A (B) in the following order;
• Read
Read the high-order of Timer A (B) first, and the low-order of Timer
A (B) next and be sure to read both high-order and low-order.
• Write
Write to the low-order of Timer A (B) first, and the high-order of
Timer A (B) next and be sure to write both low-order and high or-
der.
Timer A and Timer B can be used for the timing timer of Input cap-
ture and Output compare function.
29
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer count source set register
(TCSS : address 002A16, initial value: 0016
Timer A, B mode register
(TABM : address 001D16, initial value: 0016
)
)
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (Note 1)
1 : Not available
Timer A write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
Timer A count source selection bits
b4 b3 b2
Timer A count stop bit
0 : Count start
1 : Count stop
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
Timer B write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
0 : Ring oscillator output (Note 2)
1 : Not available
Timer B count source selection bits
b7 b6 b5
Timer B count stop bit
0 : Count start
1 : Count stop
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN)/32
1 : f(XIN)/64
0 : f(XIN)/128
1 : f(XIN)/256
0 : Timer A underflow
1 : Not available
Not used (return “0” when read)
Compare 0, 1 modulation mode bit
0: Disabled
1: Enabled
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or ring oscillator.
Compare 2, 3 modulation mode bit
0: Disabled
Do not use it at RC oscillation.
2: Ring oscillator can be used when the ring oscillator is enabled by bit 3 of CPUM.
1: Enabled
Fig. 28 Timer count source set register
Fig. 27 Structure of timer A, B mode register
Frequency
divider
Clock division
ratio selection bits
Data bus
“00”
“01”
“11”
1/2
1/16
XIN
1/32
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Ring
oscillator “10”
1/64
Timer A write
control bit
1/128
1/256
Timer A interrupt
request
Ring
oscillator
Timer A
Timer A count
stop bit
count source
selection bits
Compare
Capture
Frequency
divider
1/2
Data bus
1/16
1/32
Timer B (high-order) latch (8)
Timer B (high-order) (8)
Timer B (low-order) latch (8)
Timer B (low-order) (8)
1/64
Timer B write
control bit
1/128
1/256
Timer B interrupt
request
Timer B count source
selection bits
Timer B count
stop bit
Compare
Capture
Fig. 29 Block diagram of timer A and timer B
30
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Output compare
ꢀ Notes on Output Compare
7542 group has 4-output compare channels. Each channel (0 to 3)
has the same function and can be used to output waveform by us-
ing count value of either Timer A or Timer B.
• When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
The source timer for each channel is selected by setting value of
the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B
can be selected for the source timer to each channel, respectively.
• Do not write the same data to both of compare latch x0 and x1.
• When setting value of the compare latch is larger than timer set-
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
To use each compare channel, set “1” to the compare x output
port bit and set the port direction register corresponding to com-
pare channel to output mode.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
• When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
The compare value for each channel is set to the compare regis-
ter (low-order) and compare register (high-order).
Writing to the register for each channel is controlled by setting
value of compare register write pointer. Writing to each register is
in the following order;
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
1.Set the value of corresponded output compare channel to the
compare register write pointer.
2.Write a value to the compare register (low-order) and compare
register (high-order).
3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31)
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set
to the compare register is loaded to compare latch when the
next timer underflow.
b7
b0
Capture/compare register R/W pointer
(CCRP : address 001216, initial value: 0016
)
Compare register R/W pointer
b2 b1 b0
When count value of timer and setting value of compare latch is
matched, compare output trigger occurs.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Compare latch 00
1 : Compare latch 01
0 : Compare latch 10
1 : Compare latch 11
0 : Compare latch 20
1 : Compare latch 21
0 : Compare latch 30
1 : Compare latch 31
When “1: Enabled” is set to the compare trigger x enable bit, the
output waveform from port is inverted by compare trigger.
When “0: Disabled” is set to the compare trigger x enable bit, the out-
put waveform is not inverted, so port output can be fixed to “H” or “L”.
When “0: Positive” is set to the compare x output level latch, the
compare output waveform is turned to “H level” at compare latch
x0’s match and turned to “L level” at compare latch x1’s match.
When “1 :Negative” is set to the compare x output level latch, the
compare output waveform is turned to “L level” at compare latch
x0’s match and turned to “H level” at compare latch x1’s match.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Not used (returns “0” when read)
Capture register 0 R/W pointer
0: Capture latch 00
1: Capture latch 01
Capture register 1 R/W pointer
0: Capture latch 10
1: Capture latch 11
Not used (returns “0” when read)
Fig. 30 Structure of capture/compare register R/W pointer
Compare output interrupt is available when match of each com-
pare channel and timer count value. The interrupt request from
each channel can be disabled or enabled by setting value of com-
pare latch y interrupt source bit.
b7
b0
Compare register re-load register
(CMPR : address 001416, initial value: 0016)
Compare latch 00, 01 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare 0,1 (2,3) modulation mode
In compare modulation mode, modulation waveform can be gener-
ated by using compare channel 0 and 1, or compare channel 2 and 3.
To use this mode,
Compare latch 10, 11 re-load bit
0: Re-load disabled
1: Re-load at next underflow
• Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit.
• Set Timer A underflow for Timer B count source.
• Set Timer A for the timer source of compare channel 0 (2).
• Set Timer B for the timer source of compare channel 1 (3).
Compare latch 20, 21 re-load bit
0: Re-load disabled
1: Re-load at next underflow
Compare latch 30, 31 re-load bit
0: Re-load disabled
1: Re-load at next underflow
In this mode, AND waveform of compare 0 (1) and compare 2 (3)
is generated from Port P01 and P31, respectively. Accordingly, in
order to use this mode, set “1” to the compare 0 output port bit or
compare 2 output port bit.
Not used (returns “0” when read)
Fig. 31 Structure of compare register re-load register
31
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Capture/Compare port register
Capture/Compare status register
(CCSR : address 002216, initial value: 0016
(CCPR : address 001E16, initial value: 0016
)
)
Capture 0 input port bits
b1 b0
Compare 0 output status bit
0: “L” level output
1: “H” level output
0
0
1
1
0: Capture from P0
1: Capture from P1
0: Ring/512
0
0
1: Not available
Compare 1 output status bit
0: “L” level output
1: “H” level output
Compare 0 output port bit
0: P0
1: P0
1
1
is I/O port
is Compare 0
Compare 2 output status bit
0: “L” level output
1: “H” level output
Compare 1 output port bit
0: P0
2
2
is I/O port
is Compare 1
1: P0
Capture 1 input port bit
0: Capture from P3
1: Ring/512
Compare 3 output status bit
0: “L” level output
1: “H” level output
0
Compare 2 output port bit
Capture 0 status bit
0: latch 00 captured
1: latch 01 captured
0: P3
1: P3
1
1
is I/O port
is Compare 2
Compare 3 output port bit
0: P3
1: P3
2
2
is I/O port
is Compare 3
Capture 1 status bit
0: latch 10 captured
1: latch 11 captured
Not used (returns “0” when read)
Fig. 32 Structure of capture/compare port register
Not used (returns “0” when read)
Fig. 35 Structure of capture/compare status register
b7
b0
Timer source selection register
(TMSR : address 001F16, initial value: 0016
)
b7
b0
Compare 0 timer source bit
Compare interrupt source register
(CISR : address 002316, initial value: 0016
)
Compare 1 timer source bit
Compare 2 timer source bit
Compare 3 timer source bit
Capture 0 timer source bit
Capture 1 timer source bit
Not used (returns “0” when read)
Compare latch 00 interrupt source bit
Compare latch 01 interrupt source bit
Compare latch 10 interrupt source bit
Compare latch 11 interrupt source bit
Compare latch 20 interrupt source bit
Compare latch 21 interrupt source bit
Compare latch 30 interrupt source bit
Compare latch 31 interrupt source bit
0: Timer A
1: Timer B
Fig. 33 Structure of timer source selection register
0: Disabled
1: Enabled
b7
b0
Compare output mode register
(CMOM : address 002116, initial value: 0016
Fig. 36 Structure of compare interrupt source register
)
Compare 0 output level latch
0: Positive
1: Negative
Compare 1 output level latch
0: Positive
1: Negative
Compare 2 output level latch
0: Positive
1: Negative
Compare 3 output level latch
0: Positive
1: Negative
Compare 0 trigger enable bit
0: Disabled
1: Enabled
Compare 1 trigger enable bit
0: Disabled
1: Enabled
Compare 2 trigger enable bit
0: Disabled
1: Enabled
Compare 3 trigger enable bit
0: Disabled
1: Enabled
Fig. 34 Structure of compare output mode register
32
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Compare latch 00
Compare latch 01
Timer A latch
Timer A counter
Timer B counter
Timer B latch
Wave latch channel 0
P0
1
Compare 0 timer source bit
Compare channel 0
P0
P3
P3
2
1
2
Compare channel 1
Compare channel 2
Compare channel 3
Fig. 37 Block diagram of output compare
Data bus
Compare register
write pointer
(001216, bits 0 to 2)
Compare buffer 01 (16)
Compare buffer 00 (16)
Compare latch 00 (16)
Compare latch 00, 01
re-load bit
(001416, bit 0)
Compare latch 01 (16)
Compare 0 output
Compare 0 output
Compare 0 trigger
enable bit
(002116, bit 4)
Compare register
port bit
status bit
(001E16, bit 2)
(002216, bit 0)
I/O port
P0
1
Output latch
Timer A counter (16)
Timer B counter (16)
Compare latch 00
interrupt source
bit (002316, bit 0)
Compare 0 output
level latch
(002116, bit 0)
Compare latch 01
interrupt source
bit (002316, bit 1)
Compare 0 timer
source bit
(001F16, bit 0)
Compare interrupt
Fig. 38 Block diagram of compare channel 0
33
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Compare register
write pointer
(001216, bits 0 to 2)
I/O
port
P0
1
Compare buffer 01 (16)
Compare buffer 00 (16)
Compare latch 00 (16)
Compare latch 00, 01
re-load bit
Compare 0 output
port bit
(001416, bit 0)
(001E16, bit 2)
Compare latch 01 (16)
Compare register
Compare 0 output
status bit
Compare 0 trigger
enable bit
(002216, bit 0)
(002116, bit 4)
Output latch
Timer A counter (16)
Compare 0 output
level latch
(002116, bit 0)
Compare 0 (1)
Underflow
timer source bits
(001F16, bit 0 (bit 1)
Compare 1 output
status bit
Compare 1 trigger
enable bit
(002216, bit 1)
(002116, bit 5)
Timer B counter (16)
Output latch
Compare 1 output
level latch
(002116, bit 1)
Compare register
Compare latch 11 (16)
Compare latch 10 (16)
Compare buffer 10 (16)
Compare latch 10, 11
re-load bit
(001416, bit 1)
Compare buffer 11 (16)
Compare register
write pointer
(001216, bits 0 to 2)
Data bus
Fig. 39 Block diagram of compare channel 0, 1
34
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer count clock
Re-load the count value
Timer underflow
Timer count value
Compare latch 00
Compare latch 01
Compare 00 match
Compare 01 match
Compare output
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B
000B
0005
Compare interrupt
Compare status bit
0
1
0
Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register.
Fig. 40 Output compare mode (general waveform)
Timer count clock
Timer underflow
Re-load the count value
Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B
Compare latch 00
Compare latch 01
000B
0005
000E
000C
Compare latch 00 write
Compare latch 01 write
Compare latch 00, 01 re-load bit
Compare latch 00, 01 re-load signal
Compare 00 match
Compare 01 match
Compare output
Compare interrupt
Compare status bit
0
1
0
1
0
Fig. 41 Output compare mode (compare register write timing)
35
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Carrier wave generated by Compare 0
Timer A count clock
Timer A underflow
Timer A count value
Compare latch 00
0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003
0006
0002
Compare latch 01
Compare 00 match
Compare 01 match
Compare 0 output
Compare 0 output status bit
1
0
1
0
1
Modulation of output waveform generated by Compare 1
Timer A underflow
Compare 0 output
Timer B count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003
Compare latch 10
Compare latch 11
0004
0001
Compare 10 match
Compare 11 match
Compare 1 output
Compare interrupt
Compare 1 output status bit
0
1
0
1
0
1
Port outptu wavefowm
Modulation output
Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register.
Fig. 42 Output compare mode (compare 0, 1 modulation mode)
36
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”.
Compare 0 output
Compare 1 output
Modulation output
2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Positive”.
Compare 0 output
Compare 1 output
Modulation output
3. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Negative”.
Compare 0 output
Compare 1 output
Modulation output
4. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Negative”.
Compare 0 output
Compare 1 output
Modulation output
Fig. 43 Output compare mode (compare 0, 1 modulation mode: effect of output level latch)
37
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Input capture
ꢀ Notes on Input Capture
7542 group has 2-input capture channels. Each channel (0 and 1)
has the same function and can be used to capture count value of
either Timer A or Timer B.
• If the capture trigger is input while the capture register (low-order
and high-order) is in read, captured value is changed between
high-order reading and low-order reading. Accordingly, some
countermeasure by software is recommended, for example
comparing the values that twice of read.
The source timer for each channel is selected by setting value of
the capture x (x = 0, 1) timer source bit. Timer A and Timer B can
be selected for the source timer to each channel, respectively.
• When the ring-oscillator is selected for Timer A count source,
Timer A cannot be used for the capture source timer.
Timer B cannot be used for the capture source timer when the
system is in the following state;
To use each capture channel, set the capture x input port bits and
set the port direction register corresponding to capture channel to
input mode.
• CPU operation clock source: XIN oscillation
• Timer B count source: Timer A underflow
The input capture circuit retains the count value of selected timer
when external trigger is input. The timer count value is retained to
the capture latch x0 when rising edge is input and is retained to
the capture latch x1 when falling edge is input.
The count value of timer can be retained by software by capture y
(y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this
bit, count value of timer is retained to the corresponded capture
latch.
• Timer A count source: Ring oscillator output
• When writing “1” to capture latch x0 (x1) software trigger bit of
capture latch x0 and x1 at the same time, or external trigger and
software trigger occur simultaneously, the set value of capture x
status bit is undefined.
• When setting the interrupt active edge selection bit and noise fil-
ter clock selection bit of external interrupt CAP0, CAP1, the
interrupt request bit may be set to “1”.
When reading from the capture y software trigger bit is executed,
“0” is read out.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
The latest status of capture latch can be confirmed by reading of
the capture x status bit. This bit indicates the capture latch which
latest data is in.
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the interrupt edge selection bit or noise filter clock selection bit.
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
The valid trigger edge for capture interrupt is set by the capture x
interrupt edge selection bits. (Regardless of the setting value of
capture x interrupt edge selection bits, timer count values for both
edges are retained to the capture latch.)
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
• The capture interrupt cannot be used as the interrupt for return
from stop mode. Even when the valid edge of the capture inter-
rupt is input at stop mode, system retains the stop mode. Then,
system returns from stop mode by other external interrupts, the
capture interrupt is accepted.
Each capture input has the noise filter circuit that judges continu-
ous 4-time same level with sampling clock to be valid. The
sampling clock of noise filter is set by the capture x noise filter
clock selection bits.
In this case, after system returns from stop mode, the interrupt
request bit of the corresponding capture interrupt is set to “1”.
Reading from the register for each channel is controlled by setting
value of the capture register read pointer. Reading from each reg-
ister is in the following order;
1.Set the value of the corresponded input capture channel to the
capture register read pointer.
2.Read from the capture register (low-order) and capture register
(high-order).
38
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b7
b7
b7
b0
b0
b0
b0
Capture software trigger register
(CSTR : address 001316, initial value: 0016
)
Capture register 0 (Low-order)
(CAP0L : address 000C16
Capture latch 00 software trigger bit
)
Capture latch 01 software trigger bit
Capture latch 10 software trigger bit
Capture latch 11 software trigger bit
Capture register 0 (High-order)
(CAP0H : address 000D16
)
Capture register 1 (Low-order)
(CAP1L : address 000E16
Each software trigger occurs by setting “1” to
corresponding bit. (returns “0” when read)
)
Not used (returns “0” when read)
Capture register 1 (High-order)
(CAP1H : address 000F16
)
b7
b0
Capture mode register
(CAPM : address 002016, initial value: 0016
)
Capture 0 interrupt edge selection bits
b1 b0
Fig. 44 Structure of capture software trigger register
0
0
1
1
0: Rising and falling edge
1: Rising edge
0: Falling edge
1: Not available
Capture 1 interrupt edge selection bits
b3 b2
0
0
1
1
0: Rising and falling edge
1: Rising edge
0: Falling edge
1: Not available
Capture 0 noise filter clock selection bits
b5 b4
0
0
1
1
0: Filter stop
1: f(XIN
0: f(XIN)/8
)
1: f(XIN)/32
Capture 1 noise filter clock selection bits
b7 b6
0
0
1
1
0: Filter stop
1: f(XIN
0: f(XIN)/8
)
1: f(XIN)/32
Fig. 45 Structure of capture software trigger register/capture
mode register
39
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P0
0
0
Trigger input channel 0
Capture latch 00
Capture latch 01
Timer A latch
Timer A counter
Timer B counter
Timer B latch
P1
Ring
/512
Capture 0 timer source bit
Capture channel 0
P30
Ring
/512
Capture channel 1
Fig. 46 Block diagram of input capture
Data bus
Capture register 0
read pointer
(001216, bit 4)
Capture register
Capture latch 01 (16)
Capture latch 00 (16)
Capture 0
status bit
(002216, bit 4)
Capture pointer
(001316, bits 4, 5)
Capture 0
Capture latch 00
Falling
Rising
interrupt edge
selection bits
(002016, bits 0, 1)
software trigger bit
(001316, bit 0)
Ring/512
Capture
trigger
Capture interrupt
Capture latch 0 (16)
P1
0
Digital filter
P0
0
Capture 0 timer
source bit
Capture 0 input
port bits
Capture 0 noise
filter clock
(001F16, bit 4)
(001E16, bits 0, 1)
selection bits
(002016, bits 4, 5)
Timer A counter (16)
Timer B counter (16)
Fig. 47 Block diagram of capture channel 0
40
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Re-load the timer count value
Timer underflow
Capture input wave
Timer count value
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B
Overwrite
Capture latch 00
Capture latch 01
XXXX
000A
0001
000C
XXXX
0005
000F
Capture interrupt
Capture x (x=0, 1) status bit
1
0
1
0
1
0
Fig. 48 Capture interrupt edge selection = “rising edge”
Re-load the timer count value
Timer underflow
Capture input wave
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B
Overwrite
Timer count value
XXXX
000A
0001
000C
Capture latch 00
Capture latch 01
XXXX
0005
000F
Capture interrupt
1
0
1
0
1
0
Capture x (x=0, 1) status bit
Fig. 49 Capture interrupt edge selection = “rising and falling edge”
41
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O
(1) Clock Synchronous Serial I/O Mode
The 7542 Group has Serial I/O1 and Serial I/O2. Except that Se-
rial I/O1 has the bus collision detection function, they have the
same function.
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6) to “1”.
ꢀSerial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Receive buffer full flag (RBF)
Address 001A16
Address 001816
Receive buffer register 1
P1
0
2
/RXD1/CAP0
Receive shift register 1
Receive interrupt request (RI)
Shift clock
Clock control circuit
P1
/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator 1
Address 001C16
1/4
Clock control circuit
P1
3
/SRDY1
Falling-edge detector
F/F
Shift clock
Transmit shift register 1
Transmit buffer register 1
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P11/TXD1
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 50 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
1
1
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RxD
D
D
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 51 Operation of clock synchronous serial I/O1 function
42
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer register 1
OE
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
P10/RXD1/CAP0
ST detector
7 bits
8 bits
Receive shift register 1
PE FE SP detector
1/16
UART1 control register
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P12/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator 1
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P11/TXD1
Transmit shift register 1
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register 1
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Data bus
Fig. 52 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
D1
TSC=1ꢀ
SP
TBE=1
Serial output TXD1
ST
D0
ST
D0
D1
SP
ꢀ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
D1
RBF=1
SP
RBF=1
SP
ST
Serial input RXD1
D0
D1
ST
D0
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 53 Operation of UART serial I/O1 function
43
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit buffer register 1/receive buffer register 1 (TB1/
RB1)] 001816
ꢀꢀNotes on Serial I/O1
• Serial I/O interrupt
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
[Serial I/O1 status register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O1 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY1 output pin.
[Serial I/O1 control register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
[UART1 control register (UART1CON)] 001B16
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
The UART1 control register consists of four control bits (bits 0 to
3) which are valid when asynchronous serial I/O is selected and
set the data format of an data transfer and one bit (bit 4) which is
always valid and sets the output structure of the P11/TxD1 pin.
[Baud rate generator 1 (BRG1)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
44
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O1 status register
Serial I/O1 control register
(SIO1STS : address 001916, initial value: 8016)
(SIO1CON : address 001A16, initial value: 0016)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY1 output enable bit (SRDY)
0: P13 pin operates as ordinary I/O pin
1: P13 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P10 to P13 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P10 to P13operate as serial I/O pins)
b7
b0
UART1 control register
(UART1CON : address 001B16, initial value: E016)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P11/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 54 Structure of serial I/O1-related registers
45
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Bus collision detection (SIO1)
SIO1 can detect a bus collision by setting UART1 bus collision de-
Interrupt source set register
(INTSET: address 000A16, initial value: 0016)
Key-on wakeup interrupt valid bit
tection interrupt enable bit.
UART1 bus collision detection
interrupt valid bit
A-D conversion interrupt valid bit
When transmission is started in the clock synchronous or asyn-
chronous (UART) serial I/O mode, the transmit pin TxD1 is
compared with the receive pin RxD1 in synchronization with rising
edge of transmit shift clock. If they do not coincide with each other,
a bus collision detection interrupt request occurs.
Timer 1 interrupt valid bit
Not used (returns “0” when read)
0: Interrupt invalid
1: Interrupt valid
When a transmit data collision is detected between LSB and MSB
of transmit data in the clock synchronous serial I/O mode or be-
tween the start bit and stop bit of transmit data in UART mode, a
bus collision detection can be performed by both the internal clock
and the external clock.
b7
b0
Interrupt source discrimination register
(INTDIS: address 000B16, initial value: 0016)
Key-on wakeup interrupt discrimination bit
UART1 bus collision detection interrupt
discrimination bit
A-D conversion interrupt discrimination bit
Timer 1 interrupt discrimination bit
Not used (returns “0” when read)
A block diagram is shown in Fig. 56.
A timing diagram is shown in Fig. 57.
0: Interrupt does not occur
1: Interrupt occurs
Note: Bus collision detection can be used when SIO1 is operating
at full-duplex communication. When SIO1 is operating at
half-duplex communication, set bus collision detection inter-
rupt to be disabled.
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up/UART1 bus collision
detection interrupt request bit
CNTR0 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
Key-on wake up/UART1 bus collision
detection interrupt enable bit
CNTR0 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 55 Bus collision detection circuit related registers
UART1 bus collision detection
interrupt discrimination bit
(Address 000B16, bit 1)
TxD
RxD
D
Q
Key-on wakeup/
UART1 bus collision detection
interrupt request bit
(Address 003C16, bit 6)
Shift clock
Key-on wakeup interrupt request
UART1 bus collision detection
interrupt valid bit
(Address 000A16, bit 1)
Fig. 56 Block diagram of bus collision detection interrupt circuit
Transmit shift clock
Bus collision detection
interrupt generation
Transmit pin TxD
1
1
Receive pin RxD
Data collision
Fig. 57 Timing diagram of bus collision detection interrupt
46
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀSerial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O2 mode can be selected by setting
the serial I/O2 mode selection bit of the serial I/O2 control register
(bit 6) to “1”.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O2 control register
Receive buffer full flag (RBF)
Address 003016
Address 002E16
Receive buffer register 2
Receive shift register 2
Receive interrupt request (RI)
P04/RXD2
Shift clock
Clock control circuit
P06/SCLK2
Serial I/O2 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator 2
Address 003216
1/4
Clock control circuit
P07/SRDY2
P05/TXD2
Falling-edge detector
F/F
Shift clock
Transmit shift register 2
Transmit buffer register 2
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 002F16
Address 002E16
Data bus
Fig. 58 Block diagram of clock synchronous serial I/O2
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
2
2
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial input RxD
D
D
D
D
D
D
D
D
Receive enable signal SRDY2
Write pulse to receive/transmit
buffer register (address 002E16
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O2 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 59 Operation of clock synchronous serial I/O2 function
47
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O2 mode selection bit of the serial I/O2 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 002E16
Serial I/O2 control register Address 003016
Receive buffer register 2
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
P04/RXD2
ST detector
7 bits
8 bits
Receive shift register 2
1/16
UART2 control register
PE FE SP detector
Address 003116
Clock control circuit
Serial I/O1 synchronous clock selection bit
P06/SCLK2
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator 2
Address 003216
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P05/TXD2
Transmit shift register 2
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register 2
Address 002E16
Transmit buffer empty flag (TBE)
Address 002F16
Serial I/O2 status register
Data bus
Fig. 60 Block diagram of UART serial I/O2
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1ꢀ
TBE=1
Serial output TXD2
ST
SP
D0
D1
ST
D0
D1
SP
ꢀ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD2
D0
D1
ST
D0
D1
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O2 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 61 Operation of UART serial I/O2 function
48
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit buffer register 2/receive buffer register 2 (TB2/
RB2)] 002E16
ꢀꢀNotes on Serial I/O2
• Serial I/O interrupt
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
[Serial I/O2 status register (SIO2STS)] 002F16
The read-only serial I/O2 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O2
function and various errors.
ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
• I/O pin function when serial I/O2 is enabled.
The functions of P06 and P07 are switched with the setting values
of a serial I/O2 mode selection bit and a serial I/O2 synchronous
clock selection bit as follows.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O2 enable bit SIOE
(bit 7 of the serial I/O2 control register) also clears all the status
flags, including the error flags.
(1) Serial I/O2 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY2 output enable bit (SRDY)
Bits 0 to 6 of the serial I/O2 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O2 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
[Serial I/O2 control register (SIO2CON)] 003016
The serial I/O2 control register consists of eight control bits for the
serial I/O2 function.
(2) Serial I/O2 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
[UART2 control register (UART2CON)] 003116
“1”: P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P07 pin. It can be used as a normal I/O pin.
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P05/TxD2 pin.
[Baud rate generator 2 (BRG2)] 003216
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
49
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O2 status register
Serial I/O2 control register
(SIO2STS : address 002F16, initial value: 8016
)
(SIO2CON : address 003016, initial value: 0016
)
BRG count source selection bit (CSS)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
0: f(XIN
)
1: f(XIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P0
1: P0
RDY2 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY2 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O2 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P0
1: Serial I/O2 enabled
(pins P0 to P0 operate as serial I/O pins)
4 to P07 operate as ordinary I/O pins)
4
7
b7
b0
UART2 control register
(UART2CON : address 003116, initial value: E016
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P05/TXD2 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 62 Structure of serial I/O2-related registers
50
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
The functional blocks of the A-D converter are described below.
b7
b0
A-D control register
(ADCON : address 003416, initial value: 1016
)
Analog input pin selection bits
[A-D conversion register] AD
000 : P2
001 : P2
010 : P2
011 : P2
100 : P2
101 : P2
110 : P2
111 : P2
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-
D conversion.
(Note)
(Note)
[A-D control register] ADCON
Not used (Do not write “1” to this bit.)
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at “0” during A-D conversion,
and changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
Note: These can be used only for 36 pin version.
[Comparison voltage generator]
Fig. 63 Structure of A-D control register
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
Read 8-bit (Read only address 003516)
b7
b0
[Channel selector]
(Address 003516)
b9 b8 b7 b6 b5 b4 b3 b2
The channel selector selects one of ports P27/AN7 to P20/AN0,
and inputs the voltage to the comparator.
Read 10-bit (read in order address 003616, 003516)
b7
b0
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A-D con-
version.
b9 b8
(Address 003616)
b7
b0
(Address 003516)
b7 b6 b5 b4 b3 b2 b1 b0
Note: High-order 6-bit of address 003616 returns “0” when read.
Fig. 64 Structure of A-D conversion register
Data bus
b7
b0
A-D control register
(Address 003416
)
3
A-D interrupt request
A-D control circuit
P2
P2
P2
P2
P2
P2
P2
P2
0/AN
1/AN
2/AN
3/AN
4/AN
5/AN
6/AN
7/AN
0
1
2
3
4
5
6
7
A-D conversion register (high-order)
A-D conversion register (low-order)
(Address 003616
(Address 003516
)
)
Comparator
10
Resistor ladder
V
REF
VSS
Fig. 65 Block diagram of A-D converter
51
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 003916)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source se-
lection bit are read.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (ad-
dress 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an inter-
nal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
Data bus
Write “FF16” to the
watchdog timer
control register
Write "FF16" to the
watchdog timer
control register
“0”
“1”
Watchdog timer L (8)
Watchdog timer H (8)
1/16
X
IN
Watchdog timer H count
source selection bit
STP Instruction disable bit
STP Instruction
Reset
circuit
Internal reset
RESET
Fig. 66 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON: address 003916, initial value: 3F16
)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 67 Structure of watchdog timer control register
52
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
Poweron
The microcomputer is put into a reset status by holding the RE-
SET pin at the “L” level for 2 µs or more when the power source
voltage is 2.2 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the con-
tents of address FFFC16 as low-order address.
(Note)
Power source
voltage
0 V
RESET
VCC
Reset input
voltage
0 V
0.2 VCC
In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V
or less when the power source voltage passes 4.0 V.
In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V
or less when the power source voltage passes 2.4 V.
In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V
or less when the power source voltage passes 2.2 V.
Note : Reset release voltage Vcc = 2.2 V
RESET
VCC
Power source
voltage
detection circuit
Fig. 68 Example of reset circuit
Clock from built-in
ring oscillator RING
φ
RESET
RESETOUT
SYNC
AD
H
H,ADL
?
?
?
?
?
FFFC
FFFD
Address
Data
Reset address from the
vector table
?
?
?
?
?
ADL
AD
Notes 1 : A built-in ring oscillator applies about RING•2 MHz, φ•250 kHz frequency clock
at average of Vcc = 5 V.
8-13 clock cycles
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
Fig. 69 Timing diagram at reset
53
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address
Register contents
0016
000116
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Port P0 direction register (P0D)
X
X
X
0
0
0
0
0
000316
000516
000716
000A16
000B16
001016
001116
Port P1 direction register (P1D)
0016
Port P2 direction register (P2D)
0016
Port P3 direction register (P3D)
0016
0016
0016
Interrupt source set register (INTSET)
Interrupt source discrimination register (INTDIS)
Compare register (low-order) (CMPL)
0016
0016
0016
0016
0016
0016
0016
(8)
Compare register (high-order) (CMPH)
(9)
Capture/Compare register R/W pointer (CCRP) 001216
(10)
(11)
(12)
Capture software trigger register (CSTR)
Compare register re-load register (CMPR)
Port P0P3 drive capacity control register (DCCR)
Pull-up control register (PULL)
001316
001416
001516
001616
001716
001916
001A16
001B16
(13)
(14)
(15)
(16)
(17)
Port P1P3 control register (P1P3C)
1
1
0
1
0
1
0
0
0
0
0
0
0
0
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
0016
0
0
0016
0016
0016
0016
0016
0016
0016
001D16
001E16
001F16
002016
002116
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
Timer A, B mode register (TABM)
Capture/Compare port register (CCPR)
Timer source selection register (TMSR)
Capture mode register (CAPM)
Compare output mode register (CMOM)
Capture/Compare status register (CCSR)
002216
002316
002416
002516
Compare interrupt source register (CISR)
Timer A (low-order) (TAL)
FF16
FF16
FF16
Timer A (high-order) (TAH)
002616
002716
Timer B (low-order) (TBL)
Timer B (high-order) (TBH)
Prescaler 1 (PRE1)
FF16
FF16
0116
0016
0016
FF16
FF16
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003116
003416
Timer 1 (T1)
Timer count source set register (TCSS)
Timer X mode register (TXM)
Prescaler X (PREX)
Timer X (TX)
1
0
0
0
0
0
0
0
(35)
(36)
(37)
Serial I/O2 control register (SIO2STS)
0016
Serial I/O2 register (SIO2CON)
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
UART2 control register (UART2CON)
1
0
(38) A-D control register (ADCON)
Ring oscillation division ratio selection register (RODR)
(39)
003716
003816
003916
0
0
0
0
0
1
0
0016
MISRG
(40)
(41) Watchdog timer control register (WDTCON)
0
0
1
1
1
0
1
1
1
0016
(42)
(43)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
1
0
0
0
0
0
0
0016
(44) Interrupt request register 1 (IREQ1)
(45)
0016
0016
0016
Interrupt request register 2 (IREQ2)
(46) Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Processor status register
Program counter
(47)
(48)
(49)
X
X
X
X
X
1
X
X
Contents of address FFFD16
Contents of address FFFC16
(PC
H)
(PC
L)
Note X : Undefined
Fig. 70 Internal status of microcomputer at reset
54
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Note:
The clock frequency of the
ring oscillator depends on
the supply voltage and the
operation temperature
range.
Be careful that variable
frequencies and obtain
the sufficient margin.
M37542
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
X
IN
XOUT
R
(1) Ring oscillator operation
Open
When the MCU operates by the ring oscillator for the main clock,
connect XIN pin to VCC through a resistor and leave XOUT pin
open.
Fig. 71 Processing of XIN and XOUT pins at ring oscillator op-
eration
The clock frequency of the ring oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Note:
Externally connect a
damping resistor Rd de-
p e n d i n g o n t h e
oscillation frequency.
(A feedback resistor is
built-in.)
Use the resonator
manufacturer’s recom-
mended value because
constants such as ca-
pacitance depend on the
resonator.
M37542
(2) Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in be-
tween pins XIN and XOUT.
X
IN
XOUT
Rd
C
OUT
C
IN
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin to the external circuit of resistor R and the capacitor C at
the shortest distance and leave XOUT pin open.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
Fig. 72 External circuit of ceramic resonator
So, set the constants within the range of the frequency limits.
Note:
Connect the external
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is af-
fected by a capacitor,
a resistor and a micro-
computer.
M37542
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
X
IN
XOUT
R
C
So, set the constants
within the range of the
frequency limits.
Fig. 73 External circuit of RC oscillation
M37542
XIN
XOUT
Open
External oscillation
circuit
V
CC
SS
V
Fig. 74 External clock input circuit
55
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Oscillation control
b7
b0
• Stop mode
CPU mode register
(CPUM: address 003B16, initial value: 8016
)
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. f(XIN)/16 is forcibly
connected to the input of prescaler 1. When an external interrupt
is accepted, oscillation is restarted but the internal clock φ remains
at “H” until timer 1 underflows. As soon as timer 1 underflows, the
internal clock φ is supplied. This is because when a ceramic oscil-
lator is used, some time is required until a start of oscillation. In
case oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable.
Processor mode bits (Note 1)
b1 b0
0
0
1
1
0
1
0
1
Single-chip mode
Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Ring oscillator oscillation control bit
0
1
: Ring oscillator oscillation enabled
: Ring oscillator oscillation stop
XIN oscillation control bit
0
1
: Ceramic or RC oscillation enabled
: Ceramic or RC oscillation stop
Oscillation mode selection bit (Note 1)
0
1
: Ceramic oscillation
: RC oscillation
Clock division ratio selection bits
b7 b6
0
0
1
1
0
1
0
1
:
:
:
:
f(φ) = f(XIN)/2 (High-speed mode)
f(φ) = f(XIN)/8 (Middle-speed mode)
applied from ring oscillator
f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
• Wait mode
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37542RSS”.)
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 75 Structure of CPU mode register
ꢀ Ring oscillation division ratio
At ring oscillator mode, division ratio of ring oscillator for CPU
clock is selected by setting value of ring oscillation division ratio
selection register. The division ratio of ring oscillation for CPU
clock is selected from among 1/1, 1/2, 1/8, 1/128. The operation
clock for the peripheral function block is not changed by setting
value of this register.
ꢀ Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
ꢀ Notes on Ring Oscillation Division Ratio
• When system is released from reset, ROSC/8 (ring middle-speed
mode) is selected for CPU clock.
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is se-
lected by setting bit 5 of the CPU mode register.
• When state transition from the ceramic or RC oscillation to ring
oscillator, ROSC/8 (ring middle-speed mode) is selected for CPU
clock.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
• When the MCU operates by ring-oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
• CPU mode register
Set “10010x002” (x = 0 or 1) to CPUM.
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37542RSS” is excluded.)
b7
b0
Ring oscillation division ratio selection register
(RODR: address 003716, initial value: 0216
)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
Ring oscillator division ratio
b1 b0
0
0
1
1
0: Ring double-speed mode (ROSC/1)
1: Ring high-speed mode (ROSC/2)
0: Ring middle-speed mode (ROSC/8)
1: Ring low-speed mode (ROSC/128)
• Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 79 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 79.
Not used (returns “0” when read)
Fig. 76 Structure of ring oscillation division ratio selection
register
56
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
IN
XOUT
Rf
Main clock division ratio selection bit
Middle-, high-, low-speed mode
Timer 1
Prescaler 1
1/2
1/2
1/4
Ring oscillator mode
Main clock division
ratio selection bits
Middle-speed mode
Timing φ
(Internal
clock)
High-speed mode
Double-speed mode
Ring oscillator division
ratio selection bits
R
OSC/128
Ring oscillator
1/2
1/16
1/4
R
OSC/8
OSC/2
OSC/1
Ring oscillator mode
R
R
Q
S
R
S
Q
Q S
R
WIT
instruction
STP instruction
Reset
R
STP instruction
Interrupt disable flag l
Interrupt request
Fig. 77 Block diagram of internal clock generating circuit (for ceramic resonator)
X
OUT
XIN
Main clock division ratio selection bit
Middle-, high-, low-speed mode
Timer 1
1/4
Prescaler 1
1/2
1/2
Ring
oscillator
mode
Delay
Main clock division
ratio selection bits
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
Ring oscillator division
RING
Ring oscillator
1/16
1/2
1/4
ratio selection bits
R
OSC/128
R
OSC/8
OSC/2
OSC/1
Ring oscillator mode
R
R
Q
S
R
S
R
Q
Q S
RESET
STP instruction
WIT
instruction
STP instruction
Reset
R
Interrupt disable flag l
Interrupt request
Fig. 78 Block diagram of internal clock generating circuit (for RC oscillation)
57
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
STP mode
f(XIN) oscillation: stop
Ring oscillator: stop
Interrupt
STP
Interrupt
STP
Interrupt
STP
instruction
instruction
instruction
Interrupt
f(XIN) oscillation: enabled
Ring oscillator: stop
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: stop
Ring oscillator: enabled
STP
instruction
WAIT mode 1
WAIT mode 2
WAIT mode 4
WAIT mode 3
Interrupt
WIT
instruction
WIT
instruction
WIT
instruction
WIT
instruction
Interrupt
Interrupt
Interrupt
CPUM76=10
2
(Note 3)
CPUM
CPUM
3
=0
2
2
CPUM
CPUM
4
=0
2
2
State 1
State 2
State 3
State 4
3=1
CPUM76=00
2
2
2
4=1
01
11
(Note 4)
MISRG
1=12
Reset
released
(Note 3)
MISRG
1=12
MISRG
1=02
MISRG1=02
(Note 4)
CPUM76=10
2
(Note 3)
RESET state
State 2’
State 3’
f(XIN) oscillation: enabled
Ring oscillator: enabled
CPUM76=00
2
2
2
01
11
WIT
instruction
WIT
Interrupt
Interrupt
instruction
WAIT mode 2’
WAIT mode 3’
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
Oscillation stop detection circuit valid
Operation clock source: f(XIN) (Note 1)
Notes on switch of clock
Operation clock source: Ring oscillator (Note 2)
(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.
f(XIN)/2 (high-speed mode)
f(XIN)/8 (middle-speed mode)
f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) In operation clock = ring oscillator, the following can be selected for the CPU clock division ratio.
ROSC/1 (ring double-speed mode)
ROSC/2 (ring high-speed mode)
ROSC/8 (ring middle-speed mode)
ROSC/128 (ring low-speed mode)
(3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’,
OSC/8 (ring middle-speed mode) is selected for CPU clock.
R
(4) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.
(5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM76 = 10
2 (state 2 → state 3)
2. NOP instruction
Double-speed mode: NOP ꢀ 3
High-speed mode: NOP ꢀ 1
Middle-speed mode: NOP ꢀ 0
3. CPU4 = 12 (state 3 → state 4)
(6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
1. CPUM76 = 002 or 012 or 112 (state 3 → state 2)
2. NOP instruction
TBD
3. CPU3 = 12 (state 2 → state 1)
Fig. 79 State transition
58
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Oscillation stop detection circuit
The oscillation stop detection circuit is used for reset occurrence
when a ceramic resonator or RC oscillation circuit stops by dis-
connection. To use this circuit, set a built-in ring oscillator to be in
active.
b7
b0
MISRG(address 003816, initial value: 0016
)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF16
in prescaler 1 automatically
1: Not set automatically
”
The oscillation stop detection circuit is in active to set “1” to the
ceramic or RC oscillation stop detection function active bit. When
the oscillation stop detection circuit is in active, ceramic or RC os-
cillation is watched by the built-in ring oscillator. When stop of
ceramic or RC oscillation is detected, the oscillation stop detection
status bit is set to “1”. While “1” is set to the oscillation stop reset
bit, internal reset occurs when oscillation stop is detected.
Ceramic or RC oscillation stop detection
function active bit
0: Detection function inactive
1: Detection function active
Oscillation stop reset bit
0: Oscillation stop reset disabled
1: Oscillation stop reset enabled
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
The external reset and the oscillation stop reset can be discrimi-
nated by reading the oscillation stop detection status bit.
The oscillation stop detection status bit retains “1”, not initialized,
when the oscillation stop reset occurs. The oscillation stop detec-
tion status bit is initialized to “0” when the external reset occurs.
Accordingly, reset by oscillation stop can be confirmed by using
this bit.
Not used (return “0” when read)
Reserved bits
(Do not write “1” to these bits)
Fig. 80 Structure of MISRG
ꢀ Notes on Oscillation Stop Detection Circuit
• When the oscillation stop reset bit is set to “0”, internal reset
does not occur. If the ceramic or RC oscillation is selected for
the CPU clock, MCU will be locked when the ceramic or RC os-
cillation is stopped. So when the ceramic or RC oscillation is
selected for the main clock, set the oscillation stop reset bit to
“1”. (State 2’a of Fig. 81)
• Ceramic or RC oscillation stop detection function active bit is not
cleared by the oscillation stop internal reset. Accordingly, the
oscillation stop detection circuit is in active when system is re-
leased from internal reset cause of oscillation stop detection.
• Oscillation stop detection status bit is initialized by the following
operation.
(1) External reset
(2) Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
• The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
59
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CPUM76=10
2
Reset
released
(Note 4)
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
RESET state 1
State 3
State 2
(Note 4)
f(XIN) oscillation: enabled
Ring oscillator: enabled
CPUM76=00
2
2
2
01
11
(Note 3)
MISRG
1=12
MISRG
1=12
MISRG
1=02
MISRG
1=02
(Note 3)
(MISRG
3
is cleared to “0”.)
(MISRG
3
is cleared to “0”.)
Hardware reset
(external reset
)
f(XIN) oscillation: enabled
Ring oscillator: enabled
f(XIN) oscillation: enabled
Ring oscillator: enabled
MISRG is cleared to “0”.
3
State 3’
State 2’
State 2’a (Note 5)
State 3’a
Oscillation stop reset disabled
When oscillation stop is detected;
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG
3
is set to “1”.
MISRG3 is set to “1”.
Internal RESET does not occur.
CPUM76=10
2
Internal RESET does not occur.
State 3’c
Release from internal reset
MISRG3 is set to “1”.
Reset
released
CPUM76=00
2
2
2
Prohibitive state
MUC will be locked when Ceramic
or RC oscillation is stopped.
RESET state 2
01
11
f(XIN) oscillation: enabled
Ring oscillator: enabled
(Note 4)
Oscillation status can be
confirmed by reading MISRG3.
MISRG
2=12
MISRG
2=02
MISRG
2=12
MISRG2=02
CPUM76=10
2
State 2’b
State 3’b
(Note 4)
Oscillation stop reset enabled
When oscillation stop is detected;
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG
Internal RESET occurs.
3
is set to “1”.
MISRG
Internal RESET occurs.
3 is set to “1”.
CPUM76=00
2
2
2
01
11
Oscillation stop is detected
(internal reset)
Oscillation stop detection circuit is in active. (Note 6)
Operation clock source: f(XIN) (Note 1)
Operation clock source: Ring oscillator (Note 2)
Notes on switch of clock
(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.
f(XIN)/2 (high-speed mode)
f(XIN)/8 (middle-speed mode)
f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) In operation clock = ring oscillator, the following can be selected for the CPU clock division ratio.
ROSC/1 (ring double-speed mode)
ROSC/2 (ring high-speed mode)
ROSC/8 (ring middle-speed mode)
ROSC/128 (ring low-speed mode)
(3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation.
(4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’b → state 3’b,
R
OSC/8 (ring middle-speed mode) is selected for CPU clock.
(5) “State 2’a” is prohibitive state.
Because when oscillation stop reset bit is set to “0”, internal reset does not occur.
So if clock stop is detected at “State 2’a”, MCU will be locked.
(6) STP instruction cannot be used when oscillation stop detection circuit is in active.
Fig. 81 State transition
60
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
State transition
Do not stop the clock selected as the operation clock because of
NOTES ON PROGRAMMING
setting of CM3, 4.
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 µF to 0.1 µF is recommended.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
NOTES ON PERIPHERAL FUNCTIONS
ꢀ Interrupt
(1) When setting the followings, the interrupt request bit may be
Decimal Calculations
set to “1”.
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD in-
struction after executing one instruction before the ADC instruction
or SBC instruction.
•When setting external interrupt active edge
Related register:
Interrupt edge selection register (address 003A16)
Timer X mode register (address 002B16)
Capture mode register (address 002016)
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Ports
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the interrupt edge select bit (active edge switch bit, trigger
mode bit).
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
(2) Use a LDM instruction to cleare an interrupt discrimination bit.
LDM #$0n, $0Bn
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
Set the following values to “n”
“0”: an interrupt discrimination bit to clear
“1”: other interrupt discrimination bits
Ex.) When a key-on wakeup interrupt discrimination bit is
cleared;
A-D Conversion
Do not execute the STP instruction during A-D conversion.
LDM #00001110B and $0B.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles men-
tioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the XIN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is ex-
cluded.)
When a ceramic oscillation is selected, a double-speed mode of
the clock division ratio selection bits can be used. Do not use it
when an RC oscillation is selected.
61
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Timers
ꢀ Notes on Output Compare
• When n (0 to 255) is written to a timer latch, the frequency divi-
• When the selected source timer of each compare channel is
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
sion ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched,
stop a count of timer X.
• Do not write the same data to both of compare latch x0 and x1.
• When setting value of the compare latch is larger than timer set-
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
• When the compare x trigger enable bit is cleared to “0” (dis-
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
ꢀ Timer X
(1) CNTR0 interrupt active edge selection-1
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
(2) CNTR0 interrupt active edge selection-2
According to the setting value of CNTR0 active edge switch bit,
the interrupt request bit may be set to “1”.
ꢀ Notes on Input Capture
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
• If the capture trigger is input while the capture register (low-order
and high-order) is in read, captured value is changed between
high-order reading and low-order reading. Accordingly, some
countermeasure by software is recommended, for example
comparing the values that twice of read.
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the active edge switch bit.
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
• When the ring-oscillator is selected for Timer A count source,
Timer A cannot be used for the capture source timer.
Timer B cannot be used for the capture source timer when the
system is in the following state;
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
ꢀ Notes on Timer A, B
(1) Setting of timer value
• CPU operation clock source: XIN oscillation
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped. Accordingly, in order to set the initial value for timer when
it is stopped, set “0: Write to latch and timer simultaneously” to
timer A (B) write control bit.
• Timer B count source: Timer A underflow
• Timer A count source: Ring oscillator output
• When writing “1” to capture latch x0 (x1) software trigger bit of
capture latch x0 and x1 at the same time, or external trigger and
software trigger occur simultaneously, the set value of capture x
status bit is undefined.
(2) Read/write of timer A
• When setting the interrupt active edge selection bit and noise fil-
ter clock selection bit of external interrupt CAP0, CAP1, the
interrupt request bit may be set to “1”.
Stop timer A to read/write its data when the system is in the follow-
ing state;
• CPU operation clock source: XIN oscillation
• Timer A count source: Ring oscillator output
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀ Set the corresponding interrupt enable bit to “0” (disabled).
ꢀ Set the interrupt edge selection bit or noise filter clock selection bit.
ꢀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
(3) Read/write of timer B
Stop timer B to read/write its data when the system is in the fol-
lowing state;
• CPU operation clock source: XIN oscillation
• Timer B count source: Timer A underflow
• Timer A count source: Ring oscillator output
ꢀ Set the corresponding interrupt enable bit to “1” (enabled).
• The capture interrupt cannot be used as the interrupt for return
from stop mode. Even when the valid edge of the capture inter-
rupt is input at stop mode, system retains the stop mode. Then,
system returns from stop mode by other external interrupts, the
capture interrupt is accepted.
In this case, after system returns from stop mode, the interrupt
request bit of the corresponding capture interrupt is set to “1”.
62
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Notes on Serial I/O1
• Serial I/O interrupt
ꢀ Notes on Serial I/O2
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
ꢀ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
• I/O pin function when serial I/O2 is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
The functions of P06 and P07 are switched with the setting values
of a serial I/O2 mode selection bit and a serial I/O2 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
(1) Serial I/O2 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
Clock synchronous type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0” : P06 pin turns into an output pin of a synchronous clock.
“1” : P06 pin turns into an input pin of a synchronous clock.
Setup of a SRDY2 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY1 output pin.
“0” : P07 pin can be used as a normal I/O pin.
“1” : P07 pin turns into a SRDY2 output pin.
(2) Serial I/O1 mode selection bit → “0” :
(2) Serial I/O2 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O2 synchronous clock selection bit
“0”: P06 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
“1”: P06 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P07 pin. It can be used as a normal I/O pin.
• Bus collision detection
ꢀ A-D Converter
Bus collision detection can be used when SIO1 is operating at full-
duplex communication. When SIO1 is operating at half-duplex
communication, set bus collision detection interrupt to be dis-
abled.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
63
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
ꢀ Notes on Oscillation Stop Detection Circuit
• When the oscillation stop reset bit is set to “0”, internal reset
does not occur. If the ceramic or RC oscillation is selected for
the CPU clock, MCU will be locked when the ceramic or RC os-
cillation is stopped. So when the ceramic or RC oscillation is
selected for the main clock, set the oscillation stop reset bit to
“1”. (State 2’a of Fig. 81)
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is se-
lected by setting bit 5 of the CPU mode register.
• Ceramic or RC oscillation stop detection function active bit is not
cleared by the oscillation stop internal reset. Accordingly, the
oscillation stop detection circuit is in active when system is re-
leased from internal reset cause of oscillation stop detection.
• Oscillation stop detection status bit is initialized by the following
operation.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
(1) External reset
• CPU mode register
(2) Write “0” data to the ceramic or RC oscillation stop detection
function active bit.
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37542RSS” is excluded.)
• The oscillation stop detection circuit is not included in the emu-
lator MCU “M37542RSS”.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
• Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 79 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 79.
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
* For the mask ROM confirmation, ROM programming order con-
firmation and the mark specifications, refer to the “Mitsubishi
MCU Technical Information” Homepage
ꢀ Notes on Ring Oscillation Division Ratio
• When system is released from reset, ROSC/8 (ring middle-speed
mode) is selected for CPU clock.
(http://www.infomicom.maec.co.jp/indexe.htm).
•
When state transition from the ceramic or RC oscillation to ring oscil-
lator, ROSC/8 (ring middle-speed mode) is selected for CPU clock.
• When the MCU operates by ring-oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
Set “10010x002” (x = 0 or 1) to CPUM.
64
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
36P2R-A
Plastic 36pin 450mil SSOP
EIAJ Package Code
SSOP36-P-450-0.80
JEDEC Code
–
Weight(g)
0.53
Lead Material
Alloy 42
e
b2
36
19
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.35
0.13
14.8
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
1
18
1
2
A
2.0
0.4
0.15
15.0
8.4
0.8
11.93
0.5
1.765
0.7
–
–
D
G
b
0.5
0.2
15.2
8.6
–
12.23
0.7
–
c
D
E
e
H
L
A
2
A1
e
E
b
y
L1
z
–
Z
1
0.85
0.15
10°
–
–
–
y
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
65
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MMP
32P4B
Plastic 32pin 400mil SDIP
EIAJ Package Code
JEDEC Code
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
SDIP32-P-400-1.78
–
32
17
1
16
D
Dimension in Millimeters
Symbol
Min
–
Nom
–
Max
5.08
–
A
A
1
0.51
–
–
3.8
A2
–
b
0.35
0.9
0.63
0.22
27.8
8.75
–
–
3.0
0°
0.45
1.0
0.73
0.27
28.0
8.9
1.778
10.16
–
0.55
1.3
1.03
0.34
28.2
9.05
–
–
–
15°
b1
b2
c
D
E
e
e
b1
b
b2
SEATING PLANE
e1
L
–
66
MITSUBISHI MICROCOMPUTERS
7542 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
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on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2002MITSUBISHI ELECTRIC CORP.
New publication, effective Nov. 2002.
Specifications subject to change without notice.
REVISION HISTORY
7542 GROUP DATA SHEET
Rev.
1.0
Date
Description
Summary
Page
11/27/02
First Edition
(1/1)
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