M38195EB-XXXFS [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38195EB-XXXFS |
| 厂家： | 
Mitsubishi Group |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总60页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT MICROCOMPUTER
●D-A converter ................................................. 8-bit ✕ 1 channels
●Zero cross detection input............................................ 1 channel
●Fluorescent display function
DESCRIPTION
The 3819 group is a 8-bit microcomputer based on the 740 family
core technology.
Segments ........................................................................ 16 to 42
Digits.................................................................................. 6 to 16
●2 Clock generating circuit
The 3819 group has a flourescent display automatic display circuit
and an 16-channel 8-bit A-D converter as additional functions.
The various microcomputers in the 3819 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Clock (XIN-XOUT) ................................. Internal feedback resistor
Sub-clock (XCIN-XCOUT) .........Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscil-
lator)
For details on availability of microcomputers in the 3819 group, re-
fer to the section on group expansion.
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8.4 MHz oscillation frequency and high-speed selected)
In middle-speed mode............................................... 2.8 to 5.5 V
(at 8.4 MHz oscillation frequency)
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ......................... 0.48 µs
(at 8.4 MHz oscillation frequency)
In low-speed mode .................................................... 2.8 to 5.5 V
(at 32 kHz oscillation frequency)
●Memory size .................................................................................
ROM ............................................. 4K to 60 K bytes
●Power dissipation
RAM ........................................... 192 to 2048 bytes
In high-speed mode ..........................................................35 mW
(at 8.4 MHz oscillation frequency)
●Programmable input/output ports ............................................ 54
●High-breakdown-voltage output ports ...................................... 52
●Interrupts ................................................. 20 sources, 16 vectors
●Timers ............................................................................. 8-bit ✕ 6
●Serial I/O (Serial I/O1 has an automatic transfer function)
...................................................... 8-bit ✕ 3(clock-synchronized)
●PWM output circuit ............... 8-bit ✕ 1(also functions as timer 6)
●A-D converter ............................................... 8-bit ✕ 16 channels
In low-speed mode ............................................................ 60 µW
(at 3 V power source voltage and 32 kHz oscillation frequency )
●Operating temperature range .................................... –10 to 85°C
APPLICATION
Musical Instruments, household appliance, etc.
PIN CONFIGURATION (TOP VIEW)
81
50
P8
P8
P8
P8
P8
P8
P8
P8
PA
PA
7
6
5
4
3
2
/SEG15
/SEG14
/SEG13
/SEG12
/SEG11
/SEG10
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
/DIG14
/DIG15
/DIG16
/DIG17
/DIG18
/DIG19
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1
0
7
6
/SEG
/SEG
/SEG
/SEG
9
8
7
6
M38197MA-XXXFP
V
CC
V
X
X
SS
PA
PA
PA
PA
PA
PA
5
4
3
2
1
0
/SEG
/SEG
/SEG
/SEG
/SEG
/SEG
5
4
3
2
1
0
OUT
IN
PB
0
1
/XCOUT
/XCIN
PB
RESET
P40
P41
P42
P43
/INT
0
V
EE
AVSS
/INT
/INT
2
3
VREF
Package type : 100P6S-A
100-pin plastic-molded QFP
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2
I N T
0
I N T
c i r c u i t
d e t e r m i n a t i o n
I n t e r r u p t i n t e r v a l
4
, 3 I N T I N T
d e t e c t i o n c i r c u i t
Z e r o c r o s s
/ Z 1 C R I N T
2
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
VCC, VSS
VEE
Name
Function
Function except a port function
Power source
•Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS.
Pull-down
Power source
•Applies voltage supplied to pull-down resistors of ports P0, P1, P20–P23, P3, and P9.
Analog reference
voltage
VREF
•Reference voltage input pin for A-D converter and D-A converter
•GND input pin for A-D converter and D-A converter
•Connect AVSS to VSS.
Analog power source
Reset input
AVSS
•Reset input pin for active “L”
RESET
•Input and output pins for the main clock generating circuit
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN pin and XOUT pin to
set oscillation frequency.
XIN
Clock input
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.
Clock output
XOUT
•This clock is used as the oscillating source of system clock.
•8-bit output port
•This port builds in pull-down resistor between
port P0 and the VEE pin.
•At reset this port is set to VEE level.
•The high-breakdown-voltage P-channel
open-drain
P00/SEG32/
DIG0–P07/
SEG39/DIG7
Output port P0
FLD automatic display pins
P10/SEG40/
DIG8–P17/
DIG15
•8-bit output port with the same function as
FLD automatic display pins
port P0
Output port P1
Output port P2
•4-bit output port with the same function as
FLD automatic display pins
port P0
P20/DIG16–
P23/DIG19
•4-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•At reset this port is set to input mode.
•TTL input level
I/O port P2
P24–P27
•CMOS 3-state output
•8-bit output port with the same function as
P30/SEG24–
P37/SEG31
Output port P3
Input port P4
FLD automatic display pins
port P0
P40/INT0,
P45/INT1/
ZCR
•2-bit input port
•CMOS compatible input level
External interrupt input pins
A zero cross detection circuit input pin (P45)
P42/INT2–
P44/INT4
•6-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
P41
I/O port P4
P46/T1OUT,
P47/T3OUT
Timer output pins
3
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Continued)
Pin
Name
Function
Function except a port function
P50/SIN2/AN8,
Serial I/O2 function pins
A-D conversion input pins
P51/SOUT2/AN9,
P52/SCLK2/AN10,
P53/SRDY2/AN11
•8-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
I/O port P5
P54/SIN3/AN12,
P55/SOUT3/AN13,
P56/SCLK3/AN14,
P57/SRDY3/AN15
Serial I/O3 function pins
A-D conversion input pins
P60
P61/PWM
PWM output pin (Timer output pin)
Timer input pins
•8-bit CMOS I/O port with the same function
as ports P24–P47
•CMOS compatible input level
•CMOS 3-state output
P62/CNTR0,
P63/CNTR1
I/O port P6
P64/SIN1,
P65/SOUT1,
P66/SCLK11,
P67/SRDY1/CS/
SCLK12
Serial I/O1 function pins
•8-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
P70/AN0–
P77/AN7
I/O port P7
A-D conversion input pins
•8-bit I/O port with the same function as ports
P24–P27
•CMOS compatible input level
•The high-breakdown-voltage P-channel
open-drain
P80/SEG8–
P87/SEG15
I/O port P8
•8-bit output port with the same function as
port P0
P90/SEG16–
P97/SEG23
Output port P9
I/O port PA
FLD automatic display pins
•8-bit I/O port with the same function as ports
P24–P27
•CMOS compatible input level
•The high-breakdown voltage P-channel open-
drain
PA0/SEG0–
PA7/SEG7
I/O pins for sub-clock generating circuit (con-
nect a ceramic resonator or a quarts-crystal
oscillator)
PB0/XCOUT,
PB1/XCIN
•4-bit CMOS I/O port with the same function
as ports P24–P27
•CMOS compatible input level
•CMOS 3-state output
I/O port PB
PB2/DA
PB3
D-A conversion output pin
4
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3819
7
M
A
XXX FP
Package type
FP : 100P6S-A package
FS : 100D0 package
ROM number
Omitted in some types.
ROM/PROM size
: 4096 bytes
1
2 : 8192 bytes
: 12288 bytes
: 16384 bytes
3
4
5 : 20480 bytes
: 24576 bytes
: 28672 bytes
6
7
8 : 32768 bytes
: 36864 bytes
: 40960 bytes
9
A
B : 45056 bytes
: 49152 bytes
: 53248 bytes
C
D
E : 57344 bytes
: 61440 bytes
F
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
Memory type
M
E
: Mask ROM version
: EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
5
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Packages
GROUP EXPANSION
100P6S-A........................... 0.65 mm-pitch plastic molded QFP
100D0........................... Ceramic LCC(built-in EPROM version)
Mitsubishi plans to expand the 3819 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM ver-
sions
ROM/PROM capacity .................................. 40 K to 60 K bytes
RAM capacity .............................................. 1024 to 2048 bytes
Memory Expansion Plan
Under development
M38199MF/EF
ROM size (bytes)
60K
56K
52K
48K
Mass product
M38198MC/EC
44K
Mass product
40K
36K
32K
28K
24K
20K
16K
12K
8K
M38197MA
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Products under development : the development schedule and specifications may be revised without notice.
Currently supported products are listed below.
(P) ROM size (bytes)
As of May 1996
Product
RAM size (bytes)
1024
Package
Remarks
ROM size for User in (
)
Mask ROM version
M38197MA-XXXFP
M38197MA-XXXKP
M38198MC-XXXKP
M38199MF-XXXKP
M38198MC-XXXFP
M38198EC-XXXFP
M38198ECFP
100P6S-A
40960
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
(40830)
100P6P-E
49152
100P6S-A
100D0
1536
2048
(49022)
One Time PROM version (blank)
EPROM version
M38198ECFS
Mask ROM version
M38199MF-XXXFP
M38199EF-XXXFP
M38199EFFP
61440
One Time PROM version
One Time PROM version (blank)
EPROM version
100P6S-A
100D0
(61310)
M38199EFFS
6
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CPU Mode Register
Central Processing Unit (CPU)
The CPU mode register is allocated at address 003B16. The CPU
mode register contains the stack page selection bit and the inter-
nal system clock selection bit.
The 3819 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
X
COUT drivability selection bit
0 : Low drive
1 : High drive
Port XC switch bit
0 : I/O port function
1 : XCIN-XCOUT oscillating function
Main clock (XIN-XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN-XOUT selected (middle/high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
Fig. BA-1 Structure of CPU mode register
7
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Zero page
Special function register (SFR) area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the reset is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
000016
RAM area
SFR area
Zero
RAM capacity
Address XXXX16
(bytes)
004016
010016
page
192
256
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
RAM
384
512
640
XXXX16
768
896
Reserved area
1024
1536
2048
044016
Not used
RAM area for serial I/O automatic transfer
Not used
0F0016
0F1F16
ROM area
0F8016
0FDF16
RAM area for FLD automatic display
Not used
ROM capacity
(bytes)
Address YYYY16
Address ZZZZ16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
YYYY16
ZZZZ16
Reserved ROM area
(common ROM area,128 bytes)
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
RO
M
FF0016
FFDC16
Special
page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. CA-1 Memory map
8
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 Port P0 (P0)
002016 Timer 1 (T1)
000116
000216 Port P1 (P1)
002116 Timer 2 (T2)
002216 Timer 3 (T3)
000316
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
002316 Timer 4 (T4)
002416 Timer 5 (T5)
002516 Timer 6 (T6)
000616 Port P3 (P3)
000716
002616 Serial I/O3 register (SIO3)
002716 Timer 6 PWM register (T6PWM)
000816 Port P4 (P4)
000916 Port P4 direction register (P4D)
000A16 Port P5 (P5)
002816 Timer 12 mode register (T12M)
002916 Timer 34 mode register (T34M)
002A16
Timer 56 mode register (T56M)
000B16 Port P5 direction register (P5D)
000C16 Port P6 (P6)
002B16
002C16
D-A conversion register (DA)
AD-DA control register (ADCON)
000D16 Port P6 direction register (P6D)
002D16
A-D conversion register (AD)
000E16 Port P7 (P7)
000F16 Port P7 direction register (P7D)
002E16
002F16
001016 Port P8 (P8)
003016 Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
001116 Port P8 direction register (P8D)
003116
001216
003216 Port P0 segment/digit switch register (P0SDR)
Port P9 (P9)
001316
001416
003316 Port P2 digit/port switch register (P2DPR)
003416 Port P8 segment/port switch register (P8SPR)
Port PA (PA)
001516
003516
Port PA direction register (PAD)
Port PB (PB)
Port PA segment/port switch register (PASPR)
FLDC mode register 1 (FLDM1)
001616
001716
003616
003716 FLDC mode register 2 (FLDM2)
Port PB direction register (PBD)
Serial I/O automatic transfer data pointer (SIODP)
001816
003816
003916
FLD data pointer (FLDDP)
Zero cross detection control register (ZCRCON)
001916 Serial I/O1 control register (SIO1CON)
001A16 Serial I/O automatic transfer control register (SIOAC)
003A16 Interrupt edge selection register (INTEDGE)
001B16 Serial I/O1 register (SIO1)
003B16 CPU mode register (CPUM)
Serial I/O automatic transfer interval register (SIOAI)
001C16
003C16 Interrupt request register 1 (IREQ1)
001D16
003D16 Interrupt request register 2 (IREQ2)
Serial I/O2 control register (SIO2CON)
001E16 Serial I/O3 control register (SIO3CON)
001F16
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
Serial I/O2 register (SIO2)
Fig. CA-2 Memory map of special function register (SFR)
9
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-break-
down-voltage pins (ports P0, P1, P20–P23, P3, P8, P9, PA). The
high-breakdown-voltage ports have P-channel open-drain output
with VCC –40 V of breakdown voltage.
Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O
ports (ports P24–P27, P41–P44, P46, P47, P5–P8, PA, and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, each pin can be set to be input or
output.
Each pin in ports P0, P1, P20–P23, P3, and P9 has an internal
pull-down resistor connected to VEE. Ports P8 and PA have no in-
ternal pull-down resistors, so that connect an external resistor to
each port. At reset, the P-channel output transistor of each port
latch is turned off, so it becomes VEE level (“L”) by the pull-down
resistor.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port latch is read, not the value of the pin itself. A pin which is set
for input the value of the pin itself is read because the pin is in
floating state. If a pin set for input is written to, only the port latch
is written to and the pin remains floating.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register 1
(address 003616) shows the rising transition of the output transis-
tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register 1 is set to “0” (strong drivability).
Diagram
No.
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
FLDC mode register 1
FLDC mode register 2
Port P0
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
P00/SEG32/
DIG0–
FLD automatic dis-
play function
(1)
Output
Port P0
P07/SEG39/
DIG7
segment/digit
switch register
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
P10/SEG40/
DIG8–
FLDC mode register 1
FLDC mode register 2
FLD automatic dis-
play function
(1)
(2)
Output
Output
Port P1
Port P2
Port P3
P17/DIG15
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
FLDC mode register 1
FLDC mode register 2
P20/DIG16–
P23/DIG19
FLD automatic dis-
play function
(3)
(4)
Port P2 digit/port
switch register
Input/output,
individual bits
TTL level input
CMOS 3-state output
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
P24–P27
P30/SEG24–
P37/SEG31
FLD automatic dis- FLDC mode register 1
Output
Input
(5)
(6)
play function
FLDC mode register 2
P40/INT0
P45/INT1/
ZCR
External interrupt
Interrupt edge
CMOS compatible
input level
input
selection register
Zero cross detec-
Zero cross detection
tion circuit input
control register
P42/INT2–
P44/INT4
P41
Port P4
(7)
(4)
(8)
(P45)
CMOS compatible
input level
Input/output,
individual bits
CMOS 3-state output
Timer 12 mode register
Timer output
P46/T1OUT,
P47/T3OUT
Timer 34 mode register
10
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Diagram
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
No.
(9)
P50/SIN2/
AN8
Serial I/O2 control
register
P51/SOUT2/
AN9,
Serial I/O2 func-
tion I/O
(10)
AD/DA control regis-
ter
A-D conversion in-
put
P52/SCLK2/
AN10
P53/SRDY2/
AN11
CMOS compatible
input level
(11)
(9)
Port P5
CMOS 3-state output
P54/SIN3/
AN12
P55/SOUT3/
AN13,
Serial I/O3 control
register
Serial I/O3 func-
tion I/O
(10)
AD/DA control regis-
ter
A-D conversion in-
put
P56/SCLK3/
AN14
P57/SRDY3/
AN15
(11)
(4)
Input/output,
individual bits
P60
Timer 56 mode regis-
ter
PWM (timer) out-
put
P61/PWM
(8)
P62/CNTR0,
P63/CNTR1
P64/SIN1
Interrupt edge selec-
tion register
Timer input
(7)
CMOS compatible
input level
Port P6
(9)
CMOS 3-state output
Serial I/O1 control
register
P65/SOUT1,
P66/SCLK11
P67/SRDY1/
CS/SCLK12
(10)
Serial I/O1 func-
tion I/O
Serial I/O automatic
transfer control regis-
ter
(11)
(12)
CMOS compatible
input level
P70/AN0–
P77/AN7
AD/DA control regis-
ter
A-D conversion in-
put
Port P7
Port P8
CMOS 3-state output
CMOS compatible
input level
FLDC mode register
Segment/port switch
register
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
P80/SEG8–
P87/SEG15
(13)
FLD automatic
display function
High-breakdown-
voltage P-channel
open-drain output
with pull-down
resistor
P90/SEG16–
P97/SEG23
Output
FLDC mode register
Port P9
Port PA
(5)
CMOS compatible
input level
FLDC mode register
Segment/port switch
register
PA0/SEG0–
PA7/SEG7
Input/output,
individual bits
(13)
High-breakdown-
voltage P-channel
open-drain output
PB0/XCOUT,
PB1/XCIN
I/O for sub-clock
generating circuit
(14)
(15)
CPU mode register
CMOS compatible
input level
Input/output,
individual bits
Port PB
D-A conversion AD/DA control regis-
output ter
(16)
(4)
PB2/DA
PB3
CMOS 3-state output
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-
tial, a current will flow from VCC to VSS through the input-stage gate.
11
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P1
0
, P1
1
Shift signal from previous stage
S/D switch register
Blanking signal
for key-scan
Dimmer signal
(Note)
✽
Data bus
Port latch
Local data bus
V
EE
Shift signal to next stage
(2) Ports P12–P17
Shift signal from previous stage
Dimmer signal
(Note)
✽
Port latch
Data bus
VEE
Shift signal to next stage
(3) Ports P20–P23
Shift signal from previous stage
D/P switch register
Dimmer signal
(Note)
✽
Port latch
Data bus
Blanking signal
for key-scan
V
EE
Shift signal to next stage
(4) Ports P24–P27, P41, P60, PB3
Direction
register
Data bus
Port latch
✽: High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. UA-2 Port block diagram (1)
12
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(5) Ports P3, P9
Dimmer signal
(Note)
Local data bus
Data bus
✽
Port latch
VEE
(6) Ports P40, P45
Data bus
INT
0
, INT
1
interrupt input
Zero cross
detection
circuit
input
(only P4
5)
(7) Ports P42–P44, P62, P63
Direction
register
Data bus
Port latch
INT
2
–INT
4
interrupt input
CNTR0,CNTR1 input
(8) Ports P46, P47, P61
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Direction
register
Data bus
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
✽: High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. UA-3 Port block diagram (2)
13
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P50, P54, P64
Direction
register
Data bus
Port latch
Serial I/O input
A-D conversion input
Analog input pin selection bit
(10) Ports P51, P52, P55, P56, P65, P66
P-channel output disable signal
Output OFF control signal
Serial I/O port selection bit
Direction
register
Data bus
Port latch
SOUT or SCLK
Serial clock input
(only P5
A-D conversion input
Analog input pin selection bit
2, P56, P66)
(11) Ports P53, P57, P67
S
RDY output enable bit
Direction
register
Data bus
Port latch
Serial ready output
or SCLK
CS input
(only P6
A-D conversion input
7
)
Analog input pin selection bit
(12) Port P7
Direction
register
Data bus
Port latch
A-D conversion input
Analog input pin selection bit
Fig. UA-4 Port block diagram (3)
14
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P8, PA
S/P switch register
Dimmer signal
(Note)
Directionregister
Local
data bus
✽
Port latch
Data bus
rea
d
(14) Port PB0
Port XC switch
bit
Direction
register
Data bus
Port latch
Oscillation circuit
Port PB1
Port XC switch bit
(15) Port PB1
Port XC switch
bit
Direction
register
Data bus
Port latch
Sub-clock generating circuit input
(16) Port PB2
Direction
register
Port latch
Data bus
D-A conversion output
D-A output enable bit
✽: High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. UA-5 Port block diagram (4)
15
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt Operation
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft-
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering. The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Notes on Use
When the active edge of an external interrupt (INT0 to INT4) is
changed or when switching interrupt sources in the same vector
address, the corresponding interrupt request bit may also be set.
Therefore, please take following sequence;
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit.
The I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
(1) Disable the external interrupt which is selected.
(2) Change the active edge.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Remarks
Interrupt Source
Priority
Generating Conditions
High
Low
FFFD16
FFFC16
At reset
Reset (Note 2)
INT0
1
2
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt (active edge
selectable)
FFFB16
FFF916
FFFA16
FFF816
At detection of either rising or
falling edge of INT1/ZCR input
External interrupt (active edge
selectable)
INT1/ZCR
INT2
3
4
At detection of either rising or
falling edge of INT2 input
External interrupt (active edge
selectable)
FFF716
FFF516
FFF616
FFF416
Valid when interrupt interval
determination is operating
Remote control/
counter overflow
At 8-bit counter overflow
Valid when serial I/O ordinary
mode is selected
At completion of data transfer
Serial I/O1
5
Valid when serial I/O automatic
transfer mode is selected
Serial I/O
automatic transfer
At completion of the last data
transfer
Valid when serial I/O2 is se-
lected
At completion of data transfer
At completion of data transfer
6
7
FFF316
FFF116
FFF216
FFF016
Serial I/O2
Serial I/O3
Valid when serial I/O3 is se-
lected
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
STP release timer underflow
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
8
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
9
10
11
12
13
At detection of either rising or External interrupt (active edge
INT3
14
FFE316
FFE216
falling edge of INT3 input
selectable)
Valid when INT4 interrupt is
selected
External interrupt (active
edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
15
FFE116
FFE016
At completion of A-D conver-
sion
Valid when A-D conversion in-
terrupt is selected
A-D conversion
FLD blanking
At falling edge of the last digit
immediately before blanking
period starts
Valid when FLD blanking in-
terrupt is selected
16
17
FFDF16
FFDD16
FFDE16
FFDC16
Valid when FLD digit interrupt
is selected
At rising edge of each digit
At BRK instruction execution
FLD digit
Non-maskable software inter-
rupt
BRK instruction
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
16
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. DD-1 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
INT
0
1
2
3
4
interrupt edge selection bit
/ZCR interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
0 : INT4 interrupt
INT
4
/AD conversion interrupt switch bit
1 : A-D conversion interrupt
CNTR
CNTR
0
1
pin active edge switch bit
pin active edge switch bit
0 : Rising edge count
1 : Falling edge count
b7
b0
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16
Interrupt request register 2
(IREQ2 : address 003D16
)
)
INT
INT
INT
0
1
2
interrupt request bit
/ZCR interrupt request bit
interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Remote control/counter overflow
interrupt request bit
Serial I/O1 interrupt request bit
Serial I/O automatic transfer
interrupt request bit
Serial I/O2 interrupt request bit
Serial I/O3 interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
INT
INT
3
interrupt request bit
interrupt request bit
4
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON2 : address 003F16)
(ICON1 : address 003E16
)
INT
INT
INT
0
1
2
interrupt enable bit
/ZCR interrupt enable bit
interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Remote control/counter overflow
interrupt enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer
interrupt enable bit
Serial I/O2 interrupt enable bit
Serial I/O3 interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
INT
INT
3
interrupt enable bit
interrupt enable bit
4
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. DD-2 Structure of interrupt-related registers
17
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6.
Each timer has the 8-bit timer latch. The timers count down.
Once a timer reaches 0016, at the next count pulse the contents of
each timer latch is loaded into the corresponding timer, and sets
the corresponding interrupt request bit to “1”.
The count can be stopped by setting the stop bit of each timer to
“1”. The internal clock φ can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(XIN) or f(XCIN).
Timer 1 and Timer 2
The count sources of timer 1 and timer 2 can be selected by set-
ting the timer 12 mode register. A rectangular waveform of timer 1
underflow signal divided by 2 is output from the P46/T1OUT pin.
The waveform polarity changes each time timer 1 overflows. The
active edge of the external clock CNTR0 can be switched with the
bit 6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer
12 mode register are cleared to “0”, timer 1 is set to “FF16”, and
timer 2 is set to “0116”.
Timer 3 and Timer 4
The count sources of timer 3 and timer 4 can be selected by set-
ting the timer 34 mode register. A rectangular waveform of timer 3
underflow signal divided by 2 is output from the P47/T3OUT pin.
The waveform polarity changes each time timer 3 overflows.
The active edge of the external clock CNTR1 can be switched with
the bit 7 of the interrupt edge selection register.
Timer 5 and Timer 6
The count sources of timer 5 and timer 6 can be selected by set-
ting the timer 56 mode register.
A rectangular waveform of timer 6 underflow signal divided by 2 is
output from the P61/PWM pin. The waveform polarity changes
each time timer 6 overflows.
Timer 6 PWM Mode
Timer 6 can output a rectangular waveform with duty cycle n/(n +
m) from the P61/PWM pin by setting the timer 56 mode register
(refer to fig. FB-3). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM out-
put is “H”(n=0 is prior than m=0). In the PWM mode, interrupts
occur at the rising edge of the PWM output.
18
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Timer 1
count
XCIN
Timer 1 latch (8)
RESET
Internal system
clock selection
bit
source
selection bit
“1”
“0”
FF16
STP instruction
Timer 1 interrupt request
“1”
“0”
Timer 1 (8)
1/16
XIN
Timer 1
count stop
bit
P46/T1OUT
P46 latch
1/2
Timer 1 output
selection bit
Timer 2
count
Timer 2 latch (8)
source
selection bit
“00”
“01”
P46 direction register
0116
Timer 2 (8)
Timer 2 interrupt request
Timer 2
“10”
count stop
bit
Rising/falling
edge switch
P62/CNTR0
Timer 3
count
Timer 3 latch (8)
Timer 3 (8)
source
selection bit
“1”
“0”
Timer 3 interrupt request
P47/T3OUT
P47 latch
1/2
Timer 3
count stop bit
Timer 3 output
selection bit
Timer 4
count
Timer 4 latch (8)
Timer 4 (8)
source
selection bit
“01”
Timer 4 interrupt request
P47 direction register
“00”
“10”
Timer 4
count stop
bit
Rising/falling
edge switch
P63/CNTR1
Timer 5
count
Timer 5 latch (8)
Timer 5 (8)
source
selection bit
“1”
“0”
Timer 5 interrupt request
Timer 5
count stop bit
Timer 6
count
Timer 6 latch (8)
Timer 6 (8)
source
selection bit
“01”
Timer 6 interrupt request
“00”
“10” Timer 6
count stop
bit
Timer 6 PWM register (8)
P61 latch
P61/PWM
PWM
“1”
“0”
1/2
Timer 6 output
selection bit
Timer 6 operating
mode selection bit
P61 direction register
Fig. FB-1 Timer block diagram
19
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Timer 12 mode register
(T12M : address 002816
Timer 34 mode register
(T34M : address 002916)
)
Timer 1 count stop bit
0 : Operating
Timer 3 count stop bit
0 : Operating
1 : Stopped
1 : Stopped
Timer 2 count stop bit
0 : Operating
Timer 4 count stop bit
0 : Operating
1 : Stopped
1 : Stopped
Timer 1 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
Timer 3 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
1 : Timer 2 underflow
1 : f(XCIN
)
Not used (returns “0” when read)
Timer 2 count source selection bits
b5 b4
Not used (returns “0” when read)
Timer 4 count source selection bits
b5 b4
0
0
1
1
0 : Timer 1 underflow
1 : f(XCIN
0 : External count input CNTR
1 : Not available
0
0
1
1
0 : f(XIN)/16 or f(XCIN)/16
1 : Timer 3 underflow
0 : External count input CNTR
1 : Not available
)
0
1
Timer 1 output selection bit (P4
0 : I/O port
6
)
Timer 3 output selection bit (P4
0 : I/O port
7)
1 : Timer 1 output
1 : Timer 3 output
Not used (returns “0” when read)
Not used (returns “0” when read)
b7
b0
Timer 56 mode register
(T56M : address 002A16
)
Timer 5 count stop bit
0 : Operating
1 : Stopped
Timer 6 count stop bit
0 : Operating
1 : Stopped
Timer 5 count source selection bit
0 : f(XIN)/16 or f(XCIN)/16
1 : Timer 4 underflow
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
b5 b4
0
0
1
1
0 : f(XIN)/16 or f(XCIN)/16
1 : Timer 5 underflow
0 : Timer 4 underflow
1 : Not available
Timer 6 (PWM) output selection bit (P61)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(do not write “1”)
Fig. FB-2 Structure of timer-related registers
20
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer 6
count
source
Timer 6
PWM output
n ✕ ts
m ✕ ts
(n + m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: If the value set in timer 6 is n and the value set in the timer 6 PWM register is m, a PWM waveform with
duty cycle n/(n + m) and period (n + m) 5 ts (ts : the frequency of the timer 6 count source) is output.
Fig. FB-3 Timing in timer 6 PWM mode
21
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 3819 group has built-in 8-bit clock synchronized serial I/O ✕ 3
channels (serial I/O1, serial I/O2, and serial I/O3).
Serial I/O1 builds in the automatic transfer function. The function
can be switched to the serial I/O ordinary mode with the serial I/O
automatic transfer control register (address 001A16).
Serial I/O2 and Serial I/O3 can be used only in the serial I/O ordi-
nary mode.
The I/O pins of the serial I/O function are also used as I/O ports
P5 and P64–P67, and their operation is selected with the serial I/O
control registers (addresses 001916, 001D16, and 001E16).
Serial I/O Control Registers
(SIO1CON, SIO2CON, SIO3CON)
001916, 001D16, 001E16
Each of the serial I/O control registers (addresses 001916,
001D16, and 001E16) consists of 8 selection bits which control the
serial I/O function.
22
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Main
Local
Main data Local data
SI/O automatic
transfer RAM
address bus address bus
bus
bus
(0F0016 to 0F1F16)
SI/O automatic
transfer data
pointer
Address decorder
SI/O automatic
transfer
Serial I/O automatic
transfer interrupt request
controller
SI/O automatic transfer
interval register
1/8
XCIN
XIN
Internal
1/16
1/32
1/64
1/128
1/256
system clock
selection bit
“1”
“0”
Synchronous
clock selection
bit
P67 latch
“1”
(Note)
P67/SRDY1/
CS/SCLK12
SRDY1
Synchronization
circuit
Internal synchronous
clock selection bit
“0”
CS
External clock
P66 latch
“0”
P66/SCLK11
Serial I/O1
Serial I/O counter 1(3)
“1”
interrupt request
Serial I/O1 port selection bit
“0”
P65 latch
P65/SOUT1
“1”
Serial I/O1 port selection bit
P64/SIN1
Serial I/O shift register 1(8)
1/8
1/16
1/32
1/64
1/128
1/256
Synchronous
P53 latch
“0”
clock selection
bit
“1”
P53/SRDY2
P52/SCLK2
SRDY2
Synchronization
circuit
Internal synchronous
clock selection bit
“1”
SRDY2 output selection bit
External clock “0”
“0”
“1”
P52 latch
Serial I/O2
Serial I/O counter 2(3)
interrupt request
Serial I/O2 port selection bit
“0”
P51 latch
P51/SOUT2
P50/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O shift register 2(8)
1/8
1/16
1/32
1/64
1/128
P57 latch
“0”
1/256
“1”
P57/SRDY3
P56/SCLK3
SRDY3
Synchronization
circuit
Internal synchronous
clock selection bit
“1”
SRDY2 output selection bit
External clock “0”
“0”
“1”
P56 latch
Serial I/O3
Serial I/O counter 3(3)
interrupt request
Serial I/O3 port selection bit
“0”
P55 latch
P55/SOUT3
P54/SIN3
“1”
Serial I/O3 port selection bit
Serial I/O shift register 3(8)
Note:
Selected with the synchronous clock selection bit, SRDY1 output selection bit, serial I/O1 port selection bit (these 3 bits are of the serial
I/O1 control register), automatic transfer control bit, and synchronous clock output pin selection bit (these 2 bits are ofthe serial I/O
automatic transfer register).
Fig. GA-1 Serial I/O block diagram
23
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O1 control register
Serial I/O2 control register
(SIO1CON(SC1) : address 001916
)
(SIO2CON(SC2) : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8 or f(XCIN)/8
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
✽
Serial I/O1 port selection bit (P6
0 : I/O port
1 : SOUT1,SCLK11,and SCLK12 ✽ output pins
5
, P66, and P6
7
)
Serial I/O2 port selection bit (P5
0 : I/O port
1 : SOUT2 and SCLK2 output pins
1, and P52)
SRDY1 output selection bit (P6
7
)
SRDY2 output selection bit (P5
3)
0 : I/O port
1 : SRDY1/CS ✽ output pin (Note)
0 : I/O port
1 : SRDY2 output pin
Transfer direction selection bit
0 : LSB first
Transfer direction selection bit
0 : LSB first
1 : MSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
Synchronous clock selection bit
0 : External clock
1 : Internal clock
1 : Internal clock
P65
/SOUT1 P-channel output disable bit
P51/SOUT2 P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
b7
b0
Serial I/O3 control register
(SIO3CON(SC3) : address 001E16
)
Internal synchronous clock selection bits
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0 : f(XIN)/8 or f(XCIN)/8
1 : f(XIN)/16 or f(XCIN)/16
0 : f(XIN)/32 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/64
0 : f(XIN)/128 or f(XCIN)/128
1 : f(XIN)/256 or f(XCIN)/256
Serial I/O3 port selection bit (P5
0 : I/O port
5 and P56)
1 : SOUT3 and SCLK3 output pins
SRDY3 output selection bit (P5
7)
0 : I/O port
1 : SRDY3 and SCLK3 output pins
Transfer direction selection bit
0 : LSB first
1 : MSB first
Synchronous clock selection bit
0 : External clock
1 : Internal clock
P55/SOUT3 P-channel output disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
✽ : Valid only in serial I/O automatic transfer mode.
Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the SRDY1 signal pin becomes the CS signal input pin.
Fig. GA-2 Structure of serial I/O control registers
24
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
If external clock is selected, control the clock externally be-
cause the contents of the serial I/O register continue to shift
during inputting the transfer clock. In this case, note that the
SOUT pin does not go to high impedance state at the comple-
tion of data transfer.
(1) Serial I/O Ordinary Mode
Either an internal clock or an external clock can be selected
as the synchronous clock for serial I/O transfer. A dedicated
divider is built in as the internal clock for selecting of 6 clocks.
If internal clock is selected, transfer starts with a write signal
to a serial I/O register (addresses 001B16, 001F16, or
002616). After 8 bits have been transferred, the SOUT pin goes
to high impedance state.
The interrupt request bit is set at the completion of the trans-
fer of 8 bits, regardless of whether the internal or external
clock is selected.
Synchronous
clock
Transfer clock
Serial I/O register
write signal
(Note)
Serial I/O output
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D7
S
OUT
Serial I/O input
S
IN
Receive enable
signal
S
RDY
Interrupt request bit set
Note : If internal clock is selected, the SOUT pin goes to high impedance state
at the completion of data transfer.
Fig. GA-3 Serial I/O timing in the serial I/O ordinary mode (for LSB first)
(2) Serial I/O Automatic Transfer Mode
The serial I/O1 has the automatic transfer function. For auto-
b7
b0
matic transfer, switch to the automatic transfer mode by
Serial I/O automatic transfer control register
(SIOAC : address 001A16
)
setting the serial I/O automatic transfer control register (ad-
dress 001A16).
Automatic transfer control bit
0 : Serial I/O ordinary mode
(serial I/O1 interrupt)
The following memory spaces and registers used to enable
automatic transfer mode:
1 : Automatic transfer mode
(serial I/O1 automatic transfer interrupt)
Automatic transfer start bit
0 : Transfer completion
1 : Transferring(starts by writing “1”)
Transfer mode switch bit
0 : Fullduplex(transmit and receive)
mode
1 : Transmit-only mode
Synchronous clock output
pin selection bit
0 : SCLK11
1 : SCLK12
• 32-byte serial I/O automatic transfer RAM
• A serial I/O automatic transfer control register
• A serial I/O automatic transfer interval register
• A serial I/O automatic transfer data pointer
When using serial I/O automatic transfer, set the serial I/O1
control register (address 001916) in the same way as the se-
rial I/O ordinary mode. However, note that when external
clock is selected, port P67 becomes the CS input pin by set-
ting the bit 4 (the SRDY1 output selection bit ) of the serial I/O1
control register to “1”.
Not used (return “0” when read)
Serial I/O Automatic Transfer Control Register
(SIOAC) 001A16
Fig. GA-4 Structure of serial I/O automatic transfer control register
The serial I/O automatic transfer control register (address 001A16)
consists of 4 bits which control automatic transfer.
25
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Automatic Transfer Data Pointer
(SIODP) 001816
● Setting of Serial I/O Automatic Transfer
Data
The serial I/O automatic transfer data pointer (address 001816)
consists of 5 bits which indicate addresses in serial I/O automatic
transfer RAM (the value which adds 0F0016 to the serial I/O auto-
matic transfer data pointer is actual address in memory).
Set the value (the number of transfer data-1) to the serial I/O au-
tomatic transfer data pointer for specifying the storage address of
first data.
When data is stored in the serial I/O automatic transfer RAM,
store the first data at the address set with the serial I/O auto-
matic transfer data pointer so that the last data can be stored
at address 0F0016.
Serial I/O Automatic Transfer Interval Register
(SIOAI) 001C16
The serial I/O automatic transfer interval register (address
001C16) consists of a 5-bit counter that determines the transfer in-
terval Ti during automatic transfer.
● Serial I/O Automatic Transfer RAM
The serial I/O automatic transfer RAM is the 32 bytes from ad-
dress 0F0016 to address 0F1F16.
When writing the value n to the serial I/O automatic transfer inter-
val register, Ti=(n+2) ✕ Tc (Tc: the length of one bit of the transfer
clock) occurs. However, note that this transfer interval setting is
valid only when selecting the internal clock as the clock source.
Bit
5
4
3
2
1
0
7
6
Address
0F0016
0F0116
0F0216
0F1D16
0F1E16
0F1F16
Fig. GA-5 Bit allocation of serial I/O automatic transfer RAM
Transfer clock
Serial I/O output
DO
0
DO
1
DO
2
DO
3
DO
4
DO5
DO
6
DO7
S
OUT
Serial I/O input
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI7
S
IN
T
C
1-byte data
T
i
Fig. GA-6 Serial I/O automatic transfer interval timing
26
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
● Setting of Serial I/O Automatic Transfer
Timing
(2.1) Operation in Full Duplex Mode
In full duplex mode, data can be transmitted and received at the
same time. Data in the automatic transfer RAM is transmitted in
sequence in accordance with the serial I/O automatic transfer data
pointer and simultaneously reception data is written to the auto-
matic transfer RAM.
The timing of serial I/O automatic transfer is set with the serial
I/O1 control register (address 001916) and the serial I/O auto-
matic transfer interval register (address 001C16).
The serial I/O1 control register sets the transfer clock speed,
and the serial I/O automatic transfer interval register sets the
serial I/O automatic transfer interval. This setting of transfer in-
terval is valid only when selecting the internal clock as the
clock source.
The transfer timing of each bit is the same as that in ordinary op-
eration mode, and the transfer clock stops at “H” after eight
transfer clocks are counted.
When selecting the internal clock, the transfer clock remains at “H”
for the time set with the serial I/O automatic transfer interval regis-
ter, then the data at the next address (the address is indicated with
the serial I/O automatic transfer data pointer) are transferred.
If when selecting the external clock, the setting of the automatic
transfer interval register is invalid, so control the transfer clock ex-
ternally.
● Start of Serial I/O Automatic Transfer
Automatic transfer mode is set by writing “1” to the bit 0 of the
serial I/O automatic transfer control register (address 001A16),
then automatic transfer starts by writing “1” to the bit 1.
The bit 1 of the serial I/O automatic transfer control register is
always “1” during automatic transfer; writing “0” can complete
the serial I/O automatic transfer.
The last data transfer completes when the contents of the serial
I/O automatic transfer pointer reach “0016”. At that point, the serial
I/O automatic transfer interrupt request bit is set to “1” and the bit
1 of the serial I/O automatic transfer control register is cleared to
“0” to complete the serial I/O automatic transfer.
● Operation in Serial I/O Automatic Transfer
Modes
There are two modes for serial I/O automatic transfer: full du-
plex mode and transmit-only mode. Either internal or external
clock can be selected for each of these modes.
(2.2) Operation in Transmit-Only Mode
The operation in transmit-only mode is the same as that in full du-
plex mode, except for that data is not transferred from the serial
I/O1 register to the serial I/O automatic transfer RAM.
Transfer direction selection bit
LSB first (SC1
MSB first (SC1
5
5
= “0” ) : MSB
= “1” ) : LSB
LSB
MSB
DO
7
DO
6
DO
5 DO4
DO
3
DO
2
DO
1
2
DO
DO
DO
0
S
IN
SOUT
DO
7
DI
DI
DI
0
DO
DO
6
DO
DO
5
DO
4
DO
DO
3
DO
1
2
7
6
DO5
4
DO
3
4
1
2
DI
DI
0
1
6
DI
0
DO7
DO6
DO
5
DO
DO
3
•
•
•
DI
5
DI
4
DI
3
DI
2
DI
1
DI0
DI
7
DI
Transfer clock
Serial I/O1 register
Fig. GA-7 Serial I/O1 register transfer operation in full duplex mode
27
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When using both the SCLK11 and SCKL12 by switching, switch the
P67/SRDY1/CS/SCLK12 to the P67 (SC14=0) and set the P67 direc-
tion register to input mode. Note that switch SIOAC3 during “H” of
transfer clock at the completion of automatic transfer.
(2.3) When Selecting the Internal Clock
When selecting the internal clock, the P67/SRDY1/CS/SCLK12 pin
can be used as the SRDY1 pin by setting SC14 to “1”.
When selecting the internal clock, the P67 pin can be used as the
synchronous clock output pin SCLK12 by setting SIOAC3 to “1”. In
this case, the SCLK11 pin goes to high impedance state.
Select the function of the P67/SRDY1/CS/SCLK12 and P66/SCLK11
with the following registers (refer to Table GA-1):
Table GA-1. SCLK11 and SCLK12 selection
SC16
SC14
SC33
SIOAC3 P66/SCLK11 P67/SCLK12
0
SCLK11
P67
1
0
1
High
impedance
●the bit 3 (SC13), the bit 4(SC14), and the bit 6(SC16) of the se-
rial I/O1 control register
1
SCLK12
Note : SC13: Serial I/O1 port selection bit
●the bit 3 (SIOAC3) of the serial I/O automatic transfer control
register
SC14: SRDY1 output selection bit
SC16: Synchronous clock selection bit
SIOAC3: Synchronous clock output pin selection bit
Bit 1 write signal of serial I/O
automatic transfer control
register
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
Data pointer
n
0
n-1
Transfer clock
(internal or SCLK output)
Receive
enabled signal
S
RDY
Serial I/O output
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
DO
0
DO6 DO7
S
out
Serial I/O input
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
0
DI
6
DI7
S
IN
Transfer interval
Fig. GA-8 Timing diagram during serial I/O automatic transfer (internal clock selected, SRDY used)
Bit 1 write signal of serial I/O
automatic transfer control
register
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
Data pointer
m-1
0
m
n
Bit 3 of serial I/O automatic
transfer control register
Transfer clock
(internal)
S
CLK11 output
CLK12 output
S
Serial I/O output
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
DO0
DI0
DO6 DO7
DO0 DO1 DO2 DO3
S
out
Serial I/O input
DI7
DI0
DI1 DI2 DI3
DI4 DI5
DI6
DI
DI6
DI0
DI1 DI2
DI
3
7
S
IN
Transfer interval
Fig. GA-9 Timing during serial I/O automatic transfer (internal clock selected, SCLK11 and SCLK12 used)
28
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not using the CS input, note that the SOUT pin will not go to
high impedance state, even after transfer is completed.
(2.4) When Selecting the External Clock
When selecting the external clock, the internal clock and the set-
ting of transfer interval with the serial I/O automatic transfer
interval register are invalid, but the serial I/O output pin SOUT1 and
the internal transfer clock can be controlled from the outside by
setting the SRDY1 pin to the CS (input) pin.
When not using the CS input, or when CS is “L”, control the exter-
nal clock because the data in the serial I/O register will continue to
shift while the external clock is input, even after the completion of
automatic transfer (Note that the automatic transfer interrupt re-
quest bit is set and the bit 1 of the serial I/O automatic transfer
register is cleared at the point when the specified number of bytes
of data have been transferred.)
When the CS input is “L”, the SOUT1 pin and the internal transfer
clock are enabled.
When the CS input is “H”, the SOUT1 pin goes to high impedance
state and the internal transfer clock goes to “H”.
Select the function of the P67/SRDY1/CS/SCLK12 with the following
registers (refer to Table GA-2):
Table GA-2. P67/SRDY1/CS selection
SC16
SC14
0
SIOAC0
P67/SRDY1/CS
●the bit 4 (SC14) and the bit 6 (SC16) of the serial I/O1 control
register
✕
0
P67
SRDY1
CS
0
●the bit 0 (SIOAC0) of the serial I/O automatic transfer control
register
1
1
Note : SC14: SRDY1 output selection bit
SC16: Synchronous clock selection bit
SIOAC0: Automatic transfer control bit
Switch the CS pin from “L” to “H” or from “H” to “L” during “H” of the
transfer clock (SCLK11 input) after transferring 1-byte data.
When selecting the external clock, set the external clock to “L” af-
ter 9 cycles or more of the internal clock φ after setting the start
bit. After transferring 1-byte data, leave 11 cycles or more of the
internal clock φ free for the transfer interval.
Bit 1 write signal of serial I/O
automatic transfer control
register
Bit 1 of serial I/O automatic
transfer control register
Write signal from RAM to
serial I/O1 register
Write signal from serial I/O1
register to RAM
n-1
Data pointer
n
External input
CS
Transfer clock
SCLK input
Transfer clock
(internal)
Serial I/O output
X
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
S
OUT
Serial I/O input
DI
0
DI1
DI
2
DI
3
DI4
DI
5
DI
6
DI
7
X
X
X
X
X
SIN
Note: Data marked with X is invalid.
Fig. GA-10 Timing during serial I/O automatic transfer (external clock selected)
29
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The functional blocks of the A-D converter are described below.
b7
b0
AD/DA control register
(ADCON : address 002C16
)
A-D Conversion Register (AD) 002D16
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. This register should not be read dur-
ing A-D conversion.
Analog input pin selection bits
b3 b2 b1 b0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 : P7
0
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
1 : P7
0 : P7
1 : P7
0 : P7
1 : P7
0 : P7
1 : P7
0 : P5
1 : P5
0 : P5
1 : P5
0 : P5
1 : P5
0 : P5
1 : P5
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
AD/DA Control Register (ADCON) 002C16
The AD/DA control register controls the A-D and the D-A conver-
sion process. Bits 0 to 3 of this register select analog input pins.
Bit 4 is the AD conversion completion bit. The value of this bit re-
mains at “0” during an A-D conversion, then changes to “1” when
the A-D conversion is completed.
/SIN2/AN
/SOUT2/AN
8
9
/SCLK2/AN10
/SRDY2/AN11
/SIN3/AN12
/SOUT3/AN13
/SCLK3/AN14
/SRDY3/AN15
The A-D conversion starts by writing “0” to this bit. Bit 6 controls
the output of D-A converter.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
Not used (returns “0” when read)
DA output enable bit
0 : Disable
AVSS and VREF by 256, and outputs the divided voltages.
1 : Enable
Not used (returns “0” when read)
Channel Selector
The channel selector selects one of the input ports P77/AN7–P70/
AN0, P57/SRDY3/AN15–P50/SIN2/AN8, and inputs to the compara-
tor.
Fig. JA-1 Structure of A-D control register
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to 500 kHz or more during A-D conversion.
Note : When using the A-D conversion interrupt, set the INT4/AD conver-
sion interrupt switch bit (the bit 5 of the interrupt selection register)
to “1”.
30
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
b7
b0
AD-DA control register
(address 002C16
)
4
A-D control circuit
A-D conversion interrupt request
P7
P7
P7
P7
P7
P7
P7
P7
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
8
9
Comparator
A-D conversion register
(Address 002D16
8
)
P5
P5
P5
P5
P5
P5
P5
P5
0
1
/SIN2/AN
/Sout2/AN
2
3
/SCLK2/AN10
/SRDY2/AN11
/SIN3/AN12
Resistor ladder
4
5
6
/SOUT3/AN13
/SCLK3/AN14
7
/SRDY3/AN15
V
REF
AVSS
Fig. JA-2 A-D converter block diagram
D-A CONVERTER
The 3819 group has internal D-A converter with 8-bit resolutions ✕
1 channel.
D-A conversion is performed by setting the value in the D-A con-
version register. The result of D-A conversion is output from the
DA pin by setting the DA output enable bit to “1” . At this time, the
corresponding bit (PB2/DA) of the port PB direction register should
be set to “0” (input status).
D-A conversion register (8)
R-2R resistor ladder
The output analog voltage V is determined with the value n
(n: decimal number) in the D-A conversion register as follows:
DA output enable bit
PB /DA
2
V=VREF ✕ n/256 (n=0 to 255)
✽VREF: the reference voltage
At reset, the D-A conversion register is cleared to “0016”, the DA
output enable bits are cleared to “0”, and the PB2/DA pin goes to
high impedance state. The D-A output does not build in a buffer, so
connect an external buffer when driving a low-impedance load.
Set VCC to 3.0 V or more when using the D-A converter.
Fig. JB-1 D-A converter block diagram
"0"
DA output enable bit
2R
R
R
R
R
R
R
R
PB2/DA
"1"
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
"0"
D-A conversion
register
"1"
AVSS
V
REF
Fig. JB-2 Equivalent connection circuit of D-A converter
31
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Port P0 segment/digit switch register
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control
circuits.
• Port P2 digit/port switch register
• Port PA segment/port switch register
• Port P8 segment/port switch register
The FLD controller consists of the following components:
• 42 pins for segments
• 96-byte FLD automatic display RAM
The segment pins can be used from 16 up to 42 pins (maximum)
and the digit pins can be used from 6 up to 16 pins (maximum).
The segment and the digit pins can be used up to 52 pins (maxi-
mum) in total.
• 20 pins for digits
• FLDC mode register 1
• FLDC mode register 2
• FLD data pointer
In the FLD automatic display mode ports P12 to P17 become digit
pins DIG10 to DIG15 automatically.
• FLD data pointer reload register
Main
address bus
FLD automatic
display RAM
Main
data bus
Local
data bus
S/P PA
S/P PA
S/P PA
S/P PA
S/P PA
S/P PA
S/P PA
S/P PA
0
1
2
3
4
5
6
7
/SEG
/SEG
/SEG
/SEG
/SEG
/SEG
/SEG
/SEG
0
1
2
3
4
5
6
7
G1 (SEG PA)
G2 (SEG PA)
0F8016
8
G15 (SEG PA)
G16 (SEG PA)
G1 (SEG P8)
G2 (SEG P8)
0F8F16
0F9016
003516
001416
Local
S/P P8
S/P P8
S/P P8
S/P P8
S/P P8
S/P P8
S/P P8
S/P P8
0
1
2
3
4
5
6
7
/SEG
/SEG
8
address bus
9
/SEG10
/SEG11
/SEG12
/SEG13
/SEG14
/SEG15
G15 (SEG P8)
G16 (SEG P8)
G1 (SEG P9)
G2 (SEG P9)
8
8
8
0F9F16
0FA016
003416
001016
G15 (SEG P9)
G16 (SEG P9)
G1 (SEG P3)
G2 (SEG P3)
P9
P9
P9
P9
P9
P9
P9
P9
0
/SEG16
/SEG17
/SEG18
/SEG19
/SEG20
/SEG21
/SEG22
/SEG23
0FAF16
0FB016
1
2
3
4
5
6
7
G15 (SEG P3)
G16 (SEG P3)
G1 (SEG P0)
G2 (SEG P0)
0FBF16
0FC016
001216
P3
P3
P3
P3
P3
P3
P3
P3
0
/SEG24
/SEG25
/SEG26
/SEG27
/SEG28
/SEG29
/SEG30
/SEG31
1
2
3
4
5
6
7
G15 (SEG P0)
G16 (SEG P0)
G1 (SEG P1)
G2 (SEG P1)
0FCF16
0FD016
000616
S/D P0
S/D P0
S/D P0
S/D P0
S/D P0
S/D P0
S/D P0
S/D P0
0
1
2
3
4
5
6
7
/SEG32/DIG
/SEG33/DIG
/SEG34/DIG
/SEG35/DIG
/SEG36/DIG
/SEG37/DIG
/SEG38/DIG
/SEG39/DIG
0
1
2
3
4
5
6
7
G15 (SEG P1)
G16 (SEG P1)
8
0FDF16
003216
000016
FLD data pointer
reload register
S/D P1
S/D P1
P1
0
1
2
3
4
5
6
7
/SEG40/DIG
/SEG41/DIG
/DIG10
/DIG11
/DIG12
/DIG13
/DIG14
/DIG15
8
9
(address 003816
)
8
P1
P1
P1
P1
Address
decoder
FLD data pointer
(address 003816
)
P1
FLDC mode
register 1
(address 003616
003716
000216
)
D/P P2
D/P P2
D/P P2
D/P P2
0
/DIG16
/DIG17
/DIG18
/DIG19
4
1
2
3
003316
000416
Timing
generator
FLD blanking interrupt
FLD digit interrupt
Fig. KA-1 FLD control circuit block diagram
32
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
register respectively which are used to control the FLD automatic
display and set the blanking time Tscan for key-scan.
FLDC Mode Registers (FLDM 1, FLDM 2)
003616, 003716
The FLDC mode register 1 (address 003616) and FLDC mode reg-
ister 2 (address 003716) are a seven bit register and an eight bit
b7
b0
FLDC mode register 1
(FLDM 1 : address 003616
)
T
scan control bits
b1 b0
0 0 : 0 FLD digit interrupt (at rising edge of each digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
1 1 : 3 ✕ Tdisp
FLD blanking interrupt
(at falling edge of the last digit)
T
off control bits
(Setting of digit/segment OFF time)
b5 b4 b3 b2
0 0 0 0 : 1/16 ✕ Tdisp
0 0 0 1 : 2/16 ✕ Tdisp
0 0 1 0 : 3/16 ✕ Tdisp
0 0 1 1 : 4/16 ✕ Tdisp
0 1 0 0 : 5/16 ✕ Tdisp
0 1 0 1 : 6/16 ✕ Tdisp
0 1 1 0 : 7/16 ✕ Tdisp
0 1 1 1 : 8/16 ✕ Tdisp
1 0 0 0 : 9/16 ✕ Tdisp
1 0 0 1 : 10/16 ✕ Tdisp
1 0 1 0 : 11/16 ✕ Tdisp
1 0 1 1 : 12/16 ✕ Tdisp
1 1 0 0 : 13/16 ✕ Tdisp
1 1 0 1 : 14/16 ✕ Tdisp
1 1 1 0 : 15/16 ✕ Tdisp
1 1 1 1 : 16/16 ✕ Tdisp
Not used (returns “0” when read)
High-breakdown-voltage drivability selection bit
0 : Strong drivability
1 : Weak drivability
Fig. KA-2 Structure of FLDC mode register 1
b7
b0
FLDC mode register 2
(FLDM 2 : address 003716
)
Automatic display control bit(P0, P1, P2
0 : Ordinary mode
0–P23, P3, P8, P9, PA)
1 : Automatic display mode
Display start bit
0 : Display stopped
1 : Display in progress
(display starts by writing “1” to this bit which is set to “0”)
T
disp control bits
(digit time setting, at 8 MHz oscillation frequency)
b5 b4 b3 b2
0 0 0 0 : 128 µs
0 0 0 1 : 256 µs
0 0 1 0 : 384 µs
0 0 1 1 : 512 µs
0 1 0 0 : 640 µs
0 1 0 1 : 768 µs
0 1 1 0 : 896 µs
0 1 1 1 : 1024 µs
1 0 0 0 : 1152 µs
1 0 0 1 : 1280 µs
1 0 1 0
Not available
1 1 1 1
Pl
Pl
0 segment/digit switch bit
0 : Digit
1 : Segment
1
segment/digit switch bit
0 : Digit
1 : Segment
Fig. KA-3 Structure of FLDC mode register 2
33
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When using the FLD automatic display mode, set the number
of segments and digits for each port.
● Pins for FLD Automatic Display
Ports P0, P1, P20–P23, P3, P8, P9, and PA is selected for the
FLD automatic display function by setting the automatic display
control bit of the FLDC mode register 2 (address 003716) to
“1”.
Table L-1. Pins in FLD automatic display mode
Port Name
Automatic Display Pins
SEG0–SEG7
or
Setting Method
The individual bits of the segment/port switch register (address 003516) can be set each pin
to either segment (“1”) or general-purpose I/O port (“0”).
PA0–PA7
PA0–PA7
SEG8–SEG15
or
The individual bits of the segment/port switch register (address 003416) can be used to set
each pin to either segment (“1”) or general-purpose I/O port (“0”).
P80–P87
P80–P87
P90–P97
P30–P37
SEG16–SEG23
SEG24–SEG31
SEG32–SEG41
or
None (segment only)
None (segment only)
P00–P07
P10, P11
The individual bits of the segment/digit switch register (address 003216) and the bit 6, 7 of
the FLDC mode register 2 can be used to set each pin to segment (“1”) or digit (“0”). (Note)
DIG0–DIG9
DIG10–DIG15
DIG16–DIG19
or
P12–P17
P20–P23
None (digit only)
The individual bits of the digit/port switch register (address 003316) can be used to set each
pin to digit (“1”) or general-purpose output port (“0”). (Note)
P20–P23
Note : Be sure to set digits in sequence.
Number of segments
Number of segments
Number of digits
Number of digits
24
8
0 PA
PA
0 PA
PA
0 PA
PA
0 PA
0 PA
30
10
0 PA
PA
0 PA
PA
0 PA
PA
0 PA
0 PA
36
16
1 SEG
SEG
1 SEG
SEG
1 SEG
SEG
1 SEG
1 SEG
24
30
36
8
10
16
Port PA
(has the segment/port
switch register)
Port P3
(segment only)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
0
0
1
0
0
1
0
0
1
Port P8
(has the segment/port
switch register)
Port P0
(has the segment/digit
switch register)
0 P8
0 P8
0 P8
0 P8
0
0 P8
0 P8
0 P8
0 P8
0
1 SEG
1 SEG
1 SEG10
1 SEG11
8
9
1 SEG32
1 SEG33
1 SEG34
1 SEG35
1 SEG32
1 SEG33
1 SEG34
1 SEG35
1 SEG32
1 SEG33
1 SEG34
1 SEG35
1
1
2
3
4
5
6
7
2
3
0
1
1
1
1
0
P8
0 P8
SEG12
SEG12
1 SEG13
SEG36
1 SEG37
SEG36
1 SEG37
DIG
0 DIG
4
5
6
7
G
G
G
G
16
15
14
13
1 SEG13
0
1
1
1
1
0
P8
0 P8
SEG14
SEG14
SEG38
1 SEG39
SEG38
DIG
1 SEG15
1 SEG15
1 SEG39
0 DIG
Port P9
(segment only)
Port P1
(has the segment/digit
switch register)
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
0 DIG
0 DIG
8
9
G
G
G
G
G
G
G
G
8
7
6
5
4
3
2
1
1 SEG40
1 SEG41
DIG10
DIG11
DIG12
DIG13
DIG14
DIG15
0 DIG
0 DIG
8
9
G
G
G
G
G
G
G
G
12
11
10
9
DIG10
DIG11
DIG12
DIG13
DIG14
DIG15
G
G
G
G
G
G
10
9
DIG10
DIG11
DIG12
DIG13
DIG14
DIG15
8
8
7
7
6
6
5
5
Port P2
(has the digit/port
switch register)
0 P2
0
1
2
3
1 DIG16
G
G3
G2
G1
4
1 DIG16
G
G
G
G
4
3
2
1
0
0
1
1
1
1
P2
P2
DIG17
DIG18
DIG17
DIG18
0 P2
1 DIG19
1 DIG19
Fig. KA-4 Segment/digit setting example
34
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The FLD data pointer indicates the data address in the FLD auto-
matic display RAM to be transferred to a segment. The FLD data
pointer reload register indicates the first digit address of the most
significant segment.
● FLD Automatic Display RAM
The FLD automatic display RAM area is the 96 bytes from ad-
dresses 0F8016 to 0FDF16. The FLD automatic display RAM
area can store 6-byte segment data up to 16 digits (maximum).
Addresses 0F8016 to 0F8F16 are used for PA segment data,
addresses 0F9016 to 0F9F16 are used for P8 segment data,
addresses 0FA016 to 0FAF16 are used for P9 segment data,
addresses 0FB016 to 0FBF16 are used for P3 segment data,
addresses 0FC016 to 0FCF16 are used for P0 segment data,
and addresses 0FD0 to 0FDF16 are used for P1 segment data.
The value which adds 0F8016 to these data is actual address in
memory.
The contents of the FLD data pointer indicate the first address of
segment P1(the contents of the FLD data pointer reload register)
at the start of automatic display. The FLDC data pointer content
changes repeatedly as follows: when transferring the segment P1
data to the segment, the content decreases by –16; when transfer-
ring the segment P0 data, it decreases by –16; when transferring
the segment P3 data, it decreases by –16; when transferring the
segment P9 data, it decreases by –16; when transferring the seg-
ment P8 data, it decreases by –16; when transferring the segment
PA data, it increases by +79. Once it reaches “00”, at the next tim-
ing the value in the FLD data pointer reload register is transferred
to the FLD data pointer. In this way, the 6-byte data of P1, P0, P3,
P9, P8 and PA segments for 1 digit are transferred.
FLD Data Pointer and FLD Data Pointer
Reload Register
(FLDDP) 003816
Both the FLD data pointer and FLD data pointer reload register
are 7-bit registers allocated at address 003816. When writing data
to this address, the data is written to the FLD data pointer reload
register, when reading data from this address, the value in the
FLD data pointer is read.
35
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bit
7
6
5
4
3
2
1
0
Address
0F8016
The last digit
(The last data of segment PA)
SEG
SEG
7
7
SEG
6
6
SEG
SEG
5
5
SEG
4
4
SEG
SEG
3
3
SEG
2
2
SEG
SEG
1
1
SEG
SEG
0
0
0F8116
SEG
SEG
SEG
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment PA
data area
0F8E16
0F8F16
0F9016
0F9116
SEG
SEG
7
7
SEG
6
6
SEG
SEG
5
5
SEG
4
4
SEG
SEG
3
3
SEG
2
2
SEG
SEG
SEG
SEG
1
1
9
9
SEG
SEG
SEG
SEG
0
0
8
8
SEG
SEG
SEG
The last digit
(The last data of segment P8)
SEG15
SEG15
SEG14
SEG14
SEG13
SEG13
SEG12
SEG12
SEG11
SEG11
SEG10
SEG10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment P8
data area
0F9E16
0F9F16
0FA016
0FA116
SEG15
SEG15
SEG23
SEG23
SEG14
SEG14
SEG22
SEG22
SEG13
SEG13
SEG21
SEG21
SEG12
SEG12
SEG20
SEG20
SEG11
SEG11
SEG19
SEG19
SEG10
SEG10
SEG18
SEG18
SEG
SEG
9
9
SEG
SEG
8
8
The last digit
(The last data of segment P9)
SEG17
SEG17
SEG16
SEG16
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment P9
data area
0FAE16
0FAF16
0FB016
0FB116
SEG23
SEG23
SEG31
SEG31
SEG22
SEG22
SEG30
SEG30
SEG21
SEG21
SEG29
SEG29
SEG20
SEG20
SEG28
SEG28
SEG19
SEG19
SEG27
SEG27
SEG18
SEG18
SEG26
SEG26
SEG17
SEG17
SEG25
SEG25
SEG16
SEG16
SEG24
SEG24
The last digit
(The last data of segment P3)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment P3
data area
0FBE16
0FBF16
0FC016
0FC116
SEG31
SEG31
SEG39
SEG39
SEG30
SEG30
SEG38
SEG38
SEG29
SEG29
SEG37
SEG37
SEG28
SEG28
SEG36
SEG36
SEG27
SEG27
SEG35
SEG35
SEG26
SEG26
SEG34
SEG34
SEG25
SEG25
SEG33
SEG33
SEG24
SEG24
SEG32
SEG32
The last digit
(The last data of segment P0)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment P0
data area
0FCE16
0FCF16
0FD016
0FD116
SEG39
SEG39
SEG38
SEG38
SEG37
SEG37
SEG36
SEG36
SEG35
SEG35
SEG34
SEG34
SEG33
SEG33
SEG41
SEG41
SEG32
SEG32
SEG40
SEG40
The last digit
(The last data of segment P1)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Segment P1
data area
0FDE16
0FDF16
SEG41
SEG41
SEG40
SEG40
Fig. KA-5 FLD automatic display RAM and bit allocation
36
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
quence from the last data respectively. The first data of the
segment PA, P8, P9, P3, P0, and P1 is stored at an address
which adds the value of (the digit number–1) to the corre-
sponding address 0F8016, 0F9016, 0FA016, 0FB016, 0FC016,
and 0FD016.
● Data Setup
When data is stored in the FLD automatic display RAM, the
last data of segment PA is stored at address 0F8016, the last
data of segment P8 is stored at address 0F9016, the last data
of segment P9 is stored at address 0FA016, the last data of
segment P3 is stored at address 0FB016, the last data of seg-
ment P0 is stored at address 0FC016, and the last data of
segment P1 is stored at address 0FD016 to allocate in se-
Set the low-order 4 bits of the FLD data pointer reload register
to the value given by the number of digits–1. “1” is always writ-
ten to bit 6 and bit 4, and “0” is always written to bit 5. Note that
“0” is always read from bits 6, 5 and 4 when reading.
For 30 segments and 15 digits
For 30 segments and 15 digits
(FLD data pointer reload register = 14)
(FLD data pointer reload register = 14)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
Note :
Shaded areas are used.
Fig. KA-6 Example of using the FLD automatic display RAM (1)
37
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
For 42 segments and 8 digits
For 42 segments and 8 digits
(FLD data pointer reload register = 7)
(FLD data pointer reload register = 7)
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Address
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
Note :
Shaded areas are used.
Fig. KA-6 Example of using the FLD automatic display RAM (2) (continued)
38
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
During automatic display bit 1 of the FLDC mode register 2 al-
ways keeps “1”, automatic display can be interrupted by writing
“0” to the bit 1.
● Timing Setting
The digit time (Tdisp) can be set with the FLDC mode register 2
(address 003716). The Tscan and digit/segment OFF time (Toff)
can be set with the FLDC mode register 1 (address 003616).
Note that flickering will occur if the repetition frequency (1/
(Tdisp ✕ number of digits + Tscan)) is an integral multiple of the
digit timing Tdisp.
● Key-scan
If key-scan is performed with the segment during the key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to the bit 0 (automatic display control bit) of the
FLDC mode register 2 (address 003716).
2. Set the port corresponding to the segment for key-scan to
the output port.
● FLD Automatic Display Start
To perform FLD automatic display, set the following registers.
• Port P0 segment/digit switch register
• Port P2 digit/port switch register
• Port P8 segment/port switch register
• Port PA segment/port switch register
• FLDC mode register 1
3. Perform the key-scan.
4. After the key-scan is performed, write “1” (automatic display
mode) to the bit 0 of FLDC mode register 2 (address
003716).
• FLDC mode register 2
Note on performance of key-scan in the above 1 to 4 sequence.
1. Do not write “0” to the bit 1 of FLDC mode register 2 (ad-
dress 003716).
• FLD data pointer
Automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register 2 (address 003716), and the auto-
matic display is started by writing “1” to the bit 1.
2. Do not write “1” to the port corresponding to the digit.
Tdisp
Tscan
G n
G n-1
G n-2
G 1
Segment
output
Segment setting by software
FLD digit interrupt occurs
FLD blanking interrupt occurs
at the falling edge of the last digit
at the rising edge of each digit
Digit
Segment
Toff
Tdisp
Fig. KA-7 FLDC timing
39
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
determination register (address 003016), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter is cleared to “0016”. The 8-bit binary up counter con-
tinues to count up again from “0016”.
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 3819 group builds in an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising transition (falling transition) of an input signal pulse on
the P42/INT2 pin to the rising transition (falling transition) of the
signal pulse that is input next.
➅When count value reaches “FF16”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16” to the in-
terrupt interval determination register to generate the counter
overflow interrupt request.
How to determine the interrupt interval is described below.
➀Enable the INT2 interrupt by setting the bit 2 of the interrupt con-
trol register 1 (address 003E16). Select the rising interval or
falling interval by setting the bit 2 of the interrupt edge selection
register (address 003A16).
Noise filter
The P42/INT2 pin builds in the noise filter.
The noise filter operation is described below.
➀Select the sampling clock of the input signal with the bits 2 and
3 of the interrupt interval determination control register. When
not using the noise filter, set “002”.
➁Set the bit 0 of the interrupt interval determination control regis-
ter (address 003116) to “1” (interrupt interval determination
operating).
➁The P42/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in series,
the signal is recognized as the interrupt signal, and the interrupt
request occurs.
➂Select the sampling clock of 8-bit binary up counter by setting
the bit 1 of the interrupt interval determination control register.
When writing “0”, f(XIN)/256 is selected (the sampling interval:
32 µs at f(XIN) = 8.38 MHz) ; when “1”, f(XIN)/512 is selected (the
sampling interval: 64 µs at f(XIN) = 8.38 MHz).
When setting the bit 4 of interrupt interval determination control
register to “1”, the interrupt request can occur at both rising and
falling edges.
➃When the signal of polarity which is set on the INT2 pin (rising or
falling transition) is input, the 8-bit binary up counter starts
counting up of the selected counter sampling clock.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 2 cycles or more.
Note : In the low-speed mode (CM7=1), the interrupt interval determination
function can not operate.
➄When the signal of polarity above ➃ is input again, the value of
the 8-bit binary up counter is transferred to the interrupt interval
The counter
f(XIN)/256
sampling clock
The counter overflow
f(XIN)/512
8-bit binary up counter
interrupt request or
selection bit
remote control interrupt request
Noise filter
INT2 interrupt input
Interrupt interval
determination register
address 003016
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
1/256
1/128
1/64
Data bus
Divider
f(XIN)
Fig. DE-1 Block diagram of interrupt interval datermination circuit
40
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register
(IIDCON : address 003116
)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/256
1 : f(XIN)/512
Noise filter sampling clock selection bits(INT
2)
0 0 : Filter stop
0 1 : f(XIN)/64
1 0 : f(XIN)/128
1 1 : f(XIN)/256
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection
Not used (return “0” when read)
Fig. DE-2 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
Sampling clock
INT2 pin
Acceptance
of interrupt
Counter
sampling clock
FF
FE
N
6
5
4
8-bit binary
3
3
2
2
1
1
1
up counter value
0
0
0
0
6
3
FF
Interrupt interval
determination
register value
N
6
3
FF
Remote control
interrupt request
Remote control
interrupt request
Remote control
interrupt request
Counter overflow
interrupt request
Fig. DE-3 Interrupt interval determination operation example (at rising edge active)
41
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(When IIDCON4 = “1”)
Noise filter
Sampling clock
INT2 pin
Acceptance
of interrupt
Counter
sampling clock
FF
FE
N
4
3
8-bit binary
up counter value
2
1
1
1
1
1
1
0
0
0
0
0
0
0
N
1
4
1
1
1
FF
Interrupt interval
determination
register value
N
4
1
1
1
FF
Remote Remote
control control
interrupt interrupt
request request
Remote Remote Remote Remote
control control control control
interrupt interrupt interrupt interrupt
request request request request
Counter
overflow
interrupt
request
Fig. DE-4 Interrupt interval determination operation example (at both-sided edge active)
42
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION CIRCUIT
The zero cross detection circuit compares the voltage applied to
P45/INT1/ZCR pin and VSS. The result can be read from the zero
cross detection circuit input bit (bit 7) of the zero cross detection
control register. It is set to “1” when the input voltage is higher than
VSS and to “0” when it is lower than VSS. The input signal to P45/
INT1/ZCR pin can select to either pass through the zero cross de-
tection comparator or not to do.
V
CC
100V AC
R
1
R2
P45/INT1/ZCR
When using 100 V AC as input signal, insert an external circuit be-
tween it and P45/INT1/ZCR pin. Set the input current limiting
resistors used in the external circuit to a value which satisfies the
absolute maximum rating of port P45.
VSS
Fig. JE-1 External circuit example for zero cross detection
b7
b0
Zero cross detection control register
(ZCRCON : address 003916
)
Zero cross detection ON/OFF selection bit
0 : Without passing through zero cross detection comparator
1 : Passing through zero cross detection comparator
Not used (returns “0” when read)
Noise filter sampling clock selection bits (INT
1)
b3 b2
0 0 : Not use noise filter
0 1 : f(XIN)/64 or f(XCIN)/64
1 0 : f(XIN)/128 or f(XCIN)/128
1 1 : f(XIN)/256 or f(XCIN)/256
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection
Not used (return “0” when read)
Zero cross detection circuit input bit (read only)
0 : Less than 0 V
1 : 0 V or more
Fig. JE-2 Structure of zero cross detection control register
P45/INT1/ZCR
Zero cross detection
ON/OFF selection bit
When not using
the filter
“0”
“1”
INT
1/ZCR
Rising/falling
edge switch
When using
the filter
interrupt request
Zero cross detection
circuit input bit
Noise filter
Zero cross detection comparator
One-sided/both-sided edge
detection selection bit
Noise filter sampling clock
selection bit
1/256
1/28
1/64
f(XCIN
f(XIN
)
)
Divider
Fig. JE-3 Block diagram of zero cross detection circuit
43
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
the noise filter. When passing through the noise filter, either both-
sided edge detection or one-sided edge detection can be selected
as the interrupt request generating source. The zero cross detec-
tion control register is used for this selection. Furthermore, switch
between rising edge and falling edge is performed with the bit 1 of
the interrupt edge selection register (address 003A16).
NOISE FILTER
The noise filter uses a sampling clock to remove the noise compo-
nent digitally from the input signal of P45/INT1/ZCR pin. The
sampling clock can be selected from 8 µs, 16 µs, or 32 µs (at
f(XIN)= 8.38 MHz) and this is used to change the noise component
to be removed. It is also possible to generate an internal trigger
and INT1/ZCR interrupt request directly without passing through
One-sided/both-sided edge
detection selection bit
(bit 4 of ZCRCON)
“0”
INT
1/ZCR
C
“1”
Input signal from
P4 /INT /ZCR pin
A
B
interrupt request
D
Q
S
R
Q
D
Q
D
Q
5
1
C
C
C
R
R
R
Sampling clock
RESET
Fig. JE-4 Noise filter circuit diagram
RESET
Sampling clock
P4 /INT /ZCR
Input signal from
5
1
0 V
(Note 1)
P4
5/INT
1
/ZCR pin
A
B
C
(Note 2)
Switched with
bit 4 of ZCRCON
(one-sided edge)
(both-sided edge)
INT
1/ZCR
interrupt request
Notes 1
2
: Ignored this because of treating this as noise
: INT /ZCR interrupt request occurs
1
Fig. JE-5 Timing of noise filter circuit
44
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between 2.8 V and 5.5
V, and XIN oscillation is stable), reset is released. In order to give
the XIN clock time to stabilize, internal operation does not begin
until after about 4000 XIN clock cycles (256 cycles of f(XIN)/16) are
completed. After the reset is completed, the program starts from
the address contained in address FFFD16 (high-order) and ad-
dress FFFC16 (low-order). Make sure that the reset input voltage
is 0.5 V or less for 2.8 V of VCC.
Power source
(Note)
voltage
RESET
VCC
0 V
Reset input
voltage
0.2VCC
0 V
Note : Reset release voltage : VCC = 2.8 V
RESET
VCC
Power source voltage
detection circuit
Fig. VB-2 Example of reset circuit
X
IN
φ
RESET
Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Reset address from
vector table
?
?
?
?
AD
L
ADH
Data
SYNC
Notes 1 : f(XIN) and f(φ) are in the relationship : f(XIN) = 8
•
f(φ)
about 4000
IN clock cycles
2 : A question mark (?) indicates an undefined state that depends on the previous state.
X
Fig. VB-2 Reset sequence
45
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address
Register contents
0016
Address
Register contents
(1) Port P0
(000016
(000216
(000416
(000516
(000616
(000816
(000916
)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
• • •
(31) Timer 6
(002516
(002816
(002916
)
• • •
• • •
• • •
• • •
• • •
• • •
• • •
FF16
0016
0016
0016
0016
1016
0016
(2) Port P1
)
)
)
)
)
)
(32) Timer 12 mode register
(33) Timer 34 mode register
(34) Timer 56 mode register
(35) D-A conversion register
(36) AD/DA control register
(37) Interrupt interval determination
control register
)
)
0016
(3) Port P2
0016
(4) Port P2 direction register
(5) Port P3
(002A16
(002B16
(002C16
)
)
)
0F16
0016
(6) Port P4
0016
(7) Port P4 direction register
(8) Port P5
(003116
(003216
(003316
(003416
)
0016
(000A16
(000B16
)
)
0016
(9) Port P5 direction register
(10) Port P6
(38) Port P0 segment/digit
switch register
)
• • •
• • •
• • •
0016
0016
0016
0016
(000C16
(000D16
)
)
0016
(11) Port P6 direction register
(12) Port P7
(39) Port P2 digit/port switching
register
)
)
0016
(000E16
(000F16
)
0016
(13) Port P7 direction register
(14) Port P8
)
(40) Port P8 segment/port
switch register
0016
(001016
(001116
(001216
(001416
(001516
(001616
(001716
(001916
)
)
)
)
)
)
)
)
0016
(15) Port P8 direction register
(16) Port P9
(41) Port PA segment/port switch
(42) FLDC mode register 1
(43) FLDC mode register 2
(44) Zero cross detection control
register
(003516
(003616
(003716
(003916
)
)
)
)
• • •
• • •
• • •
• • •
0016
0016
0016
0016
0016
0016
(17) Port PA
0016
(18) Port PA direction register
(19) Port PB
0016
0016
(20) Port PB direction register
(21) Serial I/O1 control register
(45) Interrupt edge selection register (003A16
)
)
)
)
)
• • •
• • •
• • •
• • •
• • •
• • •
0016
0016
(46) CPU mode register
(003B16
(003C16
(003D16
(003E16
0016
0 1 0 0 1 0 0 0
(22) Serial I/O automatic transfer (001A16
control register
)
(47) Interrupt request register 1
(48) Interrupt request register 2
(49) Interrupt control register 1
(50) Interrupt control register 2
(51) Processor status register
(52) Program counter
0016
0016
0016
0016
0016
(23) Serial I/O automatic transfer (001C16
interval register
)
)
• • •
0016
(003F16
)
(24) Serial I/O2 control register
(25) Serial I/O3 control register
(26) Timer 1
(001D16
(001E16
• • •
• • •
• • •
• • •
• • •
• • •
• • •
(PS) • • •
✕ ✕ ✕ ✕ ✕
0016
0016
FF16
0116
FF16
FF16
FF16
1 ✕ ✕
)
(PC
H
)
)
• • •
• • •
Contents of address FFFD16
Contents of address FFFC16
(002016
(002116
(002216
(002316
(002416
)
(PC
L
(27) Timer 2
)
(28) Timer 3
)
)
)
(29) Timer 4
(30) Timer 5
Note : ✕ : Undefined
The contents of all other registers and RAM are undefined at reset, so set their initial values.
Fig. VB-3 Internal status at reset
46
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Oscillation Control
CLOCK GENERATING CIRCUIT
Stop mode
The 3819 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is in-
put to timer 1, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
timer 1 and timer 2 interrupt enable bits to disabled (“0”) before ex-
ecuting the STP instruction.
Immediately after poweron, only the XIN oscillation circuit starts
oscillation, and XCIN and XCOUT pins function as I/O ports.
Oscillator restarts at reset or when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU until
timer 1 underflows. When using an external resonator, it is neces-
sary for oscillating to stabilize.
Frequency Control
Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set, this mode is selected.
Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore executing the WIT instruction. The internal clock restarts at
reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
High-speed mode
The internal clock φ is half the frequency of XIN.
Low-speed mode
The internal clock φ is half the frequency of XCIN.
Note : If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is re-
quired for the XCIN oscillation to stabilize, especially immediately
after poweron and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the frequency
on condition that f(XIN) > 3·f(XCIN).
XCIN
XCOUT
X
IN
XOUT
Low-power dissipation mode
When stopping the main clock XIN in the low-speed mode, the low-
power dissipation operation starts. To stop the main clock, set the
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted, set enough time for oscillation to stabilize by program-
ming.
R
f
R
d
C
CIN
C
COUT
C
IN
COUT
The low-power dissipation operation 200 µA or less (at f(XIN) = 32
kHz) can be realized by reducing the XCIN–XCOUT drivability. To re-
duce the XCIN–XCOUT drivability, clear the bit 3 of the CPU mode
register to “0”. At reset or when executing the STP instruction, this
bit is set to “1” and strong drivability is selected to help the oscilla-
tion to start.
Fig. WA-1 Ceramic resonator external circuit
XCIN
XCOUT
XIN
XOUT
Open
Open
External oscillation External oscillation
circuit or pulse circuit
V
V
CC
SS
V
CC
SS
V
Fig. WA-2 External clock input circuit
47
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
“0”
“1”
Port XC switch bit (Note 3)
Timer 1 count
source selection
bit (Note 2)
Internal system clock selection bit
(Note 1, 3)
X
IN
X
OUT
Low-speed mode
“1”
“1”
Timer 1
“0”
1/2
1/4
1/2
“0”
Middle/
High-speed mode
Main clock division ratio selection bit (Note 3)
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
or Low-speed mode
Main clock stop bit (Note 3)
Q
S
R
S
R
Q
Q
S
R
WIT
instruction
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Notes 1 : When selecting the low-speed mode, set the port X
2 : Refer to the structure of timer 12 mode register.
C
switch bit to “1”.
3 : Refer to the structure of CPU mode register (next page).
Fig. WA-3 Clock generating circuit block diagram
48
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (φ =1 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 0 (32 kHz stopped)
High-speed mode (φ = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 0 (32 kHz stopped)
CM6
CM6
CM6
CM6
“1”
“1”
“1”
“1”
“0”
“0”
“0”
“0”
Middle-speed mode (φ =1 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
High-speed mode (φ = 4 MHz)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
Low-speed mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
Low-speed mode (φ = 16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (XIN oscillating)
CM4 = 1 (32 kHz oscillating)
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
CM4 : Port XC switch bit
0 : I/O port function
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN-XOUT) stop bit
0 : Oscillating
1 : Stopped
CM6 : Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Low power dissipation mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
Low power dissipation mode (φ =16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM7 : Internal system clock selection bit
0 : XIN-XOUT selected
(middle/high-speed mode)
1 : XCIN-XCOUT selected
CM5 = 1 (XIN stopped)
CM4 = 1 (32 kHz oscillating)
CM5 = 1 (XIN stopped)
CM4 = 1 (32 kHz oscillating)
(low-speed mode)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode
is ended.
Timer operates in the wait mode.
3 : When the stop mode is released in middle/high-speed mode, a delay of approximately 0.5 ms occurs automatically by timer 1.
4 : When the stop mode is released in low-speed mode, a delay of approximately 0.125 s occurs automatically by timer 1.
5 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. WA-4 State transitions of system clock
49
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
When using the internal clock, set the synchronous clock to inter-
nal clock, then clear the serial I/O interrupt request bit before
executing a serial I/O transfer and serial I/O automatic transfer.
Interrupts
A-D Converter
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing
a BBC or BBS instruction.
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500 kHz or more during an A-D conver-
sion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. Only the ADC
and SBC instructions yield proper decimal results. After execut-
ing an ADC or SBC instruction, execute at least one instruction
before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flag are invalid.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions. The frequency of the internal
clock φ is half of the XIN or XCIN frequency.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
At the STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode regis-
ter are cleared.
Timers
The XCOUT drivability selection bit (the CPU mode register) is set
to “1” (high drive) in order to start oscillating.
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
• The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• the data transfer instruction (LDA, etc.)
• the operation instruction when the index X mode flag (T) is “1”
• the addressing mode which uses the value of a direction register
as an index
• the bit-test instruction (BBC or BBS, etc.) to a direction register
• the read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
50
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter.
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical
copies)
Package
100P6S-A
100D0
Name of Programming Adapter
PCA4738F-100A
PCA4738L-100A
Set the address of PROM programmer in the user ROM area.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after writing, the procedure shown in Figure
XC-1 is recommended to verify programming.
Programming with
PROM Programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM Programmer
Functional check in target device
Caution : The screening temperature is far higher than
the storage temperature. Never expose to
150°C exceeding 100 hours.
Fig. XC-1 Programming and testing of One Time PROM version
51
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Ratings
Unit
V
VCC
VEE
Power source voltage
–0.3 to 7.0
Pull-down power source voltage
Input voltage P24–P27, P41–P44, P46, P47,
V
CC –40 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
VI
V
P50–P57, P60–P67, P70–P77, PB0–PB3
VI
VI
VI
VI
Input voltage P40, P45
V
V
V
V
Input voltage P80–P87, PA0–PA7
V
CC –40 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
All voltages are based on VSS.
Output transistors are cut off.
Input voltage RESET, XIN
Input voltage XCIN
Output voltage P00–P07, P10–P17, P20–P23,
P30–P37, P80–P87, P90–P97, PA0–PA7
Output voltage P24–P27, P41–P44, P46, P47, P50–P57,
P60–P67, P70–P77, PB0–PB3, XOUT,
XCOUT
VO
V
CC –40 to VCC +0.3
V
VO
–0.3 to VCC
600
+0.3
V
Ta = 25°C
Pd
Power dissipation
mW
°C
Topr
Tstg
Operating temperature
–10 to 85
–40 to 125
Storage temperature
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Symbol
VCC
Unit
Parameter
Min.
4.0
Typ.
5.0
5.0
0
Max.
5.5
High-speed mode
V
V
V
V
V
V
V
V
Power source voltage
Power source voltage
Middle/Low-speed mode
2.8
5.5
VSS
VEE
VCC–38
2.0
VCC
VCC
VCC
Pull-down power source voltage
Analog reference voltage (when using A-D converter)
Analog reference voltage (when using D-A converter)
Analog power source voltage
VREF
3.0
AVSS
VIA
0
0
VCC
VCC
Analog input voltage AN0–AN15
“H” input voltage
P40–P47, P50–P57, P60–P67,
P70–P77, PB0–PB3
P24–P27
VIH
0.75VCC
V
“H” input voltage
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
VIH
VIH
VIH
VIH
0.4VCC
0.8VCC
0.8VCC
0.8VCC
VCC
VCC
VCC
VCC
V
V
V
V
P80–P87, PA0–PA7
RESET
XIN, XCIN
P40–P47, P50–P57, P60–P67,
P70–P77, PB0–PB3
P24–P27
VIL
0
0.25VCC
V
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
VIL
VIL
VIL
VIL
0
0
0
0
0.16VCC
0.2VCC
0.2VCC
0.2VCC
V
V
V
V
P80–P87, PA0–PA7
RESET
XIN, XCIN
52
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
mA
mA
Min.
Typ.
Max.
–240
“H” total peak output current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87, P90–P97,
(Note 1)
PA6, PA7
ΣIOH(peak)
ΣIOL(peak)
“H” total peak output current P41–P44, P46, P47, P50–P57,
P60–P67, P70–P77, PA0–PA5,
–60
(Note 1)
PB0–PB3
“L” total peak output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
100
–120
–30
mA
mA
mA
(Note 1)
PB0–PB3
“H” total average output current P00–P07, P10–P17, P20–P27,
P30–P37, P80–P87, P90–P97,
(Note 1)
PA6, PA7
ΣIOH(avg)
ΣIOL(avg)
“H” total average output current P41–P44, P46, P47, P50–P57,
P60–P67, P70–P77, PA0–PA5,
(Note 1)
PB0–PB3
“L” total average output current P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
50
mA
mA
mA
(Note 1)
“H” peak output current
PB0–PB3
P00–P07, P10–P17, P20–P23,
IOH(peak)
IOH(peak)
IOL(peak)
P30–P37, P80–P87, P90–P97,
–40
–10
(Note 2)
“H” peak output current
PA0–PA7
P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 2)
“L” peak output current
PB0–PB3
P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
10
mA
mA
mA
(Note 3)
PB0–PB3
“H” average output current
P00–P07, P10–P17, P20–P23,
IOH(avg)
IOH(avg)
IOL(avg)
P30–P37, P80–P87, P90–P97,
–18
–5.0
(Note 3)
PA0–PA7
“H” average output current
P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
(Note 3)
PB0–PB3
“L” average output current
P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
5.0
mA
(Note 3)
PB0–PB3
f(CNTR0)
f(CNTR1)
f(XIN)
Clock input frequency for timers 2 and 4
250
kHz
(duty cycle 50%)
8.4
50
MHz
kHz
Main clock input oscillation frequency (Note 4)
Sub-clock input oscillation frequency (Note 4, 5)
f(XCIN)
32.768
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports.The total average
current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
2 : The peak output current is the peak current flowing in each port.
3 : The average output current in an average value measured over 100 ms.
4 : When the oscillation frequency has a 50% duty cycle.
5 : When using the microcomputer in low-speed operation mode, set the sub-clock input oscillation frequency on
condition that f(XCIN) < f(XIN)/3.
53
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Vcc = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Typ.
Unit
V
Symbol
Parameter
Test conditions
Min.
Max.
“H” output voltage P00–P07, P10–P17, P20–P23,
P30–P37, P80–P87, P90–P97,
PA0–PA7
VOH
IOH=–18 mA
VCC–2.0
“H” output voltage P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
PB0–PB3
V
VOH
IOH=–10 mA
IOL=10 mA
VCC–2.0
“L” output voltage P24–P27, P41–P44, P46, P47,
P50–P57, P60–P67, P70–P77,
PB0–PB3
V
V
VOL
2.0
5.0
When using a non-port
function
Hysteresis INT0–INT4, SIN1, SIN2, SIN3, SCLK11,
SCLK2, SCLK3, CS, CNTR0, CNTR1
VT+–VT–
0.4
VT+–VT–
VT+–VT–
0.5
0.5
Hysteresis RESET, XIN
Hysteresis XCIN
“H” input current P24–P27, P40–P47, P50–P57,
V
V
VI=VCC
IH
µA
P60–P67, P70–P77, PB0–PB3
µA
µA
µA
“H” input current P80–P87, PA0–PA7 (Note)
IH
5.0
5.0
VI=VCC
VI=VCC
VI=VCC
“H” input current RESET, XCIN
“H” input current XIN
IH
IH
4.0
“L” input current P24–P27, P40–P47, P50–P57,
VI=VSS
–5.0
µA
IL
IL
P60–P67, P70–P77, PB0–PB3
“L” input current P80–P87, PA0–PA7 (Note)
µA
µA
µA
VI=VSS
VI=VSS
VI=VSS
–5.0
–5.0
“L” input current RESET, XCIN
“L” input current XIN
IL
IL
–4.0
500
Output load current P00–P07, P10–P17, P20–P23,
P30–P37, P90–P97
VEE=VCC–36 V, VOL=VCC,
Output transistors “off”
µA
µA
V
150
900
–10
ILOAD
ILEAK
VRAM
Output leakage current P00–P07, P10–P17,
P20–P23, P30–P37,
VEE=VCC–38 V,
VOL=VCC–38 V,
P80–P87, P90–P97,
Output transistors “off”
PA0–PA7
When clock is stopped
RAM hold voltage
2
5.5
Note : Except when reading ports P8 or PA.
54
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
mA
Min.
Max.
15
• High-speed mode
f(XIN) = 8.4 MHz
7.5
1
f(XCIN) = 32 kHz
Output transistors “off”
• High-speed mode
f(XIN) = 8.4 MHz (in WIT state)
f(XCIN) = 32 kHz
mA
mA
mA
Output transistors “off”
• Middle-speed mode
f(XIN) = 8.4 MHz
3
f(XCIN) = stopped
Output transistors “off”
• Middle-speed mode
f(XIN) = 8.4 MHz (in WIT state)
f(XCIN) = stopped
1
Output transistors “off”
Power source current
ICC
• Low-speed mode
f(XIN) = stopped, f(XCIN) = 32 kHz
Low-power dissipation mode set
(CM3) = 0
60
200
µA
µA
Output transistors “off”
• Low-speed mode
f(XIN) = stopped
(in WIT state)
f(XCIN) = 32 kHz
20
40
Low-power dissipation mode set
(CM3) = 0
Output transistors “off”
Increase at A-D converter operating
f(XIN) = 8.4 MHz
mA
mA
0.6
Increase at zero cross detection
(P45 = VCC)
1
All oscillation stopped
Ta = 25°C
0.1
1
µA
(in STP state)
Ta = 85°C
10
Output transistors “off”
55
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION INPUT CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
50, 60 1000
100
Max.
fZCR
∆VT
Input frequency of zero cross detection
Hz
Voltage error of zero cross detection distinction
50 Hz or 60 Hz
mV
–100
0
1/fZCR
100V AC
P45/INT1/ZCR
clamp correction
input waveform
5.7 V
0 V
VI
VT
– 0.7 V
Zero cross detection
comparator output
Fig. ZA-1 Zero cross detection input characteristics
A-D CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, high-speed operation mode f(XIN) = 500 kHz to 8.4 MHz, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
±1
Max.
8
–
–
Resolution
Bits
LSB
tc (φ)
µA
Absolute accuracy (excluding quantization error)
Conversion time
VCC = VREF = 5.12 V
VREF = 5 V
±2.5
50
TCONV
49
50
IVREF
IIA
Reference power source input current
Analog port input current
150
0.5
35
200
5.0
µA
RLADDER
Ladder resistor
kΩ
D-A CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to VCC, Ta = –10 to 85°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
2.5
Max.
8
–
–
Resolution
Bits
%
1.0
2.5
3
VCC = 4.0 to 5.5 V
VCC = 3.0 to 5.5 V
Absolute accuracy
%
Tsu
Setting time
µs
RO
Output resistor
kΩ
mA
1
4
IVREF
Reference power source input current (Note)
3.2
Note : Exclude currents flowing through the A-D converter ladder resistor
56
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2.0
119
30
Max.
tW(RESET)
tC(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT4 input “H” pulse width
INT0–INT4 input “L” pulse width
Serial I/O clock input cycle time
Serial I/O clock input “H” pulse width
Serial I/O clock input “L” pulse width
Serial I/O input setup time
tWH(XIN)
tWL(XIN)
30
tC(XcIN)
20
tWH(XcIN)
tWL(XcIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
5.0
5.0
4.0
1.6
1.6
80
80
tC(SCLK)
1.0
400
400
200
200
tWH(SCLK)
tWL(SCLK)
tsu(SCLK–SIN)
th(SCLK–SIN)
Serial I/O input hold time
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –10 to 85°C, unless otherwise noted)
Limits
Symbol
tWH(SCLK)
tWL(SCLK)
Parameter
Test conditions
CL = 100 pF
Unit
Min.
Typ.
Max.
tc(SCLK)
/2–160
ns
ns
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
tc(SCLK)
/2–160
CL = 100 pF
td(SCLK–SOUT)
tv(SCLK–SOUT)
tr(SCLK)
Serial I/O output delay time
ns
ns
ns
ns
0.2tc(SCLK
)
Serial I/O output hold time
0
Serial I/O clock output rising time
Serial I/O clock output falling time
CL = 100 pF
CL = 100 pF
40
40
tf(SCLK)
High-breakdown-voltage P-channel open-
drain output rising time (Note 1)
CL = 100 pF
VEE = VCC –36 V
tr(Pch–strg)
ns
55
High-breakdown-voltage P-channel open-
drain output falling time (Note 2)
CL = 100 pF
VEE = VCC –36 V
tf(Pch–weak)
µs
1.8
Notes 1: When the bit 7 of the FLDC mode register 1 (address 003616) is at “0”.
2: When the bit 7 of the FLDC mode register 1 (address 003616) is at “1”.
P0, P1, P2
0–P23,
P56
P52
P66
/SCLK3
/SCLK2
,
,
High-breakdown-voltage
P-channel open-drain
output port
P3, P8, P9, PA
Serial clock output port
/SCLK11
C
L
CL
(Note)
V
EE
Note : Ports P8 and PA need external resistors.
Fig. ZA-2 Circuit for measuring output switching characteristics
57
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tC(CNTR)
t
WH(CNTR)
tWL(CNTR)
0.8VCC
CNTR
CNTR
0
1
0.2VCC
tWH(INT)
tWL(INT)
0.8VCC
0.2VCC
INT
INT
0
4
-
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
t
WH(XIN
)
tWL(XIN)
0.8VCC
X
IN
0.2VCC
t
C(XCIN)
t
WH(XCIN
)
tWL(XCIN)
0.8VCC
X
CIN
0.2VCC
t
C(SCLK)
t
f
t
r
t
WL(SCLK
)
tWH(SCLK)
0.8VCC
SCLK
0.2VCC
tsu(SIN-S
CLK
)
th(SCLK-SIN)
0.8VCC
0.2VCC
S
IN
t
d(SCLK
-SOUT)
tv(SCLK-SOUT)
S
OUT
58
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
3819 GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
980109
(1/1)
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