M38225E6HFP [MITSUBISHI]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机![M38225E6HFP](http://pdffile.icpdf.com/pdf1/p00088/img/icpdf/M38225_466696_icpdf.jpg)
型号: | M38225E6HFP |
厂家: | ![]() |
描述: | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
文件: | 总78页 (文件大小:980K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀ2 clock generating circuits
DESCRIPTION
(connect to external ceramic resonator or quartz-crystal oscillator)
ꢀPower source voltage
The 3822 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
In high-speed mode .................................................. 4.0 to 5.5 V
In middle-speed mode ............................................... 2.5 to 5.5 V
(Extended operating temperature version:
2.0 to 5.5 V, Ta= – 20 to 85°C
The 3822 group has the LCD drive control circuit, an 8-channel
A-D converter, and a serial I/O as additional functions.
The various microcomputers in the 3822 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
3.0 to 5.5 V, Ta= – 40 to – 20°C)
(One time PROM version: 2.5 to 5.5 V)
For details on availability of microcomputers in the 3822 group, re-
fer to the section on group expansion.
(M version: 2.2 to 5.5 V)
(H version: 2.0 to 5.5 V)
In low-speed mode .................................................... 2.5 to 5.5 V
(Extended operating temperature version:
2.0 to 5.5 V, Ta= – 20 to 85°C
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀThe minimum instruction execution time ........................... 0.5 µs
(at 8 MHz oscillation frequency)
3.0 to 5.5 V, Ta= – 40 to – 20°C)
(One time PROM version: 2.5 to 5.5 V)
ꢀMemory size
(M version: 2.2 to 5.5 V)
ROM ................................................................. 4 K to 48 K bytes
RAM ................................................................. 192 to 1024 bytes
ꢀProgrammable input/output ports ............................................ 49
(H version: 2.0 to 5.5 V)
ꢀPower dissipation
In high-speed mode ..........................................................32 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 45 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
ꢀOperating temperature range................................... – 20 to 85°C
(Extended operating temperature version: – 40 to 85 °C)
ꢀ
Software pull-up/pull-down resistors (Ports P0-P7 except port P40)
ꢀInterrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
ꢀTimers ........................................................... 8-bit ꢀ 3, 16-bit ꢀ 2
ꢀSerial I/O ...................... 8-bit ꢀ 1 (UART or Clock-synchronized)
ꢀA-D converter ................................................. 8-bit ꢀ 8 channels
ꢀLCD drive control circuit
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
Bias ................................................................................... 1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG7
65
66
67
68
69
70
71
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P20
P21
P22
P23
P24
P25
P26
P27
VSS
XOUT
XIN
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VCC
VREF
AVSS
COM3
COM2
COM1
COM0
VL3
72
73
74
75
76
77
78
79
80
M38224M6HXXXFP
P70/XCOUT
P71/XCIN
RESET
P40
P41/φ
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package type : 80P6N-A (80-pin plastic-molded QFP)
Fig. 1 M38224M6HXXXFP pin configuration
(The pin configuration of 80D0 is same as this.)
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
40
61
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
/SEG30
/SEG31
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M38223M4MXXXGP
M38224M6HXXXHP
V
CC
REF
AVSS
V
X
X
SS
V
OUT
IN
COM
COM
COM
COM
3
2
1
0
P7
P7
0
/XCOUT
1
/XCIN
RESET
P4
P4
0
1/φ
V
V
V
L3
L2
L1
P4
P4
2
/INT
/INT
0
1
3
Package type : 80P6S-A/80P6Q-A
(80-pin plastic-molded QFP)
Fig. 2 M38223M4MXXXGP/M38224M6HXXXHP pin configuration
2
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
p u e k a w n o y e K
n o i t c n u f t r o p e m i t l a e R
φ
1 T N I , 0 T N I
3 T N I , 2 T N I
T D A
Fig. 3 Functional block diagram
3
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”).
VREF
AVSS
Analog refer-
ence voltage
•Reference voltage input pin for A-D converter.
Analog power
source
•GND input pin for A-D converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
LCD power
source
VL1–VL3
•Input 0 – VL3 voltage to LCD.
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
SEG0–SEG11
Segment output
I/O port P0
•LCD segment output pins.
P00/SEG16–
P07/SEG23
•8-bit output port.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each port to be individually
programmed as either input or output.
P10/SEG24–
P17/SEG31
I/O port P1
I/O port P2
•Pull-down control is enabled.
•Key input (key-on wake-up) interrupt
•8-bit I/O port.
P20 – P27
input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•4-bit input port.
•LCD segment output pins
P3
P3
4
/SEG12
/SEG15
–
Input port P3
7
•CMOS compatible input level.
•Pull-down control is enabled.
4
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function except a port function
Table 2 Pin description (2)
Pin
Name
Function
Input port P4
P40
•1-bit Input port.
•CMOS compatible input level.
•7-bit I/O port.
•φ clock output pin
•Interrupt input pins
P41/φ
I/O port P4
•CMOS compatible input level.
•CMOS 3-state output structure.
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
•Serial I/O function pins
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
I/O port P5
•Interrupt input pins
P50/INT2,
P51/INT3
•CMOS compatible input level.
•CMOS 3-state output structure.
•Real time port function pins
•Timer X, Y function pins
P52/RTP0,
P53/RTP1
•I/O direction register allows each pin to be individually
programmed as either input or output.
P54/CNTR0,
P55/CNTR1
•Pull-up control is enabled.
P56/TOUT
P57/ADT
•Timer 2 output pins
•A-D trigger input pins
P60/AN0–
P67/AN7
I/O port P6
•8-bit I/O port.
•A-D conversion input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•2-bit I/O port.
P70/XCOUT,
P71/XCIN
I/O port P7
•Sub-clock generating circuit I/O pins.
•CMOS compatible input level.
•CMOS 3-state output structure.
(Connect a resonator. External clock
cannot be used.)
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
5
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M38224
M
6
H
XXX
FP
Package type
FP : 80P6N-A package
GP : 80P6S-A package
HP : 80P6Q-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM version shipped in blank and EPROM version.
Normally, using hyphen.
When electrical characteristic, or division of identification code using
alaphanumeric character
– :Standard
D :Extended operating temperature version
M :M version
H :H version
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (STANDARD, ONE TIME
PROM VERSION, EPROM VERSION)
Mitsubishi plans to expand the 3822 group (Standard, One Time
PROM version, EPROM version) as follows:
Memory Size
ROM size ............................................................. 8 K to 48 K bytes
RAM size ............................................................ 384 to 1024 bytes
Package
Memory Type
Support for Mask ROM, One Time PROM, and EPROM versions
80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
80D0 ....................... 0.8 mm-pitch ceramic LCC (EPROM version)
Memory Expansion Plan
ROM size (bytes)
48K
Under development
M38227EC
32K
28K
24K
20K
Mass product
M38223M4/E4
16K
12K
8K
Mass product
M38222M2
4K
1024
192 256
384
512
RAM size (bytes)
640
768
896
Note: Products under development or planning: the development schedule and specifications
may be revised without notice.
Fig. 5 Memory expansion plan
Currently products are listed below.
Table 3 List of products
As of August 2000
ROM size (bytes)
Product
RAM size (bytes)
384
Package
Remarks
ROM size for User in (
)
M38222M2-XXXFP
M38222M2-XXXGP
M38222M2-XXXHP
M38223M4-XXXFP
M38223E4FP
80P6N-A
80P6S-A
80P6Q-A
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
8192
(8062)
80P6N-A
80P6S-A
One Time PROM version (blank)
Mask ROM version
16384
(16254)
M38223M4-XXXGP
M38223E4GP
512
One Time PROM version (blank)
Mask ROM version
M38223M4-XXXHP
M38223E4HP
80P6Q-A
One Time PROM version (blank)
EPROM version
80D0
80P6N-A
80P6Q-A
80D0
M38223E4FS
M38227ECFP
One Time PROM version (blank)
One Time PROM version (blank)
EPROM version
49152
(49022)
1024
M38227ECHP
M38227ECFS
7
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Package
(EXTENDED OPERATING TEMPERATURE
VERSION)
80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
Mitsubishi plans to expand the 3822 group (extended operating
temperature version) as follows:
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................................ 48 K bytes
RAM size ....................................................................... 1024 bytes
Memory Expansion Plan
ROM size (bytes)
48K
Mass product
M38227MCD
32K
28K
24K
20K
16K
12K
8K
4K
1024
192 256
384
512
640
768
896
RAM size (bytes)
Fig. 6 Memory expansion plan for extended operating temperature version
Currently products are listed below.
Table 4 List of products for extended operating temperature version
As of August 2000
ROM size (bytes)
ROM size for User in (
RAM size (bytes)
1024
Package
80P6N-A
Remarks
Product
)
M38227MCDXXXFP
49152(49022)
Mask ROM version
8
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (M VERSION)
Package
Mitsubishi plans to expand the 3822 group (M version) as follows:
80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6S-A .................................. 0.65 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................... 16 K to 24 K bytes
RAM size .............................................................. 512 to 640 bytes
Memory Expansion Plan
ROM size (bytes)
48K
32K
28K
24K
Mass product
M38224M6M
20K
Mass product
M38223M4M
16K
12K
8K
4K
1024
192 256
384
512
RAM size (bytes)
640
768
896
Fig. 7 Memory expansion plan for M version
Currently products are listed below.
Table 5 List of products for M version
As of August 2000
ROM size (bytes)
Product
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
M38223M4MXXXFP
M38223M4MXXXGP
M38223M4MXXXHP
M38224M6MXXXFP
M38224M6MXXXHP
80P6N-A
80P6S-A
80P6Q-A
80P6N-A
80P6Q-A
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
16384
(16254)
512
640
24576
(24446)
9
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION (H VERSION)
Mitsubishi plans to expand the 3822 group (H version) as follows:
Package
80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................... 16 K to 48 K bytes
RAM size ............................................................ 512 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
48K
Mass product
M38227MCH
Mass product
M38227M8H
32K
28K
24K
Mass product
M38224M6H
20K
Mass product
M38223M4H
16K
12K
8K
4K
1024
192 256
384
512
RAM size (bytes)
640
768
896
Fig. 8 Memory expansion plan for H version
Currently products are listed below.
Table 6 List of products for H version
As of August 2000
ROM size (bytes) ROM
Product
RAM size (bytes)
512
Package
Remarks
size for User in (
)
M38223M4HXXXFP
M38223M4HXXXHP
M38224M6HXXXFP
M38224M6HXXXHP
M38227M8HXXXFP
M38227M8HXXXHP
M38227MCHXXXFP
M38227MCHXXXHP
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
16384
(16254)
24576
(24446)
640
32768
(32638)
1024
49152
(49022)
10
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3822 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 10.
Store registers other than those described in Figure 10 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b7
b0
PCH
PCL
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig.9 740 Family CPU register structure
11
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 7 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
12
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 8 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
V flag
–
T flag
SET
CLT
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
13
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 11 Structure of CPU mode register
14
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ter (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
004016
005016
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
LCD display RAM area
010016
RAM
XXXX16
084016
Reserved area
Not used
ROM area
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 12 Memory map diagram
15
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
000016
002016
002116
002216
002316
002416
Timer X (low) (TXL)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Timer 1 (T1)
000116 Port P0 direction register (P0D)
Port P1 (P1)
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
Port P1 output control register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516 Timer 2 (T2)
Timer 3 (T3)
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
φ output control register (CKOUT)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
A-D control register (ADCON)
A-D conversion register (AD)
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Transmit/Receive buffer register
Segment output enable register (SEG)
LCD mode register (LM)
(TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Fig. 13 Memory map of special function register (SFR)
16
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
b7
b0
Direction Registers (ports P2, P41-P47, and
P5-P7)
PULL register A
(PULLA: address 001616)
The 3822 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P41–P47 and P5-P7). The I/O ports P2,
P41–P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
P00–P07 pull-down
P10–P17 pull-down
P20–P27 pull-up
P34–P37 pull-down
P70, P71 pull-up
Not used (return “0” when read)
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
b7
b0
PULL register B
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
(PULLB : address 001716)
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
0: Disable
1: Enable
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 14 Structure of PULL register A and PULL register B
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
17
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 List of I/O port function
Name
Input/Output
Input/output,
Non-Port Function
Pin
I/O Format
Related SFRs
Diagram No.
P00/SEG16–
Port P0
CMOS compatible
LCD segment output
PULL register A
(1)
P07/SEG23
individual ports input level
Segment output enable
register
CMOS 3-state output
P10/SEG24–
P17/SEG31
Port P1
Port P2
Input/output,
individual bits
CMOS compatible
input level
(2)
(3)
(4)
P20–P27
PULL register A
Key input (key-on
wake-up) interrupt
input
Interrupt control register 2
CMOS 3-state output
Input
Input
CMOS compatible
input level
PULL register A
P34/SEG12–
P37/SEG15
LCD segment output
Port P3
Port P4
Segment output enable
register
CMOS compatible
input level
P40
P41/φ
(5)
(2)
φ clock output
CMOS compatible
input level
PULL register B
Input/output,
individual bits
φ
output control register
CMOS 3-state output
P42/INT0,
P43/INT1
PULL register B
External interrupt input
Interrupt edge selection
register
(6)
(7)
(8)
(9)
(2)
Serial I/O function I/O
External interrupt input
PULL register B
P44/RXD
Serial I/O control register
Serial I/O status register
UART control register
P45/TXD
P46/SCLK
P47/SRDY
CMOS compatible
input level
P50/INT2,
P51/INT3
PULL register B
Input/output,
individual bits
Port P5
Interrupt edge selection
register
CMOS 3-state output
Real time port
function output
PULL register B
P52/RTP0,
P53/RTP1
(10)
(11)
Timer X mode register
PULL register B
Timer X function I/O
P54/CNTR0
P55/CNTR1
P56/TOUT
Timer X mode register
Timer Y function input
Timer 2 function output
PULL register B
(12)
(13)
Timer Y mode register
PULL register B
Timer 123 mode register
A-D trigger input
(12)
(14)
PULL register B
P57/ADT
A-D control register
P60/AN0–
P67/AN7
Input/output,
individual bits
Port P6
Port P7
CMOS compatible
input level
A-D conversion input
CMOS 3-state output
(15)
(16)
CMOS compatible
input level
P70/XCOUT
P71/XCIN
Input/output,
individual bits
PULL register A
Sub-clock
CPU mode register
generating circuit I/O
CMOS 3-state output
LCD common output
LCD segment output
COM0–COM3
SEG0–SEG11
Output
Output
LCD mode register
(17)
(18)
Common
Segment
Notes1: How to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to VSS through the input-stage gate.
18
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P1
(2) Ports P2, P42, P43, P50, P51
V
L2/VL3
Pull-up control
V
L1/VSS
Segment output enable bit
(Note)
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Key input (Key-on wake-up) interrupt input
INT –INT interrupt input
0
3
Pull-down control
Segment output enable bit
Note: Bit 0 of direction register.
(3) Ports P34–P37
(4) Port P4
0
VL2/VL3
Data bus
V
L1/VSS
Data bus
Pull-down control
Segment output enable bit
(6) Port P4
4
(5) Port P4
1
Pull-up control
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
φ output control bit
φ
Serial I/O input
Fig. 15 Port block diagram (1)
19
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8) Port P4
6
(7) Port P4
5
Serial I/O clock-
synchronized selection bit
Serial I/O enable bit
Pull-up control
Pull-up control
P4
5
/T
x
D P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output
Serial I/O clock input
(9) Port P4
7
(10) Ports P52, P53
Pull-up control
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Real time port control bit
Data for real time port
Serial I/O ready output
(11) Port P5
4
(12) Ports P55, P5
7
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer X operating mode bit
(Pulse output mode selection)
Timer output
CNTR1 interrupt input
A-D trigger interrupt input
CNTR0 interrupt input
Fig. 16 Port block diagram (2)
20
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(14) Port P6
(13) Port P5
6
Pul-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
T
OUT output control bit
Timer output
A-D conversion input
Analog input pin selection bit
(15) Port P7
0
(16) Port P7
1
Port X
C
switch bit + Pull-up control
Port XC switch bit + Pull-up control
Port X
C
switch bit
Port X
C
switch bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillation circuit
Port P7
Sub-clock generating circuit input
1
Port XC switch bit
(17) COM
0
–COM
3
(18) SEG –SEG11
0
V
L2/VL3
VL3
The voltage applied to the sources of
V
L1/VSS
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
V
V
L2
L1
The gate input signal of each transistor is
controlled by the LCD duty ratio and the
bias value.
Fig. 17 Port block diagram (3)
21
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
nal, and one software.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
ꢀNotes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit or the interrupt source select bit
to “1”.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
ꢀSet the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
ꢀSet the corresponding interrupt enable bit to “1” (enabled).
Table 10 Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
At reset
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
At detection of either rising or External interrupt
falling edge of INT0 input
(active edge selectable)
INT1
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
At detection of either rising or External interrupt
3
4
5
falling edge of INT1 input
(active edge selectable)
Serial I/O
reception
At completion of serial I/O data
reception
Valid when serial I/O is selected
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
Serial I/O
transmission
Valid when serial I/O is selected
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
8
9
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
CNTR1
11
FFE916
FFE816
At detection of either rising or External interrupt
falling edge of CNTR1 input
(active edge selectable)
Timer 1
INT2
12
13
FFE716
FFE516
FFE616
FFE416
At timer 1 underflow
At detection of either rising or External interrupt
falling edge of INT2 input
(active edge selectable)
INT3
At detection of either rising or
falling edge of INT3 input
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
External interrupt
(active edge selectable)
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode)
(Valid at falling)
ADT
At falling of ADT input
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
At completion of A-D conversion
At BRK instruction execution
A-D conversion
BRK instruction
Valid when A-D interrupt is se-
lected
17
FFDD16
FFDC16
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
22
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 18 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
1
2
3
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
INT
INT
2
interrupt request bit
interrupt request bit
3
Timer Y interrupt request bit
Key input interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
INT
INT
2
interrupt enable bit
interrupt enable bit
3
Timer Y interrupt enable bit
Key input interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 19 Structure of interrupt-related registers
23
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
“1” to “0”. An example of using a key input interrupt is shown in
Figure 20, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Key Input Interrupt (Key-on wake-up)
A Key-on wake-up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PX
X
“L” level output
PULL register A bit 2 = “1”
Port P2
direction register = “1”
7
Key input interrupt request
ꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
Port P2
latch
7
P2
7
output
output
Port P2
6
direction register = “1”
ꢀ
Port P2
latch
6
P2
6
Port P2
5
direction register = “1”
ꢀ
ꢀ
Port P2
latch
5
P2
5
output
output
Port P2
4
direction register = “1”
Port P2
latch
4
P2
4
Port P2
direction register = “0”
3
Port P2
ꢀ
ꢀ
ꢀꢀ
ꢀꢀ
Input reading circuit
Port P2
latch
3
P2
P2
3
input
Port P2
direction register = “0”
2
Port P2
latch
2
2
input
input
Port P2
direction register = “0”
1
ꢀ
ꢀꢀ
Port P2
latch
1
P2
1
Port P2
0
direction register = “0”
ꢀ
ꢀ
Port P2
latch
0
P2
0
input
ꢀ P-channel transistor for pull-up
ꢀ
ꢀꢀ CMOS output buffer
Fig. 20 Connection example when using key input interrupt and port P2 block diagram
24
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
responding to that timer is set to “1”.
TIMERS
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 3822 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Real time port
control bit “1”
Q D
Data bus
P52 data for real time port
P52
Latch
“0”
P52 latch
Real time port
control bit “1”
P52 direction register
Q D
P53 data for real time port
Real time port
P53
Latch
“0”
P53 direction register
control bit “0”
Timer X mode register
write signal
P53 latch
“1”
f(XIN)/16
(f(XIN)/16 in low-speed mode✽)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer X (low) latch (8)
Timer X (low) (8)
Timer X (high) latch (8)
Timer X (high) (8)
Timer X
interrupt
request
“0”
P54/CNTR0
“10”
“1”
Pulse width
CNTR0
interrupt
request
measurement
mode
CNTR0 active
edge switch bit
Pulse output mode
“0”
“1”
S
Q
Q
Timer Y operating mode bits
T
“00”,“01”,“10”
CNTR1
interrupt
request
P54 direction register
Pulse width HL continuously measurement mode
Rising edge detection
P54 latch
Pulse output mode
f(XIN)/16
“11”
Period
measurement mode
Falling edge detection
✽
(f(XCIN)516 in low-speed mode
)
Timer Y stop
control bit
CNTR1 active
edge switch bit
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
“00”,“01”,“11”
Timer Y
interrupt
request
“0”
P55/CNTR1
Timer Y (low) (8)
“10” Timer Y operating
“1”
mode bits
f(XIN)/16
Timer 1
interrupt
request
(f(XCIN)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 2 write
control bit
Timer 2 count source
selection bit
Timer 2 latch (8)
Timer 1 latch (8)
Timer 1 (8)
“0”
Timer 2
interrupt
request
XCIN
Timer 2 (8)
“1”
“1”
f(XIN)/16
✽
(f(XCIN)/16 in low-speed mode
)
TOUT output
TOUT output
control bit
active edge
TOUT output
control bit
switch bit
“0”
S
Q
Q
P56/TOUT
T
“1”
P56 latch
P56 direction register
Timer 3 latch (8)
Timer 3 (8)
“0”
Timer 3
interrupt
request
f(XIN)/16(f(XCIN)/16 in low-speed mode✽)
“1”
Timer 3 count
source selection bit
✽
Internal clock φ =XCIN /2
Fig. 21 Timer block diagram
25
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
ꢀReal time port control
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
output independent of the timer X operation.) If the data for the
real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
ꢀNote on CNTR0 interrupt active edge
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
(3) Event Counter Mode
switch bit.
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
b7
b0
Timer X mode register
(TXM : address 002716
)
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P5
2
data for real time port
data for real time port
P53
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
ꢀTimer X write control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when writing in the timer latch at
the timer underflow, the value is set in the timer and the latch at
one time. Additionally, unexpected value may be set in the high-or-
der counter when the writing in high-order latch and the underflow
of timer X are performed at the same timing.
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for CNTR
Timer X stop control bit
0 : Count start
0 interrupt
1 : Count stop
Fig. 22 Structure of timer X mode register
26
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
Timer Y mode register
(TYM : address 002816
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period Measurement Mode
0
0
1
0 : Timer mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously measurement
mode
1
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
Timer Y stop control bit
0 : Count start
1 interrupt
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
1 : Count stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
Fig. 23 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
ꢀNote on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
27
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer
whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916)
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
ꢀTimer 2 write control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
ꢀTimer 2 output control
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN)
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output
mode.
Not used (return “0” when read)
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.
ꢀNotes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Fig. 24 Structure of timer 123 mode register
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
28
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
Address 001816
Receive buffer register
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
1/4
(f(XCIN) in low-speed mode)
1/4
P47/SRDY1
Clock control circuit
Falling-edge detector
F/F
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit buffer register
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 25 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial output T
XD
Serial input R
X
D
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
Notes
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 26 Operation of clock synchronous serial I/O function
29
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
OE
Receive buffer register
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
P45
/T
X
D
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 27 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=0
TSC=1ꢀ
SP
TBE=1
TBE=1
ST
D
0
D1
ST
D
0
D1
SP
Serial output TXD
1 start bit
ꢀGenerated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D
0
D
1
ST
D
0
D1
Serial input RXD
Notes
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 28 Operation of UART serial I/O function
30
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON) ]001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
ꢀNotes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
ꢀSet the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀSet the transmit enable bit to “1”.
ꢀSet the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀSet the serial I/O transmit interrupt enable bit to “1” (enabled).
31
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 001916
Serial I/O control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 29 Structure of serial I/O control registers
32
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
b7
b0
A-D control register
(ADCON : address 003416)
Analog input pin selection bits
0 0 0 : P60/AN0
0 0 1 : P61/AN1
0 1 0 : P62/AN2
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
0 1 1 : P63/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
Fig. 30 Structure of A-D control register
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock
φ.
Data bus
b7
b0
A-D control register
P57/ADT
3
ADT/A-D interrupt request
A-D control circuit
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
A-D conversion
register
Comparator
8
Resistor ladder
AVSS
VREF
Fig. 31 A-D converter block diagram
33
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
ꢀLCD display RAM
ꢀSegment output enable register
ꢀLCD mode register
ꢀSelector
Table 11 Maximum number of display pixels at each duty ratio
ꢀTiming controller
Duty ratio
2
Maximum number of display pixel
64 dots
ꢀCommon driver
ꢀSegment driver
or 8 segment LCD 8 digits
96 dots
ꢀBias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
3
4
or 8 segment LCD 12 digits
128 dots
Up to 128 pixels can be controlled for LCD display. When the LCD
or 8 segment LCD 16 digits
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enable bit 0
0 : Input port P3 –P3
4
7
1 : Segment output SEG12–SEG15
Segment output enable bit 1
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
Segment output enable bit 2
0 : I/O port P02–P07
1 : Segment output SEG18–SEG23
Segment output enable bit 3
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
Segment output enable bit 4
0 : I/O port P1
2
1 : Segment output SEG26
Segment output enable bit 5
0 : I/O port P13–P17
1 : Segment output SEG27–SEG31
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
Bias control bit
0 : 1/3 bias
0
0
0
, COM
–COM
–COM
1
2
3
)
)
)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (or f(XCIN)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 32 Structure of segment output enable register and LCD mode register
34
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 33 Block diagram of LCD controller/driver
35
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 12 Bias control and applied voltage to VL1–VL3
Bias Control and Applied Voltage to LCD
Power Input Pins
Bias value
Voltage value
To the LCD power input pins (VL1–VL3), apply the voltage shown
VL3=VLCD
in Table 12 according to the bias value.
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
VL3=VLCD
1/2 bias
VL2=VL1=1/2 VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Note 1: VLCD is the maximum value of supplied voltage for the
LCD panel.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Table 13 Duty ratio control and common pins used
Duty ratio selection bit
Duty
Common pins used
ratio
Bit 1
Bit 0
2
3
4
0
1
1
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Contrast control
Contrast control
V
L3
V
L3
R1
R4
V
L2
V
L2
R2
R3
V
L1
V
L1
R5
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
Fig. 34 Example of circuit at each bias
36
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
LCD Drive Timing
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
(frequency of count source for LCDCK)
f(LCDCK) =
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
Bit
7
6
5
4
3
1
0
2
Address
SEG0
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
COM0
COM3
COM2 COM1
COM2 COM1 COM0
COM3
Fig. 35 LCD display RAM map
37
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
L3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
L3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
0
COM
1
V
L3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 36 LCD drive waveform (1/2 bias)
38
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
VL3
SEG
0
VSS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 37 LCD drive waveform (1/3 bias)
39
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
φ CLOCK SYSTEM OUTPUT FUNCTION
The internal system clock φ can be output from port P41 by setting
the φ output control register. Set bit 1 of the port P4 direction reg-
ister to “1” when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002A16
)
φ output control bit
0 : port function
1 : φ clock output
Not used (return “0” when read)
Fig. 38 Structure of φ output control register
40
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
Power
source
voltage
RESET
VCC
0V
Reset input
voltage
V
IL spec.
0V
RESET
VCC
Power source voltage
detection circuit
Fig. 39 Reset Circuit Example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
?
?
?
?
FFFC
FFFD
ADH, ADL
Data
ADL
ADH
SYNC
XIN : about 8000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ)
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 40 Reset Sequence
41
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Register Contents
0016
Address
000116
(1)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
PULL register A
0016
0016
0016
0016
0016
0016
000316
000516
000916
000B16
000D16
000F16
001616
001716
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
003416
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(2)
(3)
(4)
(5)
(6)
(7)
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
(8)
0016
0
(9)
PULL register B
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
Sirial I/O status register
Sirial I/O control register
UART control register
Timer X(Low)
0016
0
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
0016
1
Timer X(High)
Timer Y(Low)
Timer Y(High)
Timer 1
Timer 2
Timer 3
Timer X mode register
Timer Y mode register
Timer 123 mode register
φ output control register
A-D control register
Segment output enable register
LCD mode register
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0016
0016
0016
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
1
0016
0016
0016
0016
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Contents of address FFFD16
Contents of address FFFC16
(PCH)
(PCL)
Note: The contents of all other registers and RAM are undefined after reset, so they must be
initialized by software.
ꢀ: undefined
Fig. 41 Initial status of microcomputer after reset
42
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 3822 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait Mode
Frequency Control
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) High-speed Mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode
ꢀThe internal clock φ is half the frequency of XCIN.
ꢀA low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
X
CIN
X
COUT
X
IN
XOUT
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
Rf
Rd
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high-
speed and low-speed, set the frequency on condition that
f(XIN) > 3f(XCIN).
C
OUT
C
CIN
C
COUT
CIN
Fig. 42 Ceramic resonator circuit
XCOUT
XCIN
XIN
XOUT
Rf
Open
Rd
External oscillation circuit
CCIN
CCOUT
VCC
VSS
Fig. 43 External clock input circuit
43
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“1”
“0”
Port XC switch bit
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
(Note)
XIN
XOUT
Low-speed mode
“1”
“1”
“0”
Timer 1
Timer 2
1/2
1/2
1/4
“0”
Middle-/High-speed mode
“0”
“1”
Main clock division ratio selection bit
Middle-speed mode
“1”
“0”
Timing φ
(Internal system clock)
High-speed mode
or Low-speed mode
Main clock stop bit
Q
Q
S
R
S
R
S
R
Q
WIT
instruction
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port XC switch bit to “1” .
Fig.44 Clock generating circuit block diagram
44
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM6
Middle-speed mode (f(φ) = 1 MHz)
High-speed mode (f(φ) = 4 MHz)
“1”
“0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM6
Middle-speed mode (f(φ) = 1 MHz)
High-speed mode (f(φ) = 4 MHz)
“1”
“0”
CM7 = 0 (8 MHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7 = 0 (8 MHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM6
Low-speed mode (f(φ) =16 kHz)
Low-speed mode (f(φ) = 16 kHz)
“1”
“0”
CM7 = 1 (32 kHz selected)
CM6 = 0 (High-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port
1: XCIN, XCOUT
CM5 : Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
CM6 : Main clock division ratio selection bit
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
CM7 : Internal system clock selection bit
0: XIN–XOUT selected
CM6
Low-speed mode (f(φ) =16 kHz)
Low-speed mode (f(φ) = 16 kHz)
CM7 = 1 (32 kHz selected)
CM6 = 1 (Middle-speed)
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
“1”
“0”
CM7=1(32 kHz selected)
CM6=0(High-speed)
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is
ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 45 State transitions of system clock
45
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
sion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Interrupt
Instruction Execution Time
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Decimal Calculations
The frequency of the internal clock φ is half of the XIN frequency.
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
46
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
✽
1.Mask ROM Order Confirmation Form
✽
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk
Table 14 Programming adapter
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Mitsubishi MCU Technical Information” Homepage
(http://www.infomicom.mesc.co.jp/).
Package
80P6N-A
80P6S-A
80P6Q-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738G-80A
PCA4738H-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 46 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 46 Programming and testing of One Time PROM version
47
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Absolute maximum ratings (Standard, One Time PROM version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
All voltages are based on VSS.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
V
V
V
V
V
V
V
Input voltage VL1
–0.3 to VL2
VL1 to VL3
VI
VI
VI
VI
VO
Input voltage VL2
Input voltage VL3
VL2 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
VO
–0.3 to VL3+0.3
–0.3 to VCC +0.3
300
V
V
VO
Pd
mW
°C
°C
Ta = 25°C
Operating temperature
Storage temperature
Topr
Tstg
–20 to 85
–40 to 125
Table 16 Recommended operating conditions (Standard, One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
Typ.
5.0
5.0
5.0
0
Max.
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
4.0
2.5
2.5
5.5
5.5
5.5
VCC
Power source voltage
Power source voltage
VSS
VREF
AVSS
VIA
V
V
V
V
V
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
2.0
VCC
0
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
VIH
0.7VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
48
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 Recommended operating conditions (Standard, One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
40
–20
–20
20
20
–2
“H” peak output current
–5
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
IOL(peak)
IOL(peak)
5
“L” peak output current
“L” peak output current
mA
mA
P00–P07, P10–P17 (Note 2)
10
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
–1.0
–2.5
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
mA
mA
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
mA
mA
“L” average output current
“L” average output current
2.5
5.0
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
(2.5 V ≤ VCC ≤ 4.0 V)
4.0
MHz
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(2ꢀVCC)-4 MHz
8.0 MHz
(4ꢀVCC)-8 MHz
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
Main clock input oscillation frequency
(Note 4)
f(XIN)
High-speed mode
(2.5 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea-
sured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
49
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Electrical characteristics (Standard, One Time PROM version)
(VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
IOH = –2.5 mA
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 2.5 V
VCC–1.0
VCC–2.0
VCC–0.5
V
V
IOH = –5 mA
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–1.0
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P17
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
1.0
V
IOL = 10 mA
IOL = 2.5 mA
2.0
0.5
V
V
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 2.5 V
1.0
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.5 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
140
45
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
–5.0
µA
µA
–4.0
Note: When “1” is set to port XC switch bit (bit 4 at address 003B16) of the CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
50
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 Electrical characteristics (Standard, One Time PROM version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
2.0
Typ.
Max.
5.5
VRAM
V
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
13
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
1.6
3.2
mA
Output transistors “off”
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
25
7.0
15
36
14
22
9.0
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
4.5
0.1
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10
Table 20 A-D converter characteristics (Standard, One Time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 8 MHz, middle-/high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Bits
Resolution
VCC = VREF = 5V
±2
LSB
Absolute accuracy
(excluding quantization error)
12.5
(Note)
f(XIN) = 8 MHz
VREF = 5 V
tCONV
Conversion time
µs
RLADDER
IVREF
IIA
Ladder resistor
kΩ
µA
µA
35
12
50
100
200
5.0
Reference power source input current
Analog port input current
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
51
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Timing requirements 1 (Standard, One Time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 22 Timing requirements 2 (Standard, One Time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
500/(VCC-2)
250/(VCC-2)-20
250/(VCC-2)-20
230
230
2000
950
950
400
200
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
52
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 23 Switching characteristics 1 (Standard, One Time PROM version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note 1)
–30
tv(SCLK–TXD)
tr(SCLK)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
10
10
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 24 Switching characteristics 2 (Standard, One Time PROM version)
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–50
tC (SCLK)/2–50
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
–30
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
20
20
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
53
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 25 Absolute maximum ratings (Extended operating temperature version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
All voltages are based on VSS.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
VI
VI
VI
VI
VO
Input voltage VL1
Input voltage VL2
VL2 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
Input voltage VL3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
–0.3 to VL3
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
VO
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
–0.3 to VL3
–0.3 to VCC +0.3
300
V
V
VO
Pd
Ta = 25°C
mW
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
–40 to 85
–65 to 150
Table 26 Recommended operating conditions (Extended operating temperature version)
(VCC = 2.0 to 5.5 V, Ta = –20 to 85 °C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
Typ.
5.0
5.0
5.0
5.0
5.0
0
Max.
High-speed mode f(XIN) = 8 MHz
4.0
2.0
3.0
2.0
3.0
5.5
5.5
5.5
5.5
5.5
–
Ta = 20 to 85°C
– –
Ta = 40 to 20°C
–
Ta = 20 to 85°C
Middle-speed mode
f(XIN) = 8 MHz
VCC
Power source voltage
Low-speed mode
–
–
Ta = 40 to 20°C
Power source voltage
VSS
VREF
AVSS
VIA
V
V
V
V
V
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
2.0
VCC
0
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4 = 0)
VIH
0.7VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4 = 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
54
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 27 Recommended operating conditions (Extended operating temperature version)
(VCC = 2.0 to 5.5 V, Ta = –20 to 85 °C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20° C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
40
–20
–20
20
20
–2
“H” peak output current
–5
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
P00–P07, P10–P17 (Note 2)
5
mA
mA
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
10
(Note 2)
–1.0
–2.5
mA
mA
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
2.5
5.0
mA
mA
“L” average output current
“L” average output current
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
4.0
MHz
MHz
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
VCC
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
Main clock input oscillation frequency
(Note 4)
f(XIN)
High-speed mode
(2.0 V ≤ VCC ≤ 4.0 V)
2ꢀVCC MHz
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mesured
over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
55
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 28 Electrical characteristics (Extended operating temperature version)
(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –2.5 mA
Unit
Min.
Max.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 3.0 V
VCC–0.9
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 3.0 V
VCC–0.9
V
2.0
0.5
V
V
IOL = 5 mA
“L” output voltage
P00–P07, P10–P17
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 3.0 V
1.1
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 2.5 mA
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 3.0 V
1.1
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.0 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
170
55
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
–5.0
µA
µA
–4.0
Note: When “1” is set to port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above men-
tioned.
56
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 29 Electrical characteristics (Extended operating temperature version)
(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, and VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
V
Min.
2.0
Max.
5.5
VRAM
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
1.6
13
mA
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
3.2
Output transistors “off”
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
25
7.0
15
36
14
22
9.0
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
4.5
0.1
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10
Table 30 A-D converter characteristics (Extended operating temperature version)
(VCC = 3.0 to 5.5 V, VSS =AVSS = 0 V, Ta = –40 to 85 °C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
±2
LSB
Absolute accuracy
(excluding quantization error)
VCC = VREF = 4.0V to 5.5V
f(XIN) = 8 MHz
VCC = VREF = 3.0 V to 4.0V
f(XIN) = 2 ꢀ VCC MHz
12.5
(Note)
tCONV
Conversion time
µs
f(XIN) = 8 MHz
VREF = 5 V
RLADDER
IVREF
IIA
Ladder resistor
35
kΩ
µA
µA
100
200
5.0
12
50
Reference power source input current
Analog port input current
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
57
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 31 Timing requirements 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
125
45
twH(XIN)
twL(XIN)
Main clock input “L” pulse width
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
CNTR0, CNTR1 input cycle time
250
105
105
80
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
80
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 32 Timing requirements 2 (Extended operating temperature version)
(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
125
twH(XIN)
twL(XIN)
45
Main clock input “L” pulse width
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
CNTR0, CNTR1 input cycle time
900/(VCC–0.4)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
450/(VCC–0.4)–20
450/(VCC–0.4)–20
230
230
2000
950
950
400
200
twH(SCLK)
twL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
58
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 33 Switching characteristics 1 (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note 1)
–30
tv(SCLK–TXD)
tr(SCLK)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
10
10
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 34 Switching characteristics 2 (Extended operating temperature version)
(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20 °C, unless otherwise noted)
Limits
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–50
tC (SCLK)/2–50
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
–30
50
50
50
50
tf(SCLK)
20
20
tr(CMOS)
tf(CMOS)
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
59
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 35 Absolute maximum ratings (M version)
Symbol Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
All voltages are based on VSS.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
V
V
V
V
V
V
V
Input voltage VL1
–0.3 to VL2
VL1 to VL3
VI
VI
VI
VI
VO
Input voltage VL2
Input voltage VL3
VL2 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3 +0.3
–0.3 to VL3 +0.3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
VO
–0.3 to VL3 +0.3
–0.3 to VCC +0.3
300
V
V
VO
Pd
mW
°C
°C
Ta = 25°C
Operating temperature
Storage temperature
Topr
Tstg
–20 to 85
–40 to 150
Table 36 Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
Typ.
5.0
5.0
5.0
0
Max.
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
4.0
2.2
2.2
5.5
5.5
5.5
VCC
Power source voltage
Power source voltage
VSS
V
V
V
V
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
VREF
AVSS
VIA
2.0
VCC
VCC
0
AVSS
60
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 37 Recommended operating conditions (M version)
(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47,
P52, P53,P56,P60–P67,P70,P71 (CM4= 0)
VIH
0.7VCC
V
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
Table 38 Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
V
Min.
Max.
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47,
P52, P53,P56,P60–P67,P70,P71 (CM4= 0)
0.8VCC
VIH
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
0.95VCC
0.95VCC
0.95VCC
0
VIH
VIH
VIH
VIL
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.2 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
0
0
0
VIL
VIL
VIL
0.05 VCC
0.05 VCC
0.05 VCC
V
V
V
RESET
XIN
61
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 39 Recommended operating conditions (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
40
–20
–20
20
20
–2
“H” peak output current
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
–5
(Note 2)
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
mA
mA
P00–P07, P10–P17 (Note 2)
5
10
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
–1.0
–2.5
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
mA
mA
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
mA
mA
“L” average output current
“L” average output current
2.5
5.0
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
(2.2 V ≤ VCC ≤ 4.0 V)
4.0
MHz
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(10ꢀVCC-4)/9 MHz
8.0 MHz
(20ꢀVCC-8)/9 MHz
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
Main clock input oscillation frequency
(Note 4)
f(XIN)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
62
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 40 Electrical characteristics (M version)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
IOH = –2.5 mA
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 2.5 V
VCC–1.0
VCC–2.0
VCC–0.5
V
V
IOH = –5 mA
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–1.0
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P7
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
1.0
V
IOL = 10 mA
IOL = 2.5 mA
2.0
0.5
V
V
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 2.5 V
1.0
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.2 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
140
45
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
–5.0
µA
µA
–4.0
Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
63
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 41 Electrical characteristics (M version)
(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
2.0
Typ.
Max.
5.5
VRAM
V
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
13
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
1.6
3.2
mA
Output transistors “off”
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
25
7.0
15
36
14
22
9.0
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
4.5
0.1
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10
Table 42 A-D converter characteristics (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Bits
Resolution
VCC = VREF = 5V
±2
LSB
Absolute accuracy
(excluding quantization error)
12.5
(Note)
f(XIN) = 8 MHz
VREF = 5 V
tCONV
Conversion time
µs
RLADDER
IVREF
IIA
Ladder resistor
kΩ
µA
µA
12
50
35
100
200
5.0
Reference power source input current
Analog port input current
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
64
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 43 Timing requirements 1 (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 44 Timing requirements 2 (M version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
900/(VCC–0.4)
450/(VCC–0.4)–20
450/(VCC–0.4)–20
230
230
2000
950
950
400
200
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
twH(SCLK)
twL(SCLK)
t
su(R
XD–SCLK)
th(SCLK–RXD)
Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
65
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 45 Switching characteristics 1 (M version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note 1)
–30
tv(SCLK–TXD)
tr(SCLK)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
10
10
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 46 Switching characteristics 2 (M version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–50
tC (SCLK)/2–50
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
–30
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
20
20
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
66
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 47 Absolute maximum ratings (H version)
Symbol Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
All voltages are based on VSS.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
–0.3 to VL2
VL1 to VL3
V
V
V
V
V
V
V
Input voltage VL1
VI
VI
VI
VI
VO
Input voltage VL2
VL2 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
Input voltage VL3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
–0.3 to VL3
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
VO
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
–0.3 to VL3
–0.3 to VCC +0.3
300
V
V
VO
Pd
mW
°C
°C
Ta = 25°C
Operating temperature
Storage temperature
Topr
Tstg
–20 to 85
–40 to 150
Table 48 Recommended operating conditions (H version)
(VCC = 2.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
V
Min.
Typ.
5.0
5.0
5.0
0
Max.
High-speed mode f(XIN) = 8 MHz
Middle-speed mode f(XIN) = 8 MHz
Low-speed mode
4.0
2.0
2.0
5.5
5.5
5.5
VCC
Power source voltage
Power source voltage
VSS
VREF
AVSS
VIA
V
V
V
V
V
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
2.0
VCC
0
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
VIH
0.7VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
67
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 49 Recommended operating conditions (H version)
(VCC = 2.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
40
–20
–20
20
20
–2
“H” peak output current
–5
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
5
mA
mA
P00–P07, P10–P17 (Note 2)
10
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
–1.0
–2.5
mA
mA
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
2.5
5.0
mA
mA
“L” average output current
“L” average output current
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
(4.0 V ≤ VCC ≤ 5.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
4.0
MHz
MHz
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
VCC
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
MHz
Main clock input oscillation frequency
(Note 4)
f(XIN)
High-speed mode
(2.0 V ≤ VCC ≤ 4.0 V)
2ꢀVCC
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 4, 5)
32.768
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50 %.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
68
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 50 Electrical characteristics (H version)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
IOH = –2.5 mA
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 2.5 V
VCC–1.0
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–1.0
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P7
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
1.0
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 2.5 mA
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 2.5 V
1.0
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.0 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
140
45
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
5.0
µA
µA
–4.0
Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
69
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 51 Electrical characteristics (H version)
(VCC =2.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
2.0
Typ.
Max.
5.5
VRAM
V
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
13
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
1.6
3.2
mA
Output transistors “off”
A-D converter stopped
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
25
7.0
15
36
14
22
9.0
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
4.5
0.1
µA
µA
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10
Table 52 A-D converter characteristics (H version)
(VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
–
–
Resolution
Bits
Absolute accuracy
(excluding quantization error)
VCC = VREF = 4.0 V to 5.5 V
f(XIN) = 8 MHz
±2
LSB
VCC = VREF = 2.2 V to 4.0V
f(XIN) = 2 ꢀ VCC MHz
12.5
(Note)
tCONV
Conversion time
µs
f(XIN) = 8 MHz
VREF = 5 V
RLADDER
IVREF
IIA
Ladder resistor
kΩ
µA
µA
35
100
200
5.0
12
50
Reference power source input current
Analog port input current
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
70
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 53 Timing requirements 1 (H version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
250
105
105
80
80
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 54 Timing requirements 2 (H version)
(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
2
Typ.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
125
45
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
900/(VCC–0.4)
450/(VCC–0.4)–20
450/(VCC–0.4)–20
230
230
2000
950
950
400
200
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
71
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 55 Switching characteristics 1 (H version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note 1)
–30
tv(SCLK–TXD)
tr(SCLK)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
30
tf(SCLK)
tr(CMOS)
tf(CMOS)
10
10
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Table 56 Switching characteristics 2 (H version)
(VCC = 2.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Typ.
Max.
350
ns
ns
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–50
tC (SCLK)/2–50
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
–30
50
50
50
50
tf(SCLK)
tr(CMOS)
tf(CMOS)
20
20
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
Measurement output pin
1 kΩ
100 pF
Measurement output pin
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1”. (N-channel open-
drain output mode)
Fig. 47 Circuit for measuring output switching characteristics
72
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR)
tWH(CNTR)
0.8VCC
tWL(CNTR)
CNTR0, CNTR1
0.2VCC
tWH(INT)
0.8VCC
tWL(INT)
INT0–INT3
0.2VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
tr
tWH(SCLK)
tWL(SCLK)
0.2VCC
SCLK
0.8VCC
tsu(RXD-SCLK)
th(SCLK-RXD)
RXD
TXD
0.8VCC
0.2VCC
td(SCLK-TXD)
tv(SCLK-TXD)
Fig. 48 Timing diagram
73
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
80P6N-A
Plastic 80pin 14ꢀ20mm body QFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
QFP80-P-1420-0.80
HD
D
80
65
1
64
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.3
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.2
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.35
0.15
14.0
20.0
0.8
16.8
22.8
0.6
1.4
–
–
–
0.5
–
14.6
20.6
b
c
D
E
e
24
41
25
40
A
HD
L1
HE
L
L1
x
y
F
e
b
L
b2
x
M
Detail F
I
2
–
–
–
y
M
M
D
E
–
MMP
80P6S-A
Plastic 80pin 14ꢀ14mm body QFP
EIAJ Package Code
QFP80-P-1414-0.65
JEDEC Code
Weight(g)
1.11
Lead Material
Alloy 42
MD
HD
D
80
61
1
60
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
13.8
–
16.5
16.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
14.2
–
17.1
17.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
14.0
0.65
16.8
16.8
0.6
1.4
–
b
c
D
E
e
20
41
A
21
40
HD
L1
HE
L
L1
x
y
F
M
–
–
b
e
x
b2
0.35
–
14.6
14.6
y
L
I
2
–
–
–
Detail F
M
M
D
E
–
74
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MMP
80P6Q-A
Plastic 80pin 12ꢀ12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
JEDEC Code
Weight(g)
0.47
Lead Material
Cu Alloy
M
D
–
HD
D
80
61
l
2
1
60
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.5
0.28
0.175
12.1
12.1
–
c
D
E
e
20
41
21
40
H
H
L
D
13.8
13.8
0.3
–
0.45
–
–
–
0°
–
14.0
14.0
0.5
1.0
0.6
0.25
–
–
14.2
14.2
0.7
–
0.75
–
0.08
0.1
10°
–
A
E
L
1
F
L1
e
Lp
A3
x
y
–
b
y
x
M
L
b2
0.225
–
12.4
12.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
75
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
•
•
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2001 MITSUBISHI ELECTRIC CORP.
Specifications subject to change without notice.
REVISION HISTORY
3822 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
1.0
2.0
01/20/98
10/23/00
First Edition
1
1
1
1
1
1
1
2
3
4
5
6
7
“●Memory size” of “FEATURES” is partly revised.
“●Serial I/O” of “FEATURES” is partly revised.
“●A-D converter” of “FEATURES” is added.
“●2 clock generating circuits” of “FEATURES” is partly revised.
“●Power source voltage” of “FEATURES” is partly revised.
“●Power dissipation” of “FEATURES” is partly added.
Product name into Figure 1 is revised.
Product name into Figure 2 is revised.
Figure 3 is partly revised.
“Function” of “Vcc, Vss” into Table 1 is partly revised.
“Function except a port function” into Table 2 is partly revised.
Figure 4 is partly revised.
Explanations of “GROUP EXPANSION (STANDARD, ONE TIME PROM VER-
SION, EPROM VERSION)” are partly revised.
Figure 5 is partly revised.
7
7
8
Table 3 is partly revised.
Explanations of “GROUP EXPANSION (EXTENDED OPERATING TEMPERA-
TURE VERSION)” are partly revised.
Figure 6 is partly revised.
8
8
Table 4 is partly revised.
9
9
“GROUP EXPANSION (M VERSION)” is added.
Figure 7 is added.
9
Table 5 is added.
10
10
10
11–13
11
12
12
13
15
17
18
21
22
22
22
22
24
25
26
26
29
30
32
33
33
34
“GROUP EXPANSION (H VERSION)” is added.
Figure 8 is added.
Table 6 is added.
Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
Figure 9 is added.
Figure 10 is added.
Table 7 is added.
Table 8 is added.
Figure 12 is partly revised.
Figure 14 is partly revised.
Table 9 is partly revised.
Figure 17 is partly revised.
Explanations of “Interrupt Control” is partly added.
Explanations of “Interrupt Operation” is partly revised.
Explanations of “●Notes” are partly revised.
Table 9 is partly revised.
Explanations of “Key Input Interrupt (Key-on wake up)” are partly revised.
Figure 21 is partly revised.
Explanations of “●Timer X write control” are partly revised.
Explanations of “●Real time port control” are partly revised.
Figure 25 is partly revised.
Figure 27 is partly revised.
Figure 29 is partly revised.
Explanations of “[Channel Selector]” are partly added.
Explanations of “[Comparator and Control Circuit]” are partly added.
Figure 32 is partly revised.
(1/2)
REVISION HISTORY
3822 GROUP DATA SHEET
Rev.
2.0
Date
Description
Summary
Page
35
40
41
41
Figure 33 is partly revised.
10/23/00
Explanations of “φ CLOCK SYSTEM OUTPUT FUNCTION” are partly revised.
Explanations of “RESET CIRCUIT” are partly revised.
Figure 39 is partly revised.
43
46
47
47
Explanations of “CLOCK GENERATING CIRCUIT” are partly eliminated.
Explanations of “Decimal Calculations” are partly eliminated.
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly added.
Table 14 is partly revised.
50
52
Test conditions of IIL of P00–P07, P10–P17, P34–P37, P40 is added.
Limit of tC(CNTR) into Table 21 is revised.
52
Limit of tWH(CNTR) into Table 21 is revised.
52
Limit of tWL(CNTR) into Table 21 is revised.
52
Limit of tC(CNTR) into Table 22 is revised.
52
Limit of tWH(CNTR) into Table 22 is revised.
52
Limit of tWL(CNTR) into Table 22 is revised.
54–72
74, 75
Tables 25 to 56 are added.
“PACKAGE OUTLINE” is added.
Explanations of “•Bit 3: Decimal mode flag (D)” are partly added.
Figure 17 is partly revised.
Explanations of “■Notes on interrupts” are revised.
Figure 21 is partly revised.
“■Notes on serial I/O” is added.
Figure 44 is partly revised.
13
21
22
25
31
44
47
2.1
01/31/01
Explanations of “DATA REQUIRED FOR MASK ORDERS” are partly revised.
(2/2)
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