M5M29FB800FP [MITSUBISHI]
8,388,608-BIT (1048,576-576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY; 8,388,608位（ 1048,576-576 - WORD ×8位/ 524,288 - WORD BY16 - BIT ） CMOS 3.3V -ONLY ，块擦除闪存
| 型号： | M5M29FB800FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8,388,608-BIT (1048,576-576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY |
| 文件： | 总14页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The MITSUBISHI M5M29FB/T800FP, VP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories suitable for
mobile and personal computing, and communication products. The M5M29FB/T800FP, VP, RV are fabricated by CMOS technology for
the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 44pin SOP or 48pin
TSOP(I).
FEATURES
.................................
.................................
Organization
524,288 word x 16bit
1,048,576 word x 8 bit
VCC = 3.3V±0.3V
.............................
..............................
PIN CONFIGURATION (TOP VIEW)
Supply voltage ................................
Access time
80/100/120ns (Max)
Power Dissipation
Read
RESET/
.......................
.......................
.......................
108 mW (Max.)
144 mW (Max.)
0.72 mW (Max.)
3.3µW (typ.)
POWER DOWN
INPUT
/RP
1
2
44
NC
A18
A17
Program/Erase
Standby
WRITE ENABLE
INPUT
43
/WE
3
42
41
A8
A9
.......................
Deep power down mode
Auto program
Program Time
4
5
A7
A6
A5
A4
A3
A2
A1
40
39
A10
A11
A12
A13
A14
A15
A16
.......................
.................................
7.5ms (typ.)
128word
6
ADDRESS
INPUTS
Program Unit
Auto Erase
Erase time
Erase Unit
ADDRESS
INPUTS
7
8
9
38
37
.................................
50 ms (typ.)
36
35
34
33
.................................
........................
10
11
12
Boot Block
8Kword / 16Kbyte x 1
4Kword / 8Kbyte x 2
16Kword / 32Kbyte x 1
32Kword / 64Kbyte x 15
A0
/CE
Parameter Block
CHIP ENABLE
INPUT
BYTE ENABLE
INPUT
.......................
...........................
.......................................
/BYTE
GND
Main Block
13
14
32
31
30
29
28
GND
/OE
DQ0
OUTPUT ENABLE
INPUT
Program/Erase cycles
100Kcycles
DQ15/A-1
DQ7
15
16
17
Boot Block
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ14
DQ6
...........................
...........................
M5M29FB800
M5M29FT800
Other Functions
Bottom Boot
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
Top Boot
18
19
20
27
26
25
DQ13
DQ5
Software Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Sleep
DQ12
DQ4
21
22
24
23
VCC
Outline 600mil 44-pin SOP
(FP: 44P2A-A)
Package
48-Lead, 12mmx 20mm TSOP (type-I)
44-Lead SOP
APPLICATION
Code Storage PC BIOS
Digital Cellular Phone/Telecommunication
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A16
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A15
A14
A15
/BYTE
/BYTE
A14
A13
3
3
GND
GND
A13
A12
A11
A10
A9
A12
A11
A10
A9
4
4
DQ15/A-1 DQ15/A-1
5
5
DQ7
DQ7
6
DQ14
DQ14
6
7
DQ6
7
DQ6
8
8
A8
DQ13
DQ13
A8
9
DQ5
DQ5
9
NC
NC
/WE
/RP
NC
NC
/WE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ12
DQ4
VCC
DQ4
VCC
/RP
M5M29FB/T800VP
M5M29FB/T800RV
NC
DQ11
DQ3
NC
DQ11
DQ3
/WP
/WP
RY/BY
A18
RY/BY
DQ10
DQ10
DQ2
DQ2
A18
A17
A7
A6
A5
A4
A3
A2
A1
A17
A7
DQ9
DQ1
DQ8
DQ0
/OE
GND
/CE
A0
DQ9
DQ1
A6
DQ8
A5
DQ0
/OE
A4
A3
A2
A1
28
27
26
25
GND
/CE
23
24
A0
Outline 48pin TSOP type-I (12 X 20mm)
VP(Normal bend): 48P3R-B
RV(Reverse bend): 48P3R-C
NC : NO CONNECTION
This product is compatible with HN29WB/T800 by Hitachi Ltd.
1
1
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
128 WORD PAGE BUFFER
A18
Boot Block
8KW
4KW
A17
A16
Parameter Block1
VCC (3.3V)
GND (0V)
Parameter Block2
Main Block
4KW
A15
A14
A13
A12
A11
A10
A9
16KW
Main Block
32KW
X-DECODER
ADDRESS
INPUTS
A8
A7
A6
A5
Main Block
32KW
A4
A3
Y-GATE / SENSE AMP.
Y-DECODER
A2
A1
A0
STATUS / ID REGISTER
MULTIPLEXER
/CE
/OE
/WE
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
CUI
WSM
/WP
/RP
/BYTE
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
INPUT/OUTPUT
BUFFERS
RY/BY
READY/BUSY OUTPUT
D3 D2 D1
D15/A-1D14D13D12
D0
DATA INPUTS/OUTPUTS
FUNCTION
Output Disable
The M5M29FB/T800FP,VP,RV includes on-chip program/erase
control circuitry. The Write State Machine (WSM) controls block
erase and page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
When /OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
Standby
When /CE is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected during
block erase or program, the internal control circuits remain active
and the device consume normal active power until the operation
completes.
A Deep Powerdown mode is enabled when the /RP pin is at GND,
minimizing power consumption.
Read
The M5M29FB/T800FP,VP,RV has three read modes, which
accesses to the memory array, the Device Identifier and the Status
Register. The appropriate read command are required to be
written to the CUI. Upon initial device powerup or after exit from
deep powerdown, the M5M29FB/T800 automatically resets to read
array mode. In the read array mode, low level input to /CE and
/OE, high level input to /WE and /RP, and address signals to the
address inputs (A0-A18) output the data of the addressed location
to the data input/output(D0-15).
Deep Power-Down
When /RP is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, /RP low will abort
either operation. Memory array data of the block being altered
become invalid.
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing /WE to low level, while /CE is at low level and /OE is at
high level. Address and data are latched on the earlier rising edge
of /WE and /CE. Standard micro-processor write timings are used.
2
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS
DATA PROTECTION
The device operations are selected by writing specific software
command into the Command User Interface.
The M5M29FB/T800 provides selectable block locking of memory
blocks. Each block has an associated nonvolatile lock-bit which
Read Array Command (FFH)
determines the lock status of the block.
In addition, the
The device is in Read Array mode on initial device powerup and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. The device remains in Read Array
mode until the other commands are written.
M5M29FB/T800 has a master Write Protect pin (WP) which
prevents any modifications to memory blocks whose lock-bits are
set to "0", when /WP is low. When /WP is high or /RP is VHH, all
blocks can be programmed or erased regardless of the state of
the lock-bits, and the lock-bits are cleared to "1" by erase.
Read Device Identifier Command (90H)
Though PROM programmers can normally read device identifier
codes by raising A9 to VID, multiplexing high voltage onto address
lines is not desired for micro-processor system. It is an other
means to read device identifier codes that Read Device Identifier
Code Command(90H) is written to the command latch. Following
the command write, the manufacturer code and the device code
can be read from address 0000H and 0001H, respectively.
Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.2V, the device
is set to the Read-only mode.
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (3.0V).
During power up, /RP=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface.
The contents of Status Register are latched on the later falling
edge of /OE or /CE. So /CE or /OE must be toggled every status
read.
Clear Status Register Command (50H)
The Erase Status and Program Status bits are set to "1"s by the
Write State Machine and can only be reset by the Clear Status
Register command of 50H. These bits indicates various failure
conditions.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Page Program Commands(41H)
Page Program allows fast programming of 128words of data.
Writing of 41H initiates the page program operation. From 2nd
cycle to 129th cycle write data must be serially inputted. Address
A6-0 have to be incremented from 00H to 7FH. After completion
of data loading, the WSM controls the program pulse application
and verify operation.
Basically re-program must not be done on a page which has
already programmed.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The device
continues to output Status Register data when read, after the
Suspend command is written to it. Polling the WSM Status and
Suspend Status bits will determine when the erase operation or
program operation has been suspended. At this point, writing of
the Read Array command to the CUI enables reading data from
blocks other than that which is suspended. When the Resume
command of D0H is written to the CUI, the WSM will continue with
the erase or program processes.
3
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
x8 ( Bytemode) x16 ( Wordmode)
x8 ( Bytemode) x16 ( Wordmode)
FC000H-FFFFFH 7E000H-7FFFFH
F0000H-FFFFFH 78000H-7FFFFH
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
08000H-0FFFFH 04000H-07FFFH
32Kword MAIN BLOCK
8Kword BOOT BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
FA000H-FBFFFH 7D000H-7DFFFH
F8000H-F9FFFH 7C000H-7CFFFH
F0000H-F7FFFH 78000H-7BFFFH
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
16Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
16Kword MAIN BLOCK
06000H-07FFFH 03000H-03FFFH
04000H-05FFFH 02000H-02FFFH
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
00000H-03FFFH 00000H-01FFFH
A-1-A18(Bytemode)A0-A18(Wordmode)
8Kword BOOT BLOCK
00000H-0FFFFH 00000H-07FFFH
A-1-A18(Bytemode)A0-A18(Wordmode)
M5M29FB800 Memory Map
M5M29FT800 Memory Map
BUS OPERATIONS
Bus Operations for Word-Wide Mode (/BYTE=VIH)
Pins
/CE
/OE
/WE
/RP
DQ0-15
RY/BY
Mode
Array
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
X
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
VOH (Hi-Z)
1)
Read
Status Register
Lock Bit Status
Identifier Code
X
X
VOH (Hi-Z)
Output disable
Stand by
X
2)
Hi-Z
X
Program
VIH
VIH
VIH
X
VIL
VIL
VIL
X
Command/Data in
Command
X
Write
Erase
X
X
Others
Command
VOH (Hi-Z)
Deep Power Down
Hi-Z
Bus Operations for Byte-Wide Mode (BYTE=VIL)
Pins
/CE
/OE
/WE
/RP
RY/BY
DQ0-7
Mode
Array
VOH (Hi-Z)
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
X
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
Data out
1)
Read
Status Register
Lock Bit Status
Identifier Code
Status Register Data
Lock Bit Data (DQ6)
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
X
VOH (Hi-Z)
Identifier Code
Hi-Z
Output disable
Stand by
X
2)
Hi-Z
X
Program
VIH
VIH
VIH
X
VIL
VIL
VIL
X
Command/Data in
Command
Command
Hi-Z
X
Write
Erase
Others
X
X
VOH (Hi-Z)
Deep Power Down
1) X at RY/BY is VOL or VOH(Hi-Z).
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
4
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command List
1st bus cycle
Address
2nd bus cycle
Address
3rd bus cycle
Address
Command
Mode
Data
(D7-0)
Mode
Data
(D7-0)
Mode
Write
Data
(D7-0)
Read Array
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
X
X
X
X
X
X
FFH
90H
70H
50H
41H
20H
B0H
D0H
71H
77H
A7H
F0H
2)
2)
Device Identifier
Read Status Register
Read
Read
IA
ID
3)
X
SRD
Clear Status Register
4)
4)
4)
Page Program
Block Erase / Confirm
Suspend
Write
Write
WA0
WD0
D0H
WA1
WD1
5)
BA
Resume
6)
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
Read
Write
Write
DQ6
D0H
D0H
BA
BA
X
Write
Write
Write
7)
Sleep
1) In the word-wide mode, upper byte data (D8-D15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code,
/BYTE =VIL : A-1, A1-A18 = VIL, /BYTE =VIH : A1-A18 = VIL
3) SRD = Status Register Data
4) WA=Write Address, WD=Write Data.
/BYTE =VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A-1-A6.
Page size is 256Byte (256byte x 8bit), /BYTE =VIH : Write Address and Write Data must be provided
sequentially from 00H to 7FH for A0-A6. Page size is 128word (128word x 16bit).
5) BA = Block Address ( Addresses except Block Address mest be VIH.)
6) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
7) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels.
The Read Array command (FFH) must be written to get the device out of sleep mode.
BLOCK LOCKING
SOP Package
TSOP Package
Write Protection Provided
/RP Lock Bit(Internally)
/RP
/WP Lock Bit(Internally)
X
X
0
X
All Blocks Locked (Deep Power Down Mode)
All Blocks UnLocked
VIL
VIL
X
X
VHH
VIH
VIH
VHH
VIH
VIH
VIH
X
0
1
X
Blocks Locked (Depend on Lock Bit Data)
Blocks Unlocked (Depend on Lock Bit Data)
All Blocks Unlocked
VIL
VIL
VIH
1
D6 provides Lock Status of each block after writing the Read Lock Status command (71H).
In case of TSOP package, /WP pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).
STATUS REGISTER
Definition
Symbol
Status
"1"
Ready
Suspended
Error
"0"
Busy
Write State Machine Status
Suspend Status
SR.7 (D7)
SR.6 (D6)
SR.5 (D5)
SR.4 (D4)
SR.3 (D3)
SR.2 (D2)
SR.1 (D1)
SR.0 (D0)
Operation in Progress / Completed
Successful
Erase Status
Program Status
Error
Error
Successful
Successful
Block Status after Program
Reserved
-
-
Reserved
-
-
Device in Sleep
Device Not in Sleep
Device Sleep Status
*The RY/BY is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY signal to transition high indicating a Ready WSM condition.
*D3 indicates the block status after the page programming. When D3 is "1", the page has the over-programed cell . If over-program occures, the device is block
fail. However if D3 is "1", please try the block erase to the block. The block may revive.
DEVICE IDENTIFIER CODE
Pins
Hex. Data
A0
D7
D6
D5
D4
D3
D2
D1
D0
Code
Manufacturer Code
Device Code (-T)
Device Code (-B)
VIL
VIH
VIH
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1CH
5DH
5EH
In the word-wide mode, the same data as D7-0 is read out from D15-8.
A9 = VHH Mode : A9 = 11.5V~13.0V Set A9 to VHH min.200ns before falling edge of /CE in ready status. Min.200ns after return to VIH ,device can't be accessed.
A1~A8, A10~A18, /CE,/OE = VIL, /WE = VIH
D15/A-1 = VIL (/BYTE = L)
5
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Min
Max
Unit
V
Vcc
Vcc voltage
-0.2
-0.6
4.6
4.6
All input or output voltage except Vcc,A9,/RP1)
VI1
VI2
Ta
With respect to Ground
V
A9,RP supply voltage
14.0
-0.6
0
V
Ambient temperature
70
80
°C
Tbs
Temperature under bias
-10
-65
°C
Tstg
I OUT
Storage temperature
Output short circuit current
°C
mA
125
100
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Limits
Parameter
Symbol
Test conditions
Unit
Typ
Min
Max
8
pF
pF
CIN
COUT
Input capacitance (Address, Control Pins)
Output capacitance
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
12
DC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V, unless otherwise noted)
Limits
Typ1)
Symbol
Parameter
Test conditions
0V£VIN£VCC
Unit
Min
Max
±1.0
±10
ILI
Input leakage current
Output leakage current
µA
µA
µA
0V£VOUT£VCC
ILO
ISB1
VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH
50
1
200
VCC standby current
VCC = 3.6V, VIN=GND or VCC,
/CE = /RP = /WP= VCC±0.3V
ISB2
5
µA
ISB3
ISB4
VCC = 3.6V, VIN=VIL/VIH, /RP = VIL
5
1
15
5
µA
µA
VCC deep powerdown current
VCC = 3.6V, VIN=GND or VCC, /RP =GND±0.3V
VCC = 3.6V, VIN=VIL/VIH, /CE = VIL,
/RP=OE=VIH, f = 10MHz, IOUT = 0mA
ICC1
ICC2
VCC read current for Word or Byte
VCC Write current for Word or Byte
7
25
30
mA
mA
VCC = 3.6V,VIN=VIL/VIH, /CE =/WE= VIL,
/RP=/OE=VIH
ICC3
ICC4
ICC5
I RP
VCC program current
VCC erase current
VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH
VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH
VCC = 3.6V, VIN=VIL/VIH, /CE = /RP =/WP = VIH
/RP = VHH max
40
40
mA
mA
µA
µA
µA
V
VCC suspend current
200
all block unlock current
100
/RP
A9 intelligent identifier current
unlock voltage
IID
A9 = VID max
100
VIHH
VID
/RP
11.4
11.4
– 0.5
2.0
12.0
12.0
12.6
12.6
0.8
A9 intelligent identifier voltage
Input low voltage
V
VIL
V
V
V
V
V
V
Vcc+0.5
VIH
Input high voltage
VOL
VOH1
VOH2
VLKO
Output low voltage
IOL = 5.8mA
IOH = –2.5mA
IOH = –100µA
0.45
0.85Vcc
Vcc–0.4
1.5
Output high voltage
Low VCC Lock-Out voltage 2)
2.5
All currents are in RMS unless otherwise noted.
1) Typical values at Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.
If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
6
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~70°C, Vcc = 3.3±0.3V)
Read-Only Mode
Limits
M5M29FB/T800-80
M5M29FB/T800-10
M5M29FB/T800-12 Unit
Symbol
Parameter
Min
80
Typ
Max
Min
100
Typ
Max
Min
120
Typ
Max
tRC
tAVAV Read cycle time
tAVQV Address access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta (AD)
80
80
40
100
100
50
120
120
60
ta (CE)
ta (OE)
tCLZ
tELQV Chip enable access time
tGLQV Output enable access time
tELQX Chip enable to output in low-Z
0
0
0
0
0
0
tDF(CE) tEHQZ Chip enable high to output in high Z
tGLQX Output enable to output in low-Z
tDF(OE) tGHQZ Output enable high to output in high Z
tPLQZ /RP low to output high-Z
ta(BYTE) tFL/HQV /BYTE access time
25
25
30
tOLZ
25
25
30
tPHZ
150
150
300
80
25
100
25
120
30
ns
tBHZ
tOH
tFLQZ
tOH
/BYTE low to output high-Z
ns
ns
ns
ns
ns
Output hold from /CE, /OE, addresses
0
0
0
tBCD
tELFL/H /CE low to /BYTE high or low
tAVFL/H Address to /BYTE high or low
tWHGL /OE hold from /WE high
5
5
5
5
5
5
tBAD
tOEH
80
100
500
120
500
tPS
tPHEL
/RP recovery to /CE low
500
ns
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V)
Write Mode (/WE control)
Limits
Unit
Symbol
Parameter
M5M29FB/T800-80
M5M29FB/T800-10
M5M29FB/T800-12
Min
80
50
10
50
10
0
Typ
Max
Min
100
50
10
50
10
0
Typ
Max
Min
120
50
10
50
10
0
Typ
Max
tWC
tAS
tAVAV
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVWH
tWHAX
tDVWH
tWHDX
tELWL
tWHEH
tWLWH
tWHWL
Address set-up time
Address hold time
Data set-up time
tAH
tDS
tDH
tCS
tCH
tWP
tWPH
tBS
Data hold time
Chip enable set-up time
Chip enable hold time
Write pulse width
Write pulse width high
0
0
0
60
20
50
80
60
20
50
100
60
20
50
120
tFL/HWH Byte enable high or low set-up time
tWHFL/H Byte enable high or low hold time
tBH
tBLS
tWPS
tPHHWH Block Lock set-up to write enable high
80
0
100
0
120
0
ns
ns
tBLH
tQVPH
Block Lockhold from valid SRD
tWPH
tDAP
tDAE
tWHRH1 Duration of auto-program operation
tWHRH2 Duration of auto-block erase operation
7.5
50
120
600
80
7.5
50
120
600
100
7.5
50
120
600
120
ms
ms
ns
tWHRL tWHRL
tPS tPHWL
Write enable high to RY/BY low
/RP high recovery to write enable low
500
500
500
ns
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at Vcc=3.3V, Ta=25°C
May 1997 , Rev.6.1
7
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70°C, Vcc = 3.3V±0.3V)
Write Mode (/CE control)
Limits
Unit
Symbol
Parameter
M5M29FB/T800-80
M5M29FB/T800-10
M5M29FB/T800-12
Min
80
50
10
50
10
0
Typ
Max
Min
100
50
10
50
10
0
Typ
Max
Min
120
50
10
50
10
0
Typ
Max
tWC
tAS
tAVAV
Write cycle time
ns
ns
ns
ns
ns
ns
ns
tAVEH
tEHAX
tDVEH
tEHDX
tWLEL
tEHWH
Address set-up time
Address hold time
Data set-up time
tAH
tDS
tDH
tWS
tWH
tCEP
Data hold time
Write enable set-up time
Write enable hold time
/CE pulse width
0
0
0
tELEH
60
20
50
80
60
20
60
20
ns
ns
ns
ns
tCEPH tEHEL
/CE pulse width high
tBS
tBH
tFL/HEH Byte enable high or low set-up time
tEHFL/H Byte enable high or low hold time
50
100
50
120
tBLS
tWPS
tPHHEH Block Lock set-up to write enable high
80
0
100
0
120
0
ns
ns
tBLH
tQVPH
Block Lockhold from valid SRD
tWPH
tDAP
tDAE
tEHRH1
tEHRH2
Duration of auto-program operation
Duration of auto-block erase operation
/CE enable high to RY/BY low
7.5
50
120
600
80
7.5
50
120
600
100
7.5
50
120
600
120
ms
ms
ns
tEHRL tEHRL
tPS tPHEL
/RP high recovery to write enable low
500
500
500
ns
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at Vcc=3.3V, Ta=25°C
Erase and Program Performance
Typ
Unit
Parameter
Min
Max
ms
sec
ms
Block Erase Time
50
1.9
7.5
600
3.8
Main Block Write Time (Page Mode)
Page Write Time
120
Vcc Power Up / Down Timing
Symbol
Parameter
Min
2
Typ
Max
Unit
µs
tVCS
/RP =VIH set-up time from Vccmin
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contens during power up/down.
The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches
Vccmin during power up/down. By holding /RP VIL, the contens of memory is protected during Vcc power up/down.
During power up, /RP must be held VIL for min.2µs from the time Vcc reaches Vccmin.
During power down, /RP must be held VIL until Vcc reaches GND.
/RP doesn't have latch mode ,so /RP must be held VIH during read operation or erase/program operation.
8
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
3.3V
VCC
GND
tVCS
VIH
/RP
VIL
VIH
/CE
VIL
tPS
tPS
VIH
VIL
/WE
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
TEST CONDITIONS
VIH
FOR AC CHARACTERISTICS
ADDRESSES
ADDRESS VALID
tRC
VIL
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : £5ns (80ns)
VIH
VIL
ta (AD)
/CE
/OE
£10ns (100/120ns)
Reference voltage
at timing measurement : 1.5V
tDF(CE)
ta (CE)
VIH
VIL
tOEH
tDF(OE)
tOH
Output load : 1TTL gate +
CL(100pF for 100/120ns)
CL(30pF for 80ns)
VIH
VIL
/WE
DATA
/RP
ta (OE)
tOLZ
or
1.3V
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
OUTPUT VALID
tPHZ
1N914
tPS
3.3kW
VIH
VIL
DUT
CL =30/100pF
BYTE AC WAVEFORMS FOR READ OPERATION
VIH
ADDRESSES
(A0 - A18)
ADDRESS VALID
ta(AD)
ADDRESS VALID
VIL
VIH
VIL
/CE
tDF(CE)
tDF(OE)
ta(CE)
ta(OE)
VIH
VIL
/OE
ta(BYTE)
tOLZ
tBAD
ta(BYTE)
tCLZ
VIH
VIL
/BYTE
tBCD
tOH
VIH
VIL
tBAD
HIGH-Z
HIGH-Z
VALID
VALID
tBHZ
DATA
(D0 - D7)
OUTPUT VALID
ta(AD)
VIH
DATA
VALID
(D8 - D14) VIL
VIH
D15 / A-1
A-1
D15
A-1
VIL
When /BYTE=VIH, /CE=/OE=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
9
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/WE control)
READ STATUS
WRITE READ
PROGRAM
REGISTER ARRAY COMMAND
VIH
ADDRESS VALID
A7~A18
VIL
/BYTE=VIL
(A-1~A6)
02H~FEH
02H~7EH
00H
00H
01H
01H
FFH
7FH
VIH
VIL
/BYTE=VIH
(A0 ~A6)
tAH
tWC
tAS
VIH
VIL
ta(CE)
ta(OE)
/CE
/OE
tCS
tCH
VIH
VIL
tOEH
tDAE,tDAP
tWPH
VIH
VIL
/WE
tDH
tWP
41H
tDS
VIH
VIL
DATA
RY/BY
/BYTE
SRD
FFH
DIN
DIN
DIN
DIN
tWHRL
VOH
VOL
tBS
tBH
VIH
VIL
tBLH
tBLS
VHH
VIH
tPS
/RP
VIL
VIH
tWPH
tWPS
/WP
VIL
AC WAVEFORMS FOR ERASE OPERATIONS (/WE control)
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
ERASE
VIH
ADDRESSES
ADDRESS VALID
tAS
VIL
tWC
tAH
ta(CE)
VIH
VIL
/CE
/OE
tCS
tCH
ta(OE)
VIH
VIL
tOEH
tDAP,tDAE
tWPH
VIH
VIL
/WE
tDH
tWP
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tWHRL
VOH
VOL
RY/BY
tBS
tBH
VIH
VIL
/BYTE
/RP
tBLH
tBLS
VHH
VIH
tPS
tWPH
tWPS
VIL
VIH
VIL
/WP
10
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (/CE control)
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
PROGRAM
VIH
VIL
ADDRESS VALID
A7~A18
/BYTE=VIL
(A-1~A6)
02H~FEH
02H~7EH
00H
00H
01H
01H
FFH
7FH
VIH
VIL
/BYTE=VIH
(A0 ~A6)
tWC
tAS
tAH
VIH
VIL
ta(CE)
ta(OE)
/CE
/OE
tCEPH
VIH
VIL
tCEP
tOEH
tDAE,tDAP
tWS
tWH
VIH
VIL
/WE
tDH
tDS
VIH
VIL
DATA
RY/BY
/BYTE
FFH
41H
DIN
DIN
DIN
DIN
SRD
tEHRL
VOH
VOL
tBS
tBH
VIH
VIL
tBLH
tBLS
VHH
VIH
tPS
/RP
VIL
VIH
tWPH
tWPS
/WP
VIL
AC WAVEFORMS FOR ERASE OPERATIONS (/CE control)
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
ERASE
VIH
ADDRESSES
ADDRESS VALID
tAS
VIL
tWC
tAH
ta(CE)
VIH
VIL
/CE
/OE
tCEPH
tCEP
ta(OE)
VIH
VIL
tOEH
tDAP,tDAE
tWS
tWH
VIH
VIL
/WE
tDH
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tEHRL
VOH
VOL
RY/BY
tBS
tBH
VIH
VIL
/BYTE
/RP
tBLH
tBLS
VHH
VIH
tPS
tWPH
tWPS
VIL
VIH
VIL
/WP
11
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FULL STATUS CHECK PROCEDURE
STATUS REGISTER
READ
SR.4 =1
and
COMMAND SEQUENCE ERROR
BLOCK ERASE ERROR
SR.5 =1
?
YES
NO
NO
NO
NO
SR.5 = 0 ?
YES
PROGRAM ERROR
(PAGE, LOCK BIT)
SR.4 = 0 ?
YES
PROGRAM ERROR
(BLOCK)
SR.3 = 0 ?
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
LOCK BIT PROGRAM FLOW CHART
PAGE PROGRAM FLOW CHART
START
START
WRITE 77H
WRITE 41H
WRITE D0H
BLOCK ADDRESS
n = 0
n = n+1
WRITE
ADDRESS n, DATA n
SR.7 = 1 ?
NO
YES
n = FFH ?
or
LOCK BIT PROGRAM
FAILED
SR.4 = 0 ?
YES
NO
n = 7FH ?
NO
YES
LOCK BIT PROGRAM
SUCCESSFUL
STATUS REGISTER
READ
NO
NO
SR.7 = 1 ?
WRITE B0H ?
YES
YES
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
YES
12
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK ERASE FLOW CHART
SUSPEND / RESUME FLOW CHART
START
START
WRITE 20H
WRITE B0H
SUSPEND
WRITE D0H
BLOCK ADDRESS
STATUS REGISTER
READ
STATUS REGISTER
READ
SR.7 = 1?
YES
NO
NO
PROGRAM / ERASE
COMPLETED
SR.6 =1?
NO
NO
WRITE B0H ?
SR.7 = 1 ?
YES
WRITE FFH
YES
YES
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
READ ARRAY DATA
BLOCK ERASE
COMPLETED
YES
DONE
READING ?
NO
YES
RESUME
WRITE D0H
OPERATION
RESUMED
13
May 1997 , Rev.6.1
MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
OPERATION STATUS and EFFECTIVE COMMAND
14
May 1997 , Rev.6.1
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