M5M29GB160BVP-90_技术文档

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DESCRIPTION

The MITSUBISHI Mobile FLASH M5M29GB/T160BVP are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with

alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in

one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for

mobile and personal computing, and communication products. The M5M29GB/T160BVP are fabricated by CMOS technology for the

peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in in 48pin TSOP(I) .

FEATURES

Boot Block

........................

.................................

Organization

1048,576 word x 16bit

2,097,152 word x 8 bit

VCC = 2.7~3.6V

M5M29GB160BVP

M5M29GT160BVP

Bottom Boot

Top Boot

Other Functions

.............................

Supply voltage ................................

Soft Ware Command Control

Selective Block Lock

Erase Suspend/Resume

Program Suspend/Resume

Status Register Read

..............................

Access time

80ns (Vcc=3.3V+/-0.3V)

90ns (Vcc=2.7~3.6V)

Power Dissipation

Alternating Back Ground Program/Erase Operation

Between Bank(I) and Bank(II)

.................................

Read

54 mW (Max. at 5MHz)

0.33µW (typ.)

..........

(After Automatic Power saving)

.................................

Program/Erase

126 mW (Max.)

0.33µW (typ.)

Package

.................................

Standby

48-Lead, 12mm x 20mm TSOP (type-I)

.......................

Deep power down mode

0.33µW (typ.)

Auto program for Bank(I)

.................................

Program Time

4ms (typ.)

Program Unit

.........................

(Byte Program)

(Page Program)

1word/1byte

128word/256byte

APPLICATION

Code Strage

Digital Cellular Phone

Telecommunication

.........................

Auto program for Bank(II)

.................................

Program Time

4ms (typ.)

128word/256byte

.................................

Program Unit

Mobile Computing Machine

PDA (Personal Digital Assistance)

Car Navigation System

Video Game Machine

Auto Erase

Erase time

Erase Unit

.................................

40 ms (typ.)

.....................

Bank(I) Boot Block

16Kword/32Kbyte x 1

16Kword/32Kbyte x 7

32Kword/64Kbyte x 28

..............

......................

Parameter Block

Bank(II) Main Block

.........................................

Program/Erase cycles

100Kcycles

PIN CONFIGURATION (TOP VIEW)

160BVP

1

48

A16

A15

A14

A13

A12

A¹¹

A10

A9

2

3

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

GND

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

4

5

6

7

8

A8

9

A¹⁹

NC

WE#

RP#

NC

WP#

RY/BY#

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

M5M29GB/T

160BVP

DQ11

DQ3

DQ¹⁰

DQ2

DQ9

DQ1

DQ⁸

DQ⁰

OE#

GND

CE#

A0

A18

A17

A⁷

A6

A5

A4

A3

A2

A1

Outline 48pin TSOP type-I (12 X 20mm)

VP(Normal bend)

NC : NO CONNECTION

Mar 1999. Rev1.8

1

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK DIAGRAM

A19

A18

128 WORD PAGE BUFFER

Main Block

32KW

A17

VCC (3.3V)

GND (0V)

A16

A15

A14

A13

A12

A11

A10

A9

28

X-DECODER

Main Block

32KW

16KW

Parameter Block7

Parameter Block6

Parameter Block5

Parameter Block4

Parameter Block3

Parameter Block2

ADDRESS

INPUTS

16KW

A8

A7

Parameter Block1

Boot Block

A6

A5

A4

A3

A2

A1

A0

Y-GATE / SENSE AMP.

MULTIPLEXER

Y-DECODER

STATUS / ID REGISTER

CHIP ENABLE INPUT

CE#

OUTPUT ENABLE INPUT OE#

WRITE ENABLE INPUT WE#

^{WRITE PROTECT INPUT}WP#

CUI

WSM

INPUT/OUTPUT

BUFFERS

RESET/POWER DOWN INPUT

RP#

BYTE#

BYTE ENABLE INPUT

READY/BUSY OUTPUT RY/BY#

DQ15/A-1

DQ14DQ13DQ12

DQ3DQ2DQ1DQ0

DATA INPUTS/OUTPUTS

M5M29GB/T160BVP (8/16 bit version)

Mar 1999. Rev1.8

2

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

FUNCTION

Deep Power-Down

The M5M29GB/T160BVP includes on-chip program/erase control

circuitry. The Write State Machine (WSM) controls block erase

and byte/page program operations. Operational modes are

selected by the commands written to the Command User Interface

(CUI). The Status Register indicates the status of the WSM and

when the WSM successfully completes the desired program or

block erase operation.

When RP# is at VIL, the device is in the deep powerdown

mode and its power consumption is substantially low. During

read modes, the memory is deselected and the data

input/output are in a high-impedance(High-Z) state. After

return from powerdown, the CUI is reset to Read Array , and

the Status Register is cleared to value 80H.

During block erase or program modes, RP# low will abort

either operation. Memory array data of the block being altered

become invalid.

A Deep Powerdown mode is enabled when the RP# pin is at GND,

minimizing power consumption.

Automatic Power-Saving (APS)

Read

The Automatic Power-Saving minimizes the power

consumption during read mode. The device automatically

turns to this mode when any addresses or CE# isn't changed

more than 200ns after the last alternation. The power

consumption becomes the same as the stand-by mode. While

in this mode, the output data is latched and can be read out.

New data is read out correctly when addresses are changed.

The M5M29GB/T160BVP has three read modes, which accesses

to the memory array, the Device Identifier and the Status Register.

The appropriate read command are required to be written to the

CUI. Upon initial device powerup or after exit from deep

powerdown, the M5M29GB/T160BVP automatically resets to read

array mode. In the read array mode, low level input to CE# and

OE#, high level input to WE# and RP#, and address signals to the

address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output

the data of the addressed location to the data input/output

(D7-D0:Byte Mode, D15-D0:Word Mode).

Write

Writes to the CUI enables reading of memory array data, device

identifiers and reading and clearing of the Status Register. They

also enable block erase and program. The CUI is written by

bringing WE# to low level, while CE# is at low level and OE# is at

high level. Address and data are latched on the earlier rising edge

of WE# and CE#. Standard micro-processor write timings are

used.

Alternating Background Operation (BGO)

The M5M29GB/T160BVP allows to read array from one bank

while the other bank operates in software command write cycling

or the erasing / programming operation in the background. Read

array operation with the other bank in BGO is performed by

changing the bank address without any additional command.

When the bank address points the bank in software command

write cycling or the erasing / programming operation, the data is

read out from the status register. The access time with BGO is the

same as the normal read operation.

Output Disable

When OE# is at VIH, output from the devices is disabled. Data

input/output are in a high-impedance(High-Z) state.

Standby

When CE# is at VIH, the device is in the standby mode and its

power consumption is reduced. Data input/output are in a

high-impedance(High-Z) state. If the memory is deselected

during block erase or program, the internal control circuits

remain active and the device consume normal active power

until the operation completes.

Mar 1999. Rev1.8

3

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

C)Single Data Load to Page Buffer (74H)

/ Page Buffer to Flash (0EH/D0H)

SOFTWARE COMMAND DEFINITIONS

The device operations are selected by writing specific software

command into the Command User Interface.

Single data load to the page buffer is performed by writing 74H

followed by a second write specifying the column address and

data. Distinct data up to 256byte/128word can be loaded to the

page buffer by this two-command sequence. On the other hand,

all of the loaded data to the page buffer is programed

simultaneously by writing Page Buffer to Flash command of 0EH

followed by the confirm command of D0H. After completion of

programing the data on the page buffer is cleared automatically.

This command is valid for only Bank(I) alike Word/Byte Program.

Read Array Command (FFH)

The device is in Read Array mode on initial device power up and

after exit from deep powerdown, or by writing FFH to the

Command User Interface. After starting the internal operation the

device is set to the read status register mode automatically.

Read Device Identifier Command (90H)

Clear Page Buffer Command (55H)

It can normally read device identifier codes when Read Device

Identifier Code Command(90H) is written to the command latch.

Following the command write, the manufacturer code and the

device code can be read from address 00000H and 00001H,

respectively.

Loaded data to the page buffer is cleared by writing the Clear

Page Buffer command of 55H followed by the Confirm command

of D0H. This command is valid for clearing data loaded by Single

Data Load to Page Buffer command.

Suspend/Resume Command (B0H/D0H)

Read Status Register Command (70H)

Writing the Suspend command of B0H during block erase

operation interrupts the block erase operation and allows read out

from another block of memory. Writing the Suspend command of

B0H during program operation interrupts the program operation

and allows read out from another block of memory. The Bank

address is required when writing the Suspend/Resume Command.

The device continues to output Status Register data when read,

after the Suspend command is written to it. Polling the WSM

Status and Suspend Status bits will determine when the erase

operation or program operation has been suspended. At this

point, writing of the Read Array command to the CUI enables

reading data from blocks other than that which is suspended.

When the Resume command of D0H is written to the CUI,

the WSM will continue with the erase or program processes.

The Status Register is read after writing the Read Status Register

command of 70H to the Command User Interface. Also, after

starting the internal operation the device is set to the Read Status

Register mode automatically.

The contents of Status Register are latched on the later falling

edge of OE# or CE#. So CE# or OE# must be toggled every status

read.

Clear Status Register Command (50H)

The Erase Status, Program Status and Block Status bits are set to

"1"s by the Write State Machine and can only be reset by the Clear

Status Register command of 50H. These bits indicates various

failure conditions.

DATA PROTECTION

Block Erase / Confirm Command (20H/D0H)

The M5M29GB/T160BVP provides selectable block locking of

memory blocks. Each block has an associated nonvolatile lock-bit

which determines the lock status of the block. In addition, the

M5M29GB/T160BVP has a master Write Protect pin (WP#) which

prevents any modifications to memory blocks whose lock-bits are

set to "0", when WP# is low. When WP# is high, all blocks can be

programmed or erased regardless of the state of the lock-bits,

and the lock-bits are cleared to "1" by erase. See the BLOCK

LOCKING table on P.9 for details.

Automated block erase is initiated by writing the Block Erase

command of 20H followed by the Confirm command of D0H. An

address within the block to be erased is required. The WSM

executes iterative erase pulse application and erase verify

operation.

Program Commands

A)Word/Byte Program (40H)

Word/Byte program is executed by a two-command sequence.

The Word/Byte Program Setup command of 40H is written to the

Command Interface, followed by a second write specifying the

address and data to be written. The WSM controls the program

pulse application and verify operation. The Word/Byte Program

Command is Valid for only Bank(I).

Power Supply Voltage

When the power supply voltage (Vcc) is less than VLKO, Low VCC

Lock-Out voltage, the device is set to the Read-only mode.

Regarding DC electrical characteristics of VLKO, see P.10

A delay time of 2 us is required before any device operation is

initiated. The delay time is measured from the time Vcc reaches

Vccmin (2.7V).

During power up, RP#=GND is recommended. Falling in Busy

status is not recommended for possibility of damaging the device.

B)Page Program for Data Blocks (41H)

Page Program for Bank(I) and Bank(II) allows fast programming of

128words/256bytes of data. Writing of 41H initiates the page

program operation for the Data area. From 2nd cycle to 257th

cycle (Byte Mode)129th cycle (Word Mode), write data must be

serially inputted. Address A6-A0,A-1 (Byte Mode) / A6-A0 (Word

Mode) have to be incremented from 00H to 7FH/FFH. After

completion of data loading, the WSM controls the program pulse

application and verify operation.

MEMORY ORGANIZATION

The M5M29GB/T160BVP has one 32Kbyte boot block, seven

32Kbyte parameter blocks, for Bank(I) and twenty-eight 64Kbyte

main blocks for Bank(II). A block is erased independently of other

blocks in the array.

Mar 1999. Rev1.8

4

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Mitsubishi 16M Flash Memory Type name

M 5 M 29G T 160B VP

Operating Voltage :

29G : 2.7 - 3.6V

Standard / BGO Type

Boot Block :

T : Top Boot

B : Bottom Boot

29W : 1.65 - 2.2V

Standard / BGO Type

Package :

VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout)

WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm

Density/Write Protect/

Word Organizetion:

160B : 16M WP#, x8/x16

161B : 16M WP1# & WP2#, x16

Mar 1999. Rev1.8

5

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

MEMORY ORGANIZATION

x8 ( Bytemode)

1F0000H-1FFFFFH

1E0000H-1EFFFFH

1D0000H-1DFFFFH

1C0000H-1CFFFFH

x16 ( Wordmode)

F8000H-FFFFFH

F0000H-F7FFFH

E8000H-EFFFFH

E0000H-E7FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

A8000H-AFFFFH

A0000H-A7FFFH

98000H-9FFFFH

90000H-97FFFH

x8 ( Bytemode)

x16 ( Wordmode)

FC000H-FFFFFH

F8000H-FBFFFH

F4000H-F7FFFH

F0000H-F3FFFH

EC000H-EFFFFH

E8000H-EBFFFH

E4000H-E7FFFH

E0000H-E3FFFH

D8000H-DFFFFH

D0000H-D7FFFH

C8000H-CFFFFH

C0000H-C7FFFH

B8000H-BFFFFH

B0000H-B7FFFH

1F8000H-1FFFFFH

1F0000H-1F7FFFH

1E8000H-1EFFFFH

1E0000H-1E7FFFH

16Kword BOOT BLOCK 35

32Kword MAIN BLOCK 35

32Kword MAIN BLOCK 34

32Kword MAIN BLOCK 33

32Kword MAIN BLOCK 32

32Kword MAIN BLOCK 31

32Kword MAIN BLOCK 30

32Kword MAIN BLOCK 29

32Kword MAIN BLOCK 28

32Kword MAIN BLOCK 27

32Kword MAIN BLOCK 26

32Kword MAIN BLOCK 25

32Kword MAIN BLOCK 24

32Kword MAIN BLOCK 23

32Kword MAIN BLOCK 22

32Kword MAIN BLOCK 21

16Kword PARAMETER BLOCK 34

16Kword PARAMETER BLOCK 33

16Kword PARAMETER BLOCK 32

1B0000H-1BFFFFH

1A0000H-1AFFFFH

1D8000H-1DFFFFH

1D0000H-1D7FFFH

16Kword PARAMETER BLOCK 31

16Kword PARAMETER BLOCK 30

16Kword PARAMETER BLOCK 29

16Kword PARAMETER BLOCK 28

32Kword MAIN BLOCK 27

32Kword MAIN BLOCK 26

32Kword MAIN BLOCK 25

32Kword MAIN BLOCK 24

32Kword MAIN BLOCK 23

32Kword MAIN BLOCK 22

190000H-19FFFFH

180000H-18FFFFH

1C8000H-1CFFFFH

1C0000H-1C7FFFH

170000H-17FFFFH

160000H-16FFFFH

1B0000H-1BFFFFH

1A0000H-1AFFFFH

150000H-15FFFFH

140000H-14FFFFH

130000H-13FFFFH

120000H-12FFFFH

190000H-19FFFFH

180000H-18FFFFH

170000H-17FFFFH

160000H-16FFFFH

110000H-1FFFFFH

100000H-10FFFFH

F0000H-FFFFFH

E0000H-EFFFFH

D0000H-DFFFFH

C0000H-CFFFFH

B0000H-BFFFFH

A0000H-AFFFFH

90000H-9FFFFH

88000H-8FFFFH

80000H-87FFFH

78000H-7FFFFH

70000H-77FFFH

68000H-6FFFFH

60000H-67FFFH

58000H-5FFFFH

50000H-57FFFH

48000H-4FFFFH

150000H-15FFFFH

140000H-14FFFFH

A8000H-AFFFFH

A0000H-A7FFFH

98000H-9FFFFH

90000H-97FFFH

88000H-8FFFFH

80000H-87FFFH

78000H-7FFFFH

70000H-77FFFH

68000H-6FFFFH

32Kword MAIN BLOCK 21

32Kword MAIN BLOCK 20

32Kword MAIN BLOCK 19

32Kword MAIN BLOCK 18

32Kword MAIN BLOCK 17

32Kword MAIN BLOCK 16

32Kword MAIN BLOCK 15

32Kword MAIN BLOCK 14

32Kword MAIN BLOCK 13

32Kword MAIN BLOCK 12

32Kword MAIN BLOCK 11

32Kword MAIN BLOCK 10

32Kword MAIN BLOCK 20

32Kword MAIN BLOCK 19

32Kword MAIN BLOCK 18

32Kword MAIN BLOCK 17

32Kword MAIN BLOCK 16

32Kword MAIN BLOCK 15

32Kword MAIN BLOCK 14

32Kword MAIN BLOCK 13

130000H-13FFFFH

120000H-12FFFFH

110000H-11FFFFH

100000H-10FFFFH

F0000H-FFFFFH

E0000H-EFFFFH

D0000H-DFFFFH

80000H-8FFFFH

70000H-7FFFFH

40000H-47FFFH

38000H-3FFFFH

C0000H-CFFFFH

B0000H-BFFFFH

60000H-67FFFH

58000H-5FFFFH

32Kword MAIN BLOCK 12

32Kword MAIN BLOCK 11

32Kword MAIN BLOCK 10

60000H-6FFFFH

50000H-5FFFFH

40000H-4FFFFH

38000H-3FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

1C000H-1FFFFH

A0000H-AFFFFH

90000H-9FFFFH

80000H-8FFFFH

70000H-7FFFFH

50000H-57FFFH

48000H-4FFFFH

40000H-47FFFH

38000H-3FFFFH

32Kword MAIN BLOCK

9

8

32Kword MAIN BLOCK

9

8

7

6

5

16Kword PARAMETER BLOCK

7

6

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

18000H-1BFFFH

14000H-17FFFH

10000H-13FFFH

0C000H-0FFFFH

08000H-0BFFFH

04000H-07FFFH

60000H-6FFFFH

50000H-5FFFFH

40000H-4FFFFH

30000H-3FFFFH

20000H-2FFFFH

10000H-1FFFFH

30000H-37FFFH

28000H-2FFFFH

20000H-27FFFH

18000H-1FFFFH

10000H-17FFFH

08000H-0FFFFH

16Kword PARAMETER BLOCK

5

4

3

2

1

32Kword MAIN BLOCK

4

3

2

1

00000H-07FFFH

00000H-03FFFH

00000H-0FFFFH

00000H-07FFFH

32Kword MAIN BLOCK

0

16Kword BOOT BLOCK 0

A19-A0

(Word Mode)

A¹⁹-A-1

(Byte Mode)

A19-A0

(Word Mode)

A19-A-1

(Byte Mode)

M5M29GB160BVP Memory Map

M5M29GT160BVP Memory Map

6

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BUS OPERATIONS

Bus Operations for Word-Wide Mode

Pins

CE#

OE#

WE#

RP#

DQ0-15

RY/BY#

Mode

Array

VIL

VIH

VIL

X

VIL

VIH

X

VIH

VIL

Data out

Status Register Data

Lock Bit Data (DQ6)

Identifier Code

Hi-Z

VOH (Hi-Z)

1)

Read

Status Register

Lock Bit Status

Identifier Code

X

VOH (Hi-Z)

Output disable

Stand by

X

2)

X

VIH

X

Hi-Z

Program

VIL

X

Command/Data in

Command

Write

Erase

X

Others

Deep Power Down

Command

VOH (Hi-Z)

Hi-Z

Bus Operations for Byte-Wide Mode

Pins

CE#

OE#

WE#

VIH

RP#

RY/BY#

DQ0-7

Mode

Array

VOH (Hi-Z)

VIL

VIH

Data out

1)

Read

Status Register

Lock Bit Status

Identifier Code

Status Register Data

Lock Bit Data (DQ6)

X

VIH

X

VIH

X

VOH (Hi-Z)

Identifier Code

Hi-Z

Output disable

Stand by

X

2)

X

Hi-Z

VIH

VIL

X

Program

VIH

VIL

X

Command/Data in

Write

Erase

Others

VIH

Command

X

VOH (Hi-Z)

Deep Power Down

X

VIL

Hi-Z

1) X at RY/BY# is VOL or VOH(Hi-Z).

*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.

A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.

2) X can be VIH or VIL for control pins.

Mar 1999. Rev1.8

7

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

SOFTWARE COMMAND DEFINITION

Command List

3rd ~257th bus cycles (Byte Mode)

2nd bus cycle

Address

1st bus cycle

Address

3rd ~129th bus cycles (Word Mode)

Command

Data

Mode

Address

(DQ7-0)

1)

(DQ7-0)

Mode

(DQ15-0)

Read Array

Write

X

FFH

90H

70H

50H

55H

40H

41H

74H

0EH

20H

B0H

D0H

71H

77H

A7H

2)

Device Identifier

Read Status Register

Clear Status Register

Clear Page Buffer

Read

IA

ID

3)

4)

Bank

X

Bank

SRD

1)

Write

X

D0H

WD

5)

6)

7)

Bank(I)

Byte/Word Program

WA

WA0

7)

Page Program

Single Data Load to Page Buffer

Page Buffer to Flash

Bank

Bank(I)

WD0

WD

Write

WAn

WDn

5)

WA

5)

8)

1)

5)

D0H

Bank(I)

Bank

WA

9)

Block Erase / Confirm

Suspend

BA

Resume

Bank

X

Bank

X

10)

1)

Read Lock Bit Status

Lock Bit Program / Confirm

Erase All Unlocked Blocks

BA

Read

Write

DQ6

D0H

Write

BA

X

1)

1) In the word-wide version(Byte#=H), upper byte data (DQ8-DQ15) is ignored.

2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code

3) Bank = Bank Address (Bank(I) or Bank(II)) : A19-A17.

4) SRD = Status Register Data

5) Byte/Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).

6) WA = Write Address,WD = Write Data

7) WA0,WAn=Write Address, WD0,WDn=Write Data.

Byte Mode : Write Address and Write Data must be provided sequentially from 00H to FFH for A6-A0,A-1. Page size is 256Byte (256byte x 8bit),

and also A19-A7(Block Address, Page Address) must be valid.

Word Mode : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit).

and also A19-A7(Block Address, Page Address) must be valid.

8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid.

9) BA = Block Address : BA = Block Address : A19-A14(Bank1) A19-A15(Bank2)

10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.

Mar 1999. Rev1.8

8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

BLOCK LOCKING

Write Protection Provided

Lock

160B

Bit

BANK(I)

BANK(II)

Data

Note

Lock Bit

WP#

RP#

VIL

(Internally)

Boot

Parameter

Locked

Deep Power Down Mode

X

0

1

X

Locked

VIL

VIH

Unlocked Unlocked

VIH

All Blocks Unlocked

Unlocked Unlocked Unlocked Unlocked

1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).

WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).

2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and

00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read

mode to array read mode.

STATUS REGISTER

Definition

Symbol

Status

"1"

Ready

Suspended

Error

"0"

Busy

Write State Machine Status

SR.7 (DQ7)

SR.6 (DQ6) Suspend Status

SR.5 (DQ5) Erase Status

Operation in Progress / Completed

Successful

Program Status

SR.4 (DQ4)

SR.3 (DQ3)

SR.2 (DQ2)

SR.1 (DQ1)

SR.0 (DQ0)

Error

Successful

Block Status after Program

Reserved

-

Reserved

*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.

A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.

*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the

over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.

9

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

DEVICE IDENTIFIER CODE

Pins

Hex. Data

1CH

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

A0

Code

VIL

0

1

0

1

0

1

0

1

0

1

Manufacturer Code

Device Code (-T160BVP)

Device Code (-B160BVP)

VIH

A0H

A1H

In the word-wide mode, the upper data(D15-8) is "0".

ABSOLUTE MAXIMUM RATINGS

Symbol

Conditions

Parameter

Min

Max

Unit

V

Vcc

Vcc voltage

-0.2

-0.6

4.6

With respect to Ground

1)

All input or output voltage

Ambient temperature

VI1

Ta

V

-40

-50

-65

85

95

°C

mA

Tbs

Temperature under bias

Tstg

Storage temperature

125

100

I OUT

Output short circuit current

1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage

on input/output pins is V^CC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.

CAPACITANCE

Limits

Parameter

Symbol

Test conditions

Unit

Typ

Min

Max

8

pF

CIN

COUT

Input capacitance (Address, Control Pins)

Output capacitance

Ta = 25°C, f = 1MHz, Vin = Vout = 0V

12

DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85°C, Vcc = 2.7V ~ 3.6V, unless otherwise noted)

Limits

Typ1)

Symbol

Parameter

Test conditions

Unit

Min

Max

±1

0V≤VIN≤VCC

ILI

Input leakage current

Output leakage current

µA

0V≤VOUT≤VCC

±10

200

ILO

ISB1

VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH

50

0.1

5

VCC standby current

VCC = 3.6V, VIN=GND or VCC,

CE# = RP# = WP#= VCC±0.3V

ISB2

5

µA

ISB3

ISB4

VCC = 3.6V, VIN=VIL/VIH, RP# = VIL

15

µA

VCC deep powerdown current

VCC = 3.6V, VIN=GND or VCC, RP# =GND±0.3V

VCC = 3.6V, VIN=VIL/VIH, CE# = VIL,

RP#=OE#=VIH, IOUT = 0mA

0.1

8

2

5

15

4

5MHz

1MHz

ICC1

ICC2

VCC read current for Word or Byte

VCC Write current for Word or Byte

mA

VCC = 3.6V,VIN=VIL/VIH, CE# =WE#= VIL,

RP#=OE#=VIH

15

ICC3

ICC4

ICC5

VIL

VCC program current

VCC erase current

VCC suspend current

Input low voltage

VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH

mA

µA

V

35

200

0.8

– 0.5

2.0

Vcc+0.5

VIH

Input high voltage

Output low voltage

V

VOL

VOH1

VOH2

VLKO

IOL = 4.0mA

IOH = –2.0mA

IOH = –100µA

0.45

V

0.85Vcc

Vcc–0.4

1.5

V

Output high voltage

V

Low VCC Lock-Out voltage 2)

2.2

V

All currents are in RMS unless otherwise noted.

1) Typical values at Vcc=3.3V, Ta=25°C

2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.

If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents

may occur.

10

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C)

Read-Only Mode

Limits

Speed Item: -80

Unit

Symbol

Parameter

Vcc=3.3V+/-0.3V

Typ

Vcc=2.7~3.6V

Typ

Min

80

Max

Min

90

Max

tRC

tAVAV Read cycle time

ns

ta (AD)

ta (CE)

ta (OE)

tCLZ

tAVQV Address access time

tELQV Chip enable access time

tGLQV Output enable access time

tELQX Chip enable to output in low-Z

80

30

90

30

0

tDF(CE) tEHQZ Chip enable high to output in high Z

tOLZ tGLQX Output enable to output in low-Z

tDF(OE) tGHQZ Output enable high to output in high Z

tPHZ tPLQZ RP# low to output high-Z

ta(BYTE) tFL/HQV

25

ns

150

BYTE# access time

tFLQZ BYTE# low to output high-Z

80

25

90

25

tBHZ

tOH

ns

tOH

Output hold from CE#, OE#, addresses

F-CE# low to BYTE# high or low

0

tBCD

tBAD

tOEH

tELFL/H

ns

5

tAVFL/H Address to BYTE# high or low

0

tWHGL

tPHEL

OE# hold from WE# high

RP# recovery to CE# low

10

tPS

150

Timing measurements are made under AC waveforms for read operations.

AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C)

Write Mode (WE# control)

Limits

Speed Item: -80

Symbol

Parameter

Unit

Vcc=3.3V+/-0.3V

Typ

Vcc=2.7~3.6V

Typ

Min

90

50

0

Max

tWC

tAS

tAVAV

tAVWH

tWHAX

tDVWH

tWHDX

tWHGL

-

80

50

0

ns

Write cycle time

Address set-up time

tAH

Address hold time

Data set-up time

tDS

50

0

50

0

tDH

tOEH

Data hold time

10

30

0

OE# hold from WE# high

Latency between Read and Write FFH or 71H

tRE

tCS

tCH

tWP

30

0

tELWL

tWHEH

tWLWH

Chip enable set-up time

Chip enable hold time

0

60

30

60

30

50

80

0

Write pulse width

tWPH tWHWL

Write pulse width high

tBS

tBH

tFL/HWH

tWHFL/H

Byte enable high or low set-up time

Byte enable high or low hold time

50

90

0

tGHWL tGHWL OE# hold to WE# Low

ns

tBLS

tPHHWH

Block Lock set-up to write enable high

Block Lockhold from valid SRD

80

0

90

0

tBLH

tQVPH

ns

tDAP

tDAE

tWHRH1

tWHRH2

80

600

90

80

600

90

ms

ns

4

Duration of auto-program operation

Duration of auto-block erase operation

Write enable high to F-RY/BY# low

40

tWHRL tWHRL

tPS tPHWL

ns

150

RP# high recovery to write enable low

Read timing parameters during command write operations mode are the same as during read-only operations mode.

Typical values at Vcc=3.3V, Ta=25°C

Mar 1999. Rev1.8

11

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85°C)

Write Mode (CE# control)

Limits

Symbol

Parameter

Speed Item: -80

Unit

Vcc=3.3V+/-0.3V

Typ

Vcc=2.7~3.6V

Typ

Min

80

50

0

Min

90

50

0

Max

tWC

tAS

tAVAV

ns

Write cycle time

tAVWH

tEHAX

tDVWH

tEHDX

tEHGL

-

Address set-up time

tAH

Address hold time

tDS

50

0

50

0

Data set-up time

tDH

tOEH

Data hold time

10

30

0

10

30

0

OE# hold from CE# high

Latency between Read and Write FFH or 71H

tRE

tWS

tWLEL Write enable set-up time

tWH

tEHWH

0

Write enable hold time

tCEP

tELEH

60

CE# pulse width

ns

tCEPH tEHEL

CE# pulse width high

30

50

80

0

30

50

90

0

tBS

tBH

tFL/HWH

Byte enable high or low set-up time

tWHFL/H

Byte enable high or low hold time

OE# hold to CE# Low

tGHEL tGHEL

ns

tPHHEH

tQVPH

tBLS

tBLH

Block Lock set-up to write enable high

Block Lockhold from valid SRD

ns

80

600

90

80

600

90

ms

ns

tDAP

tDAE

tEHRH1

tEHRH2

4

Duration of auto-program operation

Duration of auto-block erase operation

F-CE# high to F-RY/BY# low

40

tEHRL tEHRL

tPS tPHWL

ns

RP# high recovery to write enable low

150

Read timing parameters during command write operation mode are the same as during read-only operation mode.

Typical values at Vcc=3.3V, Ta=25°C

Erase and Program Performance

Typ

Unit

Parameter

Min

Max

ms

sec

ms

Block Erase Time

40

1.0

4

600

1.8

80

Main Block Write Time (Page Mode)

Page Write Time

Program Suspend Latency / Erase Suspend Time

Typ

Parameter

Min

Max

Unit

µs

Program Suspend Latency

Erase Suspend Time

Please see page 19.

15

Vcc Power Up / Down Timing

Symbol

tVCS

Parameter

Min

2

Typ

Max

Unit

RP# =VIH set-up time from Vccmin

µs

Please see page 12.

During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.

The device must be protected against initiation of write cycle for memory contents during power up/down.

The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down.

By holding RP# VIL, the contents of memory is protected during Vcc power up/down.

During power up, RP# must be held VIL for min.2µs from the time Vcc reaches Vccmin.

During power down, RP# must be held VIL until Vcc reaches GND.

RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation.

12

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Vcc POWER UP / DOWN TIMING

Read /Write Inhibit

3.3V

VCC

GND

tVCS

VIH

RP#

VIL

VIH

CE#

VIL

tPS

VIH

VIL

WE#

AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS

TEST CONDITIONS

VIH

FOR AC CHARACTERISTICS

ADDRESSES

ADDRESS VALID

tRC

VIL

Input voltage : VIL = 0V, VIH = 3.0V

Input rise and fall times : ≤5ns

Reference voltage

VIH

VIL

ta (AD)

CE#

OE#

tDF(CE)

at timing measurement : 1.5V

ta (CE)

VIH

VIL

Output load : 1TTL gate +

CL(30pF)

or

tOEH

tDF(OE)

tOH

VIH

VIL

WE#

DATA

RP#

ta (OE)

tOLZ

1.3V

VOH

VOL

tCLZ

HIGH-Z

OUTPUT VALID

tPHZ

1N914

tPS

3.3kΩ

VIH

VIL

DUT

CL =30pF

13

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION

VIH

VIL

ADDRESSES

CE#

ADDRESS VALID

tRC

VIH

VIL

ta (AD)

tDF(CE)

ta (CE)

VIH

VIL

OE#

tRE

tDF(OE)

tOH

VIH

VIL

WE#

DATA

RP#

ta (OE)

tOLZ

FFH or 71H

Valid

VOH

VOL

tCLZ

HIGH-Z

OUTPUT VALID

tPHZ

tPS

VIH

VIL

In the case of use CE# is Low fixed, it is allowed to define a timming specification of tRE

from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).

(This is only for FFH,71H program and read)

BYTE AC WAVEFORMS FOR READ OPERATION

VIH

VIL

ADDRESSES

(A0 - A19,A-1*)

ADDRESS VALID

ta(AD)

ADDRESS VALID

VIH

VIL

CE#

OE#

tDF(CE)

tDF(OE)

ta(CE)

ta(OE)

VIH

VIL

ta(BYTE)

tOLZ

tBAD

ta(BYTE)

tCLZ

VIH

VIL

BYTE#

tBCD

tOH

VIH

VIL

tBAD

HIGH-Z

VALID

tBHZ

DATA

(D0 - D7)

OUTPUT VALID

ta(AD)

VIH

VIL

DATA

(D8 - D14)

VALID

VIH

VIL

D15 / A-1

A-1

D15

A-1

When BYTE#=VIH, CE#=OE#=VIL , D15/A-1 is output status. At this time, input signal must not be applied.

Mar 1999. Rev1.8

14

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)

READ STATUS

REGISTER

WRITE READ

The other bank

PROGRAM

ARRAY COMMAND

address

VIH

VIL

BANK ADDRESS

VALID

ADDRESS VALID

BANK ADDRESS VALID

A19~A7

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

01H~FEH

01H~7EH

00H

FFH

7FH

VIH

VIL

VALID

^tAHta(CE)

tWC

tAS

VIH

VIL

ta(CE)

ta(OE)

CE#

OE#

tCS

tCH

VIH

VIL

tOEH

tDAP

tGHWL

ta(OE)

tWPH

tOEH

VIH

VIL

WE#

tDH

tWP

41H

tDS

VIH

VIL

DATA

DOUT

SRD

FFH

DIN

tWHRL

VOH

RY/BY#

BYTE#

RP#

VOL

VIH

tBH

tBS

VIL

VIH

tPS

VIL

VIH

tBLH

tBLS

WP#

VIL

AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)

READ STATUS

REGISTER

WRITE READ

The other bank

PROGRAM

ARRAY COMMAND

address

VIH

BANK ADDRESS

VALID

ADDRESS VALID

A19~A7

BANK ADDRESS VALID

VALID

VIL

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

01H~FEH

01H~7EH

00H

FFH

7FH

VIH

VIL

VALID

tWC

tAS

^tAHta(CE)

VIH

VIL

ta(CE)

ta(OE)

CE#

OE#

tCEPH

ta(OE)

VIH

VIL

tCEP

tOEH

tDAP

tOEH

tGHEL

tWS

tWH

VIH

VIL

WE#

DATA

tDH

tDS

VIH

VIL

FFH

41H

DIN

DOUT

DIN

SRD

tEHRL

VOH

VOL

RY/BY#

tBH

tBS

VIH

VIL

BYTE#

RP#

tPS

VIH

VIL

VIH

tBLH

tBLS

WP#

VIL

15

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))

READ STATUS

REGISTER

WRITE READ

PROGRAM

ARRAY COMMAND

VIH

VIL

ADDRESS

VALID

BANK ADDRESS

VALID

BANK(I) ADDRESS VALID

ta(CE)

ADDRESSES

CE#

tWC

tAS

tAH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCS

tCH

ta(OE)

tWP

OE#

tOEH

tWPH

WE#

tDS

40H

DIN

SRD

FFH

DATA

tDH

RY/BY#

BYTE#

tWHRL

tBS

VIH

VIL

tPS

tBH

VIH

VIL

VIH

VIL

RP#

tDAP

tBLS

tBLH

WP#

AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (CE# control) (to only BANK(I))

READ STATUS

REGISTER

WRITE READ

PROGRAM

ARRAY COMMAND

VIH

VIL

ADDRESS

VALID

BANK ADDRESS

VALID

BANK(I) ADDRESS VALID

ta(CE)

ADDRESSES

CE#

tWC

tAS

tAH

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

ta(OE)

tCEP

tWH

OE#

tOEH

tWS

WE#

tDS

40H

DIN

SRD

FFH

DATA

tDH

RY/BY#

BYTE#

tEHRL

VIL

VIH

VIL

tBS

tBH

tPS

VIH

VIL

VIH

VIL

RP#

tDAP

tBLS

tBLH

WP#

16

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)

READ STATUS

REGISTER

WRITE READ

ERASE

ARRAY COMMAND

VIH

VIL

BANK ADDRESS

VALID

ADDRESSES

BANK ADDRESS VALID

ADDRESS VALID

tAS

tWC

tAH

ta(CE)

VIH

VIL

CE#

OE#

tCS

tCH

ta(OE)

VIH

VIL

tOEH

tDAE

tWPH

VIH

VIL

WE#

tDH

tWP

tDS

VIH

VIL

SRD

FFH

20H

D0H

DATA

tWHRL

VOH

VOL

VIH

RY/BY#

BYTE#

tBS

tBH

VIL

tPS

VIH

RP#

VIL

VIH

VIL

tBLH

tBLS

WP#

AC WAVEFORMS FOR ERASE OPERATIONS (CE# control)

READ STATUS

REGISTER

WRITE READ

ERASE

ARRAY COMMAND

VIH

BANK ADDRESS

ADDRESSES

ADDRESS VALID

tAS

BANK ADDRESS VALID

VALID

VIL

tWC

tAH

ta(CE)

VIH

VIL

CE#

OE#

tCEPH

tCEP

ta(OE)

VIH

VIL

tOEH

tDAE

tWS

tWH

VIH

VIL

WE#

tDH

tDS

VIH

VIL

SRD

FFH

20H

D0H

DATA

tEHRL

VOH

VOL

RY/BY#

tBS

tBH

VIH

VIL

BYTE#

tPS

VIH

RP#

VIL

VIH

tBLH

tBLS

WP#

VIL

17

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)

Change Bank Address

ARRAY READ FROM THE OTHER BANK

PROGRAM DATA TO ONE BANK

ADDRESS VALID

WITH BGO

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

BANK ADDRESS

VALID

A19~A7

VALID

FFH

00H

01H~FEH

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

01H~7EH

7FH

VALID

tWC

tAS

ta(CE)

tAH

CE#

OE#

tCS

tCH

ta(OE)

tOEH

tWP

tWPH

WE#

tDS

41H

DIN

SRD

DATA

RY/BY#

DOUT

tWHRL

tDH

AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control)

Change Bank Address

PROGRAM DATA TO ONE BANK

ARRAY READ FROM THE OTHER BANK

WITH BGO

VIH

BANK ADDRESS

A19~A7

ADDRESS VALID

FFH

VALID

VIL

VIH

VIL

00H

01H~FEH

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

01H~7EH

7FH

VALID

tWC

tAS

tCEPH

ta(CE)

ta(OE)

tAH

VIH

CE#

OE#

VIL

VIH

tCEP

tWS

tOEH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCH

WE#

DATA

tDS

41H

DIN

SRD

DOUT

tEHRL

tDH

RY/BY#

18

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)

Change Bank Address

READ STATUS

REGISTER

PROGRAM DATA TO

BANK(I)

ARRAY READ FROM BANK(II) WITH BGO

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

BANK ADDRESS

VALID

A19~A7

ADDRESS VALID

VALID

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

VALID

tAH

tWC

tAS

ta(CE)

ta(OE)

CE#

tCS

tCH

OE#

tOEH

tWP

tWPH

WE#

DATA

tDS

40H

DIN

SRD

DOUT

tDH

RY/BY#

tWHRL

AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (CE# control)

Change Bank Address

PROGRAM DATA TO READ STATUS

ARRAY READ FROM BANK(II) WITH BGO

BANK(I)

REGISTER

VIH

VIL

VIH

VIL

BANK ADDRESS

VALID

A19~A7

ADDRESS VALID

VALID

BYTE#=VIL

(A6~A-1)

BYTE#=VIH

(A6 ~A0)

VALID

tAS

VALID

tWC

ta(CE)

ta(OE)

VIH

CE#

OE#

tCEPH

VIL

VIH

tCEP

tWS

tOEH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCH

WE#

DATA

tDS

40H

DIN

SRD

DOUT

tDH

RY/BY#

tEHRL

19

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)

Change Bank Address

READ STATUS

REGISTER

ARRAY READ FROM THE OTHER

BLOCK ERASE IN

ONE BANK

BANK WITH BGO

VALID

VIH

VIL

BANK ADDRESS

VALID

ADDRESS VALID

tAH

VALID

ADDRESSES

CE#

tWC

tAS

tCH

ta(CE)

ta(OE)

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCS

OE#

tOEH

tWP

tWPH

WE#

tDS

20H

D0H

SRD

DOUT

DATA

tDH

RY/BY#

tWHRL

AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (CE# control)

Change Bank Address

READ DATA FROM THE OTHER BANK

WITH BGO

BLOCK ERASE IN

ONE BANK

READ STATUS

REGISTER

VIH

VIL

BANK ADDRESS

VALID

ADDRESSES

ADDRESS VALID

VALID

tWC

tAS

tAH

ta(CE)

ta(OE)

VIH

CE#

OE#

tCEPH

VIL

VIH

tCEP

tWS

tOEH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

tCH

WE#

DATA

tDS

20H

D0H

SRD

DOUT

tDH

RY/BY#

tEHRL

20

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)

READ STATUS

REGISTER

VIH

VIL

ADDRESSES

BANK ADDRESS VALID

tAS

BANK ADDRESS VALID

tAH

ta(CE)

VIH

VIL

CE#

OE#

tCS

tCH

ta(OE)

VIH

VIL

tOEH

Program Suspend Latency

VIH

VIL

WE#

tWP

S.R.6,7=1

VALID SRD

VIH

VIL

B0H

DATA

VOH

VOL

RY/BY#

VIH

RP#

tBLS

VIL

VIH

VIL

tBLH

WP#

AC WAVEFORMS FOR SUSPEND OPERATION (CE# control)

READ STATUS

REGISTER

VIH

ADDRESSES

BANK ADDRESS VALID

tAS

BANK ADDRESS VALID

VIL

tAH

ta(CE)

VIH

VIL

tCEP

CE#

OE#

ta(OE)

VIH

VIL

tOEH

Program Suspend Latency

VIH

VIL

tWS

tWH

WE#

S.R.6,7=1

VALID SRD

VIH

VIL

B0H

DATA

VOH

VOL

RY/BY#

VIH

RP#

tBLS

tBLH

VIL

VIH

WP#

VIL

Mar 1999. Rev1.8

21

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

FULL STATUS CHECK PROCEDURE

LOCK BIT PROGRAM FLOW CHART

STATUS REGISTER

READ

START

WRITE 77H

SR.4 =1

and

COMMAND SEQUENCE ERROR

BLOCK ERASE ERROR

SR.5 =1

?

YES

NO

WRITE D0H

BLOCK ADDRESS

NO

SR.5 = 0 ?

YES

SR.7 = 1 ?

NO

YES

PROGRAM ERROR

(PAGE, LOCK BIT)

SR.4 = 0 ?

YES

LOCK BIT PROGRAM

SR.4 = 0 ?

YES

FAILED

NO

PROGRAM ERROR

(BLOCK)

LOCK BIT PROGRAM

SUCCESSFUL

SR.3 = 0 ?

YES

SUCCESSFUL

(BLOCK ERASE, PROGRAM)

BYTE PROGRAM FLOW CHART

PAGE PROGRAM FLOW CHART

START

WRITE 40H

WRITE 41H

n = 0

WRITE

ADDRESS , DATA

n = n+1

WRITE

ADDRESS n, DATA n

STATUS REGISTER

READ

n = FFH ?

or

n = 7FH ?

NO

SR.7 = 1 ?

WRITE B0H ?

YES

STATUS REGISTER

READ

SUSPEND LOOP

WRITE D0H

FULL STATUS CHECK

IF DESIRED

NO

SR.7 = 1 ?

YES

WRITE B0H ?

YES

PAGE PROGRAM

COMPLETED

YES

* Byte program is admitted to only BANK(I).

SUSPEND LOOP

WRITE D0H

FULL STATUS CHECK

IF DESIRED

PAGE PROGRAM

COMPLETED

YES

Mar 1999. Rev1.8

22

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

SUSPEND / RESUME FLOW CHART

CLEAR PAGE BUFFER

START

WRITE B0H

SUSPEND

WRITE 55H

STATUS REGISTER

READ

WRITE D0H

SR.7 = 1?

YES

NO

PAGE BUFFER CLEAR

COMPLETED

PROGRAM / ERASE

COMPLETED

SR.6 =1?

SINGLE DATA LOAD TO PAGE BUFFER

YES

WRITE FFH

START

WRITE 74H

READ ARRAY DATA

WRITE

ADDRESS , DATA

DONE

READING ?

NO

YES

NO

DONE

LOADING?

RESUME

WRITE D0H

OPERATION

RESUMED

YES

SINGLE DATA LOAD

TO PAGE BUFFER

COMPLETED

* The bank address is required when writing this command. Also, there is

no need to suspend the erase or program operation when reading data

from the other bank. Please use BGO function.

BLOCK ERASE FLOW CHART

PAGE BUFFER TO FLASH

START

WRITE 20H

WRITE 0EH

WRITE D0H

BLOCK ADDRESS

WRITE D0H

PAGE ADDRESS

STATUS REGISTER

READ

STATUS REGISTER

READ

NO

WRITE B0H ?

NO

SR.7 = 1 ?

WRITE B0H ?

SR.7 = 1 ?

YES

FULL STATUS CHECK

IF DESIRED

SUSPEND LOOP

WRITE D0H

FULL STATUS CHECK

IF DESIRED

SUSPEND LOOP

WRITE D0H

BLOCK ERASE

COMPLETED

PAGE BUFFER TO FLASH

COMPLETED

YES

23

Mar 1999. Rev1.8

MITSUBISHI LSIs

M5M29GB/T160BVP-80

16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

PACKAGE DIMENSIONS

48P3E (48pin 12 x 20 mm TSOP(I))

48P3E-C

Plastic 48pin 12x20mm TSOP(I)

EIAJ Package Code

TSOP I 48-P-1220-0.50

JEDEC Code

Weight(g)

Lead Material

Cu Alloy

MD

D

H

D

l

2

Recommended Mount Pad

1

48

Dimension in Millimeters

Symbol

A

Min

Nom

Max

1.2

0.2

0.125

1.0

A

0.05

0.15

1

2

y

0.2

0.3

b

G

0.105

18.3

0.125

18.4

0.175

18.5

c

D

E

11.9

12.0

0.5

12.1

24

25

e

19.8

0.4

20.0

0.5

20.2

0.6

H_D

L

0.8

0.6

L

1

0.75

Lp

A3

z

0.45

F

L1

0.25

0.4

Z

x

y

1

0.1

10°

θ

0°

L

0.225

18.6

b

2

Lp

Detail G

0.9

l 2

M_D

Detail F

Mar 1999. Rev1.8

25


型号：	M5M29GB160BVP-90
厂家：	Mitsubishi Group
描述：	Flash, 2MX8, 90ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 光电二极管
文件：	总25页 (文件大小：254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M5M29GB160BVP-90 [MITSUBISHI]

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