M5M29GB800AVP-80I [MITSUBISHI]
Flash, 512KX16, 80ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48;
| 型号： | M5M29GB800AVP-80I |
| 厂家： | 
Mitsubishi Group |
| 描述： | Flash, 512KX16, 80ns, PDSO48, 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 光电二极管 |
| 文件： | 总22页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The MITSUBISHI Mobile FLASH M5M29GB/T800AVP, RV are 3.3V-only high speed 8,388,608-bit CMOS boot block Flash Memories with
alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in
one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for
mobile and personal computing, and communication products. The M5M29GB/T800AVP, RV are fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 48pin TSOP(I) .
FEATURES
Organization
.................................
.................................
524,288 word x 16bit
1,048,576 word x 8 bit
VCC = 2.7~3.6V
Boot Block
M5M29GB800AVP,RV
M5M29GT800AVP,RV
...........................
...........................
Bottom Boot
Top Boot
.............................
Supply voltage ................................
Other Functions
..............................
..............................
Access time
-80
80ns : Vcc=3.0V
100ns : Vcc=2.7V
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
-1I 100ns : Vcc=3.0V
120ns : Vcc=2.7V
Power Dissipation
Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)
.................................
.........
.................................
72 mW (Max. at 5MHz)
0.33µW (typ.)
(After Automatic Power saving)
Package
Program/Erase
144 mW (Max.)
0.33µW (typ.)
48-Lead, 12mm x 20mm TSOP (type-I)
.........................................
Standby
.......................
Deep power down mode
Auto program for Bank(I)
0.33µW (typ.)
.................................
Program Time
Program Unit
4ms (typ.)
.........................
.........................
APPLICATION
(Byte Program)
(Page Program)
Auto program for Bank(II)
1word/1byte
Code Storage PC BIOS
128word/256byte
Digital Cellular Phone/Telecommunication
.................................
.................................
Program Time
Program Unit
Auto Erase
Erase time
4ms (typ.)
128word/256byte
.................................
.....................
40 ms (typ.)
Erase Unit
Bank(I) Boot Block
8Kword/16Kbyte x 1
4Kword/8Kbyte x 6
32Kword/64Kbyte x 15
..............
......................
Parameter Block
Bank(II) Main Block
.........................................
Program/Erase cycles
100Kcycles
PIN CONFIGURATION (TOP VIEW)
800AVP
800AVP
800ARV
800ARV
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A16
BYTE#
GND
DQ15/A-1
DQ7
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A15
A14
A13
A12
A11
A10
A9
A15
A14
A13
A12
A11
A10
A9
BYTE#
GND
DQ15/A-1
DQ7
3
3
4
4
5
5
6
6
DQ14
DQ6
DQ14
DQ6
7
7
8
8
DQ13
DQ5
DQ13
DQ5
A8
A8
9
9
NC
NC
WE#
RP#
NC
NC
NC
WE#
RP#
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ12
DQ4
DQ12
DQ4
VCC
VCC
M5M29GB/T
800ARV
M5M29GB/T
800AVP
DQ11
DQ3
DQ11
DQ3
WP1#
RY/BY#
A18
A17
A7
WP1#
RY/BY#
A18
A17
A7
DQ10
DQ2
DQ10
DQ2
DQ9
DQ9
DQ1
DQ1
A6
DQ8
A6
DQ8
A5
DQ0
A5
DQ0
A4
OE#
GND
CE#
28
27
26
25
A4
OE#
GND
CE#
A0
A3
A3
A2
23
24
A2
A1
A0
A1
RV(Reverse bend): 48P3E-C
Outline 48pin TSOP type-I (12 X 20mm)
VP(Normal bend): 48P3E-B
NC : NO CONNECTION
June 1998 , Rev.3.1
1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
128 WORD PAGE BUFFER
A18
Main Block
32KW
A17
A16
VCC (3.3V)
GND (0V)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
15
X-DECODER
Main Block
32KW
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
Parameter Block1
4KW
4KW
4KW
4KW
4KW
4KW
ADDRESS
INPUTS
Boot Block
8KW
A4
A3
A2
A1
A0
Y-GATE / SENSE AMP.
MULTIPLEXER
Y-DECODER
STATUS / ID REGISTER
CHIP ENABLE INPUT
CE#
OUTPUT ENABLE INPUT OE#
WRITE ENABLE INPUT WE#
WRITE PROTECT INPUT WP1#
CUI
WSM
INPUT/OUTPUT
BUFFERS
RESET/POWER DOWN INPUT RP#
BYTE ENABLE INPUT
BYTE#
READY/BUSY OUTPUT RY/BY#
DQ15/A-1DQ14DQ13DQ12
DQ3DQ2DQ1DQ0
DATA INPUTS/OUTPUTS
FUNCTION
Alternating Background Operation (BGO)
The M5M29GB/T800AVP,RV allows to read array from one
bank while the other bank operates in software command
write cycling or the erasing / programming operation in the
background. Read array operation with the other bank in
BGO is performed by changing the bank address without
any additional command. When the bank address points the
bank in the erasing / programming operation, the data is
read out from the status register. The access time with BGO
is the same as the normal read operation.
The M5M29GB/T800AVP,RV includes on-chip program/erase
control circuitry. The Write State Machine (WSM) controls block
erase and byte/page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the RP# pin is at GND,
minimizing power consumption.
Read
The M5M29GB/T800AVP,RV has three read modes, which
accesses to the memory array, the Device Identifier and the Status
Register. The appropriate read command are required to be
written to the CUI. Upon initial device powerup or after exit from
deep powerdown, the M5M29GB/T800A automatically resets to
read array mode. In the read array mode, low level input to CE#
and OE#, high level input to WE# and RP#, and address signals to
the address inputs (A0-A18:Word mode, A-1, A0-A18:Byte mode)
output the data of the addressed location to the data input/output
(D0-D15:Word mode, D0-D7:Byte mode).
Output Disable
When OE# is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
Standby
When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
Write
Deep Power-Down
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while CE# is at low level and OE# is at
high level. Address and data are latched on the earlier rising edge
of WE# and CE#. Standard micro-processor write timings are
used.
When RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
June 1998 , Rev.3.1
2
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or CE# isn't changed
more than 200ns after the last alternation. The power
consumption becomes the same as the stand-by mode. While
in this mode, the output data is latched and can be read out.
New data is read out correctly when addresses are changed.
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 256byte can be loaded to the page buffer
by this two-command sequence. On the other hand, all of the
loaded data to the page buffer is programed simultaneously by
writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
SOFTWARE COMMAND DEFINITIONS
These commands are valid for only Bank(I) alike Word/Byte
Program.
The device operations are selected by writing specific software
command into the Command User Interface.
Clear Page Buffer Command (55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.
Read Device Identifier Command (90H)
Read Device Identifier Code Command(90H) is written to the
command latch for reading device identifier codes. Following the
command write, the manufacturer code and the device code can
be read from address 0000H and 0001H, respectively.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of OE# or CE#. So CE# or OE# must be toggled every status
read.
DATA PROTECTION
Clear Status Register Command (50H)
The M5M29GB/T800A provides selectable block locking of
memory blocks. Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In addition, the
M5M29GB/T800A has a master Write Protect pin (WP1#) which
prevents any modifications to memory blocks whose lock-bits are
set to "0", when WP1# is low. When WP1# is high, all blocks
can be programmed or erased regardless of the state of
the lock-bits, and the lock-bits are cleared to "1" by erase. See
the BLOCK LOCKING table on P.8 for details.
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.2V, the device
is set to the Read-only mode.
Program Commands
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (2.7V).
During power up, RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
A)Word/Byte Program (40H)
Word/Byte program is executed by a two-command sequence.
The Word/Byte Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word/Byte Program
Command is Valid for only Bank(I).
MEMORY ORGANIZATION
The M5M29GB/T800AVP,RV has one 8Kword boot block, six
4Kword parameter blocks, for Bank(I) and fifteen 32Kword main
blocks for Bank(II). A block is erased independently of other blocks
in the array.
B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words/256bytes of data. Writing of 41H initiates the page
program operation for the Data area. From 2nd cycle to 129th
cycle (Word mode)/257th cycle (Byte mode), write data must be
serially inputted. Address A6-A0 (Word mode)/A6-A0,A-1 (Byte
mode) have to be incremented from 00H to 7FH/FFH. After
completion of data loading, the WSM controls the program pulse
application and verify operation.
3
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Mitsubishi 8M Flash Memory Type name
M 5 M 29G T 800A VP - 70
Operating Voltage :
29G : 2.7 - 3.6V
Operating Temperature :
Access Speed :
: 0°C~70°C
Standard / BGO Type
70 : 70ns@Vcc=3.0V
90ns@Vcc=2.7V
80 : 80ns@Vcc=3.0V
100ns@Vcc=2.7V
10 : 100ns@Vcc=3.0V
120ns@Vcc=2.7V
: -40°C~85°C
I
Boot Block :
T : Top Boot
B : Bottom Boot
29K : 4.5 - 5.5V
Standard / BGO Type
Density/Write Protect :
800A : 8M WP1#
801A : 8M WP1# & WP2#
008A : 8M WP1# & WP2#
Package :
VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout)
VP : 48pin TSOP(I) 12mm x 20mm (Reverse Pinout)
WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm
Varied Combination
M5M29GB800AVP -70*,80,10*
-8I*,1I
M5M29GB800ARV -70*,80,10*
-8I*,1I
M5M29GT800AVP -70*,80,10*
-8I*,1I
M5M29GT800ARV -70*,80,10*
-8I*,1I
M5M29GB801AWG (-8I specification)
M5M29GB008AWG (-8I specification)
M5M29GT801AWG (-8I specification)
M5M29GT008AWG (-8I specification)
M5M29KB800AVP -70*,80,10*
-8I*,1I
M5M29KT800AVP -70*,80,10*
-8I*,1I
* : T.B.D (To Be Decided)
June 1998 , Rev.3.1
4
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
MEMORY ORGANIZATION
x8 ( Bytemode) x16 ( Wordmode)
F0000H-FFFFFH 78000H-7FFFFH
x8 ( Bytemode) x16 ( Wordmode)
FC000H-FFFFFH 7E000H-7FFFFH
8Kword BOOT BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
FA000H-FBFFFH 7D000H-7DFFFH
F8000H-F9FFFH 7C000H-7CFFFH
F6000H-F7FFFH 7B000H-7BFFFH
F4000H-F5FFFH 7A000H-7AFFFH
F2000H-F3FFFH 79000H-79FFFH
F0000H-F1FFFH 78000H-78FFFH
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
32Kword MAIN BLOCK
E0000H-EFFFFH 70000H-77FFFH
D0000H-DFFFFH 68000H-6FFFFH
C0000H-CFFFFH 60000H-67FFFH
B0000H-BFFFFH 58000H-5FFFFH
A0000H-AFFFFH 50000H-57FFFH
90000H-9FFFFH 48000H-4FFFFH
80000H-8FFFFH 40000H-47FFFH
70000H-7FFFFH 38000H-3FFFFH
60000H-6FFFFH 30000H-37FFFH
50000H-5FFFFH 28000H-2FFFFH
40000H-4FFFFH 20000H-27FFFH
30000H-3FFFFH 18000H-1FFFFH
20000H-2FFFFH 10000H-17FFFH
10000H-1FFFFH 08000H-0FFFFH
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
4Kword PARAMETER BLOCK
8Kword BOOT BLOCK
0E000H-0FFFFH 07000H-07FFFH
0C000H-0DFFFH 06000H-06FFFH
0A000H-0BFFFH 05000H-05FFFH
08000H-09FFFH 04000H-04FFFH
06000H-07FFFH 03000H-03FFFH
04000H-05FFFH 02000H-02FFFH
00000H-03FFFH 00000H-01FFFH
A18-A-1(Bytemode)A18-A0(Wordmode)
00000H-0FFFFH 00000H-07FFFH
A18-A-1(Bytemode)A18-A0(Wordmode)
M5M29GB800AVP,RV Memory Map
M5M29GT800AVP,RV Memory Map
5
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BUS OPERATIONS
Bus Operations for Word-Wide Mode (BYTE#=VIH)
Pins
CE#
OE#
WE#
RP#
DQ0-15
RY/BY#
Mode
Array
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
VOH (Hi-Z)
1)
Read
Status Register
Lock Bit Status
Identifier Code
X
X
VOH (Hi-Z)
Output disable
Stand by
X
2)
X
VIH
VIH
VIH
X
Hi-Z
X
Program
VIL
VIL
VIL
X
Command/Data in
Command
X
Write
Erase
X
X
Others
Command
VOH (Hi-Z)
Deep Power Down
Hi-Z
Bus Operations for Byte-Wide Mode (BYTE#=VIL)
Pins
CE#
OE#
WE#
RP#
RY/BY#
DQ0-7
Mode
Array
VOH (Hi-Z)
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
Data out
1)
Read
Status Register
Lock Bit Status
Identifier Code
Status Register Data
Lock Bit Data (DQ6)
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
X
VOH (Hi-Z)
Identifier Code
Hi-Z
Output disable
Stand by
X
2)
X
VIH
VIH
VIH
X
Hi-Z
X
Program
VIL
VIL
VIL
X
Command/Data in
Command
Command
Hi-Z
X
Write
Erase
Others
X
X
VOH (Hi-Z)
Deep Power Down
1) X at RY/BY# is VOL or VOH(Hi-Z).
*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
6
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command List
3rd - 257th bus cycles (Byte Mode)
3rd - 129th bus cycles (Word Mode)
1st bus cycle
Address
2nd bus cycle
Address
1)
Data
Data
Data
Command
Read Array
Mode
Mode
Mode
Address
(DQ7-0)
(DQ7-0)
(DQ15-0)
(DQ7-0)
(DQ15-0)
FFH
90H
70H
50H
55H
40H
41H
74H
0EH
20H
B0H
D0H
71H
77H
A7H
(DQ15-0)
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
Bank
2)
2)
Device Identifier
Read
Read
IA
ID
SRD
3)
3)
4)
Bank
Read Status Register
Clear Status Register
Clear Page Buffer
X
X
1)
6)
7)
6)
1)
1)
Write
Write
Write
Write
Write
Write
X
D0H
WD
6)
5)
5)
Bank(I)
WA
Byte/Word Program
3)
7)
7)
7)
7)
Bank
WA0
WA
WD0
WD
D0H
D0H
Write
WAn
WDn
Page Program
Single Data Load to Page Buffer
Page Buffer to Flash
5)
5)
6)
Bank(I)
5)
5)
8)
Bank(I)
WA
BA
3)
9)
Bank
Block Erase / Confirm
Suspend
3)
Bank
3)
Bank
Resume
9)
10)
1)
Read
Write
Write
Read Lock Bit Status
Lock Bit Program / Confirm
BA
X
Bank
DQ6
D0H
D0H
3)
9)
Write
Write
BA
11)
1)
X
X
Erase All Unlocked Blocks
1) In the word-wide mode, upper byte data (DQ8 - DQ15) is ignored.
2) IA = ID Code Address : A0 = VIL (Manufacturer's Code) : A0 = VIH (Device Code), ID = ID Code.
3) Bank = Bank Address (Bank(I) or Bank(II)). A18 - A15.
4) SRD = Status Register Data.
5) Byte/Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address, WD = Write Data.
7) WA0,WAn = Write Address, WD0,WDn = Write Data.
BYTE# = VIL : Write Address and Write Data must be provided sequentially from 00H to FFH for A6 - A-1. Page size is 256Byte (256byte x 8bit),
and also A18 - A7(Block Address, Page Address) must be valid.
BYTE# = VIH : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6 - A0. Page size is 128word (128word x 16bit),
and also A18 - A7(Block Address, Page Address) must be valid.
8) WA = Write Address.
Upper page address, A18 - A7(Block Address, Page Address) must be valid.
9) BA = Block Address : Bank(I) : A18 - A12.
Bank(II) : A18 - A15.
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
11) Read Status Register command (70H) is required to detect the completion of Erase All Unlocked Blocks. 70H command has to be written at least after 1.8s
from issuing A7H.
7
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK LOCKING
Write Protection Provided
Lock
Bit
800A
BANK(I)
BANK(II)
Note
Lock Bit
RP# WP1#
(Internally)
Boot
Parameter
Locked
Data
Deep Power Down Mode
VIL
X
X
0
1
X
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
VIL
Unlocked Unlocked
VIH
VIH
All Blocks Unlocked
Unlocked Unlocked Unlocked Unlocked
DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).
WP# pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0).
STATUS REGISTER
Definition
Symbol
Status
"1"
Ready
Suspended
Error
"0"
Write State Machine Status
SR.7 (DQ7)
Busy
SR.6 (DQ6) Suspend Status
SR.5 (DQ5) Erase Status
Operation in Progress / Completed
Successful
Program Status
SR.4 (DQ4)
SR.3 (DQ3)
SR.2 (DQ2)
SR.1 (DQ1)
SR.0 (DQ0)
Error
Error
Successful
Successful
Block Status after Program
Reserved
-
-
-
-
-
-
Reserved
Reserved
*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the
over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
*The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.
8
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DEVICE IDENTIFIER CODE
Pins
Hex. Data
1CH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
Code
Manufacturer Code
VIL
VIH
VIH
0
0
0
0
1
1
0
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
Device Code (-T800A)
Device Code (-B800A)
72H
74H
In the word-wide mode, the upper data(D15-8) is "0".
A1~A8, A10~A18, CE#,OE# = VIL, WE# = VIH, D15/A-1 = VIL (BYTE# = L)
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Min
Max
Unit
Vcc
Vcc voltage
-0.2
-0.6
-40
4.6
4.6
85
V
V
All input or output voltage except Vcc,A9,RP#1)
VI1
Ta
With respect to Ground
Ambient temperature
°C
Tbs
Tstg
I OUT
Temperature under bias
-50
-65
95
°C
Storage temperature
Output short circuit current
°C
mA
125
100
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Limits
Parameter
Symbol
Test conditions
Unit
Typ
Min
Max
8
pF
pF
CIN
COUT
Input capacitance (Address, Control Pins)
Output capacitance
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
12
DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85°C, Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Limits
Typ1)
Symbol
Parameter
Test conditions
0V£VIN£VCC
Unit
Min
Max
±1.0
±10
ILI
Input leakage current
Output leakage current
µA
µA
µA
0V£VOUT£VCC
ILO
ISB1
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
50
200
VCC standby current
VCC = 3.6V, VIN=GND or VCC,
CE# = RP# = WP#= VCC±0.3V
ISB2
0.1
5
µA
ISB3
ISB4
VCC = 3.6V, VIN=VIL/VIH, RP# = VIL
5
0.1
10
2
15
µA
µA
VCC deep powerdown current
VCC = 3.6V, VIN=GND or VCC, RP# =GND±0.3V
VCC = 3.6V, VIN=VIL/VIH, CE# = VIL,
RP#=OE#=VIH, IOUT = 0mA
5
20
4
5MHz
1MHz
ICC1
ICC2
VCC read current for Word or Byte
VCC Write current for Word or Byte
mA
mA
VCC = 3.6V,VIN=VIL/VIH, CE# =WE#= VIL,
RP#=OE#=VIH
30
ICC3
ICC4
VCC program current
VCC erase current
VCC suspend current
Input low voltage
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
40
40
mA
mA
µA
V
ICC5
VIL
200
0.8
– 0.5
2.0
Vcc+0.5
VIH
Input high voltage
Output low voltage
V
VOL
IOL = 4.0mA
IOH = –2.0mA
IOH = –100µA
0.45
2.5
V
VOH1
VOH2
VLKO
0.85Vcc
Vcc–0.4
1.5
V
Output high voltage
V
Low VCC Lock-Out voltage 2)
V
All currents are in RMS unless otherwise noted.
1) Typical values at Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.
If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
9
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V)
Read-Only Mode
Limits
M5M29GB/T800A-70
M5M29GB/T800A-80
M5M29GB/T800A-10
Unit
Symbol
Parameter
Min
70
Typ
Max
Min
80
Typ
Max
Min
100
Typ
Max
tRC
tAVAV Read cycle time
tAVQV Address access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta (AD)
70
70
40
80
80
40
100
100
50
ta (CE)
ta (OE)
tCLZ
tELQV Chip enable access time
tGLQV Output enable access time
tELQX Chip enable to output in low-Z
0
0
0
0
0
0
tDF(CE) tEHQZ Chip enable high to output in high Z
tGLQX Output enable to output in low-Z
tDF(OE) tGHQZ Output enable high to output in high Z
tPLQZ RP# low to output high-Z
ta(BYTE) tFL/HQV BYTE# access time
25
25
25
tOLZ
25
25
25
tPHZ
150
150
150
70
25
80
25
100
25
ns
tBHZ
tOH
tFLQZ
tOH
BYTE# low to output high-Z
ns
ns
ns
ns
ns
Output hold from CE#, OE#, addresses
0
0
0
tBCD
tELFL/H CE# low to BYTE# high or low
tAVFL/H Address to BYTE# high or low
tWHGL OE# hold from WE# high
5
5
5
5
5
5
tBAD
tOEH
70
80
100
500
tPS
tPHEL
RP# recovery to CE# low
500
500
ns
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V)
Write Mode (WE# control)
Limits
Symbol
M5M29GB/T800A-70
M5M29GB/T800A-80
M5M29GB/T800A-10
Parameter
Unit
Vcc=3.0-3.6V Vcc=2.7-3.6V Vcc=3.0-3.6V Vcc=2.7-3.6V Vcc=3.0-3.6V Vcc=2.7-3.6V
Typ
Typ
Typ
Typ
Typ
Typ
Max
Min
70
50
0
Max Min
MaxMin
Max Min
100
50
Max Min
100
50
Max Min
120
50
tWC tAVAV
90
50
0
80
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tAS
tAH
tDS
tDH
tCS
tCH
tWP
tAVWH
tWHAX
tDVWH
tWHDX
tELWL
tWHEH
tWLWH
Address set-up time
Address hold time
Data set-up time
0
0
0
50
0
50
0
50
0
50
50
50
0
0
0
Data hold time
0
0
0
0
0
0
Chip enable set-up time
Chip enable hold time
Write pulse width
0
0
0
0
0
0
50
20
70
50
70
60
30
90
50
90
60
20
80
50
80
70
70
80
tWPH tWHWL
tGHWL tGHWL
30
30
40
Write pulse width high
OE# hold to WE# Low
100
50
100
50
120
50
tBS
tBH
tFL/HWH
tWHFL/H
Byte enable high or low set-up time
Byte enable high or low hold time
100
100
120
tBLS
tPHHWH
70
0
90
0
80
0
100
0
100
0
120
0
ns
ns
Block Lock set-up to write enable high
Block Lockhold from valid SRD
tBLH tQVPH
4
4
4
4
4
4
tDAP tWHRH1
tDAE tWHRH2
tWHRL tWHRL
80
600
70
80
600
70
80
600
80
80
600
100
500
80
600
100
500
80 ms
600 ms
120 ns
ns
Duration of auto-program operation
Duration of auto-block erase operation
Write enable high to RY/BY# low
40
40
40
40
40
40
tPS
tPHWL
500
500
500
500
RP# high recovery to write enable low
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at Vcc=3.3V, Ta=25°C
June 1998 , Rev.3.1
10
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85°C, Vcc = 2.7V ~ 3.6V)
Write Mode (CE# control)
Limits
Symbol
M5M29GB/T800A-70
M5M29GB/T800A-80
M5M29GB/T800A-10
Parameter
Unit
Vcc=3.0-3.6V Vcc=2.7-3.6V Vcc=3.0-3.6V Vcc=2.7-3.6V Vcc=3.0-3.6V Vcc=2.7-3.6V
Typ
Typ
Typ
Typ
Typ
Typ
Max
Min
70
50
0
Max Min
MaxMin
Max Min
100
50
Max Min
100
50
Max Min
120
50
tWC tAVAV
90
50
0
80
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tAS
tAH
tDS
tDH
tWS
tAVWH
tEHAX
tDVWH
tEHDX
tWLEL
Address set-up time
0
0
0
Address hold time
50
0
50
0
50
0
50
50
50
Data set-up time
0
0
0
Data hold time
0
0
0
0
0
0
Write enable set-up time
Write enable hold time
CE# pulse width
tWH tEHWH
tCEP tELEH
0
0
0
0
0
0
50
20
70
50
70
60
30
90
50
90
60
20
80
50
80
70
70
80
tCEPH tEHEL
tGHEL tGHEL
30
30
40
CE# pulse width high
OE# hold to CE# Low
Byte enable high or low set-up time
Byte enable high or low hold time
Block Lock set-up to write enable high
100
50
100
50
120
50
tFL/HWH
tEHFL/H
tBS
tBH
tBLS
100
100
120
tPHHEH
70
0
90
0
80
0
100
0
100
0
120
0
ns
ns
tBLH
tDAP
tDAE
tEHRL
tPS
Block Lockhold from valid SRD
Duration of auto-program operation
Duration of auto-block erase operation
CE# high to RY/BY# low
tQVPH
tEHRH1
4
4
4
4
4
4
80
600
70
80
600
70
80
600
80
80
600
100
500
80
600
100
500
80 ms
600 ms
120 ns
ns
tEHRH2
tEHRL
tPHEL
40
40
40
40
40
40
RP# high recovery to write enable low 500
500
500
500
Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at Vcc=3.3V, Ta=25°C
Erase and Program Performance
Typ
Unit
Parameter
Min
Max
ms
ms
Main Block Erase Time
40
20
16
1.0
4
600
600
Boot Block Erase Time
ms
sec
Parameter Block Erase Time
Main Block Write Time (Page Mode)
Page Write Time
600
1.8
ms
80
Vcc Power Up / Down Timing
Symbol
Parameter
Min
2
Typ
Max
Unit
µs
tVCS
RP# =VIH set-up time from Vccmin
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down.
By holding RP# VIL, the contents of memory is protected during Vcc power up/down.
During power up, RP# must be held VIL for min.2µs from the time Vcc reaches Vccmin.
During power down, RP# must be held VIL until Vcc reaches GND.
RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation.
11
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
3.3V
VCC
GND
tVCS
VIH
RP#
VIL
VIH
CE#
VIL
tPS
tPS
VIH
VIL
WE#
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
TEST CONDITIONS
VIH
FOR AC CHARACTERISTICS
ADDRESSES
ADDRESS VALID
tRC
VIL
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : £5ns (70,80ns)
£10ns (100ns)
Reference voltage
at timing measurement : 1.5V
VIH
VIL
ta (AD)
CE#
OE#
tDF(CE)
ta (CE)
VIH
VIL
tOEH
tDF(OE)
tOH
Output load : 1TTL gate +
CL(100pF for 100ns)
CL(30pF for 70,80ns)
VIH
VIL
WE#
DATA
RP#
ta (OE)
tOLZ
or
1.3V
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
OUTPUT VALID
tPHZ
1N914
tPS
3.3kW
VIH
VIL
DUT
CL =30/100pF
BYTE AC WAVEFORMS FOR READ OPERATION
VIH
ADDRESSES
(A18 - A0)
ADDRESS VALID
ta(AD)
ADDRESS VALID
VIL
VIH
VIL
CE#
tDF(CE)
tDF(OE)
ta(CE)
ta(OE)
VIH
VIL
OE#
ta(BYTE)
tOLZ
tBAD
ta(BYTE)
tCLZ
VIH
VIL
BYTE#
tBCD
tOH
VIH
VIL
tBAD
HIGH-Z
HIGH-Z
VALID
VALID
tBHZ
DATA
(DQ7 - DQ0)
OUTPUT VALID
ta(AD)
VIH
DATA
VALID
(DQ14 - DQ8) VIL
VIH
DQ15 / A-1
A-1
DQ15
A-1
VIL
When BYTE#=VIH, CE#=OE#=VIL , DQ15/A-1 is output status. At this time, input signal must not be applied.
June 1998 , Rev.3.1
12
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
READ STATUS
WRITE READ
The other bank
PROGRAM
REGISTER ARRAY COMMAND
address
VIH
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
A18~A7
VIL
BYTE#=VIL
(A6~A-1)
01H~FEH
01H~7EH
00H
00H
FFH
7FH
VIH
VIL
VALID
BYTE#=VIH
(A6 ~A0)
tAH ta(CE)
tWC
tAS
VIH
VIL
ta(CE)
ta(OE)
CE#
OE#
tCS
tCH
VIH
VIL
tOEH
tDAP
tGHWL
ta(OE)
tWPH
tOEH
VIH
VIL
WE#
tDH
tWP
41H
tDS
VIH
VIL
DATA
RY/BY#
BYTE#
DOUT
SRD
FFH
DIN
DIN
DIN
tWHRL
VOH
VOL
tBS
tBH
VIH
VIL
tPS
RP#
VIH
VIL
VIH
tBLH
tBLS
WP1#
WP2#
VIL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)
READ STATUS
REGISTER
WRITE READ
The other bank
PROGRAM
ARRAY COMMAND
address
VIH
VALID
VALID
ADDRESS VALID
A18~A7
BANK ADDRESS VALID
VIL
BYTE#=VIL
(A6~A-1)
01H~FEH
01H~7EH
00H
00H
FFH
7FH
VIH
VIL
VALID
BYTE#=VIH
(A6 ~A0)
tWC
tAS
tAH ta(CE)
VIH
VIL
ta(CE)
ta(OE)
CE#
OE#
tCEPH
ta(OE)
VIH
VIL
tCEP
tOEH
tDAP
tGHEL
tOEH
tWS
tWH
VIH
VIL
WE#
tDH
tDS
VIH
VIL
DATA
RY/BY#
BYTE#
FFH
41H
DIN
DIN
DIN
SRD
DOUT
tEHRL
tBH
VOH
VOL
tBS
VIH
VIL
tPS
RP#
VIH
VIL
VIH
tBLH
tBLS
WP1#
WP2#
VIL
13
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
PROGRAM
ARRAY COMMAND
VIH
VIL
ADDRESS
VALID
BANK(I) ADDRESS VALID
ta(CE)
ADDR
CE#
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCS
tCH
ta(OE)
tWP
tWPH
OE#
tOEH
WE#
tDS
40H
DIN
SRD
FFH
DATA
RY/BY#
BYTE#
RST#
tDH
tWHRL
tBS
tBH
tPS
tDAP
tBLS
tBLH
WP1#
WP2#
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (CE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
PROGRAM
ARRAY COMMAND
VIH
VIL
ADDRESS
VALID
ADDR
CE#
BANK(I) ADDRESS VALID
ta(CE)
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ta(OE)
tCEP
tWH
OE#
tOEH
tWS
WE#
tDS
40H
DIN
SRD
FFH
DATA
RY/BY#
BYTE#
RP#
tDH
tEHRL
tBS
tBH
tPS
tDAP
tBLS
tBLH
WP1#
WP2#
14
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
ERASE
VIH
VIL
ADDRESSES
BANK ADDRESS VALID
ADDRESS VALID
tAS
tWC
tAH
ta(CE)
VIH
VIL
CE#
OE#
tCS
tCH
ta(OE)
VIH
VIL
tOEH
tDAE
tWPH
VIH
VIL
WE#
tDH
tWP
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tWHRL
VOH
VOL
RY/BY#
tBS
tBH
VIH
VIL
BYTE#
RP#
tPS
VIH
tBLH
tBLS
VIL
VIH
VIL
WP1#
WP2#
AC WAVEFORMS FOR ERASE OPERATIONS (CE# control)
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
ERASE
VIH
ADDRESSES
ADDRESS VALID
tAS
BANK ADDRESS VALID
VIL
tWC
tAH
ta(CE)
VIH
VIL
CE#
OE#
tCEPH
tCEP
ta(OE)
VIH
VIL
tOEH
tDAE
tWS
tWH
VIH
VIL
WE#
tDH
tDS
VIH
VIL
SRD
FFH
20H
D0H
DATA
tEHRL
VOH
VOL
RY/BY#
tBS
tBH
VIH
VIL
BYTE#
RP#
tPS
VIH
tBLH
tBLS
VIL
VIH
VIL
WP1#
WP2#
15
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM THE OTHER BANK
PROGRAM DATA TO ONE BANK
ADDRESS VALID
WITH BGO
VALID
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VALID
VALID
A18-7
BYTE#=VIL
(A6~A-1)
FFH
00H
00H
01H~FEH
01H~7EH
7FH
VALID
BYTE#=VIH
(A6 ~A0)
tWC
tAS
ta(CE)
tAH
CE#
tCS
tCH
ta(OE)
OE#
tOEH
tWP
tWPH
WE#
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
DATA
RY/BY#
tWHRL
tDH
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
ARRAY READ FROM THE OTHER BANK
WITH BGO
VIH
ADDRESS VALID
FFH
VALID
VALID
A18-7
VIL
VIH
VIL
BYTE#=VIL
(A6~A-1)
00H
00H
01H~FEH
01H~7EH
7FH
VALID
VALID
BYTE#=VIH
(A6 ~A0)
tWC
tAS
tCEPH
ta(CE)
ta(OE)
tAH
VIH
CE#
OE#
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
DATA
RY/BY#
tEHRL
tDH
16
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADDRESS VALID
VALID
VALID
VALID
A18-7
BYTE#=VIL
(A-1~A6)
VALID
VALID
BYTE#=VIH
(A0 ~A6)
tAH
tWC
tAS
ta(CE)
ta(OE)
CE#
tCS
tCH
OE#
tOEH
tWP
tWPH
WE#
tDS
40H
DIN
SRD
DOUT
DOUT
DATA
RY/BY#
tDH
tWHRL
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (CE# control)
Change Bank Address
PROGRAM DATA TO READ STATUS
ARRAY READ FROM BANK(II) WITH BGO
BANK(I)
REGISTER
VIH
VIL
VIH
VIL
ADDRESS VALID
VALID
VALID
VALID
A18-7
BYTE#=VIL
(A-1~A6)
VALID
tAS
VALID
BYTE#=VIH
(A0 ~A6)
tWC
ta(CE)
ta(OE)
VIH
CE#
OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
40H
DIN
SRD
DOUT
DOUT
DATA
RY/BY#
tDH
tEHRL
17
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address
READ STATUS
REGISTER
ARRAY READ FROM THE OTHER
BLOCK ERASE IN
ONE BANK
BANK WITH BGO
VALID
VIH
VIL
ADDRESS VALID
tAH
VALID
ADDRESSES
tWC
tAS
tCH
ta(CE)
ta(OE)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
CE#
tCS
OE#
tOEH
tWP
tWPH
WE#
tDS
20H
D0H
SRD
DOUT
DOUT
DATA
RY/BY#
tDH
tWHRL
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (CE# control)
Change Bank Address
READ DATA FROM THE OTHER BANK
WITH BGO
BLOCK ERASE IN
ONE BANK
READ STATUS
REGISTER
VIH
VIL
ADDRESSES
ADDRESS VALID
VALID
VALID
tWC
tAS
tAH
ta(CE)
ta(OE)
VIH
CE#
OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
SRD
20H
D0H
DOUT
DOUT
DATA
RY/BY#
tDH
tEHRL
18
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FULL STATUS CHECK PROCEDURE
LOCK BIT PROGRAM FLOW CHART
STATUS REGISTER
READ
START
WRITE 77H
SR.4 =1
and
COMMAND SEQUENCE ERROR
BLOCK ERASE ERROR
SR.5 =1
?
YES
NO
NO
NO
WRITE D0H
BLOCK ADDRESS
NO
SR.5 = 0 ?
YES
SR.7 = 1 ?
NO
YES
PROGRAM ERROR
(PAGE, LOCK BIT)
SR.4 = 0 ?
YES
LOCK BIT PROGRAM
SR.4 = 0 ?
YES
FAILED
NO
PROGRAM ERROR
(BLOCK)
LOCK BIT PROGRAM
SUCCESSFUL
SR.3 = 0 ?
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
BYTE PROGRAM FLOW CHART
PAGE PROGRAM FLOW CHART
START
START
WRITE 40H
WRITE 41H
n = 0
WRITE
ADDRESS , DATA
n = n+1
WRITE
ADDRESS n, DATA n
STATUS REGISTER
READ
n = FFH ?
or
n = 7FH ?
NO
NO
NO
SR.7 = 1 ?
WRITE B0H ?
YES
YES
YES
STATUS REGISTER
READ
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
NO
NO
SR.7 = 1 ?
YES
WRITE B0H ?
YES
PAGE PROGRAM
COMPLETED
YES
* Byte program is admitted to only BANK(I).
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
YES
June 1998 , Rev.3.1
19
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SUSPEND / RESUME FLOW CHART
CLEAR PAGE BUFFER
START
START
WRITE B0H
SUSPEND
WRITE 55H
STATUS REGISTER
READ
WRITE D0H
SR.7 = 1?
YES
NO
NO
PAGE BUFFER CLEAR
COMPLETED
PROGRAM / ERASE
COMPLETED
SR.6 =1?
SINGLE DATA LOAD TO PAGE BUFFER
YES
WRITE FFH
START
WRITE 74H
READ ARRAY DATA
WRITE
ADDRESS , DATA
DONE
READING ?
NO
YES
NO
DONE
LOADING?
RESUME
WRITE D0H
OPERATION
RESUMED
YES
SINGLE DATA LOAD
TO PAGE BUFFER
COMPLETED
* The bank address is required when writing this command. Also, there is
no need to suspend the erase or program operation when reading data
from the other bank.
BLOCK ERASE FLOW CHART
PAGE BUFFER TO FLASH
START
START
WRITE 20H
WRITE 0EH
WRITE D0H
BLOCK ADDRESS
WRITE D0H
PAGE ADDRESS
STATUS REGISTER
READ
STATUS REGISTER
READ
NO
NO
WRITE B0H ?
NO
NO
SR.7 = 1 ?
WRITE B0H ?
SR.7 = 1 ?
YES
YES
YES
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
BLOCK ERASE
COMPLETED
PAGE BUFFER TO FLASH
COMPLETED
YES
YES
20
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
OPERATION STATUS and EFFECTIVE COMMAND
21
June 1998 , Rev.3.1
MITSUBISHI LSIs
M5M29GB/T800AVP,RV
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
PACKAGE DIMENSIONS
48P3E (48pin 12 x 20 mm TSOP(I))
48P3E-B
Plastic 48pin 12x20mm TSOP(I)
EIAJ Package Code
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
MD
TSOP I 48-P-1220-0.50
D
H
D
l
2
Recommended Mount Pad
1
48
Dimension in Millimeters
Symbol
A
Min
Nom
Max
1.2
0.125
1.0
0.2
A
A
0.05
1
2
y
0.15
0.105
18.3
0.2
0.3
0.175
18.5
12.1
b
G
0.125
18.4
12.0
0.5
c
D
E
11.9
24
25
e
19.8
0.4
20.0
0.5
20.2
0.6
HD
L
0.8
0.6
L
1
0.75
Lp
A3
z
0.45
F
L1
0.25
0.25
0.4
Z
x
y
1
0.1
0.1
10°
q
0°
L
0.225
18.6
b
2
Lp
Detail G
0.9
l 2
MD
Detail F
48P3E-C
EIAJ Package Code
TSOP I 48-P-1220-0.50
Plastic 48pin 12x20mm TSOP(I)
MD
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
D
H
D
l
2
Recommended Mount Pad
1
48
Dimension in Millimeters
Symbol
A
Min
Nom
Max
1.2
0.125
1.0
0.2
A
A
0.05
1
2
y
0.15
0.105
18.3
0.2
0.3
0.175
18.5
12.1
b
G
0.125
18.4
12.0
0.5
c
D
E
11.9
24
25
e
19.8
0.4
20.0
0.5
20.2
0.6
HD
L
0.8
0.6
L
1
0.75
Lp
A3
z
0.45
F
L1
0.25
0.25
0.4
Z
x
y
q
1
0.1
0.1
10°
0°
L
0.225
18.6
b
2
Lp
Detail G
0.9
l 2
MD
Detail F
June 1998 , Rev.3.1
22
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