M5M467405DTP-5S [MITSUBISHI]
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM; EDO模式67108864位（ 16777216 - WORD 4位）动态RAM
| 型号： | M5M467405DTP-5S |
| 厂家： | 
Mitsubishi Group |
| 描述： | EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| 文件： | 总39页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Some of contents are subject to change without notice.
PRELIMINARY
DESCRIPTION
The M5M467405/465405DJ,DTP is a 16777216-word by 4-bit, M5M467805/465805DJ,DTP is a 8388608-word by 8-bit, and
M5M465165DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are
suitable for large-capacity memory systems with high speed and low power dissipation.
FEATURES
Address
access access access
time time time
Power
dissipa-
tion
RAS
OE
Power
dissipa-
tion
CAS
Cycle
time
Address
access
time
RAS
access access
time time
CAS
OE
Cycle
time
access
time
access
time
Type name
Type name
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
(max.ns) (max.ns) (max.ns) (max.ns)
(min.ns)
(typ.mW)
M5M467405DXX-5,5S
M5M467805DXX-5,5S
50
60
M5M465165DXX-5,5S
M5M465165DXX-6,6S
13
15
420
13
15
84
25
30
50
60
50
60
13
15
13
15
25
30
25
30
13
15
13
15
300
250
390
325
84
104
84
M5M467405DXX-6,6S
M5M467805DXX-6,6S
390
104
M5M465405DXX-5,5S
M5M465805DXX-5,5S
M5M465405DXX-6,6S
M5M465805DXX-6,6S
104
XX=J,TP
(M5M467405Dxx/M5M465405Dxx/M5M467805Dxx/M5M465805Dxx)
(M5M465165Dxx)
Standard 32 pin SOJ, 32 pin TSOP
Standard 50 pin SOJ, 50 pin TSOP
±
Single 3.3 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467405Dxx-5,5S / M5M467805Dxx-5,5S
M5M467405Dxx-6,6S / M5M467805Dxx-6,6S
M5M465405Dxx-5,5S / M5M465805Dxx-5,5S
M5M465405Dxx-6,6S / M5M465805Dxx-6,6S
M5M465165Dxx-5,5S
360.0mW (Max)
324.0mW (Max)
468.0mW (Max)
432.0mW (Max)
504.0mW (Max)
468.0mW (Max)
M5M465165Dxx-6,6S
Self refresh capability*
Self refresh current
400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
:Applicable to self refresh version(M5M467405/465405/467805/465805/465165DJ,DTP-5S,-6S:option) only
*
ADDRESS
Refresh Cycle
Normal S-version
8192/64ms 8192/128ms
Row Add. Col. Add.
A0-A12 A0-A10
Refresh
Part No.
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M467405Dxx
4096/64ms
4096/64ms
4096/128ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M465405Dxx A0-A11 A0-A11
8192/64ms 8192/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
A0-A12 A0-A9
M5M467805Dxx
4096/64ms
4096/64ms
4096/128ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
A0-A10
A0-A9
M5M465805Dxx A0-A11
M5M465165Dxx A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/128ms
4096/64ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467405Dxx / M5M465405Dxx
M5M467805Dxx / M5M465805Dxx
Pin Name Function
Pin Name Function
A0-A12
A0-A12
Address Inputs
Address Inputs
DQ1-DQ4 Data Inputs / Outputs
DQ1-DQ8 Data Inputs / Outputs
RAS
CAS
W
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
RAS
CAS
W
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
OE
OE
Vcc
Vss
NC
Vcc
Vss
NC
No Connection
No Connection
M5M465165Dxx
Pin Name Function
A0-A11
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
Row Address Strobe Input
RAS
Upper byte control
UCAS
LCAS
Column Address Strobe Input
Lower byte control
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Ground (0V)
W
OE
Vcc
Vss
NC
XX=J, TP
No Connection
M5M467400/465400DJ, DTP
PIN CONFIGURATION (TOP VIEW)
1
2
32
31
30
29
28
32
31
30
29
28
1
Vcc
DQ1
DQ2
NC
Vcc
DQ1
DQ2
NC
Vss
DQ4
DQ3
NC
Vss
DQ4
DQ3
NC
2
3
3
4
4
NC
NC
NC
W
5
NC
NC
NC
W
5
NC
NC
6
27 NC
26
6
27 NC
26
7
7
CAS
CAS
8
25
24
23
22
8
25
24
23
22
OE
OE
9
9
RAS
A0
A12/NC(Note)
A11
A10
RAS
A0
A12/NC(Note)
A11
A10
10
11
10
11
A1
A1
A2 12
21 A9
A2 12
21 A9
13
20
13
20
A3
A8
A3
A8
14
19
A4
14
15
16
19
A7
A4
A5
A7
A5
15
16
18
17
A6
18
17
A6
Vcc
Vss
Vcc
Vss
Outline 32P0N (400mil SOJ)
Outline 32P3N (400mil TSOP Normal Bend)
:
:
A12...M5M467405Dxx, NC...M5M465405Dxx
NO CONNECTION
Note
NC
2
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467805/465805DJ, DTP PIN CONFIGURATION (TOP VIEW)
32
31
30
29
28
27
26
25
24
23
22
1
2
Vcc
DQ1
DQ2
Vss
32
31
30
29
28
27
26
25
24
23
22
1
2
Vcc
DQ1
DQ2
DQ3
DQ4
NC
Vss
DQ8
DQ7
DQ6
DQ5
Vss
DQ8
DQ7
DQ6
DQ5
3
3
4
DQ3
DQ4
NC
4
5
5
6
6
Vss
Vcc
7
CAS
Vcc
7
CAS
8
W
RAS
A0
8
OE
W
RAS
A0
OE
9
A12/NC(Note)
A11
A10
9
A12/NC(Note)
A11
A10
10
11
10
11
A1
A1
A2 12
21 A9
A2 12
21 A9
13
20
A3
A8
13
20
A3
A8
14
19
A4
A7
14
19
A4
A7
A5
15
18
A6
A5
15
18
A6
16
17
Vcc
Vss
16
17
Vcc
Vss
Outline 32P0N (400mil SOJ)
Outline 32P3N (400mil TSOP Normal Bend)
:
:
Note
NC
A12...M5M467800Dxx, NC...M5M465800Dxx
NO CONNECTION
PIN CONFIGURATION (TOP VIEW)
M5M465165DJ, DTP
1
50
49
48
1
50
49
48
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
Vss
Vss
DQ1
DQ2
DQ3
DQ4
Vcc
2
3
4
5
6
7
8
9
DQ16
DQ15
2
3
4
5
6
7
8
9
DQ16
DQ15
47 DQ14
47 DQ14
46
46
DQ13
DQ13
45 Vss
45 Vss
Vcc
DQ5
DQ5
44 DQ12
44 DQ12
43
43
DQ6
DQ7
DQ8
NC
DQ11
DQ6
DQ7
DQ8
NC
DQ11
42
42
DQ10
DQ10
41
41
10
11
10
11
DQ9
DQ9
40
40
NC
NC
Vcc 12
Vss
Vcc 12
Vss
39
39
13
13
38 LCAS
38 LCAS
W
W
14
14
37
37
RAS
RAS
UCAS
UCAS
NC
36
NC
36
15
15
OE
OE
16
35
16
35
NC
NC
NC
NC
17
34
17
34
NC
NC
NC
NC
18
33
18
33
NC
NC
NC
NC
19
19
32
32
A0
A0
A11
A11
20
20
31
31
A1
A1
A10
A10
21
21
30
30
A2
A9
A2
A9
22
22
A3
29
28
27
26
A3
29
28
27
26
A8
A7
A8
A7
A6
23
24
25
23
24
25
A4
A5
A4
A5
A6
Vcc
Vcc
Vss
Vss
Outline 50P3G (400mil TSOP Normal Bend)
Outline 50P0G (400mil SOJ)
NC : NO CONNECTION
3
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467405(805)/465405(805,165)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467405Dxx / M5M465405Dxx / M5M467805Dxx / M5M465805Dxx
Inputs
Input/Output
Refresh
Operation
Remark
Column
address
Row
Input
Output
VLD
RAS
ACT
CAS
ACT
W
OE
address
Read
NAC
ACT
APD
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
OPN
VLD
VLD
VLD
NO
NO
EDO mode
identical
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
NAC
ACT
ACT
DNC
ACT
ACT
ACT
Write (Early write)
Write (Delayed write)
Read-modify-write
DNC
DNC
ACT
DNC
ACT
DNC
DNC
OPN
IVD
NO
VLD
NO
DNC
NAC
NAC
DNC
DNC
DNC
DNC
DNC
OPN
OPN
DNC
DNC
OPN
VLD
OPN
OPN
YES
YES
YES
NO
RAS-only refresh
Hidden refresh
CAS before RAS refresh
Standby
M5M465165Dxx
Operation
Inputs
Input/Output
DQ1~DQ8 DQ9~DQ16
Refresh
NO
Remark
Column
address
Row
UCAS
NAC
W
RAS
ACT
LCAS
ACT
OE
address
VLD
Lower byte read
NAC
ACT
APD
APD
OPN
VLD
VLD
DNC
Upper byte read
Word read
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
NAC
NAC
NAC
ACT
ACT
ACT
NAC
APD
APD
APD
APD
APD
APD
OPN
VLD
DIN
NO
NO
NO
EDO mode
identical
Lower byte write
Upper byte write
ACT
NAC
ACT
ACT
NAC
APD
APD
APD
DNC
DNC
DNC
APD
DNC
DIN
NO
Word write
ACT
ACT
ACT
ACT
NAC
ACT
ACT
NAC
ACT
ACT
DNC
NAC
NAC
DNC
ACT
APD
DNC
DNC
DIN
OPN
VLD
OPN
OPN
DIN
OPN
VLD
OPN
OPN
NO
YES
YES
RAS-only refresh
Hidden refresh
ACT
NAC
ACT
DNC
ACT
DNC
DNC
DNC
DNC
DNC
DNC
DNC
YES
NO
CAS before RAS refresh
Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Dxx / M5M465405Dxx
BLOCK DIAGRAM
Vcc (3.3V)
Vss (0V)
COLUMN ADDRESS
STROBE INPUT
CAS
CLOCK GENERATOR
CIRCUIT
ROW ADDRESS
RAS
STROBE INPUT
WRITE CONTROL
W
INPUT
A0~A11
(Note)
A0
A1
A2
A3
A4
A5
COLUMN DECODER
DQ1
SENSE REFRESH
AMPLIFIER & I /O CONTROL
DQ2
DQ3
DQ4
DATA
INPUTS / OUTPUTS
ADDRESS INPUTS
A6
A7
A8
A9
MEMORY CELL
(67108864 BITS)
A0~
A12
(Note)
A10
A11
OUTPUT ENABLE
INPUT
OE
A12
(Note)
Note Refer to Page 1 (ADDRESS)
:
M5M467805Dxx / M5M465805Dxx
BLOCK DIAGRAM
Vcc (3.3V)
Vss (0V)
COLUMN ADDRESS
STROBE INPUT
CAS
CLOCK GENERATOR
CIRCUIT
ROW ADDRESS
RAS
STROBE INPUT
WRITE CONTROL
W
INPUT
A0~A10
(Note)
A0
A1
A2
A3
A4
A5
COLUMN DECODER
DQ1
DQ2
DQ3
DQ4
SENSE REFRESH
AMPLIFIER & I /O CONTROL
DATA
INPUTS / OUTPUTS
DQ5
DQ6
DQ7
DQ8
ADDRESS INPUTS
A6
A7
MEMORY CELL
(67108864 BITS)
A0~
A12
A8
A9
(Note)
A10
A11
OUTPUT ENABLE
INPUT
OE
A12
(Note)
Note
Refer to Page 1 (ADDRESS)
:
5
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M465165Dxx
BLOCK DIAGRAM
ROW ADDRESS
STROBE INPUT
VCC (3.3V)
RAS
CLOCK GENERATOR
CIRCUIT
LOWER BYTE CONTROL
COLUMN ADDRESS
STROBE INPUT
UPPER BYTE CONTROL
COLUMN ADDRESS
STROBE INPUT
VSS (0V)
LCAS
LOWER
UPPER
DQ1
UCAS
W
DQ2
DQ8
LOWER DATA
INPUTS / OUTPUTS
WRITE CONTROL INPUT
A0~A9
COLUMN DECODER
A0
A1
A2
A3
DQ9
SENSE REFRESH
AMPLIFIER & I /O
CONTROL
DQ10
A4
A5
A6
UPPER DATA
INPUTS / OUTPUTS
ADDRESS INPUTS
DQ16
A7
A8
MEMORY CELL
(67108864BITS)
A0 ~
A11
A9
A10
A11
OUTPUT ENABLE
INPUT
OE
6
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
Parameter
Conditions
Ratings
Unit
V
~
Supply voltage
Input voltage
-0.5 4.6
~
With respect to Vss
V
-0.5 4.6
~
50
Output voltage
Output current
Power dissipation
V0
-0.5 4.6
V
mA
mW
C
I0
Ta=25
1000
Pd
C
~
Operating temperature
Storage temperature
0
70
Topr
Tstg
~
-65 150
C
C
(Ta=0 70 , unless otherwise noted) (Note 1)
~
RECOMMENDED OPERATING CONDITIONS
Limits
Unit
Symbol
Parameter
Min
3.0
0
Nom
3.3
0
Max
3.6
Supply voltage
Supply voltage
Vcc
Vss
VIH
V
V
V
V
0
High-level input voltage, all inputs
Low-level input voltage, all inputs
2.0
-0.3
Vcc+0.3
0.8
VIL
Note 1 : All voltage values are with respect to Vss.
±
~
C
(Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
[M5M467405D / M5M467805D]
Limits
Symbol
Parameter
Unit
Test conditions
Min
2.4
0
Max
Vcc
0.4
10
Typ
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
IOH=-2mA
V
IOL=2mA
V
Q floating 0V £ VOUT £ Vcc
0V£VIN £ Vcc+0.3V, Other input pins=0V
-10
-10
µA
µA
10
M5M467405D-5,5S
M5M467805D-5,5S
M5M467405D-6,6S
M5M467805D-6,6S
Average supply current
from Vcc
100
90
RAS, CAS cycling
tRC=tWC=min.
output open
ICC1 (AV)
mA
mA
operating
(Note 3,4,5)
M5M467405D-5,5S
-6,6S
M5M467805D-5,5S
RAS= CAS =VIH, output open
1
Average supply current
from Vcc
-6,6S
ICC2 (AV)
M5M467405D-5,6
M5M467805D-5,6
0.5
0.3
(Note 6)
stand-by
RAS= CAS ³ Vcc -0.2V,output open
M5M467405D-5S,6S
M5M467805D-5S,6S
M5M467405D-5,5S
M5M467805D-5,5S
M5M467405D-6,6S
M5M467805D-6,6S
Average supply current
from Vcc
100
90
RAS=VIL, CAS cycling
tHPC=min.
output open
ICC4 (AV)
ICC6 (AV)
mA
mA
EDO-Mode
(Note 3,4,5)
M5M467405D-5,5S
M5M467805D-5,5S
Average supply current
from Vcc
CAS before RAS refresh
130
120
CAS before RAS refresh cycling
tRC=min.
output open
M5M467405D-6,6S
M5M467805D-6,6S
(Note 3,5)
mode
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
7
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
±
C
(Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
[M5M465405D / M5M465805D]
~
Limits
Symbol
Parameter
Unit
Test conditions
Min
2.4
0
Max
Vcc
0.4
10
Typ
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
IOH=-2mA
V
IOL=2mA
V
Q floating 0V £ VOUT £ Vcc
0V£VIN £ Vcc+0.3V, Other input pins=0V
-10
-10
µA
µA
10
M5M465405D-5,5S
M5M465805D-5,5S
M5M465405D-6,6S
M5M465805D-6,6S
Average supply current
from Vcc
130
120
RAS, CAS cycling
tRC=tWC=min.
output open
ICC1 (AV)
mA
mA
operating
(Note 3,4,5)
M5M465405D-5,5S
-6,6S
M5M465805D-5,5S
RAS= CAS =VIH, output open
1
Average supply current
from Vcc
-6,6S
ICC2 (AV)
M5M465405D-5,6
M5M465805D-5,6
0.5
0.3
(Note 6)
stand-by
RAS= CAS ³ Vcc -0.2V,output open
M5M465405D-5S,6S
M5M465805D-5S,6S
M5M465405D-5,5S
M5M465805D-5,5S
Average supply current
from Vcc
100
90
RAS=VIL, CAS cycling
tHPC=min.
output open
ICC4 (AV)
ICC6 (AV)
mA
mA
M5M465405D-6,6S
M5M465805D-6,6S
EDO-Mode
(Note 3,4,5)
M5M465405D-5,5S
M5M465805D-5,5S
Average supply current
from Vcc
CAS before RAS refresh
130
120
CAS before RAS refresh cycling
tRC=min.
output open
M5M465405D-6,6S
M5M465805D-6,6S
(Note 3,5)
mode
[M5M465165D]
Limits
Typ
Symbol
Parameter
Test conditions
Unit
V
Min
2.4
0
Max
Vcc
0.4
10
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
IOH=-2mA
IOL=2mA
V
µA
-10
-10
Q floating 0V£ VOUT £ Vcc
0V
VIN
Vcc+0.3V, Other input pins=0V
£
£
10
µA
Average supply current
from Vcc
M5M465165D-5,5S
RAS, CAS cycling
tRC=tWC=min.
output open
140
130
1
ICC1 (AV)
mA
(Note 3,4,5) M5M465165D-6,6S
operating
M5M465165D-5,5S
-6,6S
M5M465165D-5,6
RAS= CAS =VIH, output open
Average supply current
from Vcc
ICC2 (AV)
mA
0.5
0.3
(Note 6)
RAS= CAS ³ Vcc -0.2V, output open
stand-by
M5M465165D-5S,6S
M5M465165D-5,5S
Average supply current
from Vcc
RAS=VIL, CAS cycling
tHPC=min.
120
110
ICC4 (AV)
ICC6 (AV)
mA
mA
M5M465165D-6,6S output open
(Note 3,4,5)
EDO-Mode
Average supply current
from Vcc
CAS before RAS refresh
M5M465165D-5,5S
140
130
CAS before RAS refresh cycling
tRC=min.
output open
M5M465165D-6,6S
(Note 3,5)
mode
Aug. 1999
8
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
±
(Ta=0 70 C, Vcc=3.3 0.3V, Vss=0V, unless otherwise noted)
CAPACITANCE
~
Limits
Typ
Symbol
Parameter
Unit
Test conditions
Min
Max
5
pF
pF
Input capacitance,address inputs
Input capacitance, OE input
CI (A)
7
7
7
7
7
CI (OE)
CI (W)
VI=Vss
f=1MHZ
Input capacitance, write control input
Input capacitance, RAS input
pF
pF
pF
pF
CI (RAS)
CI (CAS)
CI / O
Vi=25mVrms
Input capacitance, CAS input
Input/Output capacitance, data ports
(Ta=0 70 , Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
~
C
SWITCHING CHARACTERISTICS
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
Max
13
Min
Max
15
tCAC
tRAC
tAA
Access time from CAS
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
ns
ns
ns
ns
ns
Access time from RAS
50
60
25
30
Column address access time
Access time from CAS precharge
Access time from OE
tCPA
28
33
tOEA
tOHC
tOHR
tCLZ
tOEZ
13
15
5
5
5
5
5
5
ns
ns
Output hold time from CAS
(Note 13)
(Note 7)
Output hold time from RAS
ns
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after W high
Output disable time after CAS high
Output disable time after RAS high
ns
ns
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
13
13
13
13
15
15
15
15
tWEZ
tOFF
tREZ
ns
ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that tRCD
tRCD(max) and tASC tASC(max) and tCP
tCP(max).
³
³
³
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
£
£
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD
tRAD(max) and tASC tASC(max).
£
³
£
11: Assumes that tCP tCP(max) and tASC tASC(max).
³
±
µ
10 A) and is
12: tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT
£
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
Aug. 1999
9
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
~
±
(Ta=0 70 C, Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 14,15)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
Max
64
Min
Max
64
Refresh cycle time
tREF
ms
ms
ns
ns
ns
ns
ns
ns
Refresh cycle time (S-version only)
RAS high pulse width
128
128
tREF
tRP
30
14
5
40
14
5
tRCD
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
37
45
(Note16)
tCRP
tRPC
tCPN
0
8
0
10
12
Column address delay time from RAS low
(Note17)
(Note18)
25
10
tRAD
tASR
tASC
10
0
30
13
Row address setup time before RAS low
Column address setup time before CAS low
ns
ns
0
0
0
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
ns
ns
ns
tRAH
tCAH
tDZC
8
10
10
0
8
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
0
ns
ns
tDZO
tRDD
tCDD
tODD
tWED
tT
Delay time, data to OE low
0
0
Delay time, RAS high to data
13
13
13
13
1
15
15
15
Delay time, CAS high to data
ns
ns
Delay time, OE high to data
Delay time, W low to data
Transition time
ns
ns
(Note20)
(Note21)
15
1
50
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.
³
³
17: tRAD(max) is specified as a reference point only. If tRAD
18: tASC(max) is specified as a reference point only. If tRCD
19: Either tDZC or tDZO must be satisfied.
tRAD(max) and tASC
tRCD(max) and tASC
tASC(max), access time is controlled exclusively by tAA.
tASC(max), access time is controlled exclusively by tCAC.
£
³
20: Either tRDD or tCDD or tODD or tWED must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
84
50
8
Min
104
60
10
40
15
0
Max
Max
Read cycle time
tRC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
RAS low pulse width
10000
10000
10000
10000
CAS low pulse width
35
13
0
tCSH
tRSH
tRCS
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
tRCH
tRRH
(Note 22)
(Note 22)
0
0
0
0
tRAL
tCAL
25
13
13
30
18
15
Column address to RAS hold time
Column address to CAS hold time
tORH
tOCH
RAS hold time after OE low
CAS hold time after OE low
13
15
ns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Aug. 1999
10
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
84
50
8
Max
Min
104
60
10
40
15
0
Max
Write cycle time
tWC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
RAS low pulse width
10000
10000
10000
10000
CAS low pulse width
tCSH
tRSH
tWCS
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
RAS hold time after W low
Write pulse width
35
13
0
(Note 24)
tWCH
tCWL
tRWL
tWP
8
10
10
10
10
0
8
8
8
tDS
tDH
Data setup time before CAS low or W low
Data hold time after CAS low or W low
0
8
10
Read-Write and Read-Modify-Write Cycles
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
109
75
38
70
38
0
Max
Min
133
89
44
82
44
0
Max
Read write/read modify write cycle time
RAS low pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAS
tCAS
(Note23)
10000
10000
10000
10000
CAS low pulse width
tCSH
tRSH
tRCS
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
OE hold time after W low
28
65
40
13
32
77
47
15
tCWD
tRWD
tAWD
tOEH
(Note24)
(Note24)
(Note24)
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
³
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD ³ tAWD(min) and tCPWD ³ tCPWD(min)
³
³
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi-
nate.
Aug. 1999
11
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle,
Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
20
55
5
Max
Min
25
66
5
Max
tHPC
EDO mode read/write cycle time
ns
ns
EDO Mode read write / read modify write cycle time
tHPRWC
tDOH
tRAS
tCP
Output hold time from CAS low
ns
ns
ns
ns
ns
ns
ns
(Note26)
100000
13
RAS low pulse width for read write cycle
CAS high pulse width
65
8
77
10
33
50
7
100000
16
(Note27)
tCPRH
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
28
43
7
(Note24)
tCPWD
tCHOL
Hold time to maintain the data Hi-Z until CAS access
OE Pulse Width (Hi-Z control)
tOEPE
tWPE
7
7
ns
ns
ns
ns
ns
ns
ns
W Pulse Width (Hi-Z control)
7
7
tHCWD
28
32
47
50
15
30
33
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
tHAWD
tHPWD
40
43
13
25
28
tHCOD
tHAOD
tHPOD
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
26: tRAS(min) is specified as two cycles of CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP tCP(max) , access time is controlled exclusively by tCAC.
³
CAS before RAS Refresh Cycle (Note 28)
Limits
M5M46X405D-5,5S M5M46X405D-6,6S
M5M46X805D-5,5S M5M46X805D-6,6S
M5M465165D-5,5S M5M465165D-6,6S
Symbol
Parameter
Unit
Min
5
Max
Min
5
Max
tCSR
CAS setup time before RAS low
CAS hold time after RAS low
Read setup time before RAS low
Read hold time after RAS low
ns
ns
ns
ns
tCHR
tRSR
tRHR
10
10
10
10
10
10
Note 28: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Aug. 1999
12
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics
and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70 C, Vcc=3.3V ± 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Limits
Symbol
Parameter
Test conditions
Unit
µA
Typ
Min
Max
CAS before RAS refresh cycling
Average supply current
from Vcc
Extended - Refresh cycle
(note 5,6)
M5M46X405D-5S,6S
M5M46X805D-5S,6S
M5M465165D-5S,6S
input high level ³ Vcc-0.2V
ICC8 (AV)
500
£
input low level
0.2V
output = OPEN , tRC = 31.25µs
tRAS = tRAS(min)
~ 300ns
Average supply current
from Vcc
Self - Refresh cycle
(note 6)
M5M46X405D-5S,6S
M5M46X805D-5S,6S
M5M465165D-5S,6S
RAS = CAS
0.2V
£
ICC9 (AV)
µA
400
output = OPEN
~
(Ta=0 70 C , Vcc=3.3V ±0.3V, Vss=0V, unless otherwise noted See notes 14,15)
TIMING REQUIREMENTS
Limits
M5M46X405D-6S
M5M46X805D-6S
M5M465165D-6S
M5M46X405D-5S
M5M46X805D-5S
M5M465165D-5S
Symbol
Parameter
Unit
Max
Min
100
84
Max
Min
100
104
µS
ns
ns
tRASS
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
tRPS
tCHS
Self Refresh CAS hold time
- 50
- 50
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS £ 128 ms and tSN £ 128 ms.
tSN
tNS
Self refresh period
DISTRIBUTED REFRESH
< 128 ms >
DISTRIBUTED REFRESH
< 128 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
£
on the condition of tNS £ 16 ms and tSN 16 ms.
tSN
tNS
Self refresh period
BURST REFRESH
< 128 ms >
BURST REFRESH
< 128 ms >
13
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams (Note 29)
Read Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCPN
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
CAS
LCAS / UCAS
tRAL
tCAL
(at M5M465165Dxx only)
tRAD
tASR
tASR
tRAH
tASC
tCAH
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tRRH
tRCH
tRCS
VIH
VIL
W
tDZC
tCDD
tRDD
VIH
VIL
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
tWEZ
tREZ
tCAC
tAA
tCLZ
tOFF
tOHC
tOHR
VOH
VOL
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
Hi-Z
DATA VALID
tRAC
tOEZ
tODD
tOEA
tDZO
tOCH
VIH
VIL
tORH
OE
Indicates the don't care input.
Note 29:
£
£
£
VIH(min) £ VIN VIH(max) or VIL(min) VIN VIL(max)
Indicates the invalid output.
Indicates the skew of the two inputs. (at M5M465165Dxx only)
14
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write)
tWC
tRAS
tCSH
tRP
VIH
RAS
VIL
tRPC tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tASR
tASR
tASC
tRAH
tCAH
VIH
COLUMN
ADDRESS
ROW
ADDRESS
ROW
ADDRESS
Address
VIL
tWCS
tWCH
VIH
VIL
W
tDS
tDH
VIH
VIL
DQ1 ~DQ4 (8,16)
(INPUTS)
DATA VALID
VOH
VOL
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
VIH
VIL
OE
15
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tASC
tASR
tCAH
tRAH
tASR
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tCWL
tWP
tRWL
tRCS
VIH
VIL
W
tWCH
tDS
tDZC
tDH
VIH
VIL
Hi-Z
DATA
VALID
DQ1 ~DQ4 (8,16)
(INPUTS)
tCLZ
VOH
VOL
Hi-Z
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tOEH
tOEZ
tDZO
tODD
VIH
VIL
OE
16
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tRPC tCRP
tCSH
tCRP
tASR
tRCD
tRSH
tCAS
VIH
VIL
CAS
LCAS / UCAS
tRAD
(at M5M465165Dxx only)
tRAH
tASR
tCAH
tASC
VIH
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
Address
VIL
tCWL
tRWL
tWP
tAWD
tCWD
tRWD
tRCS
VIH
VIL
W
tDS
tDH
tDZC
VIH
VIL
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
DATA VALID
tCAC
tAA
tCLZ
VOH
VOL
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
Hi-Z
DATA
VALID
tRAC
tDZO
tODD
tOEZ
tOEH
tOEA
VIH
VIL
OE
17
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tHPC
tCAS
tRPC
tRSH
tCAS
tCRP
tRCD
tCP
tCP
tCAS
tCRP
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tCPRH
tCAH
tASR
tASC
tASC
tASR
tCAH
tCAH
tRAH
tASC
VIH
COLUMN
ADDRESS-1
COLUMN
ADDRESS-3
COLUMN
ADDRESS-2
ROW
ADDRESS
ROW
ADDRESS
Address
VIL
tRCS
tRRH
tRAL
tCAL
tCAL
tCAL
tRCH
VIH
VIL
W
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tCLZ
tDOH
tDOH
tOHC
VOH
VOL
Hi-Z
DATA
VALID-1
DATA
VALID-3
DATA
VALID-2
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tRAC
tDZO
tCPA
tCPA
tOEA
tOCH
tOEZ
VIH
VIL
OE
tODD
18
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Write Cycle (Early Write)
tRAS
tRP
VIH
RAS
VIL
tRSH
tCAS
tRPC
tCSH
tHPC
tCAS
tCRP
tCRP
tRCD
tCAS
tCP
tCP
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Dxx only)
tCAL
tCAH
tCAL
tCAH
tCAL
tCAH
tASR
tASR
tRAH
tASC
tASC
tASC
VIH
Address
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-3
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
VIL
tWCH
tWCH
tWCS
tWCH
tWCS
tWCS
VIH
W
VIL
tDH
tDH
tDS
tDH
tDS
tDS
VIH
DQ1 ~DQ4 (8,16)
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
(INPUTS)
VIL
VOH
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
VOL
VIH
OE
VIL
19
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRP
tRAS
VIH
RAS
tRPC
tRWL
VIL
tCSH
tRCD
tCAS
tHPRWC
tCAS
tCRP
tCRP
tASR
tCP
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tRAH
tCWL
tASC
tASR
tCAH
tCAH
tASC
VIH
COLUMN
ADDRESS-2
ROW
ADDRESS
COLUMN
ADDRESS-1
ROW
ADDRESS
Address
VIL
tAWD
tAWD
tCWL
tWP
tCWD
tRCS
tCWD
tRCS
tWP
VIH
VIL
W
tRWD
Hi-Z
tCPWD
tDZC
tDZC
tDH
tDH
tDS
tDS
VIH
VIL
DQ1 ~DQ4 (8,16)
(INPUTS)
Hi-Z
tCAC
DATA
VALID-1
DATA
VALID-2
tCAC
tAA
tCLZ
tAA
tCLZ
VOH
VOL
DATA
VALID
-2
Hi-Z
Hi-Z
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
DATA
VALID
-1
tRAC
tDZO
tCPA
tDZO
tODD
tOEZ
tODD
tOEA
tOEH
tOEH
tOEZ
tOEA
VIH
VIL
OE
20
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1) (Note 30)
tRAS
tRP
tRWL
VIH
RAS
tRPC
VIL
tCSH
tHPC
tCAS
tHPRWC
tCAS
tCRP
tCRP
tCP
tCP
tRCD
tCAS
tCWL
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tASR
tASR
tASC
tCAH
tASC
tRAH
tCAH
tCAH
tASC
VIH
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
Address
VIL
tCPWD
tAWD
tCWD
tRCS
tWCH
tCAL
tWCS
tCAL
tWP
tDH
VIH
VIL
W
tDZC
tDZC
tDH
tDS
tDS
VIH
VIL
DATA
VALID-3
DATA
DQ1 ~DQ4 (8,16)
(INPUTS)
VALID-2
tCAC
tAA
tAA
tWED
tCAC
tCLZ
tWEZ
tCLZ
VOH
VOL
DATA
VALID
-1
Hi-Z
DATA
VALID
-3
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tRAC
tDZO
tCPA
tOEA
tOEA
tOCH
tOEH
tOEZ
tOEZ
tDZO
VIH
VIL
OE
tODD
tODD
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
21
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2) (Note 30)
VIH
RAS
VIL
tHPC
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tASC
tASC
tCAH
VIH
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
Address
VIL
tRCH
tCAL
tCAL
tWCH
tWCS
VIH
VIL
W
tHCWD
tHAWD
tHPWD
tDH
tDZC
tDS
VIH
VIL
Hi-Z
tCAC
DATA
VALID-2
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
tCAC
tAA
tCPA
tAA
tCPA
tWED
tWEZ
tCLZ
VOH
VOL
Hi-Z
DATA
VALID-1
DATA
VALID-3
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tOEA
tHCOD
tHAOD
tHPOD
tOEZ
tODD
tDZC
VIH
VIL
OE
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
22
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRAS
tRP
VIH
RAS
VIL
tHPC
tCAS
tRPC
tCSH
tRSH
tCAS
tCRP
tCAS
tCP
tCP
tRCD
tCRP
CAS
VIH
VIL
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tRAH
tCPRH
tASC
tASR
tASR
tCAH
tASC
tCAH
tCAH
tASC
VIH
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
Address
VIL
tRRH
tRAL
tRCS
tRCH
VIH
VIL
W
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
Hi-Z
tCAC
DQ1 ~DQ4 (8,16)
(INPUTS)
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tAA
tDOH
tCLZ
Hi-Z
tCLZ
VOH
VOL
DATA
DATA
VALID-1
Hi-Z
DATA
DATA
VALID-3
DQ1 ~DQ4 (8,16)
(OUTPUTS)
VALID
-1
VALID-2
tRAC
tDZO
tOEZ
tCPA
tCPA
tOEZ
tOEA
tCHOL
tOEZ
tOCH
tOEA
VIH
VIL
OE
tODD
tOEPE
tOEPE
23
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS
tRP
VIH
RAS
VIL
tCSH
tRPC
tHPC
tCAS
tRSH
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tCRP
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tCPRH
tCAH
tASR
tASC
tASC
tCAH
tRAH
tCAH
tASR
tASC
VIH
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
Address
VIL
tRRH
tRAL
tRCH
tRCS
tRCH
tRCS
VIH
VIL
W
tWEZ
tWPE
tDZC
tRDD
tCDD
VIH
VIL
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
tCAC
tCLZ
tCAC
tAA
tCAC
tAA
tDOH
tREZ
tOHR
tOFF
tOHC
tAA
tCLZ
tWEZ
VOH
VOL
DATA
VALID-2
Hi-Z
Hi-Z
DATA
VALID-1
DATA
VALID-3
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tRAC
tCPA
tCPA
tOEA
tDZO
tOEZ
tOCH
VIH
VIL
OE
tODD
24
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
tCRP
CAS
VIH
LCAS / UCAS
(at M5M465165Dxx onlyV) IL
tASR
tRAH
tASR
VIH
Address
ROW
ADDRESS
ROW
ADDRESS
VIL
VIH
W
VIL
VIH
DQ1 ~DQ4 (8,16)
(INPUTS)
VIL
VOH
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
VOL
VIH
OE
VIL
25
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tCSR
tCSR
tRPC
tRPC
tRPC
tCHR
tCHR
tCRP
tASR
CAS
VIH
VIL
LCAS / UCAS
(at M5M465165Dxx only)
tCPN
VIH
ROW
COLUMN
Address
ADDRESS ADDRESS
VIL
tRRH
tRCH
tRCS
tRSR
tRSR
tRHR
tRHR
VIH
VIL
W
tCDD
VIH
VIL
DQ1 ~DQ4 (8,16)
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tODD
tOEZ
VIH
VIL
OE
26
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
tCRP
tCHR
tRCD
tRSH
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tRAD
tASR
tASR
tASC
tRAH
tCAH
VIH
ROW
ADDRESS
COLUMN
ROW
ADDRESS
Address
ADDRESS
VIL
tRHR
tRCS
tRRH tRSR
tRAL
VIH
VIL
W
tCDD
tRDD
tDZC
VIH
VIL
Hi-Z
DQ1 ~DQ4 (8,16)
(INPUTS)
tREZ
tOHR
tCAC
tAA
tCLZ
tOFF
tOHC
VOH
VOL
Hi-Z
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
OE
Note 31: Early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
27
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle
tRASS
tRP
tRPS
VIH
RAS
VIL
tRPC
tCHS
tCRP
tCSR
tRPC
VIH
VIL
CAS
LCAS / UCAS
(at M5M465165Dxx only)
tCPN
tASR
VIH
ROW
ADDRESS
Address
VIL
tRRH
tRCH tRSR
tRHR
VIH
VIL
W
tCDD
VIH
VIL
DQ1 ~DQ4 (8,16)
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
Hi-Z
DQ1 ~DQ4 (8,16)
(OUTPUTS)
tOEZ
VIH
VIL
OE
28
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read Cycle
(at M5M465165Dxx only)
tRC
tRP
tRAS
VIH
RAS
VIL
tRPC
tRPC
tCRP
tCSH
tCRP
tRSH
tRCD
VIH
VIL
LCAS
(or UCAS)
tCAS
VIH
VIL
tCPN
UCAS
(or LCAS)
tRAD
tRAL
tCAL
tASR
tASR
tRAH
tASC
tCAH
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
Address
tRRH
tRCS
tRCH
VIH
VIL
W
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDZC
tCDD
tRDD
~
DQ9 DQ16
VIH
VIL
Hi-Z
~
(or DQ1 DQ8)
(INPUTS)
tREZ
tOHR
tCAC
tWEZ
Hi-Z
tAA
tCLZ
tOFF
tOHC
~
VOH
VOL
DQ9 DQ16
Hi-Z
~
(or DQ1 DQ8)
DATA VALID
(OUTPUTS)
tRAC
tOEZ
tODD
tDZO
tOEA
tOCH
VIH
VIL
OE
tORH
29
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Early Write)
(at M5M465165Dxx only)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRPC
tRPC
tCRP
tRCD
tRSH
VIH
VIL
LCAS
(or UCAS)
tCRP
tCAS
VIH
VIL
UCAS
(or LCAS)
tASC
tASR
tASR
tCAH
tRAH
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
ROW
ADDRESS
Address
tWCS
tWCH
VIH
VIL
W
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDS
tDH
VIH
VIL
~
DQ9 DQ16
~
(or DQ1 DQ8)
DATA VALID
(INPUTS)
VOH
VOL
DQ9 ~DQ16
Hi-Z
~
(or DQ1 DQ8)
(OUTPUTS)
VIH
VIL
OE
30
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Delayed Write)
(at M5M465165Dxx only)
tWC
tRP
tRAS
VIH
RAS
VIL
tRPC tCRP
tCSH
tCRP
tRCD
tRSH
VIH
VIL
LCAS
(or UCAS)
tRPC tCRP
tCAS
VIH
VIL
UCAS
(or LCAS)
tASR
tRAH
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
tCWL
tRWL
tWP
tRCS
VIH
VIL
W
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
VOH
DQ1 ~ DQ8
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tWCH
tDZC
tDS
tDH
VIH
VIL
~
DQ9 DQ16
Hi-Z
tCLZ
DATA
VALID
~
(or DQ1 DQ8)
(INPUTS)
VOH
VOL
DQ9 ~DQ16
Hi-Z
Hi-Z
~
(or DQ1 DQ8)
(OUTPUTS)
tOEH
tOEZ
tDZO
tODD
VIH
VIL
OE
31
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read-Write, Upper / (Lower) Byte Read-Modify-Write Cycle.
(at M5M465165Dxx only)
tRWC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
tCSH
tRCD
tRSH
tCRP
VIH
VIL
LCAS
(or UCAS)
tRPC
tCRP
tCAS
VIH
VIL
UCAS
(or LCAS)
tRAD
tASR
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
Address
tAWD
tCWD
tCWL
tRWL
tWP
tRCS
tRWD
VIH
VIL
W
~
DQ1 DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
~
VOH
DQ1 DQ8
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDH
tDS
tDZC
VIH
VIL
DQ9 ~ DQ16
Hi-Z
~
(or DQ1 DQ8)
DATA VALID
(INPUTS)
tCAC
tAA
tCLZ
~
DQ9 DQ16
VOH
Hi-Z
Hi-Z
~
(or DQ1 DQ8)
DATA
VALID
(OUTPUTS)
VOL
tRAC
tODD
tOEH
tOEA
tDZO
tOEZ
VIH
VIL
OE
32
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
(at M5M465165Dxx only)
VIH
tRAS
tRP
RAS
VIL
tCSH
tRSH
tHPC
tCAS
tCRP
tRPC
tCRP
tRCD
tCP
tCP
VIH
VIL
LCAS
(or UCAS)
tRPC
tCRP
tCAS
tCAS
VIH
VIL
UCAS
(or LCAS)
tRAD
tCPRH
tCAH
tASR
tASC
tASC
tASR
tCAH
tCAH
tRAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
COLUMN
ADDRESS-1
Address
tRRH
tRAL
tCAL
tRCS
tCAL
tRCH
tCAL
VIH
VIL
W
tDZC
DQ1 ~DQ8
VIH
Hi-Z
~
(or DQ9 DQ16)
(INPUTS)
VIL
tREZ
tOHR
tCAC
tAA
DQ1~ DQ8
VOH
Hi-Z
DATA
VALID-2
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tCLZ
tCPA
tRDD
tDZC
tCDD
VIH
VIL
~
DQ9 DQ16
Hi-Z
~
(or DQ1 DQ8)
(INPUTS)
tCAC
tAA
tCAC
tAA
tWEZ
tOFF
tOHC
tDOH
tCLZ
VOH
VOL
DQ9 ~DQ16
Hi-Z
DATA
VALID-1
DATA
VALID-3
~
(or DQ1 DQ8)
(OUTPUTS)
tRAC
tDZO
tCPA
tODD
tOEA
tOCH
tOEZ
VIH
VIL
OE
Aug. 1999
33
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Write Cycle (Early Write)
(at M5M465165Dxx only)
tRP
tRAS
VIH
RAS
VIL
tCSH
tHPC
tRSH
tCRP
tCRP
tCRP
tRPC
VIH
VIL
LCAS
(or UCAS)
tRPC
tRCD
tCAS
tCP
tCAS
tCP
tCAS
VIH
VIL
UCAS
(or LCAS)
tCAL
tCAH
tCAL
tCAH
tCAL
tCAH
tASR
tRAH
tASC
tASC
tASR
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-1
COLUMN
ADDRESS-2
COLUMN
ADDRESS-3
Address
tWCS
tWCS
tWCH
tWCH
tWCS
tWCH
VIH
VIL
W
tDS
tDH
VIH
DQ1 ~DQ8
DATA
~
(or DQ9 DQ16)
VALID-2
Hi-Z
(INPUTS)
VIL
VOH
DQ1 ~DQ8
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDS
tDH
tDS
tDH
~
VIH
VIL
DQ9 DQ16
DATA
VALID-3
DATA
VALID-1
~
(or DQ1 DQ8)
(INPUTS)
VOH
VOL
DQ9 ~DQ16
Hi-Z
~
(or DQ1 DQ8)
(OUTPUTS)
VIH
VIL
OE
34
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle
(at M5M465165Dxx only)
tRAS
tRP
VIH
RAS
tRPC
VIL
tCSH
tRWL
tCRP
tCRP
VIH
VIL
LCAS
(or UCAS)
tRPC
tHPRWC
tRCD
tCAS
tCP
tCAS
tCRP
tASR
VIH
VIL
UCAS
(or LCAS)
tRAD
tRAH
tASR
tASC
tCWL
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS-2
COLUMN
ADDRESS-1
Address
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
W
tRWD
tCPWD
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
DQ1 DQ8
VOH
~
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDZC
tDH
tDH
tDZC
tDS
tDS
~
DQ9 DQ16
VIH
VIL
Hi-Z
Hi-Z
DATA
VALID-1
DATA
VALID-2
~
(or DQ1 DQ8)
(INPUTS)
tCAC
tCAC
tAA
tAA
tCLZ
tCLZ
VOH
VOL
DQ9 ~DQ16
Hi-Z
Hi-Z
Hi-Z
DATA
VALID
-1
DATA
VALID
-2
~
(or DQ1 DQ8)
(OUTPUTS)
tRAC
tDZO
tCPA
tDZO
tODD
tODD
tOEZ
tOEA
tOEH
tOEH
tOEZ
tOEA
VIH
VIL
OE
35
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) CAS before RAS Refresh Cycle
(at M5M465165Dxx only)
tRC
tRP
tRC
tRP
tRAS
tRAS
VIH
VIL
RAS
tRPC
tRPC
tCRP
tCSR
tRPC
tRPC
tRPC
tCRP
tCRP
tCRP
LCAS
VIH
VIL
(or UCAS)
tRPC
tCSR
VIH
VIL
UCAS
tCHR
tCHR
(or LCAS)
tCPN
tASR
VIH
VIL
ROW
ADDRESS
Address
tRCS
tRSR
tRSR
tRHR
tRCH
tRHR
VIH
VIL
W
Å
@
Å
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
@
Å
(INPUTS)
VIL
tOFF
@
Å
@
tOHC
tREZ
tOHR
VOH
DQ1 DQ8
~
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tOEZ
tCDD
tOFF
~
VIH
VIL
DQ9 DQ16
~
(or DQ1 DQ8)
(INPUTS)
~
DQ9 DQ16
VOH
VOL
Hi-Z
~
(or DQ1 DQ8)
(OUTPUTS)
tOEZ
tODD
VIH
VIL
OE
36
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Hidden Refresh Cycle (Byte Read) (Note 31)
(at M5M465165Dxx only)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
tRPC
tRPC
RAS
VIL
tRCD
tRSH
tCRP
tCRP
tCRP
VIH
VIL
LCAS
(or UCAS)
tCRP
tCHR
VIH
VIL
UCAS
(or LCAS)
tRAD
tRAH
tASR
tASC
tCAH
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
Address
tRCS
tRRH
tRSR
tRHR
tRAL
VIH
VIL
W
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
DQ1 DQ8
VOH
~
Hi-Z
Hi-Z
~
(or DQ9 DQ16)
(OUTPUTS)
VOL
tDZC
tCDD
~
DQ9 DQ16
VIH
VIL
~
(or DQ1 DQ8)
tOFF
tREZ
(INPUTS)
tCAC
tOHC
tOHR
tCLZ
tAA
DQ9 ~DQ16
VOH
VOL
Hi-Z
~
(or DQ1 DQ8)
DATA VALID
(OUTPUTS)
tOEZ
tODD
tRAC
tOEA
tDZO
tORH
VIH
VIL
OE
37
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Byte Self Refresh Cycle
(at M5M465165Dxx only)
tRASS
tRP
tRPS
VIH
RAS
VIL
tCRP
tCSR
tRPC
tRPC
tRPC
tRPC
tCRP
VIH
VIL
LCAS
(or UCAS)
tCRP
tCHS
VIH
VIL
UCAS
(or LCAS)
tCPN
tASR
VIH
VIL
ROW
ADDRESS
Address
tRSR
tRHR
tRCH
VIH
VIL
W
DQ1 ~DQ8
VIH
~
(or DQ9 DQ16)
(INPUTS)
VIL
tOFF
tOHC
tREZ
tOHR
VOH
(or DQ9 DQ16)
DQ1 DQ8
~
Hi-Z
~
(OUTPUTS)
VOL
tOEZ
tCDD
tOFF
~
DQ9 DQ16
VIH
VIL
~
(or DQ1 DQ8)
(INPUTS)
DQ9 ~DQ16
VOH
VOL
Hi-Z
~
(or DQ1 DQ8)
(OUTPUTS)
tOEZ
tODD
VIH
VIL
OE
38
Aug. 1999
MITSUBISHI ELECTRIC
(Rev. 1.0)
MITSUBISHI LSIs
M5M467405/465405DJ,DTP -5,-6,-5S,-6S
M5M467805/465805DJ,DTP -5,-6,-5S,-6S
M5M465165DJ,DTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable,but there is always the possibility that trouble may
occur with them. Trouble with semiconductors consideration to safety when making
your circuit designs,with appropriate measures such as (i) placement of substitutive,
auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application;they do not
convey any license under any intellectual property rights,or any other rights,belonging to
Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage,or infringement
of any third-party's rights,originating in the use of any product data,diagrams,charts or
circuit application examples contained in these materials.
• All information contained in these materials,including product data,diagrams and charts,
represent information on products at the time of publication of these materials,and are
subject to change by Mitsubishi Electric Corporation without notice due to product
improvements or other reasons. It is therefore recommended that customers contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use
in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,vehicular,
medical,aerospace,nuclear,or undersea repeater use.
•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
•If these products or technologies are subject the Japanese export control restrictions,they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
39
Aug. 1999
MITSUBISHI ELECTRIC
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