M5M4S16G50DFP-7 [MITSUBISHI]
Video DRAM, 512KX32, 5.6ns, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, QFP-100;
| 型号： | M5M4S16G50DFP-7 |
| 厂家： | 
Mitsubishi Group |
| 描述： | Video DRAM, 512KX32, 5.6ns, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, QFP-100 时钟 动态存储器 内存集成电路 |
| 文件： | 总33页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PRELIMINARY
Some of contents are described for general products
and are subject to change without notice.
DESCRIPTION
The M5M4S16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM,
with SSTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M5M4S16G50DFP can operate at frequencies of 100+ MHz. The
BLOCK WRITE and WRITE-PER-BIT functions provide improved performance
in graphic memory systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequencies of 143 MHz
- Fully synchronous operation referenced to clock rising edge
- Dual bank operation controlled by A10(Bank Address)
- Internal pipelined operation: column address can be changed every clock cycle
- Programmable /CAS Latency (SSTL: 2 and 3)
- Programmable Burst Length (1/2/4/8 and Full Page)
- Programmable Burst Type (Sequential / Interleave)
- Byte control using DQM0 - DQM3 signals in both read and write cycles
- Persistent Write-Per-Bit (WPB) function
- 8 Column Block Write (BW) function
- Auto Precharge / All bank precharge controlled by A9
- Auto Refresh and Self Refresh Capability
- 2048 refresh cycles /32ms
- SSTL Interface and pin58 is Vref. If pin 58 is VCCQ, then the device turned
LVTTL Interface
- 100 pin QFP package with 0.65mm lead pitch
Max.
Frequency
CLK Access
Time
M5M4V16G50DFP - 7
M5M4V16G50DFP- 8
M5M4V16G50DFP- 10
143MHz
125MHz
100MHz
5.6ns
6.4ns
8.0ns
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
DQ29 81
82
50 A7
49 A6
48 A5
47 A4
46 VSS
45 NC
44 NC
43 NC
42 NC
41 NC
40 NC
39 NC
38 NC
37 NC
36 NC
35 VDD
34 A3
33 A2
32 A1
31 A0
VSSQ
DQ30 83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ31
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
DQ0
DQ1
VSSQ
DQ2
100 Pin QFP
14.0 x 20.0 mm2
0.65 mm pitch
CLK
CKE
/CS
/RAS
/CAS
/WE
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
DSF
: Special Function Enable
: Address Input
: Row Address inputs
: Column Address inputs
: Bank Address
A0-10
A0-9
A0-7
A10
DQ0-31
DQM0-3
Vdd
VddQ
Vss
: Data I/O
: Output Disable/ Write Mask
: Power Supply
: Power Supply for Output
: Ground
VssQ
Vref
: Ground for Output
: Reference voltage
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
DQ0-31
BLOCK DIAGRAM
Color
Register
DQM0-3
I/O Buffer
Mask
Register
Memory Array
Bank #0
Memory Array
Bank #1
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
CLK CKE
A0-9
A10
/CS
/RAS
/CAS
/WE
DSF
Type Designation Code
This rule is applied only to Synchronous DRAM family.
M 5M 4 S 16 G 5 0 D FP - 8
Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns
Package Type FP: QFP
Process Generation
Function 0: Random Column, 1: 2N-rule
n
Organization 2 5: x32
Synchronous Graphics RAM
Density 16:16M bits
Interface V:LVTTL S: SSTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PIN FUNCTION
CLK
CKE
/CS
Input
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is stopped. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
Input
Input
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE, and DSF defines basic commands.
/RAS, /CAS, /
WE, and DSF
A0-9 specify the Row / Column Address in conjunction with BA. The Row
Address is specified by A0-9. The Column Address is specified by A0-7.
A9 is also used to indicate precharge option. When A9 is high at a read /
write command, an auto precharge is performed. When A9 is high at a
precharge command, both banks are precharged.
A0-9
Input
Bank Address: A10 (BA) specifies the bank to which a
command is applied. A10 (BA) must be set with ACT, PRE, READ,
WRITE commands.
A10
Input
Data In/Data out are referenced to the rising edge of CLK. These pins
are used for input mask pins for Write-Per-Bit and column/byte mask
inputs for Block Writes.
DQ0-31
Input / Output
Input/Output Byte Mask: When DQM0-3 are high during a write, data for
the current cycle is masked. When DQM0-3 are high during a read,
output data is disabled at the next cycle.
DQM0 controls byte 0 (DQ7-0), DQM1 controls byte 1 (DQ15-8), DQM2
controls byte 2 (DQ23-16), and DQM3 controls byte 3 (DQ31-24).
DQM0 -
DQM3
Input
Input
VREF
Reference voltage for all inputs.
Vdd, Vss
Power Supply
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
VddQ, VssQ
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BASIC FUNCTIONS
The M5M4V16G50DFP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS, /WE, and DSF at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A9 are used as chip select, refresh option, and precharge option,
respectively.
For a more detailed definition of commands, please see the command truth table.
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
DSF
CKE
A9
Command
define basic commands
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/CS, /RAS, DSF = L, /CAS, /WE = H]
ACT command activates a row in an idle bank indicated by A10 (BA) and row address
selected by A0 - A9.
Activate with WPB enable (ACTWPB) [/CS, /RAS = L, /CAS, /WE, DSF = H]
This command is the same as Activate except that Write-Per-Bit (WPB) is enabled. The Mask
Register’s contents are used as the WPB data.
Read (READ) [/CS, /CAS, DSF = L, /RAS, /WE = H]
READ command starts burst read from the active bank indicated by A10 (BA). First output data
appears after /CAS latency. When A9 = H at this command, the bank is deactivated after the burst read
(auto-precharge, READA).
Write (WRITE) [/CS, /CAS, /WE, DSF = L, /RAS = H]
WRITE command starts burst write to the active bank indicated by A10 (BA). Total data length to be
written is set by burst length. When A9 = H at this command, the bank is deactivated after the burst
write (auto-precharge, WRITEA).
Precharge (PRE) [/CS, /RAS, /WE, DSF = L, /CAS = H]
PRE command deactivates the active bank indicated by A10 (BA). This command also terminates
burst read /write operation. When A9 = H at this command, both banks are deactivated
(precharge all, PREA).
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BASIC FUNCTIONS (continued)
Auto-Refresh (REFA) [/CS, /RAS, /CAS, DSF = L, /WE, CKE = H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated inter-
nally. After this command, the banks are precharged automatically. Both banks must be precharged
before this command can begin.
Self-Refresh (REFS) [/CS, /RAS, /CAS, DSF, CKE = L, /WE = H]
REFS command starts self-refresh cycle. The self-refresh cycle will continue while CKE remains low.
When CKE goes high, self-refresh is exited. Refresh address including bank address are generated inter-
nally. After this command, the banks are precharged automatically. Both banks must be precharged
before this command can begin.
Burst Terminate (TERM) [/CS, /WE, DSF = L, /RAS, /CAS = H]
TERM command stops the current burst operation. During read cycles, burst data stops after CAS
latency is met.
No Operation (NOP) [/CS, DSF = L, /RAS, /CAS, /WE = H]
NOP command does not perform any operation on the SGRAM.
Mode Register Set (MRS) [/CS, /WE, /RAS, /CAS, DSF = L]
MRS command loads the mode register that defines how the device operates. The address pins, A0 -
A10, are used as input pins for the mode register data. This command must be issued after power-on to
initialize the SGRAM. The mode register can only be set when both banks are idle. During the two
cycles following this command, the SGRAM cannot accept any other commands.
Special Register Set (SRS) [/CS, /WE, /RAS, /CAS = L, DSF = H]
SRS command sets the color and mask registers. During the two cycles following this command, the
SGRAM cannot accept any other commands.
Masked Block Write (BW) [/CS, /CAS, /WE = L, /RAS, DSF = H]
BW command starts the 8 column Block Write function. Burst Length = 1 is assumed. Write data
comes from the color register and column address mask data is applied on the DQs. When A9 = H at
this command, the bank is deactivated after the burst write (auto-precharge, BWA).
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
COMMAND TRUTH TABLE
CKE CKE
COMMAND
MNEMONIC
/CS /RAS /CAS /WE
A10 A9
A0-8
DSF
n-1
H
n
X
X
Deselect
DESEL
NOP
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
L
No Operation
H
Row Address Entry &
Bank Activate
ACT
H
H
X
X
L
L
L
L
H
H
H
H
L
BA Row Add.
BA Row Add.
Row Address Entry &
Bank Activate
ACTWPB
H
Single Bank Precharge
Precharge All Banks
PRE
H
H
X
X
L
L
L
L
H
H
L
L
L
L
BA
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
L
BA
L
Col.
Column Address Entry
& Write with Auto-
Precharge
WRITEA
BW
H
H
X
L
H
L
L
L
L
L
BA
BA
H
Col.
Col.
Column Address Entry
& Masked Block Write
X
L
H
L
H
Masked Block Write
with Auto-Precharge
BWA
H
H
X
L
H
L
L
L
BA
BA
H
Col.
Col.
H
L
Column Address Entry
& Read
READ
X
L
H
H
L
Column Address Entry
& Read with Auto-
Precharge
READA
H
X
L
H
L
H
L
BA
H
Col.
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
L
L
H
H
X
H
L
L
L
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Entry
H
H
X
X
X
H
H
L
X
H
H
L
Self-Refresh Exit
REFSX
L
Burst Terminate
TERM
MRS
H
H
Mode Register Set
L
OPCODE
OPCODE
Special Register Set
SRS
H
X
L
L
L
L
H
H=High Level, L=Low Level, BA=Bank Address, Col.=Column Address (A0-A7)
Row Add.=Row Address (A0-A9), X=Don't Care, n=CLK cycle number
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE
Current State
IDLE
DSF
X
Address
Command
DESEL
Action
/CS /RAS /CAS /WE
X
NOP
H
L
L
L
L
L
L
L
L
X
H
H
H
H
H
H
H
L
X
H
H
H
L
X
H
L
L
X
X
NOP
NOP
Undefined
ILLEGAL
H
L
X
X
TERM
Undefined
ILLEGAL*2
ILLEGAL
L
H
H
L
H
L
BA, CA, A9
READ / READA
ILLEGAL*2
L
L
BA, CA, A9
BA, CA, A9
WRITE / WRITEA ILLEGAL*2
L
BW / BWA
ACT
ILLEGAL*2
H
L
L
BA, RA
Bank Active; Latch RA; No Mask
Bank Active; Latch RA; Use Mask
ILLEGAL
H
H
L
BA, RA
ACTWPB
Undefined
H
H
L
L
L
L
L
H
H
H
L
X
BA, A9
PRE / PREA NOP*4
L
L
L
L
L
L
H
L
L
L
H
H
X
X
Undefined
REFA
ILLEGAL
H
L
Auto-Refresh*5
Op-Code,
Mode-Add
SRS
MRS
Special Register Set*5
Mode Register Set*5
H
L
L
L
L
L
L
L
L
L
Op-Code,
Mode-Add
ROW ACTIVE
X
DESEL
NOP
NOP
NOP
NOP
H
L
L
X
H
H
X
H
H
X
H
L
X
L
L
X
BA
TERM
Begin Read; Latch CA;
Determine Auto-Precharge
BA, CA, A9
BA, CA, A9
BA, CA, A9
READ / READA
L
L
L
H
H
H
L
L
L
H
L
L
L
L
H
WRITE /
WRITEA
Begin Write; Latch CA;
Determine Auto-Precharge
Block Write; Latch CA;
Determine Auto-Precharge
BW / BWA
BA, RA
BA, RA
BA, A9
X
ACT
Bank Active / ILLEGAL*2
Bank Active / ILLEGAL*2
L
H
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
ACTWPB
PRE / PREA Precharge / Precharge All
REFA
ILLEGAL
H
Op-Code,
Mode-Add
H
L
SRS
Special RegisteSet *5
L
L
L
L
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE(continued)
Current State
READ
DSF
Address
Command
Action
/CS /RAS /CAS /WE
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
X
L
L
H
L
L
X
H
H
X
H
H
X
H
L
X
BA
TERM
Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3
BA, CA, A9
BA, CA, A9
BA, CA, A9
READ / READA
L
L
L
L
H
H
L
L
H
L
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Block Write, Determine Auto-
Precharge*3
H
L
H
L
L
BW / BWA
L
L
L
L
BA, RA
BA, RA
BA, A9
X
ACT
Bank Active / ILLEGAL*2
Bank Active / ILLEGAL*2
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
ACTWPB
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
H
Op-Code,
Mode-Add
H
SRS
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
L
L
L
L
L
X
L
L
WRITE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
X
BA
TERM
Terminate Burst, Latch CA,
Begin Read, Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
H
L
L
L
H
L
L
BA, CA, A9
BA, CA, A89
BA, CA, A9
READ / READA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Block Write, Determine Auto-
Precharge*3
BW / BWA
L
L
L
L
L
L
H
H
H
H
BA, RA
BA, RA
ACTWPB
ACT
Bank Active / ILLEGAL*2
Bank Active / ILLEGAL*2
L
L
L
L
L
L
H
L
L
BA, A9
X
PRE / PREA Terminate Burst, Precharge
H
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
H
L
L
L
L
L
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
DSF
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
X
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
AUTO
PRECHARGE
X
BA
TERM
H
BA, CA, A9
READ / READA ILLEGAL
WRITE /
L
L
H
L
L
BA, CA, A9
ILLEGAL
WRITEA
BW / BWA
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
H
L
H
L
BA, CA, A9
BA, RA
BA, RA
BA, A9
X
ILLEGAL
ACT
Bank Active / ILLEGAL*2
Bank Active / ILLEGAL*2
H
L
ACTWPB
PRE / PREA ILLEGAL*2
L
H
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
H
L
L
L
L
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
L
X
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
AUTO
PRECHARGE
X
BA
TERM
H
BA, CA, A9
READ / READA ILLEGAL
WRITE /
L
L
H
L
L
BA, CA, A9
ILLEGAL
WRITEA
H
L
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
H
L
BA, CA, A9
BA, RA
BA, RA
BA, A9
X
BW / BWA
ACT
ILLEGAL
Bank Active / ILLEGAL*2
Bank Active / ILLEGAL*2
H
L
ACTWPB
PRE / PREA ILLEGAL*2
L
H
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
H
L
L
L
L
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
L
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL*2
DSF
X
L
H
L
L
X
H
H
X
H
H
X
H
L
X
PRE -
CHARGING
X
BA
TERM
L
L
L
H
H
L
L
H
L
L
BA, CA, A9
BA, CA, A9
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
L
L
L
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
H
L
H
L
BA, CA, A9
BA, RA
BA, RA
BA, A9
X
BW / BWA
ACT
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
L
ACTWPB
L
PRE / PREA NOP*4 (Idle after tRP)
H
L
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
Op-Code,
Mode-Add
L
L
L
L
L
L
L
L
H
L
MRS
ILLEGAL
H
L
L
L
L
X
H
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL*2
ROW
ACTIVATING
X
L
L
L
L
X
BA
TERM
H
L
BA, CA, A9
BA, CA, A9
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
L
L
H
L
L
BA, CA, A9
BW / BWA
ILLEGAL*2
H
L
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
BA, RA
BA, RA
BA, A9
X
ACT
ILLEGAL*2
ILLEGAL*2
ACTWPB
H
L
L
PRE / PREA ILLEGAL*2
H
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
L
L
L
L
H
L
Op-Code,
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE
Address
Command
Action
DSF
H
L
L
L
L
X
H
H
H
H
X
H
H
L
X
H
L
X
L
L
L
X
DESEL
NOP
NOP
WRITE RE-
COVERING
X
NOP
BA
TERM
ILLEGAL*2
H
L
BA, CA, A9
BA, CA, A9
BA, CA, A9
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
L
L
H
L
L
L
H
L
L
L
BW / BWA
ACT
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
H
H
BA, RA
L
L
L
L
L
L
H
H
L
H
L
H
L
L
BA, RA
BA, A9
X
ACTWPB
PRE / PREA ILLEGAL*2
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
L
L
L
H
L
SRS
ILLEGAL
Op-Code,
Mode-Add
L
MRS
ILLEGAL
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
L
L
L
X
DESEL
NOP
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
RE-
FRESHING
X
BA
TERM
H
BA, CA, A9
READ / READA ILLEGAL
WRITE / WRITEA ILLEGAL
L
L
H
H
L
L
L
L
L
BA, CA, A9
BA, CA, A9
H
BW / BWA
ILLEGAL
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
BA, RA
BA, RA
BA, A9
X
ACT
ACT
ILLEGAL
ILLEGAL
PRE / PREA ILLEGAL
H
REFA
SRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
L
L
L
L
H
L
Op-Code,
Mode-Add
MRS
ILLEGAL
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE DSF
Address
Command
DESEL
NOP
Action
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
H
L
L
L
L
L
X
H
H
H
H
H
X
H
H
L
X
H
L
X
L
X
MODE
REGISTER
SETTING
X
L
BA
TERM
H
L
L
BA, CA, A9
BA, CA, A9
BA, CA, A9
READ / READA ILLEGAL
WRITE / WRITEA ILLEGAL
L
L
L
L
H
BW / BWA
ACT
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
L
L
L
L
H
H
H
L
H
H
L
L
H
L
L
BA, RA
BA, RA
BA, A9
X
ACTWPB
PRE / PREA ILLEGAL
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
L
L
L
L
H
L
SRS
ILLEGAL
Op-Code,
Mode-Add
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
/CS /RAS /CAS /WE DSF Add
Action
n-1
H
L
n
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
SELF-
REFRESH*1
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
H
H
H
H
H
H
H
L
H
L
ALL BANKS
IDLE*2
L
H
L
X
H
H
H
L
X
H
H
L
X
X
X
X
X
X
X
X
X
X
Enter Power Down
L
Enter Power Down
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle*3
Exit CLK Suspend at Next Cycle*3
Maintain CLK Suspend
H
H
L
ANY STATE
other than
listed above
H
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be
satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SGRAM
from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM0-3 high and NOP condition at
the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SGRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The
mode register stores these data until the next MRS command, which may be issued when both banks are in
idle state. After tRSC from a MRS command, the SGRAM is ready for new command.
CLK
/CS
/RAS
/CAS
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A10
0
/WE
DSF
0
0
0
LTMODE
BT
BL
A10, A9 -A0
V
CAS LATENCY
LVTTL
BURST LENGTH
BL
CL
BT= 0
BT= 1
Reserved
Reserved
2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
Reserved
Reserved
4
2
4
3
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
A7
0
Operating Mode
Normal Operation
BURST
TYPE
0
1
SEQUENTIAL
INTERLEAVED
A10 A9 A8
0
0
-
0
1
-
0
0
-
Burst Read and Single Write
All Others are Reserved
0
-
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
SPECIAL REGISTER
The Mask Register and Color Register can be loaded by setting the special register (SRS). If CR
and MR are both high, data in the Mask and Color Registers will be unknown.After tRSC from a SRS
command, the SGRAM is ready for new command.
CLK
/CS
/RAS
/CAS
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A10
0
/WE
DSF
0
0
0
CR MR 0
0
0
0
0
A10, A9 -A0
V
Operation
MR
0
1
No Load Operation
Load Mask
Mask Register
Color Register
CR
Operation
0
1
No Load Operation
Load Color
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
CLK
Read
Y
Write
Y
Command
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
0
1
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
0
2
3
3
2
4
5
5
4
6
7
7
6
0
0
1
1
1
1
-
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
0
4
5
6
7
0
1
2
3
0
1
5
6
7
0
1
2
3
0
1
2
6
7
0
1
2
3
7
0
1
2
3
4
0
1
2
3
4
5
1
2
3
4
5
6
2
3
4
5
6
7
0
1
2
3
0
1
3
2
5
4
7
6
1
0
3
2
1
0
0
1
6
7
4
5
2
3
0
1
1
0
7
6
5
4
3
2
1
0
6
7
0
1
2
3
7
6
1
0
3
2
4
5
2
3
0
1
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
NOTE:
FULL PAGE BURST is an extension of the above tables of Sequential Addressing with the length being 256.
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SGRAM has two independent banks. Each bank is activated by the ACT command with the bank
address (A10/BA). A row is indicated by the row address A9-0. The minimum activation interval between
one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by A10/BA. When both banks are active, the
precharge all command (PREA, PRE + A9=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-8
A9
ACT
Xa
Xa
0
ACT READ
PRE
ACT
Xb
Xb
1
tRRD
tRAS
tRP
Xb
Xb
1
Y
0
0
tRCD
1
A10
DQ
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The
start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A
READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind
continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited until the internal precharge is complete. The internal precharge start timing depends on
/CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing.
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
Dual Bank Interleaving READ (BL=4, CL=3)
CLK
Command
ACT
Xa
READ ACT
READ PRE
Y
tRCD
A0-8
A9
Y
0
Xb
Xb
Xa
0
1
0
0
A10
DQ
0
0
1
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
A0-8
ACT
Xa
Xa
0
READ
ACT
Xa
Xa
0
tRCD
Y
tRP
A9
1
0
A10
DQ
Qa0 Qa1 Qa2 Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CLK
Command
CL=3 DQ
CL=2 DQ
ACT
READ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set in the same
cycle as the WRITE. The following (BL -1) data is written into the RAM, when the Burst Length is BL.
The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type.
A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden
behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a
WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE,
ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge begins
at tWR after the last input datacycle. The next ACT command can be issued after tRP from the internal
precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CLK
Command
A0-8
A9
ACT
Xa
Xa
0
Write ACT
Write PRE
tRCD
tRCD
Y
0
0
Xb
Xb
1
Y
tWR
0
0
0
A10
1
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Burst Length
WRITE with Auto-Precharge (BL=4)
CLK
Command
A0-8
ACT
Xa
Xa
0
Write
ACT
Xa
Xa
0
tRCD
Y
tRP
A9
1
A10
0
tWR
DQ
Da0 Da1 Da2 Da3
Internal precharge begins
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of the same or the other bank. M5M4V16G50DFP
allows random column access. READ to READ interval is minimum 1 CLK.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-8
A9
READ READ
READ
READ
Yi
0
Yj
0
Yk
0
Yl
0
A10
0
0
1
0
DQ
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random column access is
allowed. In this case, the DQ should be controlled adequately by using the DQM0 - 3 to prevent
bus contention. The output is disabled automatically 2 cycles after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
READ
Write
A0-8
Yi
0
Yj
0
A9
A10
0
0
DQM0-3
Q
Qai0
D
Daj0 Daj1 Daj2 Daj3
control
Write control
DQM0-3
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is mini-
mum 1 CLK. A PRE command disables the data output depending on the /CAS Latency. The figure below
shows examples of when the dataout is terminated.
Read Interrupted by Precharge (BL=4)
CLK
Command
DQ
READ
PRE
Q1
Q0
PRE
Q0
Q2
Q2
Q3
Command
DQ
READ
CL=3
Q1
Command
DQ
READ PRE
Q0
Command
DQ
READ
PRE
Q2
Q0
Q0
Q0
Q1
Q3
Command
DQ
READ
PRE
Q1
CL=2
Q2
Command
DQ
READ PRE
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the
data output. READ to TERM interval is minimum 1 CLK. The figure below shows examples when the
dataout is terminated.
Read Interrupted by Burst Terminate (BL=4)
CLK
Command
DQ
READ
TERM
Q1
Q0
Q2
Q2
Q3
Command
DQ
READ
TERM
Q0
CL=3
Q1
Command
DQ
READ TERM
Q0
Command
DQ
READ
TERM
Q2
Q0
Q0
Q0
Q1
Q3
Command
DQ
READ
TERM
Q1
CL=2
Q2
Command
DQ
READ TERM
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank. Random column
access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
CLK
Command
A0-8
A9
Write Write
Write
Yk
0
Write
Yi
0
Yj
0
Yl
0
A10
0
0
1
0
DQ
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ
cycle is “don’t care”.
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-8
Write READ
Write
Yk
0
READ
Yi
0
Yj
0
Yl
0
A9
A10
0
0
0
1
DQM0-3
DQ
Dai0
Qaj0 Qaj1
Dak0 Dak1
Qbl0
MITSUBISHI ELECTRIC
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random column access is al-
lowed.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-8
Write
PRE
ACT
Xb
Xb
0
tWR
tRP
Yi
0
A89
0
0
A10
0
DQM0-3
DQ
Dai0 Dai1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write recovery time is not
required and the bank remains active. The figure below shows the case that 3 words of data are written.
Random column access is allowed. WRITE to TERM interval is minimum 1 CLK.
Write Interrupted by Burst Terminate (BL=4)
CLK
Command
A0-8
Write
TERM
Yi
0
A9
A10
0
DQM0-3
DQ
Dai0 Dai1 Dai2
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with REFA (/CS= /RAS= /CAS= DSF= L, /WE= /CKE= H)
command. The refresh address is generated internally. 2048 REFA cycles within 32ms refresh 16Mbit
memory cells. The auto-refresh is performed on each bank alternately (ping-pong refresh). Before
performing an auto-refresh, both banks must be in the idle state. Additional commands must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESLECT
/RAS
/CAS
/WE
DSF
CKE
minimum tRC
A0-9
A10
Auto Refresh on Bank 0
Auto Refresh on Bank 1
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= DSF= L, /WE= H,
CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-
refresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs
including CLK are disabled and ignored, and power consumption due to synchronous inputs is saved. To
exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting
CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be
issued after tRC, but DESEL or NOP commands must be asserted until then.
Self-Refresh
CLK
Stable CLK
/CS
NOP
/RAS
/CAS
/WE
DSF
CKE
new command
A0-9
A10
X
0
minimum tRC
for recovery
Self Refresh Entry
Self Refresh Exit
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M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating
CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or
input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be per-
formed either when the banks are active or idle, but a command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Active Power Down
CKE
Command
ACT
NOP NOP NOP NOP NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
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M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
DQM0 - 3 CONTROL
DQM0 - 3 is a dual function signal defined as the data mask for writes and the output disable for
reads.
During writes, DQM0 - 3 masks input data.
DQM0 - 3 to write mask latency is 0.
During reads, DQM0 - 3 forces output to Hi-Z.
DQM0 - 3 to output Hi-Z latency is 2.
DQM0 masks DQ0-7, DQM1 masks DQ8-15, DQM2 masks DQ16-23, DQM3 masks DQ24-031.
DQM0 - 3 Function
CLK
Command
DQM0
Write
READ
DQ(0-7)
D0
D2
D3
Q0
Q1
Q3
masked by DQM0=High
disabled by DQM0=High
DQM1
DQ(8-15)
D0
D1
D3
Q0
Q2
Q3
masked by DQM1=High
disabled by DQM1=High
DQM2
DQ(16-23)
D1
D2
D3
Q0
Q1
Q3
masked by DQM2=High
disabled by DQM2=High
DQM3
D0
D1
D2
Q1
Q2
Q3
DQ(24-31)
masked by DQM3=High
disabled by DQM3=High
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
Parameter
Conditions
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
50
Unit
V
Supply Voltage
with respect to Vss
Supply Voltage for Output with respect to VssQ
V
Input Voltage
Output Voltage
with respect to Vss
with respect to VssQ
V
VO
V
IO
Output Current
mA
mW
°C
°C
Pd
Power Dissipation
Operating Temperature
Storage Temperature
Ta = 25 °C
1000
Topr
Tstg
0 ~ 70
-65 ~ 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
3.3
0
Max.
Vdd
Supply Voltage
Supply Voltage
3.0
3.6
V
V
V
V
V
Vss
0
0
VddQ
VssQ
VIH(AC)
Supply Voltage for Output
Supply Voltage for Output
High-Level Input Voltage all inputs
3.0
0
3.3
0
3.6
0
Vref+0.40
VddQ+0.3
VIL(AC)
Vref
Low-Level Input Voltage all inputs
Input reference voltage
-0.3
1.3
Vre-0.40
1.7
V
V
V
1.5
Vtt
Termination voltage
Vref-0.05
Vref
Vrerf+0.05
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Test Condition
Limits (max.)
Unit
pF
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
Input / Output Capacitance, I/O pin
5
5
5
7
VI=Vss
f=1MHz
Vi=25mVrms
pF
pF
pF
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M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits(max)
Symbol
Parameter
Test Conditions
Unit
-7
-8
-10
Icc1s*1 operating current, single bank tRC=min, tCLK=min, BL=1, CL=3
mA
mA
mA
mA
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Icc1d*1 operating current, dual bank
tRC=min, tCLK=min, BL=1, CL=3
both banks idle, tCLK=min, CKE=H
both banks idle, tCLK=min, CKE=L
both banks active, tCLK=min, CKE=H
tCLK=min, BL=4, CL=3, 1 bank idle
tRC=min, tCLK=min
Icc2h
Icc2l
Icc3
standby current, CKE=H
standby current, CKE=L
active standby current
Icc4*1 burst current
Icc5
Icc6
Icc7
auto-refresh current
self-refresh current
CKE <0.2v
operating current, block write tCLK=min
NOTES:
1. Icc (max) is specified at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
Min.
Max.
VOH(DC) High-Level Output Voltage(DC)
VOL(DC) Low-Level Output Voltage(DC)
IOH=-16mA
IOL= 16mA
Vtt+0.8
V
V
Vtt-0.8
10
IOZ
II
Off-state Output Current
Input Current
Q floating VO=0 ~ VddQ
VIH = 0 ~ VddQ+0.3V
-10
-10
µA
µA
10
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M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels : Vref+-0.4V
Input Timing Measurement Level : Vref
Limits
(-7.5)
Min. Max. Min. Max.
Symbol Parameter
-7
-8
Unit
-10
Min. Max.
Min. Max.
CL=2 10
12
7.5
3
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
tCLK CLK cycle time
CL=3
7
3
10
tCH
tCL
tT
CLK High pulse width
CLK Low pulse width
Transition time of CLK
3
3.5
3.5
3
3
3
1
10
1
10
1
2.5
1
10
1
10
tIS
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
2.0
1
2.0
1
2.5
tIH
tRC
1.0
84
28
90
30
96
32
100
30
tRCD* Row to Column Delay
tRAS Row Active time
56 10000 60 10000
64 10000
70 10000
tRP
Row Precharge time
Write Recovery time
28
7
30
30
8
30
10
30
tWR
7.5
tRRD Act to Act Delay time
Mode Register Set
21
22.5
24
tRSC
14
7
15
16
8
20
ns
ns
Cycle time
tPDE Power Down Exit time
7.5
10
32
tREF Refresh Interval time
tBWC Block Write Cycle time
tBPL Block Write to Precharge
32
32
32
ms
ns
ns
14
7
15
16
8
20
10
7.5
Vref
Vref
CLK
Any AC timing is
referenced to the input
signal crossing through
the Vref level.
Signal
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SGRAM (Rev. 0.0)
M5M4S16G50DFP -7, -8,-10
April '97 Preliminary
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol Parameter
-7
Min. Max.
8.0
(-7.5)
Min. Max.
9.0
-8
-10
Unit
Min.
Max. Min. Max.
CL=2
CL=3
9.0
6.4
11.0
8.0
ns
ns
tAC
Access time from CLK
5.6
6.0
Output Hold time from
CLK
tOH
tOLZ
tOHZ
2.0
0
2.0
0
2.5
0
2.5
0
ns
ns
ns
Delay time, output low
impedance from CLK
Delay time, output high
impedance from CLK
2.5
7
2.5
7
2.5
8
2.5
8
Output Load Condition
VTT=Vref
CLK
Vref
Vref
50ohm
VREF
=0.45 x VddQ
DQ
VOUT
30pF
Output Timing Measurement
Reference Point
CLK
Vref
DQ
Vref
tOHZ
tAC
tOH
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