M5M4V64S40ATP-8A [MITSUBISHI]
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM; 64M （ 4 - X银行1048576 -字×16位）同步DRAM
| 型号： | M5M4V64S40ATP-8A |
| 厂家： | 
Mitsubishi Group |
| 描述： | 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM |
| 文件： | 总51页 (文件大小：1081K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Some of contents are subject to change without notice.
PIN CONFIGURATION
(TOP VIEW)
DESCRIPTION
The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V64S40ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
1
2
3
4
5
6
7
54
Vss
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC (Vref)
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
BA0(A13)
BA1(A12)
A10
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
A0
A1
A2
A3
Vdd
Vss
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
CLK
: Master Clock
: Clock Enable
: Chip Select
CKE
- 4096 refresh cycles /64ms
/CS
- Column address A0-A7
/RAS
/CAS
/WE
: Row Address Strobe
: Column Address Strobe
: Write Enable
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
DQ0-15
DQML/U
A0-11
BA0,1
Vdd
: Data I/O
: Output Disable/ Write Mask
: Address Input
Max.
CLK Access
Time
: Bank Address
Frequency
: Power Supply
6ns
VddQ
Vss
: Power Supply for Output
: Ground
M5M4V64S40ATP-8A
125MHz
6ns
8ns
M5M4V64S40ATP-8
M5M4V64S40ATP-10
100MHz
100MHz
VssQ
: Ground for Output
1
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
DQ0-15
BLOCK DIAGRAM
I/O Buffer
Memory Array Memory Array Memory Array Memory Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
A0-11 BA0,1
Control Signal Buffer
Clock Buffer
CLK CKE
/CS /RAS /CAS /WE DQM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 5M 4 V 64 S 4 0 A TP - 8
Access Item
Package Type TP: TSOP(II)
Process Generation
Function 0: Random Column, 1: 2N-rule
Organization 2n 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 64:64M bits
Interface S: SSTL, V:LVTTL
Memory Style (DRAM)
Use, Recommended Operating Conditions, etc
Mitsubishi Main Designation
2
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
CKE
Input
/CS
Input
Input
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
/RAS, /CAS, /WE
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-7 . A10 is also used to indicate precharge option. When
A0-11
BA0,1
Input
Input
A10 is high at a read / write command, an auto precharge is performed.
When A10 is high at a precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-15
Input / Output
Input
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the
current cycle is masked. When DQMU/L is high in burst read,
Dout is disabled at the next but one cycle.
DQMU/L
Vdd, Vss
Power Supply
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
VddQ, VssQ
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V64S40ATP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3
signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.
To know the detailed definition of commands, please see the command truth table.
CLK
Chip Select : L=select, H=deselect
Command
/CS
/RAS
/CAS
/WE
CKE
A10
Command
define basic commands
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge,
READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is
set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-
precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /
write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated inter-
nally. After this command, the banks are precharged automatically.
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
CKE CKE
COMMAND
MNEMONIC
/CS /RAS /CAS /WE BA0,1 A11
A10 A0-9
n-1
H
n
X
X
Deselect
DESEL
NOP
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
No Operation
H
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
X
L
V
Column Address Entry
& Write with Auto-
Precharge
WRITEA
READ
H
H
X
X
L
L
H
H
L
L
L
V
V
X
X
H
L
V
V
Column Address Entry
& Read
H
Column Address Entry
& Read with Auto-
Precharge
READA
H
X
L
H
L
H
V
X
H
V
Auto-Refresh
REFA
REFS
H
H
H
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
Self-Refresh Entry
L
L
H
H
H
L
X
H
H
L
X
H
H
L
X
H
X
X
X
L
X
X
X
L
X
X
X
L
X
X
Self-Refresh Exit
REFSX
Burst Terminate
TBST
MRS
X
H
H
X
X
L
L
L
L
Mode Register Set
V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
5
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
IDLE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT Bank Active, Latch RA
PRE / PREA NOP*4
H
H
L
L
L
H
REFA
MRS
Auto-Refresh*5
Op-Code,
Mode-Add
L
L
L
L
Mode Register Set*5
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
NOP
NOP
X
BA
TBST
Begin Read, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Precharge / Precharge All
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
X
BA
TBST
Terminate Burst, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA Begin New Read, Determine
Auto-Precharge*3
Terminate Burst, Latch CA,
WRITE /
Begin Write, Determine Auto-
WRITEA
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
6
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
Action
WRITE
H
X
X
X
X
NOP (Continue Burst to END)
L
L
H
H
H
H
H
L
X
NOP
NOP (Continue Burst to END)
Terminate Burst
BA
TBST
Terminate Burst, Latch CA,
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine Auto-
Precharge*3
Terminate Burst, Latch CA,
WRITE /
L
L
H
L
L
L
BA, CA, A10
BA, RA
Begin Write, Determine Auto-
WRITEA
Precharge*3
H
H
ACT
Bank Active / ILLEGAL*2
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
AUTO
X
PRECHARGE
BA
TBST
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
ILLEGAL
L
H
L
L
BA, CA, A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
AUTO
X
PRECHARGE
BA
TBST
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
ILLEGAL
WRITEA
L
H
L
L
BA, CA, A10
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
7
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL*2
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
PRE -
CHARGING
X
BA
TBST
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA NOP*4 (Idle after tRP)
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL*2
ROW
ACTIVATING
X
BA
TBST
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
WRITE RE-
COVERING
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL*2
ACT ILLEGAL*2
PRE / PREA ILLEGAL*2
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
8
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State /CS /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
RE-
FRESHING
X
BA
TBST
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
MODE
REGISTER
SETTING
X
BA
TBST
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
9
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
CKE CKE
Current State
/CS /RAS /CAS /WE Add
Action
n-1
H
L
n
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
SELF-
REFRESH*1
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
H
H
H
H
H
H
H
L
H
L
ALL BANKS
IDLE*2
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
Enter Power Down
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle*3
Exit CLK Suspend at Next Cycle*3
Maintain CLK Suspend
H
H
L
ANY STATE
other than
listed above
H
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be
satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
10
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
CKEL
CKEH
CLK
SUSPEND
ACT
POWER
DOWN
CKEL
CKEH
TBST (for Full Page)
TBST (for Full Page)
ROW
ACTIVE
WRITE
READ
WRITEA
READA
READ
CKEL
CKEL
CKEH
WRITE
SUSPEND
READ
SUSPEND
WRITE
CKEH
READ
WRITE
WRITEA
READA
WRITEA
READA
PRE
CKEL
CKEL
CKEH
WRITEA
SUSPEND
READA
SUSPEND
PRE
WRITEA
CKEH
READA
PRE
POWER
APPLIED
POWER
PRE
PRE
CHARGE
ON
Automatic Sequence
Command Sequence
11
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CLK
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
/CS
until the next MRS command, which may be issued when both banks
are inÅ@idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
/RAS
/CAS
/WE
V
BA0,1 A11-A0
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
WM
LTMODE
BT
BL
BL
BT= 0
BT= 1
CL
/CAS LATENCY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
2
4
4
BURST
LENGTH
LATENCY
MODE
8
8
3
R
R
R
FP
R
R
R
R
R
R
R
R
0
1
SEQUENTIAL
INTERLEAVED
0
1
BURST
BURST
TYPE
WRITE
MODE
SINGLE BIT
R: Reserved for Future Use
FP: Full Page
12
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MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
CLK
Command
Address
DQ
Read
Write
Y
Y
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
13
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the
speed of CLK determines which CL should be used. First output data is available after CL cycles
from READ command.
/CAS Latency Timing(BL=4)
CLK
ACT
X
READ
Command
Address
tRCD
Y
CL=2
DQ
DQ
Q0
Q1
Q0
Q2
Q1
Q3
Q2
CL=2
CL=3
CL=3
Q3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be
automatically
performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated
(Hi-Z)
after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be
used to stop the output of data.
Burst Length Timing( CL=2 )
tRCD
CLK
ACT
X
Command
Address
READ
Y
DQ
DQ
DQ
DQ
DQ
Q0
BL=1
BL=2
BL=4
BL=8
BL=FP
Q0 Q1
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Qm Q0 Q1
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
Full Page counter rolls over
and continues to count.
14
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank
addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval be-
tween one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC, although
the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge
all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the
precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin
tRCmin
Command
A0-9
ACT
ACT READ
PRE
ACT
Xb
tRRD
tRAS
tRP
Xa
Xb
Xb
Xb
Y
0
tRCD
A10
Xa
1
Xb
A11
Xa
Xb
BA0,1
DQ
00
01
00
01
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The
start address is specified by A7-0(X16), and the address sequence of burst data is defined by the
Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be
hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after
READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
15
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
A0-9
ACT
Xa
READ ACT
READ PRE
Y
tRCD
Y
0
Xb
Xb
Xb
A10
Xa
0
0
A11
Xa
BA0,1
DQ
00
00
10
10
00
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
A0-9
BL + tRP
ACT
Xa
READ
ACT
Xa
tRCD
BL
tRP
Y
1
Xa
Xa
A10
Xa
Xa
A11
00
00
00
BA0,1
DQ
Qa0 Qa1 Qa2 Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK
Command
CL=3 DQ
CL=2 DQ
ACT
READ
BL
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
16
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same
cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The
start address is specified by A7-0 (x 16), and the address sequence of burst data is defined by the
Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be
hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE
command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-
precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhib-
ited till the internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode
Register can be programmed for burst read and single write. In this mode the write data is only clocked in
when the WRITE command is issued and the remaining burst length is ignored. The read data burst length
os unaffected while in this mode
Multi Bank Interleaving WRITE (BL=4)
CLK
ACT
Xa
Write ACT
Write PRE
Y
PRE
Command
A0-9
tRCD
tRCD
Y
0
Xb
Xb
Xb
10
Xa
0
0
0
0
0
A10
Xa
A11
00
00
10
00
10
BA0,1
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
WRITE with Auto-Precharge (BL=4)
CLK
Command
A0-9
ACT
Xa
Write
ACT
Xa
tRCD
tRP
tWR
Y
1
A10
A11
Xa
Xa
Xa
Xa
00
00
00
BA0,1
DQ
Da0 Da1 Da2 Da3
Internal precharge starts
17
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0. A burst write starts in the same cycle as a
write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8,
and full-page, like burst read operations.
tRCD
CLK
Command
Address
ACT
X
WRITE
Y
DQ
DQ
DQ
DQ
DQ
Q0
BL=1
BL=2
Q0 Q1
Q0 Q1 Q2 Q3
BL=4
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10
BL=8
Qm Q0 Q1
BL=FP
M5M4V64S20A : m=1023
M5M4V64S30A : m=511
M5M4V64S40A : m=255
Full Page counter rolls over
and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1. In a single write operation, data is only
written to the column address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0.)
CLK
ACT
X
Command
WRITE
tRCD
Y
Address
DQ
Q0
18
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1 CLK.
Read Interrupted by Read (BL=4, CL=3)
CLK
READ READ
READ
Yk
READ
Command
A0-9
Yi
0
Yj
0
Yl
0
0
A10
A11
00
00
10
01
BA0,1
DQ
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this
case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output
is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
READ
Write
Yj
Command
A0-9
Yi
0
0
A10
A11
00
00
BA0,1
DQM
Qai0
Q
D
Daj0 Daj1 Daj2 Daj3
DQM control Write control
19
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is mini-
mum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result,
READ to PRE interval determines valid data length to be output. The figure below shows examples of
BL=4.
Read Interrupted by Precharge (BL=4)
CLK
READ
PRE
Q0
Command
DQ
Q1
Q1
Q2
READ
PRE
Command
DQ
CL=3
Q0
Q0
READ PRE
Command
DQ
READ
PRE
Q1
Command
DQ
Q0
Q2
READ
PRE
Q0
Command
DQ
CL=2
Q1
READ PRE
Command
DQ
Q0
20
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation
and disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly
used to interrupt FP bursts. The figures below show examples, of how the output data is terminated
with TBST.
Read Interrupted by Burst Terminate(BL=4)
CLK
Command
DQ
READ
TBST
Q1
Q0
Q2
Q2
Q3
Command
DQ
READ
TBST
Q0
CL=3
Q1
Command
DQ
READ TBST
Q0
Command
DQ
READ
TBST
Q2
Q0
Q0
Q0
Q1
Q3
CL=2
Command
DQ
READ
TBST
Q1
Q2
Command
DQ
READ TBST
21
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
CLK
Write Write
Write
Yk
Write
Yl
Command
A0-9
Yi
0
Yj
0
0
0
A10
A11
00
00
10
00
BA0,1
DQ
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ
cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Write READ
Write
Yk
READ
Command
A0-9
Yi
0
Yj
0
Yl
0
0
A10
A11
00
00
10
00
BA0,1
DQM
DQ
Dai0
Qaj0 Qaj1
Dbk0 Dbk1
Qal0
22
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random column access is al-
lowed. Write recovery time (tWR) is required from the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Write
Yi
PRE
ACT
Xb
Command
A0-9
tWR
tRP
0
0
Xb
A10
Xb
A11
00
00
00
BA0,1
DQM
DQ
Dai0 Dai1 Dai2
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the waveforms
below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK
WRITE
TBST
Command
A0-9
Yi
0
A10
0
BA
DQMU/DQML
(DQM)
Dai0
Dai1
DQ
Dai2
23
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command.
The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
24
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored,
so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable
CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX.
After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP
commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
tSRX
new command
X
A0-11
BA0,1
00
minimum tRC
+1 CLOCK
for recovery
Self Refresh Entry
Self Refresh Exit
25
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating
CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or
input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be per-
formed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Active Power Down
CKE
Command
ACT
NOP NOP NOP NOP NOP NOP NOP
DQ Suspend by CKE
CLK
CKE
Write
D0
READ
Command
D1
D2
D3
Q0
Q1
Q2
Q3
DQ
26
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
DQM CONTROL
DQMU/L is a dual function signal defined as the data mask for writes and the output disable for reads.
During writes, DQMU/L masks input data word by word. DQMU/L to write mask latency is 0.
During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK
Command
DQMU/L
Write
READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
27
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
Parameter
Conditions
Ratings
-0.5 ~ 4.6
Unit
V
Supply Voltage
with respect to Vss
Supply Voltage for Output with respect to VssQ
-0.5 ~ 4.6
V
Input Voltage
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
with respect to VssQ -0.5 ~ VddQ+0.5
50
V
IO
Output Current
mA
mW
°C
°C
Pd
Power Dissipation
Operating Temperature
Storage Temperature
Ta = 25 °C
1000
0 ~ 70
Topr
Tstg
-65 ~ 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
0
Vdd
Vss
Supply Voltage
Supply Voltage
V
V
V
V
V
V
VddQ
VssQ
Supply Voltage for Output
Supply Voltage for Output
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
3.0
0
3.3
0
3.6
0
VIH
VIL
2.0
-0.3
Vdd+0.3
0.8
Note:*
VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable.
VIL(min) = -2V AC for pulse width<=3ns acceptable.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
min.
max.
5
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Test Condition
VI=Vss
Unit
pF
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
Input Capacitance, I/O pin
2.5
2.5
2.5
4
f=1MHz
5
pF
Vi=25mVrms
pF
4
6.5
pF
28
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, Output Open, unless otherwise noted)
Limits (max)
Symbol
Parameter
Test Conditions
Unit
-8A
-8
-10
Icc1s
Icc1d
Icc2h
Icc2l
operating current, single bank
operating current, dual bank
standby current, CKE=H
mA
mA
mA
mA
mA
mA
tRC=min, tCLK=min, BL=1, CL=3
tRC=90ns, tCLK=min, BL=1, CL=3
all banks idle, tCLK=min
115 115
90
125
22
2
125
22
2
140
25
2
standby current, CKE=L
all banks idle, tCLK=min
Icc3h
Icc3l
active standby current, CKE=H
active standby current, CKE=L
all banks active, tCLK=min
all banks active, tCLK=min
45
2
55
5
55
5
all banks active, tCLK=min, BL=4,
CL=3
Icc4
Icc5
burst current
mA
mA
125 125
115
140
auto-refresh current
tRC=min, tCLK=min
150 150
-8A,-8,-10
CKE <0.2v
-8L,-10L
1
1
1
mA
mA
Icc6
self-refresh current
0.5
0.5
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits
Symbol
Parameter
Test Conditions
Unit
Min.
2.4
Max.
VOH (DC) High-Level Output Voltage (DC) IOH=-2mA
V
V
VOL (DC) Low-Level Output Voltage (DC)
IOL= 2mA
0.4
5
IOZ
II
Off-state Output Current
Input Current
Q floating VO=0 ~ VddQ
VIH = 0 ~ VddQ+0.3V
µA
µA
-5
-5
5
29
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
1.4V
Input Timing Measurement Level:
Limits
-8
Symbol Parameter
-8A
Unit note
-10
Min. Max.
Min.
Max.
Min.
Max.
CL=2
CL=3
12
8
15
10
3
ns
ns
15
10
4
tCLK CLK cycle time
tCH
tCL
tT
CLK High pulse width
CLK Low pulse width
Transition time of CLK
3
ns
1
3
3
ns
4
1
1
10
1
10
10
ns
1
tIS
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
2
2
ns
3
1
tIH
tRC
1
1
ns
ns
ns
ns
ns
ns
ns
ns
1
1
70
20
50
20
10
20
10
72
20
48
20
10
16
8
90
30
60
30
10
20
10
tRCD Row to Column Delay
tRAS Row Active time
100K
100K
100K
tRP
Row Precharge time
Write Recovery time
tWR
tRRD Act to Act Delay time
tCCD Col to Col Delay time
2
Mode Register Set
tRSC
16
8
20
10
ns
20
10
Cycle time
tSRX Self Refresh Exit time
tREF Refresh Interval time
ns
64
64
64
ms
Note:1
2
The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be
added to the parameter.
2 ACT commands are allowed within tRC.
1.4V
CLK
Any AC timing is
referenced to the input
signal crossing through
1.4V 1.4V.
Signal
30
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise notedsee note3)
Limits
Symbol Parameter
-8A
-8
-10
Unit
Min.
Max.
Min.
Max.
Min.
Max.
CL=2
CL=3
8
6
9
6
9
8
ns
ns
tAC
tOH
Access time from CLK
Output Hold time from
CLK
2.5
3
3
ns
Delay time, output low
impedance from CLK
tOLZ
tOHZ
0
0
3
0
3
ns
ns
Delay time, output high
impedance from CLK
2.5
6
6
8
Note:3
If tr(clock rising time) is longer than 1ns, (tT/2-0.5)ns should be added to the parameter.
Output Load Condition
VTT=1.4V
CLK
1.4V
1.4V
50W
VREF =1.4V
DQ
VOUT
50pF
Output Timing
Measurement
Reference Point
CLK
DQ
1.4V
1.4V
tOHZ
tAC
tOH
31
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQMU/L
A0-7
X
X
X
0
Y
X
X
X
0
Y
A10
A8,9,11
BA0,1
DQ
0
0
0
D0
D0 D0
D0
D0 D0
WRITE#0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
Italic parameter indicates minimum case
32
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
tRCD
tRCD
/WE
tWR
tWR
CKE
DQMU/L
A0-7
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A10
A8,9,11
0
1
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0
D0
D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
33
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
tRCD
tRCD
/WE
CKE
DQMU/L
A0-7
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A10
A8,9,11
0
0
0
BA0,1
DQ
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³ BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
34
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQMU/L
A0-7
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
Y
X
X
1
X
A10
X
0
X
A8,9,11
BA0,1
0
1
0
1
2
0
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0
DQ
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
35
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
CKE
DQMU/L
A0-7
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
A10
A8,9,11
0
1
0
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0 D0
D0
D0 D1
ACT#0
ACT#1
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
ACT#1
WRITE#1 with
AutoPrecharge
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
36
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
CKE
DQMU/L
A0-7
DQM read latency =2
Y
X
X
X
0
X
Y
X
Y
X
X
X
Y
X
X
1
X
A10
X
A8,9,11
BA0,1
DQ
0
1
0
0
1
1
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#0
READ#1 with
Auto-Precharge
ACT#1
Italic parameter indicates minimum case
37
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A10
A8,9,11
BA0,1
DQ
0
0
1
0
D0
D0 D0
D0
D0 D0
D0
D0 D1
D1
D1 D1
D0
D0 D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
38
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
DQM read latency=2
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A10
A8,9,11
BA0,1
DQ
0
0
1
0
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
39
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
tCCD
CKE
DQMU/L
A0-7
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
A10
A8,9,11
BA0,1
0
0
0
1
0
CL=3
D0
D0 D0
D0
D0 D0
D1
D1
Q0
Q0
Q0 Q0
DQ
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
40
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
DQM read latency=2
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A10
A8,9,11
BA0,1
DQ
0
0
0
1
0
0
Q0
Q0 Q0
Q0
Q0 Q0
Q1
Q1 Q0
D0 D0
WRITE#0
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
41
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
X
X
X
0
X
Y
Y
X
X
X
1
Y
X
X
1
A10
A8,9,11
BA0,1
DQ
0
1
0
1
1
D0
D0 D0
D0
D1 D1
D1
D1 D1
ACT#0
WRITE#0
PRE#0
ACT#1
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by
Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
42
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQMU/L
A0-7
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A10
A8,9,11
BA0,1
DQ
0
1
0
1
1
Q0
Q0 Q0
Q0
Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
43
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
M
X
X
X
0
Y
A10
A8,9,11
BA0,1
DQ
0
0
D0
D0
D0 D0
Auto-Ref (last of 8 cycles)
Mode
Register
Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case
44
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
X
X
X
0
Y
A10
A8,9,11
BA0,1
DQ
0
D0
D0 D0
D0
Auto-Refresh
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
Before Auto-Refresh,
all banks must be idle state.
Italic parameter indicates minimum case
45
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
CLK can be stopped
tRC
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQMU/L
A0-7
X
X
X
0
A10
A8,9,11
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
46
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQMU/L
A0-7
X
X
X
0
Y
Y
Y
A10
A8,9,11
BA0,1
DQ
0
0
0
masked
masked
D0
D0 D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
47
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM read latency=2
DQMU/L
A0-7
X
X
X
0
Y
Y
Y
A10
A8,9,11
BA0,1
DQ
0
0
0
masked
masked
Q0
Q0 Q0
READ#0
Q0
Q0
Q0
Q0
ACT#0
READ#0
READ#0
Italic parameter indicates minimum case
48
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQMU/L
A0-7
X
X
X
0
A10
A8,9,11
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
49
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
CKE latency=1
CKE latency=1
DQMU/L
A0-7
X
X
X
0
Y
Y
A10
A8,9,11
BA0,1
DQ
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
READ#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
50
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
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Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
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Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
MITSUBISHI ELECTRIC
51
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