M5M51008BKR-70VL [MITSUBISHI]

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM; 1048576 - BIT （ 131072 -字×8位）的CMOS静态RAM


型号：	M5M51008BKR-70VL
厂家：	Mitsubishi Group
描述：	1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM 1048576 - BIT （ 131072 -字×8位）的CMOS静态RAM
文件：	总7页 (文件大小：64K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

DESCRIPTION

The M5M51008BFP,VP,RV,KV,KR are

PIN CONFIGURATION (TOP VIEW)

1048576-bit CMOS

static RAM organized as 131072 word by 8-bit which are

fabricated using high-performance triple polysilicon CMOS

technology. The use of resistive load NMOS cells and CMOS

periphery result in a high density and low power static RAM.

They are low standby current and low operation current and ideal

for the battery back-up application.

The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin

small outline package which is a high reliability and high density

surface mount device(SMD).Two types of devices are available.

VP,KV(normal lead bend type package),RV,KR(reverse lead bend

type package). Using both types of devices, it becomes very easy

to design a printed circuit board.

A16

A14

A12

VCC

A15

ADDRESS

INPUT

CHIP SELECT

INPUT

WRITE CONTROL

INPUT

A13

ADDRESS

INPUTS

ADDRESS

INPUTS

A11

A10

OUTPUT ENABLE

INPUT

ADDRESS

INPUT

CHIP SELECT

INPUT

DQ8

DQ7

DQ6

DQ5

DQ4

FEATURES

DQ1

Power supply current

Access

DATA

INPUTS/

OUTPUTS

DATA

INPUTS/

OUTPUTS

DQ2 14

Active

(1MHz)

(max)

time

Type name

VCC

stand-by

(max)

DQ3

GND

M5M51008BFP,VP,RV,KV,KR-70VL

M5M51008BFP,VP,RV,KV,KR-10VL

M5M51008BFP,VP,RV,KV,KR-12VL

M5M51008BFP,VP,RV,KV,KR-15VL

M5M51008BFP,VP,RV,KV,KR-70VLL

70ns

100ns

120ns

150ns

70ns

3.3±0.3V

3.0±0.3V

3.3±0.3V

3.0±0.3V

60µA

55µA

12µA

11µA

10mA

Outline 32P2M-A

A11

A10

M5M51008BFP,VP,RV,KV,KR-10VLL 100ns

M5M51008BFP,VP,RV,KV,KR-12VLL 120ns

M5M51008BFP,VP,RV,KV,KR-15VLL 150ns

A13

DQ8

DQ7

DQ6

Low stand-by current 0.3µA (typ.)

Directly TTL compatible : All inputs and outputs

A15

DQ5

VCC

DQ4

M5M51008BVP,KV

Easy memory expansion and power down by S1,S2

Data hold on +2V power supply

Three-state outputs : OR - tie capability

OE prevents data contention in the I/O bus

Common data I/O

GND

A16

DQ3

A14

DQ2

A12

DQ1

Package

M5M51008BFP

···········3· 2pin 525mil SOP

M5M51008BVP,RV ···········3·2pin 8 X 20 mm²TSOP

M5M51008BKV,KR ···········3· 2pin 8 X 13.4 mm²TSOP

Outline 32P3H-E(VP), 32P3K-B(KV)

APPLICATION

Small capacity memory units

A12 12

A14 11

DQ1

DQ2

DQ3

GND

DQ4

DQ5

DQ6

DQ7

DQ8

A16

VCC

A15

M5M51008BRV,KR

A13

A10

A11

Outline 32P3H-F(RV), 32P3K-C(KR)

NC : NO CONNECTION

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51008B series are determined by

a combination of the device control inputs S1,S2,W and OE.

Each mode is summarized in the function table.

When setting S1 at a high level or S2 at a low level, the chip are

in a non-selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a high- impedance

state, allowing OR-tie with other chips and memory expansion by

S1 and S2. The power supply current is reduced as low as the

stand-by current which is specified as ICC3 or ICC4, and the

memory data can be held at +2V power supply, enabling battery

back-up operation during power failure or power-down operation in

the non-selected mode.

A write cycle is executed whenever the low level W overlaps with

the low level S1 and the high level S2. The address must be set up

before the write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of W,S1 or

S2,whichever occurs first,requiring the set-up and hold time

relative to these edge to be maintained. The output enable input

OE directly controls the output stage. Setting the OE at a high

level, the output stage is in a high-impedance state, and the data

bus contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a

low level while S1 and S2 are in an active state(S1=L,S2=H).

FUNCTION TABLE

Mode

ICC

S1 S2

Stand-by

Non selection High-impedance

Non selection High-impedance Stand-by

Din

Dout

Active

Write

Read

High-impedance

BLOCK DIAGRAM

DQ1

DQ2

DQ3

131072 WORDS

X 8 BITS

(1024 ROWS

X128 COLUMNS

X 8BLOCKS)

DATA

INPUTS/

OUTPUTS

A12

A14

A16

DQ4

DQ5

DQ6

20 DQ7

21 DQ8

A15 31

A13

ADDRESS

INPUTS

CLOCK

GENERATOR

A10 23

WRITE

CONTROL

INPUT

CHIP

SELECT

INPUTS

A11

OUTPUT

ENABLE

INPUT

A9 26

24 OE

32 VCC

GND

(0V)

* Pin numbers inside dotted line show those of TSOP

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Ratings

Conditions

Unit

Supply voltage

– 0.3*~4.6

– 0.3*~Vcc + 0.3

(Max 4.6)

With respect to GND

Input voltage

Output voltage

V_O

P_d

0~Vcc

700

Power dissipation

Ta=25°C

°C

T_opr

Operating temperature

0~70

Tstg

Storage temperature

– 65~150

°C

* –3.0V in case of AC ( Pulse width £ 30ns )

(Ta=0~70°C, unless otherwise noted)

DC ELECTRICAL CHARACTERISTICS

Limits

-70VL, -70VLL

-10VL, -10VLL

-12VL, -12VLL

-15VL, -15VLL

Unit

Symbol

Parameter

Test conditions

VCC=3.3±0.3V

VCC=3.0±0.3V

Min

Typ

Max

Min

Typ

Max

Vcc

+0.3V

High-level input voltage

Low-level input voltage

VIH

2.0

+0.3V

VIL

–0.3

2.4

0.6

–0.3

2.4

0.6

VOH1

High-level output voltage 1 IOH= –0.5mA

Vcc

-0.5V

Vcc

-0.5V

VOH2

High-level output voltage 2 IOH= –0.05mA

VOL

Low-level output voltage

Input current

IOL=2mA

VI=0~Vcc

0.4

±1

0.4

±1

µA

S1=VIH or S2=VIL or OE=VIH

VI/O=0~VCC

±1

Output current in off-state

±1

µA

Active supply current

(Min cycle )

S1=VIL,S2=VIH,

other inputs=VIH or VIL

Output-open(duty 100%)

ICC1

ICC2

Active supply current

(1MHz)

1) S2 £ 0.2V

2) S1 ³ VCC–0.2V,

S2 ³ VCC–0.2V

-L

ICC3

Stand-by current

µA

-LL

other inputs=0~VCC

S1=VIH or S2=VIL,

other inputs=0~VCC

ICC4

Stand-by current

0.33

* –3.0V in case of AC ( Pulse width £ 30ns )

(Ta=0~70°C, unless otherwise noted)

CAPACITANCE

Limits

Typ

Parameter

Symbol

Test conditions

Unit

Min

Max

Input capacitance

Output capacitance

VI=GND, VI=25mVrms, f=1MHz

VO=GND,VO=25mVrms, f=1MHz

Note 1: Direction for current flowing into an IC is positive (no mark).

2: Typical value is Vcc = 3V, Ta = 25°C

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted )

1TTL

(1) MEASUREMENT CONDITIONS

.................................

VCC

3.3±0.3V(-70VL,-70VLL,-10VL,-10VLL)

3.0±0.3V(-12VL,-12VLL,-15VL,-15VLL)

VIH=2.2V,VIL=0.4V

.............

.....

Input pulse level

including

scope and JIG

Input rise and fall time

5ns

...............

Reference level

VOH=VOL=1.5V

...................

Output loads

Fig.1,CL=100pF (-15VL,-15VLL,)

CL=30pF (-70VL,-10VL,12VL,-70VLL,-10VLL,12VLL)

CL=5pF (for ten,tdis)

Fig.1 Output load

Transition is measured ± 500mV from steady

state voltage. (for ten,tdis)

(2) READ CYCLE

Limits

Symbol

Parameter

-70VL,VLL

-12VL,VLL

-10VL,VLL

-15VL,VLL

Unit

Min

Max

Min

Max

Min

120

Max

Min

150

Max

tCR

Read cycle time

Address access time

100

ta(A)

100

120

150

ta(S1)

ta(S2)

ta(OE)

tdis(S1)

tdis(S2)

tdis(OE)

ten(S1)

Chip select 1 access time

100

Chip select 2 access time

Output enable access time

Output disable time after S1 high

Output disable time after S2 low

Output disable time after OE high

Output enable time after S1 low

Output enable time after S2 high

Output enable time after OE low

Data valid time after address

ten(S2)

ten(OE)

tV(A)

(3) WRITE CYCLE

Limits

Symbol

Parameter

-70VL,VLL

-12VL,VLL

Unit

-10VL,VLL

-15VL,VLL

Min

Max

Min

100

Max

Min

Max

Min

150

100

Max

tCW

Write cycle time

Write pulse width

120

tw(W)

Address setup time

tsu(A)

tsu(A-WH)

tsu(S1)

tsu(S2)

tsu(D)

Address setup time with respect to W

Chip select 1 setup time

Chip select 2 setup time

Data setup time

100

120

th(D)

Data hold time

trec(W)

tdis(W)

tdis(OE)

ten(W)

ten(OE)

Write recovery time

Output disable time from W low

Output disable time from OE high

Output enable time from W high

Output enable time from OE low

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

(4) TIMING DIAGRAMS

Read cycle

tCR

A0~16

ta(A)

tv (A)

ta (S1)

(Note 3)

tdis (S1)

tdis (S2)

ta (S2)

ta (OE)

ten (OE)

(Note 3)

tdis (OE)

ten (S1)

ten (S2)

DQ1~8

DATA VALID

W = "H" level

Write cycle (W control mode)

tCW

A0~16

tsu (S1)

(Note 3)

tsu (S2)

tsu (A-WH)

tsu (A)

tw (W)

trec (W)

tdis (W)

ten(OE)

ten (W)

tdis (OE)

DATA IN

STABLE

DQ1~8

tsu (D)

th (D)

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

Write cycle ( S1 control mode)

tCW

A0~16

tsu (A)

trec (W)

tsu (S1)

(Note 3)

(Note 5)

(Note 4)

(Note 3)

th (D)

tsu (D)

DATA IN

STABLE

DQ1~8

Write cycle (S2 control mode)

tCW

A0~16

(Note 3)

tsu (A)

tsu (S2)

trec (W)

(Note 5)

(Note 4)

(Note 3)

tsu (D)

th (D)

DATA IN

STABLE

DQ1~8

Note 3: Hatching indicates the state is "don't care".

4: Writing is executed while S2 high overlaps S1 and W low.

5: When the falling edge of W is simultaneously or prior to the falling edge of S1

or rising edge of S2, the outputs are maintained in the high impedance state.

6: Don't apply inverted phase signal externally when DQ pin is output mode.

MITSUBISHI

ELECTRIC

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

POWER DOWN CHARACTERISTICS

(1) ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted)

Limits

Typ

Symbol

Parameter

Test conditions

Unit

Min

Max

VCC (PD)

VI (S1)

Power down supply voltage

Chip select input S1

2.0

0.2

VI (S2)

Chip select input S2

VCC = 3V

-L

1) S2 £ 0.2V, other inputs = 0~3V

2) S1 ³ VCC - 0.2V,S2 ³ VCC - 0.2V

other inputs = 0~3V

ICC (PD)

Power down supply current

µA

0.3

-LL

(Note 7)

Note7: ICC (PD) = 1µA in case of Ta = 25°C

(2) TIMING REQUIREMENTS (Ta = 0~70°C, unless otherwise noted )

Limits

Typ

Symbol

Parameter

Test conditions

Unit

Min

Max

tsu (PD)

trec (PD)

Power down set up time

Power down recovery time

(3) POWER DOWN CHARACTERISTICS

S1 control mode

VCC

3.0V*

tsu (PD)

trec (PD)

2.2V

S1 ³ VCC - 0.2V

S2 control mode

VCC

3.0V*

tsu (PD)

trec (PD)

0.2V

S2 £ 0.2V

*Note 2.7V(-12VL,-12VLL,-15VL,-15VLL)

MITSUBISHI

ELECTRIC

M5M51008BKR-70VL [MITSUBISHI]

相关型号：

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