M5M51008CKV-70HI [MITSUBISHI]
Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, TSOP-32;型号: | M5M51008CKV-70HI |
厂家: | Mitsubishi Group |
描述: | Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, TSOP-32 静态存储器 光电二极管 内存集成电路 |
文件: | 总8页 (文件大小:72K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M51008CP,FP,VP,RV,KV,KR are a 1048576-bit CMOS
static RAM organized as 131072 word by 8-bit which are
fabricated using high-performance quadruple-polysilicon and
double metal CMOS technology. The use of thin film transistor
(TFT) load cells and CMOS periphery result in a high density and
low power static RAM.
NC
A16
A14
A12
A7
1
2
32
31
30
29
VCC
A15
S2
ADDRESS
INPUT
CHIP SELECT
INPUT
WRITE CONTROL
INPUT
3
4
W
They are low standby current and low operation current and ideal
for the battery back-up application.
5
28 A13
27
A6
6
A8
ADDRESS
INPUTS
The M5M51008CVP,RV,KV,KR are packaged in a 32-pin thin
small outline package which is a high reliability and high density
surface mount device(SMD). Two types of devices are available.
M5M51008CVP,KV(normal lead bend type package),
M5M51008CRV,KR(reverse lead bend type package).Using both
types of devices, it becomes very easy to design a printed circuit
board.
ADDRESS
INPUTS
A5
7
26 A9
A4
8
25 A11
OUTPUT ENABLE
A3
9
24 OE INPUT
ADDRESS
INPUT
CHIP SELECT
INPUT
A2
10
11
12
23 A10
A1
22
S1
A0
21
20
DQ8
DQ7
DQ1 13
DQ2
DATA
INPUTS/
DATA
INPUTS/
OUTPUTS
14
19 DQ6
FEATURES
OUTPUTS
DQ3 15
GND16
18
DQ5
DQ4
Power supply current
Access
17
Active
(1MHz)
(max)
Type name
time
stand-by
(max)
(max)
Outline 32P4(P), 32P2M-A(FP)
M5M51008CP,FP,VP,RV,KV,KR-55HI
M5M51008CP,FP,VP,RV,KV,KR-70HI
M5M51008CP,FP,VP,RV,KV,KR-55XI
M5M51008CP,FP,VP,RV,KV,KR-70XI
55ns
70ns
55ns
70ns
40µA
A11
A9
1
2
3
4
5
6
7
8
9
32
31
30
OE
A10
S1
(Vcc=5.5V)
15mA
(1MHz)
16µA
(Vcc=5.5V)
0.1µA
A8
A13
W
29 DQ8
(Vcc=3.0V typ)
28
DQ7
27
S2
DQ6
Low stand-by current 0.1µA (typ.)
A15
VCC
NC
26
25
24
23
22
21
20
19
18
17
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A0
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
M5M51008CVP,KV
A16 10
A14
11
Package
A12
12
M5M51008CP
M5M51008CFP
···········3· 2pin 600mil DIP
···········3· 2pin 525mil SOP
A7
13
A6
14
A1
M5M51008CVP,RV ···········3· 2pin 8 X 20 mm2 TSOP
M5M51008CKV,KR ···········3· 2pin 8 X 13.4 mm 2 TSOP
15
A5
A4
A2
16
A3
APPLICATION
Small capacity memory units
Outline 32P3H-E(VP), 32P3K-B(KV)
A4
17
16
15
14
13
12
11
10
9
A3
A5
18 A2
A6
19 A1
A7
20 A0
A12
A14
A16
NC
VCC
A15
S2
21 DQ1
22
DQ2
23
DQ3
24
GND
M5M51008CRV,KR
8
25
DQ4
7
26
27
28
29
30
31
32
DQ5
DQ6
DQ7
DQ8
S1
6
5
W
A13
A8
4
3
2
A9
A10
A11
1
OE
Outline 32P3H-F(RV), 32P3K-C(KR)
NC : NO CONNECTION
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008C series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
When setting S1 at a high level or S2 at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or S2,
whichever occurs first,requiring the set-up and hold time relative to
these edge to be maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level, the output
stage is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
FUNCTION TABLE
Mode
DQ
ICC
S1 S2
W
X
X
L
OE
X
X
H
L
L
Stand-by
Non selection High-impedance
X
H
X
Non selection High-impedance Stand-by
Din
Dout
Active
Active
Active
X
Write
Read
L
L
H
H
H
H
L
H
High-impedance
BLOCK DIAGRAM
*
*
13
14
15
21
22
23
DQ1
8
16
15
14
A4
A5
A6
DQ2
DQ3
7
6
131072 WORDS
X 8 BITS
(512 ROWS
X128 COLUMNS
X 16BLOCKS)
17
18
19
25
26
27
DATA
INPUTS/
OUTPUTS
DQ4
DQ5
DQ6
5
4
13
12
11
A7
A12
A14
A16
A15
A13
3
28
29
20
21
DQ7
DQ8
2
10
7
31
28
4
ADDRESS
INPUTS
CLOCK
GENERATOR
12
11
20
19
A0
A1
10
9
18
17
A2
A3
WRITE
CONTROL
INPUT
29
5
W
23
27
26
25
31
3
A10
A8
30
6
22
30
S1
S2
CHIP
SELECT
INPUTS
2
A9
OUTPUT
ENABLE
INPUT
1
32
8
24
32
16
OE
A11
VCC
GND
(0V)
24
* Pin numbers inside dotted line show those of TSOP
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Conditions
With respect to GND
Unit
V
Supply voltage
Input voltage
V
cc
– 0.3*~7
– 0.3*~Vcc + 0.3
VI
V
Output voltage
Power dissipation
V
VO
Pd
0~Vcc
700
Ta=25°C
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
– 40~85
– 65~150
°C
* –3.0V in case of AC ( Pulse width £ 50ns )
(Ta=– 40~85°C, Vcc=5V±10%, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Unit
Symbol
Parameter
Test conditions
Min
Typ
Max
2.2
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
V
V
Vcc + 0.3
0.8
–0.3*
2.4
IOH= –1.0mA
IOH= –0.1mA
VOH
High-level output voltage
Vcc – 0.5
VOL
II
Low-level output voltage
Input current
IOL=2mA
VI=0~Vcc
0.4
±1
V
µA
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
±1
IO
Output current in off-state
µA
55ns
70ns
80
70
15
85
70
15
2
S1 £ VCC–0.2V, S2 ³ VCC–0.2V
other inputs £ 0.2V or ³ VCC–0.2V
Output-open(duty 100%)
Active supply current
(AC, MOS level)
mA
ICC1
1MHz
55ns
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
Active supply current
(AC, TTL level)
ICC2
mA
70ns
1MHz
~25°C
~40°C
~70°C
~85°C
~25°C
~40°C
~70°C
~85°C
6
-HW
-XW
20
40
1
1) S2 £ 0.2V,
other inputs=0~VCC
2) S1 ³ VCC–0.2V,
S2 ³ VCC–0.2V,
ICC3
Stand-by current
Stand-by current
µA
other inputs=0~VCC
3
8
16
S1=VIH or S2=VIL,
other inputs=0~VCC
mA
ICC4
3
* –3.0V in case of AC ( Pulse width £ 50ns )
(Ta=– 40~85°C, Vcc=5V±10% unless otherwise noted)
Parameter
CAPACITANCE
Limits
Typ
Symbol
Test conditions
Unit
Min
Max
6
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
10
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=– 40~85°C, 5V±10% unless otherwise noted )
(1) MEASUREMENT CONDITIONS
VCC
...............
......
Input pulse level
VIH=2.4V,VIL=0.6V (-70HI,-70XI)
VIH=3.0V,VIL=0.0V (-55HI,-55XI)
5ns
1.8kW
Input rise and fall time
................
Reference level
VOH=VOL=1.5V
DQ
.....................
Output loads
Fig.1, CL=30pF (-55HW,-70HW,-55XW,-70XW)
CL=5pF (for ten,tdis)
990W
CL ( Including scope
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
Parameter
-55HI,-55XI
-70HI,-70XI
Unit
Min
55
Max
Min
70
Max
tCR
Read cycle time
Address access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
55
55
55
30
20
20
20
70
70
70
35
25
25
25
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
5
10
ten(S2)
ten(OE)
tV(A)
5
5
10
5
5
10
(3) WRITE CYCLE
Limits
-70HI,-70XI
Symbol
Parameter
-55HI,-55XI
Unit
Min
Max
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Write cycle time
Write pulse width
55
45
0
70
55
0
tw(W)
Address setup time
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
50
50
50
25
0
65
65
65
30
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
Output disable time from W low
Output disable time from OE high
Output enable time from W high
20
20
25
25
5
5
5
5
Output enable time from OE low
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
(Note 3)
tdis (OE)
(Note 3)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~16
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tsu (S2)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
W
tdis (W)
ten(OE)
ten (W)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~16
tsu (A)
trec (W)
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 5)
W
(Note 4)
(Note 3)
th (D)
tsu (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~16
S1
(Note 3)
(Note 3)
tsu (A)
tsu (S2)
trec (W)
S2
W
(Note 5)
(Note 4)
(Note 3)
(Note 3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI
ELECTRIC
6
MITSUBISHI LSIs
M5M51008CP,FP,VP,RV,KV,KR -55HI, -70HI,
-55XI, -70XI
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta=– 40~85°C, unless otherwise noted)
Limits
Typ
Symbol
VCC (PD)
VI (S1)
Parameter
Power down supply voltage
Chip select input S1
Test conditions
Unit
V
Min
2.0
2.2
Max
2.2V£Vcc(PD)
V
V
Vcc(PD)
2V£Vcc(PD)£2.2V
4.5V£Vcc(PD)
Vcc(PD)<4.5V
0.8
0.2
VI (S2)
Chip select input S2
~25°C
~40°C
~70°C
1
3
-HI
-XI
VCC = 3V
1) S2 £ 0.2V,
other inputs = 0~3V
2) S1 ³ VCC–0.2V,
S2 ³ VCC–0.2V
other inputs = 0~3V
10
20
~85°C
~25°C
~40°C
~70°C
~85°C
ICC (PD)
Power down supply current
µA
0.5
1.5
4
8
(2) TIMING REQUIREMENTS (Ta=– 40~85°C, unless otherwise noted )
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
5
ms
(3) POWER DOWN CHARACTERISTICS
S1 control mode
VCC
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
S1
S1 ³ VCC – 0.2V
S2 control mode
VCC
4.5V
4.5V
S2
tsu (PD)
trec (PD)
0.2V
0.2V
S2 £ 0.2V
MITSUBISHI
ELECTRIC
7
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MITSUBISHI ELECTRIC 8
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