M5M51008DKV-70H [MITSUBISHI]
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM; 1048576 - BIT ( 131072 -字×8位)的CMOS静态RAM型号: | M5M51008DKV-70H |
厂家: | Mitsubishi Group |
描述: | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
文件: | 总8页 (文件大小:63K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M51008DP,FP,VP,RV,KV are a 1048576-bit CMOS static
RAM organized as 131072 word by 8-bit which are fabricated using
high-performance quadruple-polysilicon and double metal CMOS
technology. The use of thin film transistor (TFT) load cells and
CMOS periphery result in a high density and low power static
RAM.
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
31
30
29
VCC
ADDRESS
A15 INPUT
CHIP SELECT
S2
W
INPUT
WRITE CONTROL
INPUT
They are low standby current and low operation current and ideal
for the battery back-up application.
28 A13
27
The M5M51008DVP,RV,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD). Two types of devices are available.
M5M51008DVP(normal lead bend type package),
A6
A8
ADDRESS
INPUTS
ADDRESS
INPUTS
A5
26 A9
A4
25 A11
24 OE
23 A10
M5M51008DRV(reverse lead bend type package).Using both types
of devices, it becomes very easy to design a printed circuit board.
OUTPUT ENABLE
INPUT
A3
ADDRESS
INPUT
CHIP SELECT
INPUT
A2 10
A1
11
22
S1
A0 12
DQ1 13
21
20
DQ8
DQ7
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
DQ2
14
19 DQ6
FEATURES
DQ3 15
GND16
18
DQ5
Power supply current
Access
17
DQ4
Active
(1MHz)
(max)
Type name
time
stand-by
(max)
(max)
Outline 32P2M-A(FP)
M5M51008DFP,VP,RV,KV-55H
M5M51008DFP,VP,RV,KV-70H
55ns
70ns
20µA
15mA
(1MHz)
A11
A9
1
2
3
4
5
6
7
8
9
32
31
30
OE
A10
S1
(Vcc=5.5V)
A8
A13
W
29 DQ8
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
28
DQ7
27
S2
DQ6
A15
VCC
NC
26
25
24
23
22
21
20
19
18
17
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A0
M5M51008DVP,KV
Package
A16 10
M5M51008DFP
···········3· 2pin 525mil S2OP
A14
11
M5M51008DVP,RV ···········3· 2pin 8 X 20 mm TSOP
2
M5M51008DKV
···········3· 2pin 8 X 13.4 mm TSOP
A12
12
A7
13
A6
14
A1
15
A5
A2
A4
16
A3
APPLICATION
Small capacity memory units
Outline 32P3H-E(VP), 32P3K-B(KV)
A4
16
17
A3
A5
15
18 A2
A6
14
19 A1
20 A0
21 DQ1
A7
13
A12
12
A14
11
22
DQ2
A16
10
23
DQ3
NC
9
24
GND
M5M51008DRV
VCC
8
25
DQ4
A15
S2
7
6
5
4
3
2
1
26
27
28
29
30
31
32
DQ5
DQ6
DQ7
DQ8
S1
W
A13
A8
A9
A10
A11
OE
Outline 32P3H-F(RV)
NC : NO CONNECTION
MITSUBISHI
ELECTRIC
1
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008D series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
When setting S1 at a high level or S2 at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
FUNCTION TABLE
Mode
DQ
ICC
S1 S2
W
X
X
L
OE
X
X
H
L
L
Stand-by
Non selection High-impedance
X
H
X
Non selection High-impedance Stand-by
Din
Dout
Active
Active
Active
X
Write
Read
L
L
H
H
H
H
L
H
High-impedance
BLOCK DIAGRAM
*
*
DQ1
13
14
15
21
22
23
A3
9
17
18
15
DQ2
DQ3
A2 10
131072 WORDS
X 8 BITS
(512 ROWS
X128 COLUMNS
X 16BLOCKS)
A5
7
DATA
INPUTS/
OUTPUTS
17
18
19
25
26
27
DQ4
DQ5
DQ6
A6
A7
6
5
14
13
12
11
10
7
A12
A14
A16
A15
4
28
29
20 DQ7
21 DQ8
3
2
31
ADDRESS
INPUTS
CLOCK
GENERATOR
A13
A8
28
27
26
25
4
3
2
1
A9
A11
WRITE
CONTROL
INPUT
29
W
5
A4
8
16
19
20
31
30
6
22
30
S1
S2
CHIP
SELECT
INPUTS
A1 11
A0
12
A10 23
OUTPUT
ENABLE
INPUT
32
8
24 OE
32 VCC
GND
(0V)
16
24
* Pin numbers inside dotted line show those of TSOP
MITSUBISHI
ELECTRIC
2
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Conditions
With respect to GND
Unit
V
Supply voltage
Input voltage
V
cc
– 0.3*~7
– 0.3*~Vcc + 0.3
VI
V
Output voltage
Power dissipation
V
VO
Pd
0~Vcc
700
Ta=25°C
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
0~70
– 65~150
°C
* –3.0V in case of AC ( Pulse width £ 50ns )
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Test conditions
DC ELECTRICAL CHARACTERISTICS
Limits
Unit
Symbol
Parameter
Min
Typ
Max
2.2
–0.3*
2.4
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
V
V
Vcc + 0.3
0.8
IOH= –1.0mA
IOH= –0.1mA
VOH
High-level output voltage
Vcc – 0.5
VOL
II
Low-level output voltage
Input current
IOL=2mA
VI=0~Vcc
0.4
±1
V
µA
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
±1
IO
Output current in off-state
µA
55ns
70ns
39
34
4
80
70
15
85
70
15
2
S1 £ 0.2V, S2 ³ VCC–0.2V
other inputs £ 0.2V or ³ VCC–0.2V
Output-open(duty 100%)
Active supply current
(AC, MOS level)
mA
ICC1
1MHz
55ns
42
37
5
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
Active supply current
(AC, TTL level)
ICC2
mA
70ns
1MHz
1) S2 £ 0.2V,
~25°C
-H ~40°C
~70°C
other inputs=0~VCC
2) S1 ³ VCC–0.2V,
S2 ³ VCC–0.2V,
6
ICC3
ICC4
Stand-by current
Stand-by current
µA
20
other inputs=0~VCC
S1=VIH or S2=VIL,
other inputs=0~VCC
mA
3
* –3.0V in case of AC ( Pulse width £ 50ns )
(Ta=0~70°C, Vcc=5V±10% unless otherwise noted)
Parameter
CAPACITANCE
Limits
Typ
Symbol
Test conditions
Unit
Min
Max
Input capacitance
Output capacitance
FP,VP,RV,KV
FP,VP,RV,KV
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
8
10
pF
pF
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
MITSUBISHI
ELECTRIC
3
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, 5V±10% unless otherwise noted )
(1) MEASUREMENT CONDITIONS
VCC
...............
Input pulse level
VIH=2.4V,VIL=0.6V (-70H)
VIH=3.0V,VIL=0.0V (-55H)
5ns
......
1.8kW
Input rise and fall time
................
Reference level
VOH=VOL=1.5V
DQ
.....................
Output loads
Fig.1, CL=100pF (-70H)
CL=30pF (-55H)
990W
CL ( Including scope
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
and JIG )
Fig.1 Output load
(2) READ CYCLE
Limits
-70H
Symbol
Parameter
-55H
Unit
Min
55
Max
Min
70
Max
tCR
Read cycle time
Address access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
55
55
55
30
20
20
20
70
70
70
35
25
25
25
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
5
10
ten(S2)
ten(OE)
tV(A)
5
5
10
5
5
10
(3) WRITE CYCLE
Limits
Symbol
Parameter
-55H
-70H
Unit
Min
55
45
0
Max
Min
70
50
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Write cycle time
Write pulse width
tw(W)
Address setup time
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
50
50
50
25
0
55
55
55
30
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
20
20
25
25
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
5
5
5
5
MITSUBISHI
ELECTRIC
4
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
(Note 3)
tdis (OE)
(Note 3)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~16
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tsu (S2)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
W
tdis (W)
ten(OE)
ten (W)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~16
tsu (A)
trec (W)
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 5)
W
(Note 4)
(Note 3)
th (D)
tsu (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~16
S1
(Note 3)
(Note 3)
tsu (A)
tsu (S2)
trec (W)
S2
W
(Note 5)
(Note 4)
(Note 3)
(Note 3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI
ELECTRIC
6
Ver. 1.1
MITSUBISHI LSIs
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, unless otherwise noted)
Test conditions
Limits
Typ
Symbol
VCC (PD)
VI (S1)
Parameter
Power down supply voltage
Chip select input S1
Unit
V
Min
2.0
2.2
Max
2.2V£Vcc(PD)
2V£Vcc(PD)£2.2V
4.5V£Vcc(PD)
Vcc(PD)<4.5V
VCC = 3V
V
V
Vcc(PD)
0.8
0.2
1
VI (S2)
Chip select input S2
~25°C
~40°C
~70°C
1) S2 £ 0.2V, other inputs = 0~3V
2) S1 ³ VCC–0.2V,S2 ³ VCC–0.2V
other inputs = 0~3V
-H
3
µA
ICC (PD)
Power down supply current
10
(2) TIMING REQUIREMENTS (Ta=0~70°C, unless otherwise noted )
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
5
ms
(3) POWER DOWN CHARACTERISTICS
S1 control mode
VCC
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
S1
S1 ³ VCC – 0.2V
Note 7: On the power down mode by controlling S1,the input level of S2 must be S2 ³ Vcc - 0.2V or
S2 £ 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state.
S2 control mode
VCC
4.5V
4.5V
S2
tsu (PD)
trec (PD)
0.2V
0.2V
S2 £ 0.2V
MITSUBISHI
ELECTRIC
7
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8
MITSUBISHI ELECTRIC
相关型号:
M5M51008DRV-55HI#BT
128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 20 MM, LEAD FREE, REVERSE, TSOP-32
RENESAS
M5M51008DRV-70H#BT
128KX8 STANDARD SRAM, 70ns, PDSO32, 8 X 20 MM, LEAD FREE, REVERSE, TSOP-32
RENESAS
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