M5M51008KV-10LL [MITSUBISHI]
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM; 1048576 - BIT （ 131072 -字×8位）的CMOS静态RAM
| 型号： | M5M51008KV-10LL |
| 厂家： | 
Mitsubishi Group |
| 描述： | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| 文件： | 总7页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M51008BP,FP,VP,RV,KV,KR are a 1048576-bit CMOS
static RAM organized as 131072 word by 8-bit which are
fabricated using high-performance triple polysilicon CMOS
technology. The use of resistive load NMOS cells and CMOS
periphery result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin
small outline package which is a high reliability and high density
surface mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy
to design a printed circuit board.
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
VCC
A15
S2
ADDRESS
INPUT
CHIP SELECT
INPUT
WRITE CONTROL
INPUT
3
4
W
5
A13
A8
6
A6
ADDRESS
INPUTS
ADDRESS
INPUTS
7
A5
A9
8
A4
A11
OE
A10
OUTPUT ENABLE
INPUT
9
A3
ADDRESS
10
11
12
13
A2
INPUT
CHIP SELECT
INPUT
A1
S1
A0
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
DQ1
Power supply current
DATA
INPUTS/
OUTPUTS
DATA
INPUTS/
OUTPUTS
Access time
(max)
DQ2 14
Active
(1MHz)
(max)
Type name
stand-by
(max)
15
DQ3
16
GND
M5M51008BP,FP,VP,RV,KV,KR-55L
M5M51008BP,FP,VP,RV,KV,KR-70L
M5M51008BP,FP,VP,RV,KV,KR-10L
M5M51008BP,FP,VP,RV,KV,KR-55LL
M5M51008BP,FP,VP,RV,KV,KR-70LL
M5M51008BP,FP,VP,RV,KV,KR-10LL
55ns
70ns
100µA
15mA
15mA
Outline 32P4(P), 32P2M-A(FP)
(Vcc=5.5V)
100ns
55ns
20µA
(Vcc=5.5V)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
OE
A10
S1
70ns
2
A9
0.3µA
(Vcc=3.0V,typ)
100ns
3
A8
4
A13
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A0
Single +5V power supply
Low stand-by current 0.3µA (typ.)
5
W
6
S2
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
7
A15
8
VCC
M5M51008BVP,KV
9
NC
10
A16
11
A14
12
Package
A12
M5M51008BP
M5M51008BFP
M5M51008BVP,RV ···········3·2pin 8 X 20 mm2 TSOP
M5M51008BKV,KR ···········3· 2pin 8 X 13.4 mm2 TSOP
···········3· 2pin 600mil DIP
···········3· 2pin 525mil SOP
13
A7
14
A6
A1
15
A5
A2
16
A4
A3
APPLICATION
Small capacity memory units
Outline 32P3H-E(VP), 32P3K-B(KV)
A4
A5
A6
A7
17
18
19
20
21
22
23
16
15
14
13
A3
A2
A1
A0
A12 12
A14 11
DQ1
DQ2
DQ3
GND
DQ4
DQ5
DQ6
DQ7
DQ8
S1
A16
NC
VCC
A15
S2
10
9
24
M5M51008BRV,KR
8
25
26
27
28
29
30
31
32
7
6
5
W
4
A13
A8
3
2
A9
A10
OE
1
A11
Outline 32P3H-F(RV), 32P3K-C(KR)
NC : NO CONNECTION
1
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M51008B series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
When setting S1 at a high level or S2 at a low level, the chip are
in a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the
memory data can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation in
the non-selected mode.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
FUNCTION TABLE
Mode
DQ
ICC
S1 S2
W
X
X
L
OE
X
X
H
L
L
Stand-by
Non selection High-impedance
X
H
X
Non selection High-impedance Stand-by
Din
Dout
Active
Active
Active
X
Write
Read
L
L
H
H
H
H
L
H
High-impedance
BLOCK DIAGRAM
*
*
DQ1
A4
A5
A6
8
16
15
14
21
22
23
13
14
15
7
6
DQ2
DQ3
131072 WORDS
X 8 BITS
(1024 ROWS
X128 COLUMNS
X 8BLOCKS)
DATA
INPUTS/
OUTPUTS
A7
A12
A14
A16
5
4
3
2
13
12
11
25
26
27
17
18
19
DQ4
DQ5
DQ6
10
7
28
29
20 DQ7
21 DQ8
A15 31
4
28
27
A13
A8
3
ADDRESS
INPUTS
CLOCK
GENERATOR
A0
A2
12
10
20
18
A3
9
17
31
A10 23
WRITE
CONTROL
INPUT
5
29
W
30
6
22
30
S1
S2
CHIP
SELECT
INPUTS
A1
11
25
19
1
A11
OUTPUT
ENABLE
INPUT
A9 26
2
32
8
24 OE
32 VCC
GND
(0V)
16
24
* Pin numbers inside dotted line show those of TSOP
2
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Ratings
Conditions
With respect to GND
Unit
V
Supply voltage
Input voltage
V
cc
– 0.3*~7
– 0.3*~Vcc + 0.3
VI
V
Output voltage
Power dissipation
V
VO
Pd
0~Vcc
700
Ta=25°C
mW
°C
Topr
Operating temperature
0~70
Tstg
Storage temperature
– 65~150
°C
* –3.0V in case of AC ( Pulse width £ 30ns )
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Test conditions
DC ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Unit
V
Min
2.2
Typ
Max
Vcc
+0.3V
High-level input voltage
Low-level input voltage
VIH
V
V
–0.3*
2.4
0.8
VIL
VOH1
High-level output voltage 1 IOH= –0.5mA
Vcc
-0.5V
VOH2
High-level output voltage 2 IOH= –0.05mA
V
VOL
II
Low-level output voltage
Input current
IOL=2mA
VI=0~Vcc
0.4
±1
V
µA
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
±1
IO
Output current in off-state
µA
35
70
Min
cycle
S1£0.2V,S2³ Vcc–0.2V,
other inputs£0.2V or ³ Vcc–0.2V
Output-open(duty 100%)
Active supply current
(AC, MOS level)
ICC1
(40)** (80)**
mA
4
15
70
1MHz
38
Min
cycle
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
Active supply current
(AC, TTL level)
ICC2
(43)** (85)**
mA
15
1MHz
-L
5
1) S2 £ 0.2V
2) S1 ³ VCC–0.2V,
S2 ³ VCC–0.2V
100
ICC3
ICC4
Stand-by current
Stand-by current
µA
-LL
20
3
other inputs=0~VCC
S1=VIH or S2=VIL,
other inputs=0~VCC
mA
* –3.0V in case of AC ( Pulse width £ 30ns )
** inside ( ) is a value of -55L,-55LL
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Parameter
CAPACITANCE
Limits
Typ
Symbol
Test conditions
Unit
Min
Max
6
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
8
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
3
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
VCC
(1) MEASUREMENT CONDITIONS
Input pulse level ·············· IVH=2.4V,VIL=0.6V (-70L,-10L,-70LL,-10LL)
VIH=3.0V,VIL=0.0V (-55L,-55LL)
1.8kW
Input rise and fall time ····· 5ns
Reference level ················OVH=VOL=1.5V
Output loads ····················· Fig.1L,=C100pF (-10L,-10LL,)
CL=30pF (-55L,-70L,-55LL,-70LL)
DQ
990W
CL ( Including scope
and JIG )
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
-70L,LL
Symbol
Parameter
Read cycle time
-55L,LL
-10L,LL
Unit
Min
55
Max
Min
70
Max
Min
Max
tCR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
ta(A)
Address access time
55
70
70
70
35
25
25
25
100
100
100
50
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
Chip select 1 access time
55
55
30
20
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
35
20
20
35
35
10
10
10
5
5
5
5
5
ten(S2)
ten(OE)
tV(A)
10
5
10
10
(3) WRITE CYCLE
Limits
-70L,LL
Symbol
Parameter
Unit
-55L,LL
-10L,LL
Min
55
45
0
Max
Min
Max
Min
100
75
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Write cycle time
Write pulse width
70
55
0
tw(W)
Address setup time
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
50
50
50
25
0
65
65
65
30
0
85
85
85
40
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
0
Output disable time from W low
Output disable time from OE high
Output enable time from W high
20
20
25
25
35
35
5
5
5
5
5
5
Output enable time from OE low
4
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
(Note 3)
(Note 3)
tdis (OE)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~16
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tsu (S2)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
W
tdis (W)
ten(OE)
ten (W)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
5
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~16
tsu (A)
trec (W)
tsu (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 5)
W
(Note 4)
(Note 3)
th (D)
tsu (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~16
S1
(Note 3)
(Note 3)
tsu (A)
tsu (S2)
trec (W)
S2
W
(Note 5)
(Note 4)
(Note 3)
(Note 3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
6
MITSUBISHI
ELECTRIC
1997-3/25
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, unless otherwise noted)
Limits
Typ
Symbol
VCC (PD)
VI (S1)
Parameter
Power down supply voltage
Chip select input S1
Test conditions
Unit
V
Min
2
Max
2.2V £ Vcc(PD)
2.2
V
Vcc(PD)
2V £ Vcc(PD) £2.2V
4.5V £ Vcc(PD)
0.8
0.2
V
VI (S2)
Chip select input S2
Vcc(PD) < 4.5V
VCC = 3V
50
-L
1) S2 £ 0.2V, other inputs = 0~3V
2) S1 ³ VCC - 0.2V,S2 ³ VCC - 0.2V
other inputs = 0~3V
ICC (PD)
Power down supply current
µA
10
0.3
-LL
(Note 7)
Note7: ICC (PD) = 1µA in case of Ta = 25°C
(2) TIMING REQUIREMENTS (Ta = 0~70°C, unless otherwise noted )
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
5
ms
(3) POWER DOWN CHARACTERISTICS
S1 control mode
VCC
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
S1
S1 ³ VCC - 0.2V
S2 control mode
VCC
4.5V
4.5V
S2
tsu (PD)
trec (PD)
0.2V
0.2V
S2 £ 0.2V
7
MITSUBISHI
ELECTRIC
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