M5M512R88DJ-15 [MITSUBISHI]
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM; 1048576 - BIT ( 131072 -字×8位)的CMOS静态RAM型号: | M5M512R88DJ-15 |
厂家: | Mitsubishi Group |
描述: | 1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM |
文件: | 总6页 (文件大小:65K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
1998.6.18 Ver.A
M5M512R88DJ-10,-12,-15
P RELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M512R88DJ is a family of 131072-word by 8-bit
static RAMs, fabricated with the high performance CMOS
silicon gate process and designed for high speed
application.
A0
A1
A2
A3
S
1
2
32
31
30
A16
A15
A14
inputs
inputs
3
4
5
29
28
27
A13
OE
output enable
input
These devices operate on a single 3.3V supply, and are
directly TTL compatible. They include a power down
feature as well.
chip select
input
data
inputs/ DQ1
DQ2
6
7
8
DQ8
DQ7
GND
VCC
DQ6
DQ5
A12
data
outputs
inputs/
26
25
24
outputs
(3.3V)
(0V)
VCC
GND
DQ3 10
DQ4
(0V)
FEATURES
•Fast access time
9
(3.3V)
data
inputs/
outputs
data
23
22
21
M5M512R88DJ-10 ... 10ns(max)
M5M512R88DJ-12 ... 12ns(max)
M5M512R88DJ-15 ... 15ns(max)
inputs/
outputs
11
W
A4 13
12
write control
input
•Low power dissipation
Active .................... 297mW(typ)
20
19
A11
A10
A5
14
inputs
inputs
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
A6
A7 16
15
18 A9
17 A8
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
Outline 32P0K
PACKAGE
M5M512R88DJ
APPLICATION
High-speed memory units
: 32pin 400mil SOJ
BLOCK DIAGRAM
6
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
A0
1
2
7
A1
A2
10
11
22
23
3
MEMORY ARRAY
512 ROWS
2048 COLUMNS
A3
A4
A5
4
inputs
13
14
15
16
17
26 DQ7
A6
A7
A8
DQ8
27
data
inputs/
outputs
COLUMN I/O CIRCUITS
S
5
COLUMN ADDRESS
DECODERS
8
VCC(3.3V)
GND(0V)
W
12
24
COLUMN INPUT BUFFERS
9
OE 28
25
18 19 20
21
29 30 31 32
A9 A10 A11 A12 A13 A14 A15 A16
inputs
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
contention problem in the write cycle is eliminated.
A read cycle is excuted by setting W at a high level and
OE at a low level while S are in an active state (S=L).
When setting S at high level, the chip is in a non-
selectable mode in which both reading and writing are
disable. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S.
The operation mode of the M5M512R88DJ is determined by
a combination of the device control inputs S, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set-up
before the write cycle and must be stable during the entire
cycle.
The data is latched into a cell on the trailing edge of W or
S, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable
input OE directly controls the output stage. Setting the OE at
a high level, the output stage is in a high impedance state,
and the data bus
Signal-S controls the power-down feature. When S goes
high, power dissapation is reduced extremely. The access
time from S is equivalent to the address access time.
FUNCTION TABLE
Mode
Non selection
Write
DQ
High-impedance
Din
Icc
S
H
L
W
X
L
OE
Stand by
Active
Active
X
X
Dout
L
H
L
Read
L
High-impedance
Active
H
H
ABSOLUTE MAXIMUM RATINGS
Parameter
Conditions
With respect to GND
Ta=25°C
Ratings
Unit
V
Symbol
*
Vcc
Supply voltage
- 2.0 ~ 4.6
*
VI
Input voltage
V
V
- 2.0 ~ VCC+0.5
*
VO
Output voltage
- 2.0 ~ VCC
Pd
Power dissipation
Operating temperature
Storage temperature(bias)
Storage temperature
1000
0 ~ 70
mW
°C
Topr
Tstg(bias)
- 10 ~ 85
- 65 ~ 150
°C
°C
T
stg
* Pulse width£5ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS (Ta=0 ~ 70°C, Vcc=3.3V +10% ,unless otherwise noted)
- 5%
Limits
Symbol
Parameter
Condition
Unit
Typ
Max
Min
2.0
VIH
VIL
VOH
VOL
II
V
V
V
V
uA
High-level input voltage
Low-level input voltage
High-level output voltage OH= - 4mA
Low-level output voltage IOL = 8mA
Vcc+0.3
0.8
I
2.4
0.4
2
Input current
VI= 0 ~ Vcc
VI(S)=VIH
VI/O= 0 ~ Vcc
IOZ
Output current in off-state
2
uA
10ns cycle
12ns cycle
15ns cycle
180
170
160
100
60
55
50
30
VI(S)=VIL
other inpus=VIH or VIL
Output-open(duty 100%)
Active supply current
(TTL level)
AC
DC
AC
DC
mA
ICC1
90
10ns cycle
12ns cycle
15ns cycle
Stand by current
(TTL level)
mA
mA
ICC2
VI(S)=VIH
VI(S)=Vcc³ 0.2V
other inputs VI£0.2V
or VI ³ Vcc - 0.2V
ICC3 Stand by current
10
Note 1: Direction for current flowing into an IC is positive (no mark).
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
CAPACITANCE (Ta=0~70°C, Vcc=3.3V+10% ,unless otherwise noted)
-5%
Limit
Typ
Unit
Symbol
Parameter
Test Condition
Min
Max
6
pF
pF
CI
Input capacitance
Output capacitance
V I =GND,V I =25mVrms,f=1MHz
VO=25mVrms,f=1MHz
VO=GND,
8
CO
Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V +10% ,unless otherwise noted)
-5%
(1)MEASUREMENT CONDITION
Input pulse levels .................................... VIH=3.0V, VIL=0.0V
Input rise and fall time .................................................... 3ns
Input timing reference levels ........................ VIH=1.5V, VIL=1.5V
Output timing reference levels ................. VOH =1.5V, VOL=1.5V
Output loads ........................................................ Fig.1,Fig.2
5.0V
Z0=50W
OUTPUT
480W
DQ
DQ
5pF
(including
scope and JIG)
255W
RL=50W
VL=1.5V
Fig.1 Output load
Fig.2 Output load for ten, tdis
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(2)READ CYCLE
Limits
M5M512R88DJ -10
M5M512R88DJ -12
M5M512R88DJ -15
Symbol
Parameter
Unit
Min
10
Max
Min
12
Max
Min
15
Max
Read cycle time
tCR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
Address access time
12
12
6
10
10
5
15
15
7
ta(S)
Chip select access time
Output enable access time
Output disable time after S high
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tv(A)
5
0
6
0
0
4
3
4
0
7
0
0
4
3
4
0
Output disable time after OE high
Output enable time after S low
5
6
7
0
4
3
Output enable time after OE low
Data valid time after address change
Power-up time after chip selection
Power-down time after chip selection
4
0
tPU
tPD
12
15
10
(3)WRITE CYCLE
Limits
M5M512R88DJ -10
M5M512R88DJ -12
M5M512R88DJ -15
Parameter
Symbol
Unit
ns
Min
10
Max
Min
Max
Min
Max
Write cycle time
tCW
12
10
15
12
Write pulse width
Address setup time(W)
tw
ns
ns
ns
9
0
0
9
5
0
0
0
0
0
tsu(A)1
0
0
0
0
Address setup time(S)
tsu(A)2
Chip select setup time
Data setup time
ns
ns
ns
ns
ns
ns
ns
tsu(S)
tsu(D)
10
6
12
7
th(D)
Data hold time
0
0
trec(W)
tdis(W)
Write recovery time
0
0
Output disable time after W low
Output disable time after OE high
Output enable time after W high
5
5
0
0
6
6
0
0
7
7
tdis(OE)
ten(W)
0
0
ten(OE)
Output enable time after OE low
ns
ns
0
9
0
0
12
tsu(A-WH) Address to W High
10
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
t CR
VIH
A
0~16
VIL
ta(A)
tv(A)
tv(A)
DATA VALID
VOH
VOL
DQ1~8
PREVIOUS DATA VALID
UNKNOWN
W=H
S=L
OE=L
Read cycle 2 (Note 3)
t CR
VIH
S
VIL
(Note 4)
ta(S)
(Note 4)
tdis(S)
ten(S)
VOH
DQ1~8
UNKNOWN
DATA VALID
VOL
tPU
tPD
ICC1
50%
50%
Icc
ICC2
W=H
OE=L
Note 3. Addresses valid prior to or coincident with S transition low.
4. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5)
t CR
VIH
VIL
OE
(Note 4)
tdis(OE)
ta(OE)
ten(OE)
(Note 4)
VOH
VOL
UNKNOWN
DATA VALID
DQ1~8
W=H
S=L
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
MITSUBISHI
ELECTRIC
5
MITSUBISHI LSIs
M5M512R88DJ-10,-12,-15
1048576-BIT (131072-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (W control mode)
tCW
VIH
A
S
0~16
VIL
tsu(S)
VIH
VIL
(Note 6)
(Note 6)
tsu(A-WH)
VIH
VIL
OE
W
tsu(A)
tw(W)
trec(W)
th(D)
VIH
VIL
tsu(D)
VIH
VIL
DQ1~8
(Input Data)
DATA STABLE
(Note 4)
tdis(W)
(Note 4)
ten(OE)
ten(W)
tdis(OE)
VOH
VOL
DQ1~8
(Output Data)
Hi-Z
Write cycle(S control)
tCW
VIH
VIL
A0~16
tsu(S)
trec(W)
tsu(A)
VIH
VIL
S
tw(W)
VIH
VIL
W
(Note 6)
(Note 6)
tsu(D)
th(D)
VIH
VIL
DQ1~8
(Input Data)
DATA STABLE
tdis(W)
(Note 4)
ten(S)
(Note 4)
VOH
VOL
Hi-Z
DQ1~8
(Output Data)
(Note 7)
Note 6: Hatching indicates the state is don't care.
7: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.
8: ten,tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
6
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