M5M5256DRV-12VXL
更新时间：2024-09-18 02:15:26
品牌：MITSUBISHI
描述：262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
概述
规格参数
数据手册M5M5256DRV-12VXL 概述
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM 262144 - BIT （ 32768 -字×8位）的CMOS静态RAM SRAM
M5M5256DRV-12VXL 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | TSOP | 包装说明： | TSOP1-R, TSSOP28,.53,22 |
| 针数： | 28 | Reach Compliance Code： | unknown |
| ECCN代码： | EAR99 | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.81 | 最长访问时间： | 120 ns |
| I/O 类型： | COMMON | JESD-30 代码： | R-PDSO-G28 |
| JESD-609代码： | e0 | 长度： | 11.8 mm |
| 内存密度： | 262144 bit | 内存集成电路类型： | STANDARD SRAM |
| 内存宽度： | 8 | 功能数量： | 1 |
| 端口数量： | 1 | 端子数量： | 28 |
| 字数： | 32768 words | 字数代码： | 32000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 70 °C |
| 最低工作温度： | 组织： | 32KX8 | |
| 输出特性： | 3-STATE | 可输出： | YES |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TSOP1-R |
| 封装等效代码： | TSSOP28,.53,22 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, THIN PROFILE | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 电源： | 3/3.3 V |
| 认证状态： | Not Qualified | 反向引出线： | YES |
| 座面最大高度： | 1.2 mm | 最大待机电流： | 0.000002 A |
| 最小待机电流： | 2 V | 子类别： | SRAMs |
| 最大压摆率： | 0.02 mA | 最大供电电压 (Vsup)： | 3.6 V |
| 最小供电电压 (Vsup)： | 2.7 V | 标称供电电压 (Vsup)： | 3 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 0.55 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 8 mm | Base Number Matches： | 1 |
M5M5256DRV-12VXL 数据手册
通过下载M5M5256DRV-12VXL数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
A14
A12
Vcc
/W
28
27
26
25
1
2
3
A7
A6
A5
A4
A13
A8
4
24 A9
5
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
A11
23
6
22 /OE
7
A3
21
20
19
A2
A1
A0
DQ1
DQ2
8
9
A10
/S
DQ8
10
11
12
18 DQ7
DQ6
DQ5
17
16
15
FEATURE
DQ3 13
GND
14
Power supply current
Active Stand-by
Access
time
DQ4
Type
Outline 28P2W-C (DFP)
(max)
100ns
120ns
150ns
(max)
(max)
M5M5256DFP,VP,RV-10VLL
M5M5256DFP,VP,RV-12VLL
M5M5256DFP,VP,RV-15VLL
A10
21
20
19
22
23
24A9
25A8
26A13
/OE
A11
12µA
(Vcc=3.6V)
/S
DQ8
DQ7 18
DQ6 17
DQ5 16
DQ415
20mA
(Vcc=3.6V)
2.4µA
(Vcc=3.6V)
M5M5256DFP,VP,RV-10VXL
M5M5256DFP,VP,RV-12VXL
M5M5256DFP,VP,RV-15VXL
100ns
120ns
150ns
27
28Vcc
/W
0.05µA
(Vcc=3.0V,
Typical)
1
2
14
DQ313
A14
A12
M5M5256DVP
GND
12
11
10
9
A7
DQ2
DQ1
A0
3
•Single +2.7~3.6V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
4 A6
5 A5
6 A4
7 A3
A1
A2 8
Outline 28P2C-A (DVP)
•Battery backup capability
•Low stand-by current··········0.05µA(typ.)
A2
A1
A0
A3
A4
A5
8
9
10
7
6
5
4 A6
DQ111
DQ2
DQ3
GND
DQ4
DQ5
DQ6
3 A7
2 A12
1 A14
12
13
PACKAGE
M5M5256DFP
M5M5256DVP,RV : 28pin 8 X 13.4 mm TSOP
: 28 pin 450 mil SOP
14
15
16
17
18
19
2
M5M5256DRV
Vcc
28
27 /W
26 A13
25 A8
DQ7
DQ8
/S 20
A10
APPLICATION
A9
A11
/OE
24
23
22
Small capacity memory units
21
Outline 28P2C-B (DRV)
MITSUBISHI
ELECTRIC
1
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
Mode
DQ
Icc
/S /W /OE
High-impedance
DIN
Stand-by
Active
H
X
X
Non selection
Write
L
L
L
L
X
L
Active
Read
DOUT
H
H
Active
H
High-impedance
BLOCK DIAGRAM
A 8
25
11
DQ1
DQ2
DQ3
32768 WORD
X 8BIT
A 13
A 14
26
1
12
13
2
A 12
A 7
15
16
DQ4
DQ5
DQ6
DATA I/O
3
4
5
6
7
(512 ROWS X
A 6
17
18
A 5
A 4
512 COLUMNS)
DQ7
DQ8
19
ADDRESS
INPUT
A 3
A 2
8
9
A 1
A 0
10
21
23
24
A 10
A 11
A 9
CLOCK
GENERATOR
WRITE CONTROL
INPUT /W
27
20
22
VCC
(3V)
28
CHIP SELECT
INPUT
/S
14 GND
(0V)
OUTPUT ENABLE
INPUT
/OE
MITSUBISHI
ELECTRIC
2
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Parameter
Supply voltage
Conditions
Ratings
-0.3*~4.6
Unit
V
-0.3*~Vcc+0.3
VI
Input voltage
V
V
mW
°C
With respect to GND
Ta=25°C
(Max 4.6)
Output voltage
VO
Pd
Topr
Tstg
0~Vcc
700
0~70
Power dissipation
Operating temperature
Storage temperature
°C
-65~150
* -3.0V in case of AC ( Pulse width £ 30ns )
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min Typ
2.0
Max
Vcc
+0.3
VIH
High-level input voltage
VIL
Low-level input voltage
-0.3*
2.4
0.6
V
V
VOH1
High-level output voltage 1 IOH=-0.5mA
Vcc
-0.5
VOH2
High-level output voltage 2 IOH=-0.05mA
V
VOL
II
Low-level output voltage
Input current
IOL=1mA
0.4
±1
V
VI=0~Vcc
uA
/S=VIH or or /OE=VIH,
VI/O=0~Vcc
IO
Output current in off-state
±1
20
uA
Min.
/S£0.2V,
Other inputs<0.2V or >Vcc-0.2V
Output-open Min. cycle
11
cycle
Active supply current
(AC, MOS level )
Icc1
mA
1MHz
1.5
11
3
Min.
cycle
/S=VIL,
other inputs=VIH or VIL
Output-open Min. cycle
20
Active supply current
(AC, TTL level )
mA
Icc2
1MHz
1.5
3
12
-VLL
-VXL
/S³ Vcc-0.2V,
other inputs=0~Vcc
Icc3
Icc4
Stand-by current
Stand-by current
uA
0.05
2.4
mA
/S=VIH,other inputs=0~Vcc
0.33
* -3.0V in case of AC ( Pulse width £ 30ns )
CAPACITANCE (Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Limits
Min Typ Max
Unit
Symbol
Parameter
Input capacitance
Output capacitance
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
pF
pF
CI
CO
6
8
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level··················I·HV=2.2V,VIL=0.4V
Input rise and fall time··········5ns
Reference level···················O·VH=VOL=1.5V
DQ
Output loads·························Fig.1,CL=30pF (-10VLL,-10VXL )
CL=50pF (-12VLL,-12VXL )
CL
(Including
scope and JIG)
CL=100pF (-15VLL,-15VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Unit
Symbol
Parameter
Read cycle time
-10VLL, VXL -12VLL, VXL -15VLL, VXL
Min Max Min Max Min Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
100
120
150
ta(A)
ta(S)
ta(OE)
tdis(S)
Address access time
100
100
50
120
120
60
150
150
75
Chip select access time
Output enable access time
Output disable time after /S high
30
30
35
35
40
40
tdis(OE) Output disable time after /OE high
ten(S)
Output enable time after /S low
ten(OE) Output enable time after /OE low
tV(A) Data valid time after address
10
10
10
10
10
10
10
10
10
(3) WRITE CYCLE
Limits
-10VLL, VXL -12VLL, VXL -15VLL, VXL
Min Max Min Max Min Max
Symbol
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
100
70
0
120
80
0
150
90
0
80
80
40
0
90
90
45
0
100
100
50
0
0
0
0
30
30
35
35
40
40
10
10
10
10
10
10
MITSUBISHI
ELECTRIC
4
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
ta (S)
/S
(Note 3)
(Note 3)
ta (OE)
(Note 3)
(Note 3)
tdis (S)
ten (OE)
/OE
tdis (OE)
ten (S)
DATA VALID
DQ1~8
/W = "H" level
Write cycle (/W control mode)
tCW
A0~14
tsu (S)
/S
(Note 3)
(Note 3)
tsu (A-WH)
/OE
/W
tsu (A)
tw (W)
trec (W)
ten (W)
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
(Note 3)
(Note 3)
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
tsu (A)
tsu (S)
trec (W)
/S
(Note 5)
/W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in overlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
6
'97.4.7
MITSUBISHI LSIs
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Limits
Typ Max
Symbol
Vcc (PD)
VI (/S)
Parameter
Power down supply voltage
Chip select input /S
Test conditions
Unit
Min
2
V
V
2
10
-VLL
-VXL
Vcc = 3V,/S³ Vcc-0.2V,
Other inputs=0~Vcc
(Note 7)
uA
Icc (PD)
Power down supply current
2
0.05
(Note 8)
Note7: ICC (PD) = 1uA in case of Ta = 25°C
Note8: ICC (PD) = 0.2uA in case of Ta = 25°C
(2) TIMING REQUIREMENTS (Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
Limits
Min Typ Max
Symbol
Unit
Parameter
Test conditions
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
ns
0
tCR
(3) POWER DOWN CHARACTERISTICS
/S control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.0V
2.0V
/S
/S³ Vcc-0.2V
MITSUBISHI
ELECTRIC
7
M5M5256DRV-12VXL 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| M5M5256DRV-12VXL-I | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-12VXLT | MITSUBISHI | Standard SRAM, 32KX8, 120ns, MIXMOS, PDSO28, 8 X 13.40 MM, PLASTIC, REVERSE, TSOP1-28 | 获取价格 |
|
| M5M5256DRV-15VLL | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-15VLL-I | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-15VLLT | MITSUBISHI | Standard SRAM, 32KX8, 150ns, MIXMOS, PDSO28, 8 X 13.40 MM, PLASTIC, REVERSE, TSOP1-28 | 获取价格 |
|
| M5M5256DRV-15VXL | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-15VXL-I | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-15VXLT | MITSUBISHI | Standard SRAM, 32KX8, 150ns, MIXMOS, PDSO28, 8 X 13.40 MM, PLASTIC, REVERSE, TSOP1-28 | 获取价格 |
|
| M5M5256DRV-45LL | MITSUBISHI | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM | 获取价格 |
|
| M5M5256DRV-45LLT | MITSUBISHI | 暂无描述 | 获取价格 |
|
M5M5256DRV-12VXL 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
