M5M5256FP-55LL-W [MITSUBISHI]
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM; 262144 - BIT ( 32768 -字×8位)的CMOS静态RAM型号: | M5M5256FP-55LL-W |
厂家: | Mitsubishi Group |
描述: | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
文件: | 总7页 (文件大小:49K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M5256DP,KP,FP,VP,RV is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
A14
A12
Vcc
/W
28
27
26
25
1
2
3
A7
A6
A5
A4
A13
A8
4
24 A9
5
Especially the M5M5256DVP,RV are packaged in a 28-pin thin
small outline package.Two types of devices are available,
M5M5256DVP(normal lead bend type package),
M5M5256DRV(reverse lead bend type package). Using both types of
devices, it becomes very easy to design a printed circuit board.
A11
23
6
22 /OE
7
A3
21
20
19
A2
A1
A0
DQ1
DQ2
8
9
A10
/S
DQ8
10
11
12
18 DQ7
DQ6
DQ5
17
16
15
FEATURE
DQ3 13
GND
14
Power supply current
Active Stand-by
Access
time
DQ4
Type
Outline 28P4 (DP)
(max)
45ns
55ns
70ns
(max)
(max)
28P4Y (DKP)
28P2W-C (DFP)
M5M5256DP, KP, FP,VP,RV-45LL
M5M5256DP, KP, FP,VP,RV-55LL
M5M5256DP, KP, FP,VP,RV-70LL
20µA
(Vcc=5.5V)
A10
21
20
19
22
23
24A9
25A8
26A13
27
/W
28Vcc
1
2
3
4 A6
5 A5
6 A4
7 A3
/OE
A11
/S
DQ8
55mA
(Vcc=5.5V)
5µA
(Vcc=5.5V)
DQ7 18
DQ6 17
DQ5 16
DQ415
GND
DQ313
DQ2
DQ1
A0
M5M5256DP, KP, FP,VP,RV-45XL
M5M5256DP, KP, FP,VP,RV-55XL
M5M5256DP, KP, FP,VP,RV-70XL
45ns
55ns
70ns
0.05µA
(Vcc=3.0V,
Typical)
M5M5256DVP
-W
14
A14
A12
A7
•Single +5V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
12
11
10
9
A1
A2 8
Outline 28P2C-A (DVP)
•Battery backup capability
A2
A1
A0
•Low stand-by current··········0.05µA(typ.)
A3
A4
A5
8
9
10
7
6
5
4 A6
DQ111
PACKAGE
DQ2
DQ3
GND
DQ4
DQ5
DQ6
3 A7
2 A12
1 A14
12
13
M5M256DP
M5M5256DKP
M5M5256DFP
: 28 pin 600 mil DIP
: 28 pin 300 mil DIP
14
15
16
17
18
19
M5M5256DRV
-W
Vcc
28
: 28 pin 450 mil SOP
2
27 /W
26 A13
25 A8
M5M5256DVP,RV : 28pin 8 X 13.4 mm TSOP
DQ7
DQ8
/S 20
A10
APPLICATION
A9
A11
/OE
24
23
22
Small capacity memory units
21
Outline 28P2C-B (DRV)
MITSUBISHI
ELECTRIC
1
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,KP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
Mode
DQ
Icc
/S /W /OE
High-impedance
DIN
Stand-by
Active
H
X
X
Non selection
Write
L
L
L
L
X
L
Active
Read
DOUT
H
H
Active
H
High-impedance
BLOCK DIAGRAM
A 8
25
11
DQ1
DQ2
DQ3
32768 WORD
X 8BIT
A 13
A 14
26
1
12
13
2
A 12
A 7
15
16
DQ4
DQ5
DQ6
DATA I/O
3
4
5
6
7
(512 ROWS X
A 6
17
18
A 5
A 4
512 COLUMNS)
DQ7
DQ8
19
ADDRESS
INPUT
A 3
A 2
8
9
A 1
A 0
10
21
23
24
A 10
A 11
A 9
CLOCK
GENERATOR
WRITE CONTROL
INPUT /W
27
20
22
VCC
(5V)
28
CHIP SELECT
INPUT
/S
14 GND
(0V)
OUTPUT ENABLE
INPUT
/OE
MITSUBISHI
ELECTRIC
2
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Parameter
Supply voltage
Conditions
Ratings
-0.3*~7.0
Unit
V
-0.3*~Vcc+0.3
VI
Input voltage
V
V
mW
°C
With respect to GND
Ta=25°C
(Max 7.0)
Output voltage
VO
Pd
Topr
Tstg
0~Vcc
700
-20~70
-65~150
Power dissipation
Operating temperature
Storage temperature
°C
* -3.0V in case of AC ( Pulse width £ 30ns )
DC ELECTRICAL CHARACTERISTICS (Ta=-20~70°C, Vcc=5V±10%, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min Typ
2.2
Max
Vcc
+0.3
VIH
High-level input voltage
VIL
Low-level input voltage
-0.3
2.4
0.8
V
V
VOH1
High-level output voltage 1
IOH=-1mA
Vcc
-0.5
VOH2
High-level output voltage 2
IOH=-0.1mA
V
VOL
II
Low-level output voltage
Input current
IOL=2mA
0.4
±1
V
VI=0~Vcc
uA
/S=VIH or or /OE=VIH,
VI/O=0~Vcc
IO
Output current in off-state
±1
uA
45ns
55ns
70ns
45ns
55ns
70ns
35
30
25
35
30
25
50
45
40
55
50
45
/S£0.2V,
Other inputs<0.2V or >Vcc-0.2V
Output-open Min. cycle
Active supply current
(AC, MOS level )
Icc1
mA
/S=VIL,
other inputs=VIH or VIL
Output-open Min. cycle
Active supply current
(AC, TTL level )
mA
Icc2
-LL
-XL
20
5
/S³ Vcc-0.2V,
other inputs=0~Vcc
Icc3
Icc4
Stand-by current
Stand-by current
uA
0.1
mA
/S=VIH,other inputs=0~Vcc
3
* -3.0V in case of AC ( Pulse width £ 30ns )
CAPACITANCE (Ta=-20~70°C, Vcc=5V±10%, unless otherwise noted)
Limits
Min Typ Max
Unit
Symbol
Parameter
Input capacitance
Output capacitance
Test conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
pF
pF
CI
CO
6
8
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = -20~70°C, Vcc=5V±10%, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level··················I·HV=2.4V,VIL=0.6V
Input rise and fall time··········5ns
Vcc
1.8kW
Reference level···················O·VH=VOL=1.5V
DQ
Output loads·························Fig.1,CL=30pF (-45LL,-45XL )
990W
CL
CL=50pF (-55LL,-55XL )
(Including
scope and JIG)
CL=100pF (-70LL,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
Fig.1 Output load
state voltage. (for ten,tdis)
Parameter
(2) READ CYCLE
Limits
-55LL, XL
Unit
Symbol
-45LL, XL
-70LL, XL
Min Max Min Max Min Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
45
55
70
ta(A)
ta(S)
ta(OE)
tdis(S)
45
45
25
15
15
55
55
30
20
20
70
70
35
25
25
tdis(OE) Output disable time after /OE high
ten(S)
Output enable time after /S low
ten(OE) Output enable time after /OE low
tV(A) Data valid time after address
5
5
10
5
5
10
5
5
10
(3) WRITE CYCLE
Limits
-55LL, XL
Min Max Min Max Min Max
-45LL, XL
-70LL, XL
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
45
35
0
55
40
0
70
50
0
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
40
40
20
0
50
50
25
0
65
65
30
0
0
0
0
15
15
20
20
25
25
5
5
5
5
5
5
MITSUBISHI
ELECTRIC
4
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
ta (S)
/S
(Note 3)
(Note 3)
ta (OE)
(Note 3)
(Note 3)
tdis (S)
ten (OE)
/OE
tdis (OE)
ten (S)
DATA VALID
DQ1~8
/W = "H" level
Write cycle (/W control mode)
tCW
A0~14
tsu (S)
/S
(Note 3)
(Note 3)
tsu (A-WH)
/OE
/W
tsu (A)
tw (W)
trec (W)
ten (W)
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
(Note 3)
(Note 3)
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
tsu (A)
tsu (S)
trec (W)
/S
(Note 5)
/W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in overlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
6
'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS (Ta = -20~70°C, Vcc=5V±10%, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min
2
Typ Max
Vcc (PD)
Power down supply voltage
V
V
V
2.2V£VCC(PD)
2.2
VI (/S)
Chip select input /S
VCC(PD)
2V£VCC(PD)£2.2V
10
-LL
-XL
Vcc = 3V,/S³ Vcc-0.2V,
Other inputs=0~Vcc
(Note 7)
uA
Icc (PD)
Power down supply current
2
0.05
(Note 8)
Note7: ICC (PD) = 1uA in case of Ta = 25°C
Note8: ICC (PD) = 0.2uA in case of Ta = 25°C
(2) TIMING REQUIREMENTS (Ta = -20~70°C, Vcc=5V±10%, unless otherwise noted )
Limits
Min Typ Max
Symbol
Unit
Parameter
Test conditions
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
ns
0
tCR
(3) POWER DOWN CHARACTERISTICS
/S control mode
Vcc
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
/S
/S³ Vcc-0.2V
MITSUBISHI
ELECTRIC
7
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