M5M5408AFP-10L-I [MITSUBISHI]
Standard SRAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32;
| 型号： | M5M5408AFP-10L-I |
| 厂家： | 
Mitsubishi Group |
| 描述： | Standard SRAM, 512KX8, 100ns, CMOS, PDSO32, 0.525 INCH, PLASTIC, SOP-32 静态存储器 光电二极管 |
| 文件： | 总7页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M5408A is 4,194,304-bit CMOS static RAM organized as
524,288-words by 8-bit, fabricated using high-performance
quadruple-polysilicon and double metal CMOS technology.
32 VCC(5V)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1
A0 12
DQ1 13
1
2
The use of thin film transistor (TFT) load cells and CMOS periphery
31
A15
results in a high density and low power static RAM.
The
3
4
5
30 A17
M5M5408A is designed for memory applications where the high
performance, high reliability, large storage, simple interfacing and
battery back-up are important design objectives.
The M5M5408A is offered in a 32-pin plastic small outline
package (SOP) and a 32-pin thin small outline package (TSOP),
providing high board level packing densities. Two types of TSOP
packages are available, M5M5408ATP(normal lead bend type
package) and M5M5408ART (reverse lead bend type package).
Using both two types makes it easy to design a printed circuit
board.
29
W
A13
28
6
7
8
27 A8
26 A9
25
A11
9
24
OE
23 A10
11
22
S
21 DQ8
20 DQ7
14
19
DQ2
DQ6
FEATURES
DQ3 15
(0V)GND 16
18 DQ5
17 DQ4
Access
time
Power supply current
Type
Active
(max)
Stand-by
(max)
Outline 32P2M-A(FP)
32P3Y-H(TP)
(max)
M5M5408AFP,TP,RT-70L-I
M5M5408AFP,TP,RT-10L-I
70ns
100ns
200µA
(Vcc=5.5v)
90mA
(Vcc=5.5V)
(5V)VCC
32
1 A18
A15 31
A17 30
W
2 A16
3 A14
4 A12
40µA
(Vcc=5.5v)
M5M5408AFP,TP,RT-70LL-I 70ns
M5M5408AFP,TP,RT-10LL-I 100ns
29
A13 28
A8 27
A9 26
A11 25
5
A7
A6
A5
A4
A3
6
7
8
• Single +5V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S
• Data retention supply voltage=+2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
24
9
OE
A10 23
S
DQ8 21
DQ7 20
10 A2
22
11
A1
12 A0
13 DQ1
• Small stand-by current………………0.4µA(typ.)
• Package
19
14
DQ6
DQ2
DQ5 18
DQ4 17
15 DQ3
16 GND(0V)
M5M5408AFP : 32 pin 525 mil SOP
M5M5408ATP : 32 pin 400 mil TSOP(II)
M5M5408ART : 32 pin 400 mil TSOP(II)
Outline 32P3Y-J(RT)
APPLICATION
Small capacity memory units, IC card, Battery operating system,
asynchronous server system
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5408A is determined by a
combination of the device control inputs S, W and OE.
Each mode is summarized in the function table.
eliminated.
A read cycle is executed by setting W at a high level and
OE at a low level while S are in an active state(S=L).
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
W or S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable OE directly controls the output stage. Setting the OE
at a high level,the output stage is in a high-impedance state,
and the data bus contention problem in the write cycle is
When setting S at a high level, the chips are in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips and memory expansion
by S. The power supply current is reduced as low as the
stand-by current which is specified as Icc3 or Icc4, and the
memory data can be held at +2V power supply, enabling
battery back-up operation during power failure or power-down
operation in the non-selected mode.
FUNCTION TABLE
S
H
L
L
L
W
X
L
OE
X
Mode
DQ
Icc
High-impedance
Standby
Non selection
X
Active
Active
Active
Write
Read
D IN
L
D OUT
H
H
High-impedance
H
BLOCK DIAGRAM
5
A7
6
A6
13
14
15
17
18
19
20
21
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
23
A10
524288 WORDS
x 8 BITS
25
A11
26
A9
512 ROWS
x
128 COLUMNS
64 BLOCKS
27
A8
x
28
A13
30
A17
31
A15
1
A18
2
A16
CLOCK
GENERATOR
3
A14
4
A12
29
22
24
7
W
A5
8
A4
S
9
A3
OE
10
A2
11
A1
VCC
32
16
(3.3V)
12
A0
GND
(0V)
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Units
Symbol
Vcc
VI
Parameter
Supply voltage
Conditions
With respect to GND
Ta=25°C
Ratings
-0.3~ 7
-0.3*~ Vcc+0.3
V
V
V
Input voltage
Output voltage
VO
0~Vcc
700
Power dissipation
Operating temperature
Storage temperature
Pd
mW
°C
Topr
-40 ~ 85
-65 ~150
T
°C
stg
*
-3.0V in case of AC (Pulse width £ 30ns)
(Ta= -40~85°C, Vcc=5V±10%, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Conditions
Units
Min
Typ
Max
Vcc+0.3
0.8
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
2.2
-0.3*
2.4
IOH=-1mA
V
VOH
High-level output voltage
=-0.1mA
IOH
Vcc-0.5
VOL
II
Low-level output voltage IOL =2mA
0.4
±1
±1
V
µA
=0~Vcc
VI
Input leakage current
Output leakage current
S=VIH,OE=VIH,VI/O=0~Vcc
IO
µA
Minimum
cycle
S£0.2V
50
25
80
30
Active supply current
(AC,MOS level)
ICC1
mA
Other inputs£ 0.2V or ³ Vcc-0.2V
Output-open (duty 100%)
1MHz
Minimum
cycle
IH
S=VIL ,W=V
60
30
90
40
Active supply current
(AC,TTL level)
ICC2
Other inputs=VIH or VIL
mA
1MHz
Output-open (duty 100%)
FP,VP,RT-L
FP,VP,RT-LL
S ³ Vcc-0.2V
200
40
3
µA
µA
ICC3 Stand by supply current
ICC4 Stand by supply current
Other inputs=0 ~Vcc
S=VIH,Other inputs=0 ~Vcc
1.0
mA
*
-3.0V in case of AC (Pulse width £ 30ns)
CAPACITANCE (Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
Limits
Typ
Units
Symbol
Parameter
Conditions
Min
Max
6
pF
pF
C i
Input capacitance (Ta=25°C )
Output capacitance (Ta=25°C )
V I =GND,Vi =25mVrms,f=1MHz
Vo=25mVrms,f=1MHz
VO=GND,
8
C o
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is Vcc=5V,Ta=25°C
Note 3: Ci, Co are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
SWITCHING CHARACTERISTICS(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
READ CYCLE
Limits
M5M5408FP,TP, M5M5408FP,TP,
RT-70L-I,-70LL-I
RT-10L-I,-10LL-I
Units
Parameter
Symbol
Min Max Min Max
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
100
tCR
ta(A)
ta(S)
Address access time
70
100
Chip select access time
Output enable access time
Output disable time after S high
70
35
100
50
(OE)
ta
(S)
tdis
25
25
35
35
tdis(OE)
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address
10
5
10
5
(S)
ten
ten(OE)
tv(A)
10
10
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
Limits
TIMING REQUIREMENTS
WRITE CYCLE
M5M5408FP,TP, M5M5408FP,TP,
RT-70L-I,-70LL-I RT-10L-I,-10LL-I Units
Symbol
Parameter
Min Max Min Max
Write cycle time
70
100
ns
ns
ns
ns
ns
ns
ns
ns
tCW
(W)
Write pulse width
tw
50
0
60
0
(A)
Address set up time
tsu
tsu
tsu
(A-WH)
(S)
Address set up time with respect to W high
Chip select set up time
Data set up time
60
60
30
0
80
80
35
0
tsu(D)
th (D)
Data hold time
(W)
trec
tdis
Write recovery time
0
0
(W)
Output disable time after W low
Output disable time after OE high
Output enable time after W high
25
25
35
35
ns
ns
tdis(OE)
ten (W)
5
5
5
5
ns
ns
(OE)
ten
Output enable time after OE low
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
TIMING DIAGRAMS
Read cycle
tCR
A
0~18
(A)
tv
(A)
ta
(S)
ta
S
(Note4)
(Note4)
(Note4)
(OE)
ta
(S)
tdis
(OE)
ten
OE
(Note4)
(OE)
tdis
(S)
ten
DQ1~8
(Dout )
W="H" level
Write cycle
(W control mode)
0~18
CW
t
A
(S)
tsu
S
(Note4)
(Note4)
(A-WH)
tsu
OE
W
(W)
tw
(A)
(W)
tsu
trec
(D)
(D)
tsu
th
DATA IN
STABLE
DQ1~8
(Din)
tdis(W)
tdis
ten (OE)
(OE)
(W)
ten
DQ1~8
(Dout)
MITSUBISHI
ELECTRIC
5
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle
(S control mode)
tCW
A
0~18
tsu(A)
tsu(S)
(W)
trec
S
(Note6)
(Note4)
(Note5)
(Note4)
W
(D)
tsu(D) th
DQ1~8
DATA IN
STABLE
(Din)
MEASUREMENT CONDITIONS
Vcc
Input pulse ·······················I·HV=2.4V, VIL=0.6V
Input rise time and fall time ······· 5ns
1.8kW
Reference level ·················OVH=VOL=1.5V
DQ
Transition is measured ±500mV from
steady state voltage (for ten,tdis).
Output loads ······················ Fig. 1,L=C100pF (FP,TP,RT-10L,-10LL)
CL=30pF (FP,TP,RT-70L,-70LL)
W
990
C L
Including
scope and JIG
(
)
CL=5pF (for ten,tdis)
Fig.1 Output load
Note 4: Hatching indicates the state is "don't care".
Note 5: A Write occurs during the overlap of a low S and a low W.
Note 6: If W goes low simultaneously with or prior to S,the output remains in the highimpedance state.
Note 7: Don't apply inverted phase signal externally when DQ pin is in output mode.
MITSUBISHI
ELECTRIC
6
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Units
Typ
Min
2
Max
cc
V
(PD) Power down supply voltage
V
V
cc
2.2
2.2V£ V (PD)
V (S)
I
Chip select input S
cc(PD)
V
2V£ V (PD) £ 2.2V
cc
-40~70°C
70~85°C
-40~70°C
70~85°C
50
µA
µA
-L
100
Vcc=3V, S³ Vcc-0.2V,
Other inputs=0~3V
cc
I
(PD) Power down supply current
Icc(PD)=1µA at Ta=25°C
µA
µA
0.4
10*
20
-LL
*
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
(2) TIMING REQUIREMINTS
Limits
Symbol
Parameter
Test conditions
Units
Min
0
Typ
Max
t
su
(PD)
ns
Power down set up time
rec
t
(PD) Power down recovery time
ms
5
Vcc
S
3.0V
3.0V
(PD)
tsu
trec(PD)
2.2V
2.2V
S ³ Vcc-0.2V
MITSUBISHI
ELECTRIC
7
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