M5M5408ATP-10L [MITSUBISHI]
Standard SRAM, 512KX8, 100ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32;
| 型号： | M5M5408ATP-10L |
| 厂家： | 
Mitsubishi Group |
| 描述： | Standard SRAM, 512KX8, 100ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总7页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
DESCRIPTION
The M5M5408A is a 4,194,304-bit CMOS Static RAM organizedas
524,288-word by 8-bit. This device is fabricated usingMitsubishi's
high-performance silicon-gate CMOS technology.This state-of-the-art
process technology, combined withinnovative circuit design
1
2
32
31
A18
A16
A14
A12
A7
A6
A5
A4
A3
VCC(5V)
A15
A17
W
A13
A8
A9
A11
OE
A10
3
4
5
30
29
28
techniques, yields
high-density and low-power devices. The
M5M5408A is suitable for memoryapplications where high reliability,
large storage, simpleinterfacing and battery back-up are important
design objectives.
The M5M5408A is available in 32-pin plastic SOP(M5M5408AFP) ,
32-pin plastic normal-lead-bend TSOP(M5M5408ATP) and 32-pin
plastic reverse-lead-bend TSOP(M5M5408ART) packages. Two
types of TSOP's are suitable forSurface Mounting on double-sided
printed circuit boards.
6
7
8
27
26
25
9
24
23
22
10
11
A2
A1
A0
S
12
13
14
21
20
19
DQ8
DQ7
DQ6
DQ5
DQ4
DQ1
DQ2
DQ3
(0V)GND
FEATURES
15
16
18
17
Access Power supply current
Type name
time
(max.)
55ns
Active
(max.)
Stand-by
(max.)
Outline32P2M-A (AFP)
32P3Y-H (ATP)
M5M5408AFP, TP, RT -55L
M5M5408AFP, TP, RT -70L
M5M5408AFP, TP, RT -10L
M5M5408AFP, TP, RT -55LL
M5M5408AFP, TP, RT -70LL
M5M5408AFP, TP, RT -10LL
100µA
70ns
30mA
(Vcc=5.5V*)
100ns
55ns
(1MHz)
20µA
(Vcc=5.5V*)
0.4µA
32
31
30
1
2
3
(5V)VCC
A15
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND(0V)
70ns
30mA
100ns
(1MHz)
A17
W
A13
A8
A9
A11
OE
A10
S
DQ8
DQ7
DQ6
DQ5
DQ4
29
28
27
4
5
6
(Vcc=3V**)
* at 70°C / **at 25°C
26
25
24
7
8
9
• Single +5V power supply
• No clocks, No refresh
23
22
21
10
11
12
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S
• Data retention supply voltage=2.0V to 5.5V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
20
19
18
13
14
15
• Battery backup capability
17
16
• Small stand-by current…………0.4µA (typical)
• Package
M5M5408AFP : 32 pin 525 mil SOP
M5M5408ATP : 32 pin 400 mil TSOP(II)
M5M5408ART : 32 pin 400 mil TSOP(II)
Outline32P3Y-J (ART)
PIN DISCRIPTION
A0 ..... A18: ADDRESS INPUTS
DQ1..... DQ8: DATA INPUTS & OUTPUTS
S: CHIP SELECT INPUT
W: WRITE ENABLE INPUT
OE: OUTPUT ENABLE INPUT
Vcc: Power supply
APPLICATION
Small capacity memory units
IC card
Battery operating system
GND: Ground
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
BLOCK DIAGRAM
5
A7
A6
A10
13
DQ1
DQ2
6
14
524288 WORDS
23
15
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
x 8 BITS
25
A11
17
512 ROWS
128 COLUMNS
x 64 BLOCKS
A9
26
18
19
20
x
A8
27
A13 28
A17
30
21
A15 31
1
A18
A16
A14
A12
2
3
CLOCK
GENERATOR
4
29
W
S
7
8
A5
A4
22
24
A3
A2
9
OE
10
A1 11
VCC
(5V)
32
16
A0
12
GND
(0V)
FUNCTION
A read cycle is executed by setting W at a high level andOEat
a low level while S are in an active state(S=L).
The operation mode of the M5M5408A is determined by
acombination of the device control inputs S, Wand OE.Each
mode is summarized in the truth table.
When setting S at a high level, the chips are in a
non-selectable mode in which both reading and writing are
disabled.In this mode, the output stage is in a high-impedance
state,allowing OR-tie with other chips and memory expansion
by S.The power supply current is reduced as low as the
stand-bycurrent which is specified as Icc3 or Icc4, and the
memorydata can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation
inthe non-selected mode.
A write cycle is executed whenever the low level Woverlaps
with the low level S. The address must be set upbefore the
write cycle and must be stable during the entirecycle. The data
is latched into a cell on the trailing edge of Wor S, whichever
occurs first, requiring the set-up and holdtime relative to these
edge to be maintained. The outputenable OE directly controls
the output stage. Setting theOE at a high level, the output
stage is in a high-impedancestate, and the data bus contention
problem in the write cycleis eliminated.
TRUTH TABLE
S
H
L
L
L
W
X
L
OE
X
Mode
Non selection
Write
DQ
Icc
High-impedance
Data input
Stand-by
Active
Active
Active
X
H
H
L
Read
Data output
H
Read
High-impedance
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Conditions
Ratings
Unit
Vcc
Vi
- 0.3 ~ 7
- 0.3* ~ Vcc + 0.3
0 ~ Vcc
V
V
Input voltage
With respect to GND
Ta=25°C
Vo
Output voltage
V
Pd
Power dissipation
Operating temperature
Storage temperature
700
mW
°C
°C
Topr
Tstg
0 ~ 70
-65 ~ 150
* -3.0V in case of AC ( Pulse width £ 50ns)
DC ELECTRICAL CHARACTERISTICS (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits
Typ.
Unit
Min.
2.2
Max.
VIH High-level input voltage
VIL Low-level input voltage
VOH High-level output voltage
Vcc+0.3
0.8
V
V
-0.3*
2.4
IOH= - 1mA
V
IOH= - 0.1mA
IOL = 2 mA
Vcc-0.5
V
VOL Low-level output voltage
0.4
±1
±1
V
Ii
Input leakage current
Output leakage current
Inputs = 0 ~ Vcc
S = VIH
µA
µA
Io
OE= VIH, DQ=0 ~ Vcc
minimum
cycle
S £ 0.2
Other inputs £ 0.2V or ³ Vcc-0.2V
Icc1 Active supply current (AC, MOS-lvel)
50
25
60
30
80
30
mA
mA
mA
mA
µA
DQ = open (duty 100%)
1MHz
minimum
cycle
S = VIL
Icc2 Active supply current (AC, TTL-level) Other inputs = VIH or VIL
DQ = open (duty 100%)
90
1MHz
40
-L
Icc3 Stand-by current
S Vcc - 0.2V,
version
-LL
100
Other inputs = 0 ~ Vcc
version
1
20
3
µA
Icc4 Stand-by current
S = VIH, other inputs=0 ~ Vcc
mA
* -3.0V in case of AC ( Pulse width £ 50ns)
CAPACITANCE (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits
Typ.
Unit
Min.
Max.
Ci
Input capacitance
Output capacitance
Vi = GND, Vi = 25mV rms, f = 1MHz
Vo = GND, Vo = 25mV rms, f = 1MHz
6
8
pF
pF
Co
Note1. Direction for current flowing into IC is indicated as positive value.
2. Typical value is for Ta=25°C and Vcc=5.0V
3. Ci and Co are random samples ,not production tested.
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
(1) MEASUREMENT CONDITIONS
Vcc
Input pulse …………………VIH=2.4V, VIL=0.6V(AFP,TP,RT-70L,-10L,-70LL,-10LL)
VIH=3.0V, VIL=0V(AFP,TP,RT-55L,-55LL)
Input rise and fall time ……5ns
1.8kW
DQ
Output reference level ……VOH=VOL=1.5V
For ten and tdis, transition is measured ±500mV
from steady state voltage
990W
C L
Output loads Show in Fig. 1;
CL=100pF(AFP,TP,RT-70L,-10L,-70LL,-10LL)
CL=30pF(AFP,TP,RT-55L,-55LL)
CL=5pF (for ten,tdis)
CL Includes jig and scope capacitance
Fig.1 Output load
(2) READ CYCLE
Limits
M5M5408AFP,TP,RT
M5M5408AFP,TP,RT
M5M5408AFP,TP,RT
Symbol
Parameter
Unit
-55L, -55LL
-70L, -70LL
-10L, -10LL
Min.
55
Max.
Min.
70
Max.
Min.
100
Max.
tCR
ta(A)
ta(S)
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
55
55
25
20
20
70
70
35
25
25
100
100
50
Chip select access time
ta(OE) Output enable access time
tdis(S) Output disable time after S high
tdis(OE) Output disable time after OE high
ten(S) Output enable time after S low
ten(OE) Output enable time after OE low
35
35
10
5
10
5
10
5
tv(A)
Data valid time after address change
10
10
10
Limits
M5M5408AFP,TP,RT
M5M5408AFP,TP,RT
M5M5408AFP,TP,RT
Symbol
Parameter
Unit
-55L, -55LL
-70L, -70LL
-10L, -10LL
Min.
Max.
Min.
Max.
Min.
Max.
tCW
tw(W)
tsu(A)
Write cycle time
55
40
0
70
50
0
100
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write pulse width
Address set up time
tsu(A-WH) Address set up time with respect to W high
50
50
25
0
60
60
30
0
80
80
35
0
tsu(S)
tsu(D)
th(D)
Chip select set up time
Data set up time
Data hold time
trec(W) Write recovery time
0
0
0
tdis(W) Output disable time after W low
tdis(OE) Output disable time after OE high
ten(W) Output enable time after W high
ten(OE) Output enable time after OE low
20
20
25
25
35
35
5
5
5
5
5
5
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0 ~ A18
ta(A)
ta(S)
tv(A)
( Note 4)
( Note 4)
( Note 4)
( Note 4)
S
tdis(S)
ta(OE)
OE
ten(OE)
ten(S)
tdis(OE)
DATA valid
DQ1 ~ DQ8
(Dout)
Write cycle ( WE control mode )
tCW
A0 ~ A18
tsu(S)
( Note 4)
( Note 4)
S
tsu(A-WH)
OE
W
tsu(A)
tw(W)
trec(W)
th(D)
tsu(D)
DQ1 ~ DQ8
(Din)
DATA valid
tdis(W)
ten(OE)
ten(W)
tdis(OE)
DQ1 ~ DQ8
(Dout)
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( S control mode )
tCW
A0 ~ A18
tsu(A)
tsu(S)
trec(W)
S
tw(W)
( Note 6)
( Note 4)
( Note 4)
( Note 5)
W
tsu(D)
th(D)
DQ1 ~ DQ8
(Din)
DATA valid
Note 4: Hatching indicates the state is "don't care".
5: A Write occurs during the overlap of a low S and a low W.
6: If W goes low simultaneously with or prior to S, the output remains in the high-impedance state.
7: Don't apply inverted phase signal externally when DQ pin is in output mode.
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Limits
Typ.
Unit
Min.
Max.
Vcc(PD) Power down supply voltage
Vi(S) Chip select input S
2
V
V
V
Vcc(PD) ³ 2.2V
2.2
2.2V ³ Vcc(PD) ³ 2.0V
Vcc(PD)
0.4
-L
50
Icc(PD) Power down supply current
Vcc=3V, S ³ Vcc-0.2V,
version
-LL
µA
µA
other inputs = 0 ~ 3V
version
10*
* Icc (PD) = 1µA at Ta=25°C
(2) TIMING REQUIREMENTS (Ta=0 - 70°C, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits
Typ.
Unit
Min.
Max.
tsu(PD) Power down set up time
trec(PD) Power down recovery time
0
5
ms
ms
(3) TIMING DIAGRAM
S control mode
Vcc
4.5V
4.5V
trec(PD)
tsu(PD)
2.2V
2.2V
S ³ Vcc - 0.2V
S
MITSUBISHI
ELECTRIC
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