M5M5V208AKV-55L [MITSUBISHI]
Standard SRAM, 256KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP-32;
| 型号： | M5M5V208AKV-55L |
| 厂家： | 
Mitsubishi Group |
| 描述： | Standard SRAM, 256KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
The M5M5V208A is a family of low voltage 2-Mbit static RAMs
organized as 262,144-words by 8-bit, fabricated by Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5V208A is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208A is packaged in 32-pin 8mm x 13.4mm STSOP
packages. Two types of STSOPs are available, M5M5V208AKV
(normal-lead-bend STSOP) and M5M5V208AKR (reverse-lead-bend
STSOP). These two types STSOPs are suitable for a surface
mounting on double-sided printed circuit boards.
From the point of operating temperature, the family is divided into
three versions; "Standard", "W-version", and "I-version". Those are
summarized in the part name table below.
• Single 2.7 ~ 3.6V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current • • • • • • • • • • 0.3µA(typ.)
PACKAGE
M5M5V208AKV,KR : 32pin 8 X 13.4 mm TSOP
PART NAME TABLE
Active
current
Icc1
(3.0V, typ.)
Access
Stand-by current Icc(PD), Vcc=3.0V
Version,
Power
Supply
Part name
(## stands for"KV"or"KR")
time
typical *
Ratings (max.)
Operating
temperature
max.
25°C 40°C 25°C 40°C 70°C
85°C
---
M5M5V208A## -55L
M5M5V208A## -70L
M5M5V208A## -55H
M5M5V208A## -70H
M5M5V208A## -55LW
M5M5V208A## -70LW
M5M5V208A## -55HW
M5M5V208A## -70HW
M5M5V208A## -55LI
M5M5V208A## -70LI
M5M5V208A## -55HI
M5M5V208A## -70HI
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
55ns
70ns
---
0.3µA
---
---
---
---
---
---
2.7 ~ 3.6V
2.7 ~ 3.6V
20µA
Standard
0 ~ +70°C
---
1µA 3µA 8µA
20mA
(f=10MHz)
---
---
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
20µA 50µA
W-version
-20 ~ +85°C
3mA
---
---
0.3µA
1µA 3µA 8µA 24µA
(f=1MHz)
---
---
---
20µA 50µA
I-version
-40 ~ +85°C
---
0.3µA
1µA 3µA 8µA 24µA
* "typical" parameter is sampled, not 100% tested.
PIN CONFIGURATION (TOP VIEW)
1
2
17 A3
16
15
32 OE
A4
A11
18
A5
A2
A10
S1
A9
31
30
3
19 A1
14
13
A6
A8
4
20
A7
A0
A13
29 DQ8
21
5
6
7
12
11
28
A12
A14
A16
A17
Vcc
A15
S2
DQ1
DQ7
W
22
DQ2
27 DQ6
S2
10
9
23
26
DQ3
A15
DQ5
8
9
24
25
Vcc
DQ4
GND
M5M5V208AKV
M5M5V208AKR
25
8
7
24
23
DQ4
A17
GND
10
11
26
A16
DQ3
DQ5
27
6
5
22
21
A14
DQ2
DQ6
12
28
W
A12
DQ1
DQ7
13
29
4
3
20
19
A13
A7
A0
DQ8
14
15
30
A8
A6
A1
S1
31
2
1
18
17
A9
A5
A2
A10
16
32
A3
A11
A4
OE
Outline 32P3K-B(KV)
Outline 32P3K-C(KR)
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208A is determined by a
combination of the device control inputs S1, S2, W and OE.
Each mode is summarized in the function table.
A read cycle is executed by setting W at a high level and
OE at a low level while S1 and S2 are in an active state (S1
= L ,S2 = H).
When setting S1 at a high level or S2 at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S1 or S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
A write cycle is executed whenever the low level W
overlaps with the low level S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
FUNCTION TABLE
S1 S2
W
OE
Mode
DQ
Icc
X
H
L
X
X
X
X
High-impedance
High-impedance
Standby
Standby
Non selection
X
Non selection
Write
L
L
H
H
L
X
L
Active
Active
D IN
H
Read
D OUT
L
H
H
H
High-impedance
Active
BLOCK DIAGRAM
*
*
8
7
16
15
A4
A5
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
DQ1
6
5
14
13
A6
A7
DQ2
DQ3
262144 WORDS
BITS
X
8
4
12
A12
DQ4
DQ5
512 ROWS
X
X
128 COLUMNS
32 BLOCKS
3
2
11
10
A14
A16
DQ6
DQ7
1
9
7
A17
A15
31
DQ8
12
20
A0
11
10
19
18
A1
A2
CLOCK
GENERATOR
9
17
31
A3
W
5
29
22
23
A10
A11
30
S1
S2
25
26
1
2
6
30
24
A9
A8
32
OE
27
28
3
4
VCC
(3V)
8
32
16
A13
GND
(0V)
24
*Pin numbers inside dotted line show reverse-lead-bend sTSOP.
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Conditions
Ratings
- 0.5*~4.6
Unit
V
Parameter
Supply voltage
- 0.5* ~ Vcc + 0.5
Input voltage
VI
With respect to GND
V
(Max 4.6)
Output voltage
Power dissipation
VO
Pd
0 ~ Vcc
700
0 ~ 70
- 20 ~ 85
- 40 ~ 85
- 65 ~150
V
Ta=25°C
mW
°C
°C
°C
°C
Standard
W - Version
I - Version
Operating temperature
Topr
Storage temperature
Tstr
* - 3.0V in case of AC ( Pulse width £ 30ns )
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
DC ELECTRICAL CHARACTERISTICS
Limits
Unit
Symbol
Parameter
Test conditions
Min Typ Max
Vcc
+0.3V
VIH
High-level input voltage
Low-level input voltage
V
2.0
- 0.3*
2.4
VIL
VOH1
0.6
V
V
High-level output voltage 1 IOH= - 0.5mA
Vcc
-0.5V
IOH= - 0.05mA
VOH2
High-level output voltage 2
V
VOL
II
Low-level output voltage
Input current
IOL=2mA
0.4
±1
V
µA
VI=0 ~ Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0 ~ Vcc
µA
Output current in off-state
IO
±1
f= 10MHz
f= 5MHz
f= 1MHz
f= 10MHz
f= 5MHz
f= 1MHz
20
10
3
22
12
3
25
13
5
27
15
5
60
2
5
10
30
0.33
S1 £ 0.2V, S2 ³ Vcc-0.2V,
other inputs £ 0.2V
or ³ Vcc-0.2V,output-open
Active supply current
(CMOS-level Input)
Icc1
mA
S1=VIL,S2=VIH,
other inputs=VIH or VIL
output-open
Active supply current
(TTL-level Input)
Icc2
mA
1) S2 £ 0.2V,
-L
other inputs=0 ~ Vcc
~+25°C
~+40°C
~+70°C
~+85°C
0.3
-H
or
µA
Icc3
Icc4
-HW
Stand-by current
Stand-by current
2) S1 ³ Vcc-0.2V,
S2 ³ Vcc-0.2V
-HI
other inputs=0 ~ Vcc
-HW / I
S1=VIH or S2=VIL,other inputs=0 ~ Vcc
mA
* - 3.0V in case of AC ( Pulse width £ 30ns )
(Vcc= 2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Limits
Unit
Symbol
Parameter
Test conditions
Typ
Min
Max
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
8
10
CI
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
3
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
( Vcc= 2.7 ~ 3.6V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
1TTL
(1) MEASUREMENT CONDITIONS
.................................
DQ
Vcc
2.7 ~ 3.6V
.............
.....
Input pulse level
VIH=2.2V,VIL=0.4V
5ns
CL
including
scope and JIG
Input rise and fall time
...............
Reference level
Output loads
VOH=VOL=1.5V
Fig.1,CL=30pF
...................
Fig.1 Output load
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
(2) READ CYCLE
Limits
-55L,H
Min Max
-70L,H
Min Max
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
ta(A)
Read cycle time
Address access time
55
55
55
55
30
20
20
20
10
10
5
70
70
70
70
35
25
25
25
10
10
5
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
10
10
(3) WRITE CYCLE
Limits
-55L,H
-55L,H
Symbol
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Unit
Min Max
Min Max
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
45
0
70
55
0
50
50
50
25
0
65
65
65
30
0
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
0
0
20
20
5
25
25
5
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
5
5
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~17
ta(A)
tv (A)
ta (S1)
S1
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
S2
ta (S2)
ta (OE)
ten (OE)
(Note 3)
(Note 3)
OE
tdis (OE)
(Note 3)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~17
tsu (S1)
S1
(Note 3)
(Note 3)
(Note 3)
S2
tsu (S2)
(Note 3)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
ten (W)
W
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
MITSUBISHI ELECTRIC
5
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~17
tsu (A)
tsu (S1)
trec (W)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 5)
W
(Note 4)
tsu (D)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~17
S1
(Note 3)
(Note 3)
tsu (A)
tsu (S2)
trec (W)
S2
(Note 5)
W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI ELECTRIC
6
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Min Typ Max
Symbol
Test conditions
Parameter
Unit
V
Power down supply voltage
Chip select input S1
Vcc (PD)
VI (S1)
2
V
2.0
0.2
50
Chip select input S2
VI (S2)
V
Vcc=3.0V
-L
1) S2 £ 0.2V,other inputs=0 ~ Vcc
or
1
3
8
24
0.3
~+25°C
~+40°C
-HI ~+70°C
-H
Power down supply current
-HW
Icc (PD)
µA
2) S1 ³ Vcc-0.2V,S2 ³ Vcc-0.2V
other inputs=0 ~ Vcc
-HW / I
~+85°C
(2) TIMING REQUIREMENTS
Limits
Min Typ Max
Unit
Symbol
Parameter
Test conditions
Power down set up time
Power down recovery time
ns
ms
tsu (PD)
trec (PD)
0
5
(3) POWER DOWN CHARACTERISTICS
S1 control mode
Vcc
2.7V
2.7V
t su (PD)
t rec (PD)
2.2V
2.2V
S1
S1 ³ Vcc - 0.2V
S2 control mode
Vcc
2.7V
2.7V
t su (PD)
trec (PD)
S2
0.2V
0.2V
S2 £ 0.2V
7
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Revision History
Revision No.
History
Date
A0.1E
A0.2E
The first edition
The second edition
09.Nov.'98
29.Nov.'99
Preliminary
Preliminary
8
MITSUBISHI ELECTRIC
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