M5M5V208VP-12L [MITSUBISHI]
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM; 2097152 - BIT （ 262144 -字×8位）的CMOS静态RAM
| 型号： | M5M5V208VP-12L |
| 厂家： | 
Mitsubishi Group |
| 描述： | 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM |
| 文件： | 总7页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V208 is 2,097,152-bit CMOS static RAM organized as
262,144-words by 8-bit which is fabricated using high-performance
quadruple-polysilicon and double metal CMOS technology. The use
of thin film transistor(TFT) load cells and CMOS periphery results in a
high density and low power static RAM. The M5M5V208 is designed
for memory applications where high reliability, large storage, simple
interfacing and battery back-up are important design objectives.
The M5M5V208VP,RV,KV,KR are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).Two types of devices are available.
PIN CONFIGURATION (TOP VIEW)
1
2
3
32
31
30
A17
A16
A14
VCC(3V)
A15
S2
4
5
6
29
28
27
A12
A7
A6
W
A13
A8
7
8
9
26
25
24
A5
A4
A3
A2
A1
A0
A9
A11
OE
A10
S1
DQ8
DQ7
DQ6
DQ5
DQ4
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy to
design a printed circuit board.
10
11
12
23
22
21
FEATURE
13
14
15
20
19
18
DQ1
DQ2
DQ3
(0V)GND
Power supply current
Active Stand-by
Access
time
(max)
Type
16
17
(max)
(max)
70ns
85ns
M5M5V208FP,VP,RV,KV,KR-70L
M5M5V208FP,VP,RV,KV,KR-85L
M5M5V208FP,VP,RV,KV,KR-10L
M5M5V208FP,VP,RV,KV,KR-12L
M5M5V208FP,VP,RV,KV,KR-70LL
M5M5V208FP,VP,RV,KV,KR-85LL
Outline 32P2M-A(FP)
60µA
1
2
32 OE
A11
A9
100ns
120ns
70ns
(Vcc=3.6V)
A10
S1
31
30
3
4
A8
27mA
(Vcc=3.6V)
A13
29 DQ8
5
6
7
28
DQ7
W
27 DQ6
S2
85ns
26
A15
Vcc
DQ5
10µ A
(Vcc=3.6V)
8
9
25
DQ4
100ns
120ns
M5M5V208FP,VP,RV,KV,KR-10LL
M5M5V208FP,VP,RV,KV,KR-12LL
M5M5V208VP,KV
24
23
A17
A16
A14
A12
A7
GND
10
11
12
13
DQ3
22
21
DQ2
DQ1
20
19
• Single 2.7 ~ 3.6V power supply
A0
14
15
A6
A1
• Operating temperature of 0 to +70°C
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
18
17
A5
A2
16
A3
A4
Outline 32P3H-E(VP), 32P3K-B(KV)
• Easy memory expansion and power down by S1 & S2
• Data retention supply voltage=2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
17 A3
16
15
A4
18
A5
A2
19 A1
14
13
A6
20
A7
A0
21
12
11
A12
A14
A16
A17
Vcc
A15
S2
DQ1
22
• Battery backup capability
• Small stand-by current · · · · · · · · · · 0.3µA(typ.)
DQ2
10
9
23
DQ3
24
GND
M5M5V208RV,KR
25
8
7
DQ4
26
DQ5
PACKAGE
27
6
5
DQ6
28
M5M5V208FP
: 32 pin 525 mil SOP
W
DQ7
29
4
3
A13
DQ8
M5M5V208VP,RV : 32pin 8 X 20 mm2
TSOP
30
A8
S1
M5M5V208KV,KR : 32pin 8 X 13.4 mm2 TSOP
31
2
1
A9
A10
32
A11
OE
APPLICATION
Outline 32P3H-F(RV), 32P3K-C(KR)
Small capacity memory units
Battery operating system
Handheld communiation tools
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208 is determined by a
combination of the device control inputs S1, S2, W and OE.
Each mode is summarized in the function table.
A read cycle is executed by setting W at a high level and
OE at a low level while S1 and S2 are in an active state (S1
= L ,S2 = H).
When setting S1 at a high level or S2 at a low level, the
chips are in a non-selectable mode in which both reading
and writing are disabled. In this mode, the output stage is in
a high-impedance state, allowing OR-tie with other chips
and memory expansion by S1 or S2. The power supply
current is reduced as low as the stand-by current which is
specified as Icc3 or Icc4, and the memory data can be held
at +2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
A write cycle is executed whenever the low level W
overlaps with the low level S1 and the high level S2. The
address must be set up before the write cycle and must be
stable during the entire cycle. The data is latched into a cell
on the trailing edge of W, S1 or S2, whichever occurs first,
requiring the set-up and hold time relative to these edge to
be maintained. The output enable OE directly controls the
output stage. Setting the OE at a high level,the output stage
is in a high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
FUNCTION TABLE
S1 S2
W
OE
Mode
DQ
Icc
X
H
L
X
X
X
X
Non selection
High-impedance
High-impedance
Standby
Standby
X
Non selection
Write
IN
L
L
H
H
L
X
L
D
Active
Active
H
Read
D OUT
L
H
H
H
High-impedance
Active
BLOCK DIAGRAM
*
*
8
7
16
15
A4
A5
21
22
13
14
DQ1
6
5
14
13
A6
A7
DQ2
DQ3
262144 WORDS
23
25
15
17
X
8 BITS
4
12
A12
DQ4
DQ5
512 ROWS
X
X
128 COLUMNS
32 BLOCKS
26
27
18
19
3
2
11
10
A14
A16
DQ6
DQ7
28
20
21
1
9
7
A17
A15
29
31
DQ8
12
20
A0
11
10
19
18
A1
A2
CLOCK
GENERATOR
9
17
31
A3
5
29
22
W
23
A10
A11
30
S1
S2
25
26
1
2
6
30
24
A9
A8
32
OE
27
28
3
4
VCC
(3V)
8
32
16
A13
GND
(0V)
24
*Pin numbers inside dotted line show those of TSOP.
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
Parameter
Supply voltage
Conditions
With respect to GND
Ta=25°C
Ratings
– 0.5*~4.6
Unit
V
– 0.5* ~ Vcc + 0.5
Input voltage
VI
V
(Max 4.6)
Output voltage
VO
Pd
Topr
Tstr
V
mW
°C
0 ~ Vcc
700
0 ~ 70
Power dissipation
Operating temperature
Storage temperature
– 65 ~150
°C
* –3.0V in case of AC ( Pulse width £ 30ns )
(Ta=0~70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Limits
DC ELECTRICAL CHARACTERISTICS
Unit
Symbol
Parameter
Test conditions
Min Typ Max
VIH
High-level input voltage
Vcc
+0.3V
–0.3*
0.6
2.0
V
VIL
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
V
V
2.4
VOH1
VOH2
IOH= –0.5mA
IOH= –0.05mA
Vcc
V
-0.5V
0.4
VOL
II
Low-level output voltage
Input current
IOL=2mA
V
µA
±1
VI=0 ~ Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0 ~ Vcc
IO
Output current in off-state
±1
µA
f= 10MHz
f= 5MHz
S1 £ 0.2V, S2³ Vcc-0.2V,
other inputs £ 0.2V
or ³ Vcc-0.2V,output-open
20
25
Active supply current
(CMOS-level Input)
mA
Icc1
13
27
15
10
22
f= 10MHz
f= 5MHz
S1=VIL,S2=VIH,
other inputs=VIH or VIL
output-open
Active supply current
(TTL-level Input)
Icc2
mA
12
-20 ~ +70°C
-L
60
1) S2 £ 0.2V or
-20 ~ +70°C
-20 ~ +40°C
+25°C
10
1
2) S1 ³ Vcc-0.2V,
S2 ³ Vcc-0.2V
other inputs=0 ~ Vcc
Icc3
Icc4
Stand-by current
Stand-by current
µA
-LL
0.3
0.6
S1=VIH or S2=VIL,other inputs=0 ~ Vcc
0.33
mA
* –3.0V in case of AC ( Pulse width £ 30ns )
(Ta=0 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted)
Limits
CAPACITANCE
Symbol
Parameter
Test conditions
Unit
Typ
Min
Max
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
7
9
CI
CO
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is for Vcc = 3V, Ta = 25°C
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta =0 ~ 70°C, Vcc= 2.7 ~ 3.6V, unless otherwise noted )
1TTL
(1) MEASUREMENT CONDITIONS
.................................
DQ
Vcc
2.7 ~ 3.6V
.............
.....
Input pulse level
VIH=2.2V,VIL=0.4V
5ns
CL
including
scope and JIG
Input rise and fall time
...............
Reference level
Output loads
VOH=VOL=1.5V
Fig.1,CL=30pF
...................
Fig.1 Output load
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
(2) READ CYCLE
Limits
-85L,LL
Min Max Min Max Min Max Min Max
-70L,LL
-10L,LL
-12L,LL
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
ta(A)
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
70
85
100
120
70
70
70
35
25
25
25
85
85
85
45
30
30
30
100
100
100
50
35
35
120
120
120
60
40
40
tdis(OE) Output disable time after OE high
ten(S1)
ten(S2)
ten(OE) Output enable time after OE low
tV(A) Data valid time after address
35
40
10
10
5
Output enable time after S1 low
Output enable time after S2 high
10
10
5
10
10
5
10
10
5
10
10
10
10
(3) WRITE CYCLE
Limits
-70L,LL
-85L,LL
-10L,LL
-12L,LL
Symbol
Parameter
Write cycle time
Write pulse width
Address setup time
Unit
Min Max Min Max Min Max Min Max
tCW
tw(W)
tsu(A)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
55
0
85
60
0
100
75
0
120
85
0
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W 65
70
70
70
35
0
85
85
85
40
0
100
100
100
45
0
Chip select 1 setup time
Chip select 2 setup time
Data setup time
65
65
30
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
0
0
25
25
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
30
30
35
35
40
40
5
5
5
5
5
5
5
5
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~17
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
tdis (OE)
(Note 3)
(Note 3)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~17
tsu (S1)
S1
(Note 3)
(Note 3)
(Note 3)
S2
tsu (S2)
(Note 3)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
ten (W)
W
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
MITSUBISHI
ELECTRIC
5
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~17
tsu (A)
tsu (S1)
trec (W)
S1
S2
(Note 3)
(Note 3)
(Note 3)
(Note 5)
W
(Note 4)
tsu (D)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~17
S1
(Note 3)
(Note 3)
tsu (A)
tsu (S2)
trec (W)
S2
(Note 5)
W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI
ELECTRIC
6
MITSUBISHI LSIs
'97.3.21
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Test conditions
Unit
Min
Typ Max
Power down supply voltage
Chip select input S1
Vcc (PD)
VI (S1)
2
2.0
V
V
V
VI (S2)
Chip select input S2
0.2
50
Vcc = 3.0V
S2 £ 0.2V or
S1 ³ Vcc - 0.2V,S2 ³ Vcc - 0.2V
-L
µA
Icc (PD)
Power down supply current
8
0.3
-LL
(Note 7)
Note7: ICC (PD) = 0.5µA (Max.) in case of Ta = +25°C
(Ta = 0 ~ 70°C, unless otherwise noted )
Limits
(2) TIMING REQUIREMENTS
Unit
Symbol
Parameter
Test conditions
Min Typ Max
tsu (PD)
trec (PD)
Power down set up time
0
5
ns
ms
Power down recovery time
(3) POWER DOWN CHARACTERISTICS
S1 control mode
Vcc
2.7V
2.7V
t su (PD)
t rec (PD)
2.2V
2.2V
S1
S1³ Vcc - 0.2V
S2 control mode
Vcc
2.7V
2.7V
t su (PD)
trec (PD)
S2
0.2V
0.2V
S2 £ 0.2V
MITSUBISHI
ELECTRIC
7
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