首页 |元器件品牌

M5M5V216ATP [MITSUBISHI]

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM; 2097152 - BIT （ 131072 - WORD 16位） CMOS静态RAM
M5M5V216ATP
型号： M5M5V216ATP
厂家： Mitsubishi Group    Mitsubishi Group
描述：

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
2097152 - BIT （ 131072 - WORD 16位） CMOS静态RAM
文件： 总7页 (文件大小：113K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
FEATURES  
DESCRIPTION  
The M5M5V216A is a family of low voltage 2-Mbit static RAMs  
organized as 131,072-words by 16-bit, fabricated by Mitsubishi's  
high-performance 0.25µm CMOS technology.  
Single +2.7~+3.6V power supply  
Small stand-by current: 0.3µA(3V,typ.)  
No clocks, No refresh  
The M5M5V216A is suitable for memory applications where a  
simple interfacing , battery operating and battery backup are the  
important design objectives.  
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small  
outline package. M5M5V216ATP (normal lead bend type package)  
, M5M5V216ART (reverse lead bend type package) , both types  
are very easy to design a printed circuit board.  
From the point of operating temperature, the family is divided into  
three versions; "Standard", "W-version", and "I-version". Those are  
summarized in the part name table below.  
Data retention supply voltage=2.0V to 3.6V  
All inputs and outputs are TTL compatible.  
Easy memory expansion by S , BC1 and BC2  
Common Data I/O  
Three-state outputs: OR-tie capability  
OE prevents data contention in the I/O bus  
Process technology: 0.25µm CMOS  
Package: 44 pin 400mil TSOP (II)  
PART NAME TABLE  
Active  
Access  
Stand-by current Icc(PD), Vcc=3.0V  
typical *  
25 C 40 C 25 C 40 C 70 C 85 C  
Version,  
Operating  
temperature  
Power  
Supply  
current  
Icc1  
(3.0V, typ.)  
Part name  
Ratings (max.)  
time  
max.  
M5M5V216ATP , RT -55L  
M5M5V216ATP , RT -70L  
M5M5V216ATP , RT -55H  
M5M5V216ATP , RT -70H  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
---  
---  
---  
--- 20µA  
---  
---  
Standard  
0 ~ +70 C  
0.3µA 1µA  
1µA 3µA 8µA  
45mA  
M5M5V216ATP , RT -55LW  
M5M5V216ATP , RT -70LW  
M5M5V216ATP , RT -55HW  
M5M5V216ATP , RT -70HW  
(10MHz)  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
2.7 ~ 3.6V  
---  
---  
---  
---  
20µA 50µA  
W-version  
-20 ~ +85 C  
5mA  
1µA 3µA 8µA 24µA  
0.3µA 1µA  
(1MHz)  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
55ns(@ 2.7V) / 50ns(@3.3V)  
70ns(@ 2.7V) / 65ns(@3.3V)  
M5M5V216ATP , RT -55L I  
M5M5V216ATP , RT -70L I  
M5M5V216ATP , RT -55H I  
M5M5V216ATP , RT -70H I  
---  
---  
---  
---  
20µA 50µA  
I-version  
-40 ~ +85 C  
0.3µA 1µA  
1µA 3µA 8µA 24µA  
* "typical" parameter is sampled, not 100% tested.  
PIN CONFIGURATION  
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A4  
A3  
A2  
A1  
A0  
A4  
A3  
A2  
A5  
A5  
A6  
A6  
A7  
OE  
A7  
OE  
Pin  
Function  
A1  
A0  
A0 ~ A16  
Address input  
BC2  
BC1  
DQ16  
DQ15  
DQ14  
DQ13  
GND  
Vcc  
BC2  
BC1  
DQ16  
DQ15  
DQ14  
DQ13  
GND  
Vcc  
S
DQ1  
DQ2  
DQ3  
DQ4  
Vcc  
S
DQ1 ~ DQ16 Data input / output  
DQ1  
DQ2  
DQ3  
DQ4  
Vcc  
GND  
DQ5  
DQ6  
DQ7  
DQ8  
WE  
A16  
A15  
A14  
A13  
A12  
Chip select input  
Write control input  
Output inable input  
Lower Byte (DQ1 ~ 8)  
Upper Byte (DQ9 ~ 16)  
Power supply  
S
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
W
OE  
BC1  
GND  
DQ5  
DQ6  
DQ7  
DQ8  
WE  
A16  
A15  
A14  
A13  
A12  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
DQ12  
DQ11  
DQ10  
DQ9  
NC  
BC2  
Vcc  
A8  
A8  
GND  
Ground supply  
A9  
A9  
Outline: TP : 44P3W - H  
A10  
A11  
NC  
A10  
A11  
RT : 44P3W - J  
NC: No Connection  
NC  
1
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
FUNCTION  
The M5M5V216ATP,RT is organized as 131,072-words by  
16-bit. These devices operate on a single +2.7~3.6V power  
supply, and are directly TTL compatible to both input and  
output. Its fully static circuit needs no clocks and no  
refresh, and makes it useful.  
When setting BC1 and BC2 at a high level or S at a high  
level, the chips are in a non-selectable mode in which both  
reading and writing are disabled. In this mode, the output  
stage is in a high-impedance state, allowing OR-tie with  
other chips and memory expansion by BC1, BC2 and S.  
The operation mode are determined by a combination of  
the device control inputs BC1 , BC2 , S , W and OE.  
Each mode is summarized in the function table.  
A write operation is executed whenever the low level W  
overlaps with the low level BC1 and/or BC2 and the low  
level S. The address(A0~A16) must be set up before the  
write cycle and must be stable during the entire cycle.  
A read operation is executed by setting W at a high level  
and OE at a low level while BC1 and/or BC2 and S are in  
an active state(S=L).  
When setting BC1 at the high level and other pins are in  
an active stage , upper-byte are in a selesctable mode in  
which both reading and writing are enabled, and lower-byte  
are in a non-selectable mode. And when setting BC2 at a  
high level and other pins are in an active stage, lower-  
byte are in a selectable mode and upper-byte are in a  
non-selectable mode.  
The power supply current is reduced as low as 0.3µA(25 C,  
typical), and the memory data can be held at +2V power  
supply, enabling battery back-up operation during power  
failure or power-down operation in the non-selected mode.  
FUNCTION TABLE  
Mode  
DQ1~8 DQ9~16  
Icc  
S BC1 BC2  
W
X
X
L
OE  
X
Non selection  
Non selection  
H
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
H
L
High-Z High-Z Standby  
High-Z High-Z Standby  
X
Write  
Read  
Din  
High-Z Active  
X
L
L
H
H
L
Dout High-Z Active  
High-Z High-Z Active  
L
H
X
L
H
H
H
L
Write  
Read  
High-Z Din  
Active  
Active  
L
H
H
L
High-Z Dout  
L
H
X
L
High-Z High-Z Active  
L
Write  
Read  
Din  
Din  
Active  
Active  
L
L
H
H
Dout  
Dout  
L
L
H
High-Z High-Z Active  
BLOCK DIAGRAM  
A0  
DQ  
1
A1  
MEMORY ARRAY  
DQ  
8
131072 WORDS  
x 16 BITS  
A15  
A16  
-
DQ  
9
CLOCK  
GENERATOR  
DQ  
16  
S
BC1  
BC2  
W
Vcc  
GND  
OE  
2
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Supply voltage  
Input voltage  
Conditions  
Ratings  
Units  
V
With respect to GND  
With respect to GND  
With respect to GND  
V
cc  
VI  
-0.5* ~ +4.6  
-0.5* ~ Vcc + 0.5  
0 ~ Vcc  
Output voltage  
Power dissipation  
VO  
Pd  
700  
mW  
C
Ta=25 C  
Standard  
W-version  
I-version  
(-L, -H)  
0 ~ +70  
Operating  
(-LW, -HW)  
(-LI, -HI)  
Ta  
- 20 ~ +85  
- 40 ~ +85  
- 65 ~ +150  
temperature  
Storage temperature  
Tstg  
C
<
* -3.0V in case of AC (Pulse width 30ns)  
=
( Vcc=2.7 ~ 3.6V, unless otherwise noted)  
Limits  
DC ELECTRICAL CHARACTERISTICS  
Symbol  
Parameter  
Conditions  
Units  
V
Min  
Max  
Typ  
High-level input voltage  
VIH  
VIL  
Vcc+0.3V  
0.6  
2.0  
Low-level input voltage  
-0.3 *  
VOH1  
VOH2  
VOL  
II  
High-level output voltage 1 IOH= -0.5mA  
2.4  
Vcc-0.5V  
High-level output voltage 2  
Low-level output voltage  
Input leakage current  
IOH= -0.05mA  
IOL=2mA  
0.4  
±1  
±1  
VI =0 ~ Vcc  
µA  
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc  
Output leakage current  
IO  
<
<
0.2V  
=
BC1 and BC2 0.2V ,  
=
S
f= 10MHz  
f= 1MHz  
-
-
-
45  
5
60  
15  
60  
15  
60  
25  
30  
10  
5
Active supply current  
( AC,MOS level )  
>
<
other inputs 0.2V or  
Vcc-0.2V  
Icc1  
=
=
Output - open (duty 100%)  
mA  
BC1 and BC2=VIL , S=VIL  
other pins =VIH or VIL  
Output - open (duty 100%)  
f= 10MHz  
f= 1MHz  
Active supply current  
( AC,TTL level )  
45  
5
Icc2  
Icc3  
-
-
+70 ~ +85 C  
+70 C  
-
-LW, -LI  
-L, -LW, -LI  
-HW, -HI  
< 1 >  
>
S
Vcc - 0.2V,  
-
-
=
other inputs = 0 ~ Vcc  
+70 ~ +85 C  
+40 ~ +70 C  
+25 ~ +40 C  
0 ~ +25 C  
-
-
-
-
Stand by supply current  
( AC,MOS level )  
< 2 >  
-H, -HW, -HI  
µA  
>
-
-
-
-
BC1 and BC2 Vcc - 0.2V  
=
1
<
S
0.2V  
-H  
=
0.3  
0.3  
0.3  
2
Other inputs=0~Vcc  
-HW  
- 20 ~ +25 C  
- 40 ~ +25 C  
2
-HI  
2
Stand by supply current  
( AC,TTL level )  
BC1 and BC2=VIH , S=VIL or S=VIH  
Other inputs= 0 ~ Vcc  
Icc4  
-
mA  
-
0.5  
<
Note 1: Direction for current flowing into IC is indicated as positive (no mark)  
Note 2: Typical value is for Vcc=3.0V and Ta=25 C  
* -3.0V in case of AC (Pulse width 30ns)  
=
(Vcc=2.7 ~ 3.6V, unless otherwise noted)  
CAPACITANCE  
Limits  
Units  
Parameter  
Symbol  
Conditions  
Typ  
Min  
Max  
8
CI  
Input capacitance  
VI=GND, VI=25mVrms, f=1MHz  
VO=GND,VO=25mVrms, f=1MHz  
pF  
Output capacitance  
CO  
10  
3
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
(Vcc=2.7 ~ 3.6V, unless otherwise noted)  
AC ELECTRICAL CHARACTERISTICS  
(1) TEST CONDITIONS  
Supply voltage  
2.7V~3.6V  
1TTL  
Input pulse  
VIH=2.2V,VIL=0.4V  
5ns  
DQ  
Input rise time and fall time  
CL  
VOH=VOL=1.5V  
Reference level  
Output loads  
Transition is measured ±500mV from  
steady state voltage.(for ten,tdis)  
Fig.1,CL=30pF  
Including scope and  
jig capacitance  
Fig.1 Output load  
CL=5pF (for ten,tdis)  
(2) READ CYCLE  
Limits  
M5M5V216ATP,RT - 70  
M5M5V216ATP,RT - 55  
Units  
Parameter  
Symbol  
Min  
55  
Max  
Min  
70  
Max  
tCR  
ta(A)  
ta(S)  
ta(BC1)  
ta(BC2)  
ta(OE)  
Read cycle time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
55  
55  
55  
55  
30  
20  
20  
20  
20  
70  
70  
70  
70  
35  
25  
25  
25  
25  
Address access time  
Chip select access time  
Byte control 1 access time  
Byte control 2 access time  
Output enable access time  
tdis(S)  
Output disable time after S high  
Output disable time after BC1 high  
Output disable time after BC2 high  
Output disable time after OE high  
Output enable time after S low  
Output enable time after BC1 low  
Output enable time after BC2 low  
Output enable time after OE low  
Data valid time after address  
tdis(BC1)  
tdis(BC2)  
tdis(OE)  
ten(S)  
ten(BC1)  
ten(BC2)  
ten(OE)  
tV(A)  
10  
10  
10  
5
10  
10  
10  
5
10  
10  
(3) WRITE CYCLE  
Limits  
M5M5V216ATP,RT - 55 M5M5V216ATP,RT - 70  
Units  
Parameter  
Symbol  
Min  
55  
45  
0
Max  
Min  
70  
55  
0
Max  
Write cycle time  
Write pulse width  
Address setup time  
Address setup time with respect to W  
Byte control 1 setup time  
Byte control 2 setup time  
Chip select setup time  
Data setup time  
Data hold time  
Write recovery time  
tCW  
tw(W)  
tsu(A)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
50  
50  
50  
50  
25  
0
65  
65  
65  
65  
30  
0
tsu(A-WH)  
tsu(BC1)  
tsu(BC2)  
tsu(S)  
tsu(D)  
th(D)  
trec(W)  
tdis(W)  
tdis(OE)  
ten(W)  
0
0
20  
20  
25  
25  
Output disable time from W low  
Output disable time from OE high  
Output enable time from W high  
Output enable time from OE low  
5
5
5
5
ten(OE)  
4
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
(4)TIMING DIAGRAMS  
Read cycle  
tCR  
A0~16  
ta(A)  
tv (A)  
ta(BC1)  
ta(BC2)  
or  
BC1  
and / or  
BC2  
(Note3)  
(Note3)  
(Note3)  
(Note3)  
tdis (BC1) or tdis (BC1)  
ta(S)  
S
tdis (S)  
(Note3)  
ta (OE)  
ten (OE)  
OE  
(Note3)  
tdis (OE)  
W = "H" level  
DQ1~16  
ten (BC1)  
ten (BC2)  
ten (S)  
VALID DATA  
Write cycle  
( W control mode )  
tCW  
A0~16  
tsu (BC1) or tsu(BC2)  
BC1  
and / or  
BC2  
(Note3)  
(Note3)  
tsu (A)  
(Note3)  
tsu (S)  
S
tsu (A-WH)  
(Note3)  
OE  
W
tw (W)  
trec (W)  
tdis (W)  
ten(OE)  
ten (W)  
tdis(OE)  
DATA IN  
STABLE  
DQ1~16  
tsu (D)  
th (D)  
5
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
Write cycle (BC control mode)  
tCW  
A0~16  
trec (W)  
tsu (BC1) or  
tsu (BC2)  
tsu (A)  
BC1  
and / or  
BC2  
S
(Note3)  
(Note5)  
(Note3)  
(Note3)  
W
(Note4)  
tsu (D)  
(Note3)  
th (D)  
DATA IN  
STABLE  
DQ1~16  
Write cycle (S control mode)  
tCW  
A0~16  
BC1  
and / or  
(Note4)  
BC2  
(Note3)  
tsu (S)  
(Note3)  
trec (W)  
tsu (A)  
S
(Note5)  
W
(Note4)  
(Note3)  
(Note3)  
tsu (D)  
th (D)  
DATA IN  
STABLE  
DQ1~16  
Note 3: Hatching indicates the state is "don't care".  
Note 4: A Write occurs during S low , overlaps BC1 and/or BC2 low and W low.  
Note 5: When the falling edge of W is simultaneously or priorto the falling edge of BC1 and/or BC2 or the falling edge of S,  
the outputs are maintained in the high impedance state.  
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.  
6
MITSUBISHI ELECTRIC  
MITSUBISHI LSIs  
revision-01, ' 98.12.08  
M5M5V216ATP,RT  
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM  
POWER DOWN CHARACTERISTICS  
(1) ELECTRICAL CHARACTERISTICS  
Limits  
Units  
Symbol  
Parameter  
Test conditions  
Typ  
Min  
2.0  
2.0  
2.0  
-
Max  
Power down supply voltage  
Byte control input BC1 & BC2  
Chip select input S  
Vcc (PD)  
VI (BC)  
VI (S)  
V
V
V
-LW, -LI  
Vcc=3.0V  
1)  
+70 ~ +85 C  
+70 C  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
-
-
50  
20  
24  
8
-L, -LW, -LI  
-HW, -HI  
-
>
BC1 and BC2 Vcc - 0.2V  
+70 ~ +85 C  
-
-
-
-
=
<
S
0.2V  
=
Power down  
supply current  
+40 ~ +70 C  
+25 ~ +40 C  
other inputs=0~3V  
Icc (PD)  
-H, -HW, -HI  
-H  
-
-
-
-
3
1
2)  
0 ~ +25 C  
-20 ~ +25 C  
-40 ~ +25 C  
1
0.3  
0.3  
0.3  
>
S
Vcc - 0.2V  
=
-HW  
-HI  
1
other inputs=0~3V  
1
Typical value is for Ta=25 C  
(2) TIMING REQUIREMINTS  
Limits  
Units  
Symbol  
Parameter  
Test conditions  
Typ  
Min  
0
Max  
tsu (PD)  
trec (PD)  
Power down set up time  
Power down recovery time  
ns  
ms  
5
(3) TIMING DIAGRAM  
BC control mode  
Vcc  
2.7V  
2.7V  
tsu (PD)  
trec (PD)  
2.2V  
BC1  
2.2V  
>
BC1 , BC2 Vcc - 0.2V  
=
BC2  
S control mode  
Vcc  
2.7V  
2.7V  
tsu (PD)  
trec (PD)  
2.2V  
2.2V  
>
S
S Vcc - 0.2V  
=
7
MITSUBISHI ELECTRIC  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
©2020 ICPDF网 联系我们和版权申明