MF0128M-05AAXX [MITSUBISHI]
8/16-bit Data Bus CompactFlash Card; 8位/ 16位数据总线CF卡
| 型号： | MF0128M-05AAXX |
| 厂家： | 
Mitsubishi Group |
| 描述： | 8/16-bit Data Bus CompactFlash Card |
| 文件： | 总32页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI STORAGE CARD
Preliminary
CompactFlash CARDS
MF0032M-05AAxx
MF0064M-05AAxx
MF0096M-05AAxx
MF0128M-05AAxx
8/16-bit Data Bus
CompactFlash Card
Connector Type
Two-piece 50-pin
DESCRIPTION
FEATURES
Mitsubishi’s CompactFlash™ cards provide large
memory capacities on a device approximately the
size of a match box (36.4mm´ 42.8mm´ 3.3mm).
The cards use an 8/16 bit data bus.
Available in 32MB, 64MB, 96MB and 128MB
capacities, Mitsubishi’s CompactFlash cards
conform to the CompactFlash Specification
released from CompactFlash Association.
· Single 5V or 3.3V Supply
· Card density of up to 128MB maximum
· Four PC Card ATA and True IDE modes
· Nonvolatile, No Batteries Required
· High reliability based on internal ECC function
· Fast read/write performance(Target)
<PC Card I/F>
Read:1.5MB/s
Using with the 68-pin adapter card, Mitsubishi's
CompactFlash card operates in PC Card
compliant sockets. It conforms to PCMCIA2.1,
JEIDA4.2 and PC Card Standard.
Write:850kB/s(64/96/128MB)
Write:450kB/s(32MB)
<TrueIDE I/F PIO=2>
Read:1.8MB/s
When the OE# signal is asserted low level by the
Host system in power on cycle, the Mitsubishi’s
CompactFlash cards can be selected in a True IDE
interface. It uses the ATA command set so no
software drivers are required.
Write:1.0MB/s(64/96/128MB)
Write:550kB/s(32MB)
· 300,000 program/erase cycles
APPLICATIONS
· Computers
· Digital Camera
· Data Communication
· Office Automation
· Industrial
· Consumer
*CompactFlash is a trademarks of SanDisk Corporation.
PRODUCT LIST
Memory capacity
(Bytes)
Data Bus
Memory
Cylinder
Head
Sector
Out line
Type I
width(bits)
MF0032M-05AAxx
MF0064M-05AAxx
MF0096M-05AAxx
MF0128M-05AAxx
3,2047,104
64,094,208
96,075,776
128,188,416
256Mbit Flash x 1
256Mbit Flash x 2
256Mbit Flash x 3
256Mbit Flash x 4
489
978
733
978
4
4
8
8
32
32
32
32
8/16
MITSUBISHI
ELECTRIC
1
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
PIN ASSIGNMENT
PC Card
Memory Mode
PC Card I/O
Mode
True IDE Interface
PC Card
Memory Mode
PC Card I/O
Mode
True IDE
Interface
Pin
Pin
Signal
I/O
Signal
I/O
Signal
I/O
Signal
I/O
Signal
I/O
Signal
I/O
1
GND
D3
-
GND
D3
-
GND
D3
-
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CD1#
D11
O
I/O
I/O
I/O
I/O
I/O
I
CD1#
D11
O
I/O
I/O
I/O
I/O
I/O
I
CD1#
D11
O
I/O
I/O
I/O
I/O
I/O
I
2
I/O
I/O
I/O
3
D4
I/O
D4
I/O
D4
I/O
D12
D12
D12
4
D5
I/O
D5
I/O
D5
I/O
D13
D13
D13
5
D6
I/O
D6
I/O
D6
I/O
D14
D14
D14
6
D7
I/O
D7
I/O
D7
I/O
D15
D15
D15
7
CE1#
A10
OE#
A9
I
CE1#
A10
OE#
A9
I
CS0#
N.U
ATA SEL#
N.U
N.U
N.U
Vcc
I
CE2#
VS1#
N.U
CE2#
VS1#
IORD#
IOWR#
WE#
CS1#
VS1#
IORD#
IOWR#
WE#
8
I
I
-
O
-
O
I
O
I
9
I
I
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I
I
-
N.U
-
I
I
A8
I
A8
I
-
WE#
READY
Vcc
I
I
I
A7
I
A7
I
-
-
O
-
IREQ#
Vcc
O
-
INTRQ
Vcc
O
-
Vcc
A6
-
Vcc
A6
-
I
I
N.U
N.U
N.U
N.U
A2
-
CSEL
VS2#
RESET
WAIT#
N.U
I
CSEL
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
I
CSEL
VS2#
RESET#
IORDY
INPACK#
REG#
DASP#
PDIAG#
D8
I
A5
I
I
A5
I
I
-
O
I
O
I
O
I
A4
A4
-
A3
I
A3
I
-
O
-
O
O
I
O
O
I
A2
I
A2
I
I
A1
I
A1
I
A1
I
REG#
BVD2
BVD1
D8
I
A0
I
A0
I
A0
I
O
O
I/O
I/O
I/O
-
O
O
I/O
I/O
I/O
-
I/O
I/O
I/O
I/O
I/O
-
D0
I/O
I/O
I/O
O
O
D0
I/O
I/O
I/O
O
O
D0
I/O
I/O
I/O
O
O
D1
D1
D1
D2
D2
D2
D9
D9
D9
WP
CD2#
IOIS16#
CD2#
IOCS16#
CD2#
D10
D10
D10
GND
GND
GND
N.U = Not used.
MITSUBISHI
ELECTRIC
2
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Signal Description
Signal Name
I/O
I
Pin No.
Description
Address bus[A10-A0]
8, 10, 11, 12,
14, 15, 16, 17,
18, 19, 20
Signals A10-A0 are address bus. A0 is invalid in
word mode. A10 is the MSB and A0 is the LSB.
Data bus[D15-D0]
I/O 31, 30, 29, 28,
27, 49, 48, 47,
6, 5, 4, 3, 2,
Signals D15-D0 are data bus. D0 is the LSB of the
Even Byte of the Word. D8 is the LSB of the Odd
Byte of the Word.
23, 22, 21
Card Enable[CE1#, CE2#]
(PC Card Memory Mode)
Card Enable[CE1#, CE2#]
(PC Card I/O Mode)
I
7, 32
CE1# and CE2# are low active card select signals.
Chip Select[CS0#, CS1#]
(True IDE Interface)
In True IDE Interface, CS0# is used to select the
Command Block Registers. CS1# is used to select
the Control Block Registers.
Output Enable[OE#]
(PC Card Memory Mode)
Output Enable[OE#]
(PC Card I/O Mode)
ATA SEL#
(True IDE Interface)
Write Enable[WE#]
(PC Card Memory Mode)
Write Enable[WE#]
(PC Card I/O Mode)
Write Enable[WE#]
(True IDE Interface)
I/O Read[IORD#]
I
I
9
OE# is used to gate Attribute and Common
Memory Read data from the Card.
OE# is used to gate Attribute Memory Read data
from the Card.
To enable True IDE Interface, this input should be
grounded by the host.
WE# is used for strobing Attribute and Common
Memory Write data into the Card.
36
WE# is used for strobing Attribute Memory Write
data into the Card.
This input should be connected Vcc by the host.
I
I
34
35
37
IORD# is used to read data from the Card’s I/O
space.
(PC Card I/O Mode)
I/O Read[IORD#]
(True IDE Interface)
I/O Write[IOWR#]
(PC Card I/O Mode)
I/O Write[IOWR#]
(True IDE Interface)
Ready[READY]
(PC Card Memory Mode)
IREQ#
(PC Card I/O Mode)
IOWR# is used to write data to the Card’s I/O
space.
O
READY signal is set high when the Card is ready to
accept a new data transfer operation.
This signal of low level is indicates that the card is
requesting software service to host, and high level
indicates that the card is not requesting.
This signal is active high interrupt request to the
host.
INTRQ
(True IDE Interface)
Card Detection[CD1#, CD2#]
O
O
26, 25
24
CD1# and CD2# provided for proper detection of
Card insertion.
This signal is held low because this card does not
have a write protect switch.
This output signal is asserted when the I/O port
address is capable of 16-bit access.
Write Protect[WP]
(PC Card Memory Mode)
IOIS16#
(PC Card I/O Mode)
IOCS16#
(True IDE Interface)
MITSUBISHI
ELECTRIC
3
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Signal Description(Continued)
Signal Name
I/O
I
Pin No.
Description
Attribute Memory Select[REG#]
(PC Card Memory Mode)
Attribute Memory Select[REG#]
(PC Card I/O Mode)
Attribute Memory Select[REG#]
(True IDE Interface)
Battery Voltage Detect[BVD2]
(PC Card Memory Mode)
Audio Digital Waveform[SPKR#]
(PC Card I/O Mode)
DASP#
44
45
41
42
When this signal is asserted, access is limited to
Attribute Memory with OE#/WE# and I/O Space
with IORD#/IOWR#.
This input signal is not used for this mode and
should be connected to Vcc by the host.
This output is driven to a high-level.
O
SPKR# is kept negated because this Card does not
have digital audio output.
I/O
I
This signal is the DISK Active/Slave Present signal
in the Master/Slave handshake protocol.
By assertion of this signal, all registers of this Card
are cleared. This signal should be kept to High-Z or
High Level by the host for at least 1ms after Vcc
applied.
This input pin is the active low hardware reset from
the host.
This signal is asserted to delay completion of the
memory or I/O access cycle.
(True IDE Interface)
Card Reset[RESET]
(PC Card Memory Mode)
Card Reset[RESET]
(PC Card I/O Mode)
Card Reset[RESET#]
(True IDE Interface)
Wait[WAIT#]
(PC card Memory Mode)
O
Wait[WAIT#]
(PC card I/O Mode)
IORDY
(True IDE Interface)
Input Port Acknowledge[INPACK#]
(PC Card I/O Mode)
O
O
43
46
This signal is asserted when the Card is selected
and can respond to an I/O Read cycle at the
address on the address bus.
This signal is not used for this mode and should not
be connected at the host.
Input Port Acknowledge[INPACK#]
(True IDE Interface)
Battery Voltage Detect[BVD1]
(PC Card Memory Mode)
STSCHG#
This output is driven to a high-level.
This signal is asserted low to alert the host to
changes in the status of Configuration Status
Register in the Attribute Memory Space.
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
VS1 is grounded so that the Card CIS can be read
at 3.3V and VS2 is N.C.
This signal is not used for this mode.
(PC Card I/O Mode)
PDIAG#
(True IDE Interface)
Voltage Sense[VS1, VS2]
I/O
O
-
33, 40
39
Cable Select[CSEL]
(PC Card Memory Mode)
Cable Select[CSEL]
(PC Card I/O Mode)
Cable Select[CSEL]
(True IDE Interface)
I
This signal is used to configure this Card as a
Master or a Slave. When this signal is grounded,
this Card is configured as a Master. When this
signal is Open, this Card is configured as a Slave.
5V or 3.3V power.
Vcc
GND
-
-
13, 38
1, 50
Ground.
MITSUBISHI
ELECTRIC
4
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
BLOCK DIAGRAM
Internal Vcc
Controller
Vcc
GND
A10-A0
CE1#/CS0#
CE2#/CS1#
OE#/ATA SEL#
WE#
RESET Circuit
POR#
IORD#
IOWR#
RES#
256Mbit AND
REG#
RESET/RESET#
Flash Memory
CE#
OE#
WE#
CDE#
SC
(x4:128MB)
D15-D0
I/O7-I/O0
R/B#
READY/IREQ#/INTRQ
WP/IOIS16#/IOCS16#
INPACK#
BVD1/STSCHG#/PDIAG#
BVD2/SPKR#/DASP#
WAIT#/IORDY
XIN
XOUT
CSEL
Resonator
VS1
VS2
Open
CD1#
CD2#
MITSUBISHI
ELECTRIC
5
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
FUNCTION TABLE
Function
REG#
CE2#
CE1#
A0
OE#
WE#
IORD#
IOWR#
D15-D8
D7-D0
Attribute Memory Read Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Invalid
Invalid
High-Z
Even Byte
Invalid
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
Attribute Memory Write Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
Even Byte
don’t care
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
Common Memory Read Function
Standby
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Odd Byte
Odd Byte
High-Z
Even Byte
Odd Byte
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
Common Memory Write Function
Standby
X
H
H
H
H
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
don’t care
don’t care
don’t care
Odd Byte
Odd Byte
don’t care
Even Byte
Odd Byte
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
I/O Read Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
High-Z
High-Z
High-Z
Odd Byte
Odd Byte
High-Z
Even Byte
Odd Byte
Even Byte
High-Z
Byte Access
Word Access
Odd Byte
L
I/O Write Function
Standby
X
L
L
L
L
H
H
H
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
don’t care
don’t care
don’t care
Odd Byte
Odd Byte
don’t care
Even Byte
Odd Byte
Even Byte
don’t care
Byte Access
Word Access
Odd Byte
L
MITSUBISHI
ELECTRIC
6
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Memory mapped mode(Index=0)
Register
REG# CE2# CE1# A10 A9-A4 A3 A2 A1 A0
OE#=”L”
WE#=“L”
1
1
1
1
0
1
1
0
0
0
0
1
0
0
0
0
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
x
0
1
x
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Data Register(D15-D0)
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
1
0
0
0
x
0
0
1
x
1
1
1
1
1
0
0
0
1
0
0
0
x
x
x
0
0
0
0
0
0
1
1
1
0
1
x
1
0
0
0
x
0
1
0
x
1
1
1
1
1
0
0
0
1
0
0
0
x
x
x
0
0
0
1
1
1
0
0
0
0
1
x
1
0
0
0
x
0
1
1
x
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
x
x
x
x
x
x
x
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
x
x
0
1
x
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
1
0
0
0
x
1
1
0
x
Error Register(D15-D8)
Feature Register(D15-D8)
1
1
1
1
1
0
0
0
1
0
0
0
x
x
x
1
1
1
1
1
1
0
0
0
0
1
x
invalid
Error Register(D7-D0)
Error Register(D15-D8)
invalid
Feature Register(D7-D0)
Feature Register(D15-D8)
Device Control Register(D7-D0)
invalid
Device Control Register(D7-D0)
invalid
invalid
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
1
0
0
0
x
1
1
1
x
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
x
x
x
x
x
x
x
1
1
1
x
x
x
x
1
1
1
x
x
x
x
1
1
1
x
x
x
x
0
1
x
x
0
1
x
MITSUBISHI
ELECTRIC
7
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Contiguous I/O Map(Index=1)
Register
REG#
CE2# CE1#
A9-A4
A3
A2
A1
A0
IORD#=”L”
IOWR#=“L”
0
0
0
0
0
1
1
0
0
0
0
1
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
x
0
1
x
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Data Register(D15-D0)
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
0
0
0
x
0
0
1
x
0
0
0
1
1
0
0
0
1
x
x
x
0
0
0
0
0
0
1
1
1
0
1
x
0
0
0
x
0
1
0
x
0
0
0
1
1
0
0
0
1
x
x
x
0
0
0
1
1
1
0
0
0
0
1
x
0
0
0
x
0
1
1
x
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
x
x
x
x
x
x
x
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
1
x
x
0
1
x
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
Data Register[Even, Odd](D7-D0)
Data Register[Odd](D7-D0)
Data Register[Odd](D15-D8)
invalid(D7-D0)
0
0
0
x
1
1
0
x
Error Register(D15-D8)
Feature Register(D15-D8)
0
0
0
1
1
0
0
0
1
x
x
x
1
1
1
1
1
1
0
0
0
0
1
x
invalid
Error Register(D7-D0)
Error Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
invalid
Feature Register(D7-D0)
Feature Register(D15-D8)
Device Control Register(D7-D0)
invalid
Device Control Register(D7-D0)
invalid
0
0
0
x
1
1
1
x
0
0
0
1
1
0
0
0
1
x
x
x
1
1
1
1
1
1
1
1
1
0
1
x
invalid
MITSUBISHI
ELECTRIC
8
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Primary(Secondary) I/O(Index=2, 3)
Register
REG# CE2# CE1#
A9-A4
A3 A2 A1 A0
IORD#=”L”
IOWR#=“L”
0
0
0
0
0
1
1
0
0
0
0
1
1Fh(17h)
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
0
0
0
0
0
0
0
0
0
x
0
1
x
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Data Register[Even, Odd](D7-D0)
Feature Register(D7-D0)
Feature Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D15-D8)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Command Register(D15-D8)
Device Control Register(D7-D0)
invalid
Error Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D15-D8)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Sector Number Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D15-D8)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Cylinder High Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D15-D8)
Drive Head Register(D7-D0)
Status Register(D7-D0)
Status Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D15-D8)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
Drive Address Register(D15-D8)
0
0
0
1Fh(17h)
0
0
1
x
0
0
0
1
1
0
0
0
1
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
0
0
0
1
1
1
0
1
x
0
0
0
1Fh(17h)
0
1
0
x
0
0
0
1
1
0
0
0
1
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
1
1
1
0
0
0
0
1
x
0
0
0
1Fh(17h)
0
1
1
x
0
0
0
1
1
0
0
0
1
1Fh(17h)
1Fh(17h)
1Fh(17h)
0
0
0
1
1
1
1
1
1
0
1
x
0
0
0
3Fh(37h)
0
1
1
x
0
0
0
1
1
0
0
0
1
3Fh(37h)
3Fh(37h)
3Fh(37h)
0
0
0
1
1
1
1
1
1
0
1
x
Device Control Register(D7-D0)
invalid
invalid
IDE ATA Interface
Register
CS1#
CS0#
A2-A0
IORD#=”L”
IOWR#=“L”
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0h
1h
2h
3h
4h
5h
6h
7h
6h
7h
Data Register(D15-D0)
Error Register(D7-D0)
Data Register(D15-D0)
Feature Register(D7-D0)
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Drive Head Register(D7-D0)
Command Register(D7-D0)
Device Control Register(D7-D0)
invalid
Sector Count Register(D7-D0)
Sector Number Register(D7-D0)
Cylinder Low Register(D7-D0)
Cylinder High Register(D7-D0)
Drive Head Register(D7-D0)
Status Register(D7-D0)
Alt. Status Register(D7-D0)
Drive Address Register(D7-D0)
MITSUBISHI
ELECTRIC
9
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Configuration Register Specifications
Pin Replacement Register
This register is used for providing the signal state of READY
signal when the card configured I/O card interface.
Configuration Option Register
This register is used for the configuration of the card
configuration status and for the issuing soft reset to the card.
D7
0
D6
0
D5
D4
0
D3
1
D2
1
D1
D0
0
CREADY
RREADY
D7
D6
D5
D4
D3
D2
Index
D1
D0
Name
R/W
R/W
Description
This bit is set to “1” when the RREADY bit
SRESET
LevIREQ
CREADY
changes state. This bit may also be written by
the host.
When read, this bit indicates READY pin
states. When written, this bit acts as a mask
for writing the CREADY bit.
Name
R/W
R/W
Description
SRESET
Setting this bit to “1”, places the card in the reset
state. When the host returns this bit to “0”, the
function shall enter the same unconfigured, reset
state as the card does following a power-up and
hardware reset.
RREADY
R/W
LevIREQ
Index
R/W
R/W
If this bit is set to “0”, card generates pulse mode
interrupt. If this bit is set to “1”, card generates
level mode interrupts.
This bits is used for select operation mode of the
card as follows.
When Power on, Card Hard Reset and Soft
reset, this data is “000000” for the purpose of
Memory card interface recognition.
Index: 0 -> Memory mapped
Socket and Copy Register
This register is used for identification of the card from the
other cards. Host can read and write this register. This
register should be set by host before this card’s
Configuration Option register set.
1 -> Contiguous I/O mapped
2 -> Primary I/O mapped
3 -> Secondary I/O mapped
D7
0
D6
D5
D4
D3
D2
D1
D0
Copy Number
Socket Number
Name
R/W
Description
Configuration and Status Register
This register is used for observing the card state.
Copy Number
R/W
R/W
This bit indicates the drive number of the
card for twin card configuration.
And the host can select and drive one card
by comparing the number in this field with
the drive number of Drive Head Register.
In the way, the host can perform the card’s
master/slave organization.
D7
D6
D5
D4
0
D3
0
D2
D1
D0
0
Changed
SigChg
Iois8
PwrDwn
Intr
Socket
Number
This field indicates to the card that it is
located in the n’th socket.
Name
R/W
R/O
Description
Changed
This bit indicates that CREADY bit on the Pin
Replacement register is set to “1”. When
Changed bit is set to “1”, STSCHG# pin is held
“L” if the SigChg bit is “1” and the card is
configured for the I/O interface.
SigChg
R/W
This bit is set or reset by the host for enabling
and disabling the status change
signal(STSCHG# pin). When the card is
configured I/O card interface and this bit is set
to “1”, STSCHG# pin is controlled by Changed
bit. If this bit is set to “0”, STSCHG# pin is kept
“H”.
Iois8
R/W
R/W
This card is always configured for both 8-bit
and 16-bit I/O, so this bit is ignored.
PwrDwn
When this bit is set to “1”, the card enters
Power Down mode. When this bit is reset to
“0”, the host is requesting the card to enter the
active mode. RREADY bit on Pin Replacement
Register becomes BUSY when this bit is
changed. RREADY will not become Ready until
the power state requested has been entered.
This card automatically powers down when it is
idle, and powers back up when it receives a
command.
Intr
R/W
This bit represents the internal state of the
interrupt request. This bit state is available
whether I/O card interface has been configured
or not. This signal remains True until the
condition which caused the interrupt request
has been serviced. If interrupts are disabled by
the nIEN bit in the Device Control Register, this
bit is a zero.
MITSUBISHI
ELECTRIC
10
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
CIS Information
CIS informatoins are defined as follows.
Offset
Data
7
6
5
4
3
2
1
0
Description
0000h
0002h
01h
03h
CISTPL_DEVICE
TPL_LINK
Common Memory device information
Link to next tuple
Device Type=Dh : Function specific
0004h
D9h
Device Type
1x
WPS
Device Speed
2K
WPS=1
Device Speed=1 : 250ns
2kBytes of address space
: No WPS
0006h
0008h
000Ah
000Ch
000Eh
01h
FFh
1Ch
04h
00h
Marks end of Device Info fields
CISTPL_DEVICE_OC
TPL_LINK
Other Conditions Device information
Link to next tuple
EXT=0, Vcc=5.0V, Wait is not used.
Device Type=Dh : Function specific
WPS=1
EXT
Reserved
Device Type
1x
Vcc
Device Speed
2K
MWAIT
0010h
D9h
WPS
: No WPS
Device Speed=250ns
2kbytes of address space
0012h
0014h
0016h
0018h
001Ah
01h
FFh
1Ch
04h
02h
Marks end of Other Conditions Device Info
CISTPL_DEVICE_OC
Other Conditions Device information
Link to next tuple
EXT=0, Vcc=3.3V, Wait is not used.
Device Type=Dh : Function specific
WPS=1
TPL_LINK
EXT
Reserved
Device Type
1x
Vcc
MWAIT
001Ch
D9h
WPS
Device Speed
: No WPS
Device Speed=250ns
2kbytes of address space
001Eh
0020h
0022h
0024h
0026h
0028h
002Ah
002Ch
002Eh
0030h
0032h
0034h
0036h
0038h
003Ah
003Ch
003Eh
0040h
0042h
0044h
0046h
0048h
004Ah
004Ch
004Eh
0050h
0052h
0054h
0056h
0058h
005Ah
005Ch
005Eh
0060h
0062h
0064h
01h
FFh
18h
02h
DFh
01h
20h
04h
1Ch
00h
01h
00h
15h
1Ch
04h
01h
4Dh
49h
54h
53h
55h
42h
49h
53h
48h
49h
00h
41h
54h
41h
20h
43h
41h
52h
44h
00h
2K
Marks end of Other Conditions Device Info
CISTPL_JEDEC_C
JEDEC Identifier Tuples
Link to next tuple
PC Card ATA
with no Vpp require for any operation
Manufacturer Identification Tuple
Link to next tuple
TPL_LINK
JEDEC identifier for first device info entry.
JEDEC identifiers for remaining device info entries.
CISTPL_MANFID
TPL_LINK
PC Card manufacturer code
manufacturer information
001Ch
0001h
CISTPL_VERS_1
TPL_LINK
TPLLV1_MAJOR
TPLLV1_MINOR
Level 1 Version / Product Information
Link to next tuple
PCMCIA2.0 / JEIDA4.1
PCMCIA2.0 / JEIDA4.1
M
I
T
S
U
B
I
S
H
I
TPLLV1_INFO
A
T
A
C
A
R
D
MITSUBISHI
ELECTRIC
11
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
CIS Information(Continued)
Offset
Data
7
6
5
4
3
2
1
0
Description
0066h
0068h
006Ah
006Ch
006Eh
0070h
0072h
0074h
0076h
34h
2Eh
30h
30h
00h
FFh
21h
02h
04h
4
.
0
0
Marks end of chain.
Function Identification Tuple
Link to next tuple
PC Card ATA(Fixed Disk)
ROM=0 : No BIOS ROM
POST=1: Configure card at power on
CISTPL_FUNCID
TPL_LINK
Card Function Code
0078h
01h
Reserved
ROM
POST
007Ah
007Ch
007Eh
0080h
0082h
0084h
0086h
22h
02h
01h
01h
22h
03h
02h
CISTPL_FUNCE
TPL_LINK
Disk Function Extension Tuple Type
Disk Interface Type
CISTPL_FUNCE
TPL_LINK
Disk Function Extension Tuple Type
Function Extension Tuple
Link to next tuple
Disk Interface Type
PC Card ATA Interface
Function Extension Tuple
Link to next tuple
Basic PC Card ATA Interface tuple
V=0 : No Vpp Required
S=1 : Silicon
0088h
04h
RFU
D
N
U
S
V
U=0 : ID Drive Mfg/SN not Unique
D=0 : Single Drive on Card
P0=1 : Sleep Mode Supported
P1=1 : Standby Mode Supported
P2=1 : Idle Mode Supported
P3=1 : Drive Auto Power Control
N=0 : No Configs exclude I/O port
3F7H/377H
008Ah
0Fh
RFU
I
E
P3
P2
P1
P0
E=0 : Index bit is not emulated
I=0 : IOIS16# use is Unspecified on
Twin Card Configurations
008Ch
008Eh
1Ah
05h
CISTPL_CONF
TPL_LINK
Configuration Tuple
Link to next tuple
RFS=0 : No Reserved Field
RMS=0 : 1 Byte Register Mask
RAS=1 : 2 Byte Config Base Address
Last Index = 3
Configuration Registers are located
at 200H in Reg Space
First 4 Configuration Registers present
Configuration Table Entry Tuple
Link to next tuple
0090h
01h
RFS
RMS
RAS
0092h
0094h
0096h
0098h
009Ah
009Ch
03h
00h
02h
0Fh
1Bh
08h
TPCC_LAST
TPCC_RADR (lsb)
TPCC_RADR (msb)
RFU
RFU
RFU
E
S
P
C
I
CISTPL_CFTABLE_ENTRY
TPL_LINK
Interface Byte Follows, Default Entry,
Configuration Index = 0
009Eh
C0h
I
D
R
Configuration Index
Mem Interface; Bvd's and wProt not used; Ready
active and Wait not used for memory cycles.
00A0h
40h
W
P
B
Interface Type
T
HV
00A2h
00A4h
00A6h
00A8h
00AAh
00ACh
00AEh
00B0h
A1h
01h
55h
08h
00h
21h
1Bh
05h
M
R
X
MS
IR
AI
IO
SI
P
Has Vcc, Mem Space and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
Length of Mem Space is 2 KB
Starts at 0 on card
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
DI
PI
LV
NV
Mantissa
Exponent
Length in 256 bytes pages (lsb)
Length in 256 bytes pages (msb)
X
RFU
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
No Interface Byte, Non Default Entry,
Configuration Index = 0
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
00B2h
00h
I
D
Configuration Index
00B4h
00B6h
00B8h
00BAh
01h
01h
B5h
1Eh
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
HV
P
DI
PI
LV
Exponent
NV
Extension
MITSUBISHI
ELECTRIC
12
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
CIS Information(Continued)
Offset
Data
7
6
5
4
3
2
1
0
Description
00BCh
00BEh
1Bh
0Ah
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 1
I/O Interface; Bvd's and wProt not used;
Ready active and Wait not used for
memory cycles.
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
I/O : Range=0, Bus16=1, Bus8=1,
IO AddrLines=4
00C0h
C1h
I
D
R
Configuration Index
00C2h
41h
W
P
B
Interface Type
T
00C4h
00C6h
00C8h
99h
01h
55h
M
R
X
MS
IR
AI
IO
SI
P
DI
S
PI
HV
LV
Exponent
NV
Mantissa
00CAh
64h
R
E
IO AddrLines
00CCh
00CEh
00D0h
00D2h
00D4h
00D6h
F0h
FFh
FFh
21h
1Bh
05h
S
P
L
M
Level or Mask
Share=1, Pulse=1, Level=1, Mask=1
IRQ Level to be routed 0 - 15
recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
IRQ7
IRQ15
X
IRQ6
IRQ14
RFU
IRQ5
IRQ13
P
IRQ4
IRQ12
RO
IRQ3
IRQ11
A
IRQ2
IRQ10
IRQ1
IRQ9
T
IRQ0
IRQ8
CISTPL_CFTABLE_ENTRY
TPL_LINK
No Interface Byte, Non Default Entry,
Configuration Index = 1
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
00D8h
01h
I
D
Configuration Index
00DAh
00DCh
00DEh
00E0h
00E2h
00E4h
01h
01h
B5h
1Eh
1Bh
0Fh
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
HV
P
DI
PI
LV
NV
Exponent
Extension
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 2
I/O Interface; Bvd's and wProt not used;
Ready active and Wait not used for
memory cycles.
00E6h
C2h
I
D
R
Configuration Index
00E8h
41h
W
P
B
Interface Type
00EAh
00ECh
00EEh
99h
01h
55h
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
HV
P
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
I/O : Range=1, Bus16=1, Bus8=1,
IO AddrLines=10
DI
S
PI
LV
Exponent
NV
00F0h
EAh
R
E
IO AddrLines
Number of Address Ranges = 2
Address Size = 2
00F2h
61h
LS
AS
N Ranges
Length Size = 1
00F4h
00F6h
00F8h
00FAh
00FCh
00FEh
F0h
01h
07h
F6h
03h
01h
First I/O Base Address (LSB)
First I/O Base Address (MSB)
First I/O Length minus 1
Second I/O Base Address (LSB)
Second I/O Base Address (MSB)
Second I/O Length minus 1
First I/O Base Address = 1F0h
First I/O Range is 8 Byte Length
Second I/O Base Address = 3F6h
Second I/O Range is 2 Byte Length
Share=1, Pulse=1, Level=1, Mask=0,
IRQ14 is recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
0100h
EEh
S
X
P
L
M
IRQ Level
0102h
0104h
0106h
21h
1Bh
05h
RFU
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
No Interface Byte, Non Default Entry,
Configuration Index = 2
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
0108h
02h
I
D
Configuration Index
010Ah
010Ch
010Eh
0110h
01h
01h
B5h
1Eh
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
HV
P
DI
PI
LV
Exponent
NV
Extension
MITSUBISHI
ELECTRIC
13
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
CIS Information(Continued)
Offset
Data
7
6
5
4
3
2
1
0
Description
0112h
0114h
1Bh
0Fh
CISTPL_CFTABLE_ENTRY
TPL_LINK
Configuration Table Entry Tuple
Link to next tuple
Interface Byte Follows, Default Entry,
Configuration Index = 3
I/O Interface; Bvd's and wProt not used;
Ready active and Wait not used for
memory cycles.
Has Vcc, I/O, IRQ and Misc Info
Nominal Voltage Only Follows
Vcc Nominal is 5 Volts
I/O : Range=1, Bus16=1, Bus8=1,
IO AddrLines=10
0116h
C3h
I
D
R
Configuration Index
0118h
41h
W
P
B
Interface Type
T
011Ah
011Ch
011Eh
99h
01h
55h
M
R
X
MS
IR
AI
IO
SI
P
DI
S
PI
HV
LV
Exponent
NV
Mantissa
0120h
EAh
R
E
IO AddrLines
Number of Address Ranges = 2
Address Size = 2
0122h
61h
LS
AS
N Ranges
Length Size = 1
0124h
0126h
0128h
012Ah
012Ch
012Eh
70h
01h
07h
76h
03h
01h
First I/O Base Address (LSB)
First I/O Base Address (MSB)
First I/O Length minus 1
Second I/O Base Address (LSB)
Second I/O Base Address (MSB)
Second I/O Length minus 1
First I/O Base Address = 170h
First I/O Range is 8 Byte Length
Second I/O Base Address = 376h
Second I/O Range is 2 Byte Length
Share=1, Pulse=1, Level=1, Mask=0,
IRQ14 is recommended.
Power Down, Twin Card supported.
Configuration Table Entry Tuple
Link to next tuple
0130h
EEh
S
X
P
L
M
IRQ Level
0132h
0134h
0136h
21h
1Bh
05h
RFU
P
RO
A
T
CISTPL_CFTABLE_ENTRY
TPL_LINK
No Interface Byte, Non Default Entry,
Configuration Index = 3
Has Vcc Info
Nominal Voltage Only Follows
Vcc Nominal is 3.3 Volts
0138h
03h
I
D
Configuration Index
013Ah
013Ch
013Eh
0140h
0142h
0144h
0146h
01h
01h
B5h
1Eh
14h
00h
FFh
M
R
X
MS
IR
AI
Mantissa
IO
SI
T
HV
P
DI
PI
LV
Exponent
NV
Extension
CISTPL_NO_LINK
TPL_LINK
No Link Tuple
Link to next tuple
End of List Tuple
CISTPL_END
MITSUBISHI
ELECTRIC
14
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
ATA Register Specifications
Sector Number Register
This register is written by the host with the starting
sector number to be used in the subsequent
Data Register
Cylinder-Head-Sector command. After the command is
complete, the host may read the final sector number
from this register. When logical block addressing is
used, this register is written by the host with bit7 to 0 of
the starting logical block number and contains bit7 to 0
of the final logical block number after the command is
complete.
This register is a 16 bit register which is used to transfer
data blocks between the card data buffer and the host.
Data may be transferred by either a series of word
accesses to the Data register or a series of byte accesses
to the Data register.
D15
D14
D13
D12
D11
D10
D9
D8
Data Word
Odd Data Byte
D7
D6
D5
D4
Sector Number
Logical Block Number bits A07-A00(LBA Addressing)
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Data Word
Data Byte
Cylinder Low Register
This register is written by the host with the low-order
byte of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the low-order
byte of the final cylinder number from this register.
When logical block addressing is used, this register is
written by the host with bits15 to 8 of the starting
logical block number and contains bits15 to 8 of the
final logical block number after the command complete.
Error Register
This register contains additional information about the
source of an error which has occurred in processing of
the preceding command. This register should be
checked by the host when ERR bit in the Status register
is set. The Error register is a read only register.
D7
D6
D5
0
D4
D3
0
D2
D1
0
D0
BBK
UNC
IDNF
ABRT
AMNF
D7
D6
D5
D4
Cylinder Low Byte
Logical Block Number bits A15-A08(LBA Addressing)
D3
D2
D1
D0
Field
BBK
function
This bit is set when a Bad Block is detected in requested
ID field. Host can not read/write on data area that is
marked as a Bad Block.
Cylinder High Register
UNC
This bit is set when Uncorrectable error is occurred at
reading the card.
This register is written by the host with the high-order
byte of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the high-order
byte of the final cylinder number from this register.
When logical block addressing is used, this register is
written by the host with bits 23 to 16 of the starting
logical block number and contains bits23 to 16 of the
final logical block number after the command is
complete.
IDNF
ABRT
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because
of the card status condition. (Not ready, Write fault, etc.) or
when an invalid command has been issued.
This bit is set in case of a general error.
AMNF
Feature Register
This register is written by the host to provide command
specific information to the drive regarding features of
the drive which the host wish to utilize. The Feature
register is a write only register.
D7
D6
D5
D4
Cylinder High Byte
Logical Block Number bits A23-A16(LBA Addressing)
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Feature byte
Sector Count Register
This register is written by the host with the number of
sectors or blocks to be processed in the subsequent
command. After the command is complete, the host may
read this register to obtain the count of sectors left
unprocessed by the command.
D7
D6
D5
D4
D3
D2
D1
D0
Sector Count
MITSUBISHI
ELECTRIC
15
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Drive/Head Register
The Drive/Head register is used to specify the selected
drive of a pair of drives sharing a set of registers.
Device Control Register
This register is used to control the card interrupt request
and to issue a soft reset to the card. The Device Control
register is a write only register.
D7
X
D6
D5
X
D4
D3
D2
D1
D0
LBA
DRV
HS3
LBA27
HS2
LBA26
HS1
LBA25
HS0
LBA24
D7
X
D6
X
D5
X
D4
X
D3
1
D2
D1
D0
0
SRST
nIEN
Field
function
Field
function
X
1
don’t care.
This bit is set to “1”.
X
LBA
Undefined . “0” or “1”.
This bit is “0” for CHS addressing and “1” for Logical
Block addressing.
SRST
This bit is set to “1” in order to force the card to perform a
Command Block Reset operation. This does not change
the Card Configuration registers as a Hardware Reset
does. The card remains in Reset until this bit is reset to
“0”.
This bit is used for enabling IREQ#. When this bit is set to
“0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is
disabled.
DRV
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected.
When DRV is set, Drive1 is selected. The card is
selected to be Drive0 or to be Drive1 using the “Copy”
field of the PC Card Socket Copy Register.
HS3-0 of the head number in CHS addressing or
LBA27-24 of the Logical Block Number in LBA
addressing.
nIEN
0
HS3-0
LBA27-24
This bit is set to “0”.
Status and Alternate Status Registers
The Status register and the Alternate Status register
return the card status when read by the host. Reading
the Status register clears a pending interrupt request
while reading the Alternate Status register does not. The
Status register and the Alternate Status register are read
only registers.
Drive Address Register
This register is provided for compatibility with the AT
disk drive interface.
D7
X
D6
D5
D4
D3
D2
D1
D0
nWT
G
nHS3-0
nDS1
nDS0
Field
function
D7
D6
D5
D4
D3
D2
D1
D0
X
This bit is unknown.
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
nWTG
This bit is set to “0” when a Flash write operation is in
progress, otherwise it is set to “1”.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to “0” when Slave drive is active and
selected.
Field
function
nHS3-0
nDS1
BSY
This bit is set when the card internal operation is
executing. When this bit is set to “1”, other bits in this
register are invalid.
nDS0
This bit is set to “0” when Master drive is active and
selected.
DRDY
DRDY indicates whether the card is capable of
performing card operations.
DWF
DSC
DRQ
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
CORR
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to “0”.
IDX
ERR
This bit is set when the previous command has ended
in some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
Command Register
The Command register contains the command code
being sent to the device. Command execution begins
immediately after this register is written. The Command
register is a write only register.
D7
D6
D5
D4
D3
D2
D1
D0
Command
MITSUBISHI
ELECTRIC
16
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
ATA Command Specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support commands and command
codes which are written in command registers.
Command
Code
FR
SC
SN
y
CY
DR
HD
Check Power Mode
Execute Drive Diagnostic
Erase Sector(s)
Format Track
98h, E5h
90h
C0h
50h
ECh
97h, E3h
95h, E1h
91h
E4h
22h, 23h
C4h
20h, 21h
40h, 41h
1xh
03h
7xh
EFh
C6h
99h, E6h
96h, E2h
94h, E0h
87h
F5h
E8h
32h, 33h
C5h
CDh
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Identify Drive
Idle
y
y
Idle Immediate
Initialize Drive Parameters
Read Buffer
Read Long Sector
Read Multiple
Read Sector(s)
Read Verify Sector(s)
Recalibrate
Request Sense
Seek
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Set Features
y
y
y
Set Multiple mode
Set Sleep Mode
Standby
Standby Immediate
Translate Sector
Wear Level
Write Buffer
Write Long Sector
Write Multiple
Write Multiple without Erase
Write Sector(s)
Write Sector without Erase
Write Verify
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
y
30h, 31h
38h
3Ch
FR : Feature Register,
SC : Sector Count Register,
SN : Sector Number Register,
DR Drive bit of Drive/Head Register,
CY : Cylinder Low/High Register,
HD : Head No. of Drive/Head Register,
MITSUBISHI
ELECTRIC
17
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Check Power Mode(98h, E5h)
This command checks the power mode.
Read Multiple(C4h)
This command performs similarly to the Read Sector(s)
command. Interrupt are not generated on each sector,
but on the transfer of a block which contains the number
of sectors defined by a Set Multiple command.
Execute Drive Diagnostic(90h)
This command performs the internal diagnostic tests
implemented by the card.
Read Sector(s)(20h, 21h)
This command transfers data from the card to the host.
Data transfer starts at the sector specified by the
Cylinder, Head, and Sector Number registers, and
proceeds for the number of sectors specified in the
Sector Count register.
Erase Sector(s)(C0h)
This command is used to pre-erase and condition data
sectors in advance of a Write without Erase or Write
Multiple without Erase command.
Read Verify Sector(s)(40h, 41h)
Format Track(50h)
This command is identical to the Read Sector(s)
command, except that DRQ is not asserted, and no data
is transferred to the host.
This command writes the desired head and cylinder of
the selected drive with a FFh pattern.
Identify Drive(ECh)
Recalibrate(1xh)
This command enables the host to receive parameter
information from the card. (Refer to the Identify Drive
Information table.)
Although this command is supported for backward
compatibility, it has no actual function. The card will
always return good status at the completion of this
command.
Idle(97h, E3h)
This command causes the card to set BSY, enter the Idle
mode, clear BSY and generate an interrupt. If the sector
count is non-zero, the automatic power down mode is
enabled. If the sector count is zero, the automatic power
down mode is disabled.
Request Sense(03h)
This command requests extended error information for
the previous command.
Seek(7xh)
This command is supported for backward compatibility.
Although this command has no actual function, it does
perform a range check of valid track, and posts an IDNF
error if the Head or Cylinder specified are out of
bounds.
Idle Immediate(95h, E1h)
This command causes the card to set BSY, enter the idle
mode, clear BSY and generate an interrupt.
Initialize Drive Parameters(91h)
This command allows the host to alter the number of
sectors per track and the number of heads per cylinder.
Set Features(EFh)
This command is used by the host to establish or select
certain features.
Read Buffer(E4h)
This command enables the host to read the current
contents of the card’s sector buffer.
Set Multiple Mode(C6h)
This command enables the card to perform Read and
Write Multiple operations and establishes the block
count for these commands. This card supports 1 sector
block size.
Read Long Sector(22h, 23h)
This command is similar to the Read Sector(s)
command except the contents of the Sector Count
register are ignored and only one sector is read. The 512
data bytes and 4 ECC bytes are read into the buffer(with
no ECC correction) and then transferred to the host.
Set Sleep Mode(99h, E6h)
This command causes the card to set BSY, enter the
Sleep mode, clear BSY and generate an interrupt.
MITSUBISHI
ELECTRIC
18
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Standby(96h, E2h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
Write Sector(s)(30h, 31h)
This command transfers data from the host to the card.
Data transfer starts at the sector specified by the
Cylinder, Head, and Sector Number registers, and
proceeds for the number of sectors specified in the
Sector Count register.
Standby Immediate(94h, E0h)
This command causes the card to set BSY, enter the
Standby mode, clear BSY and generate an interrupt.
Write Sector without Erase(CDh)
Translate Sector(87h)
This command is similar to the Write Sector(s)
command. The sectors should be pre-erased with the
Erase Sector command before this command is issued. If
the sector is not pre-erased, Write Sector command
operation will occur.
This command allows the host to know the number
of times an user sector has been erased and
programmed. This card doesn't support the Hot
Count value.
Write Verify(3Ch)
Wear Leveling(F5h)
This command is similar to the Write Sector(s)
command, except each sector is verified immediately
after being written.
Although this command is supported for backward
compatibility, it has no actual function. The card will
always return good status at the completion of this
command.
Write Buffer(E8h)
This command enables the host to overwrite contents of
the card’s sector buffer with any data pattern desired.
This command has the same protocol as the Write
Sector(s) command and transfers 512 bytes.
Write Long Sector(32h, 33h)
This command is similar to the Write Sector(s) except
the contents of the Sector Count register are ignored
and only one sector is written. The 512 data bytes and 4
ECC bytes are transferred from the host and then
written from the buffer to the flash.
Write Multiple(C5h)
This command is similar to the Write Sector(s)
command. Interrupts are not presented on each sector,
but on the transfer of a block which contains the number
of sectors defined by Set Multiple command.
Write Multiple without Erase(CDh)
This command is similar to the Write Multiple
command. The sectors should be pre-erased with the
Erase Sector command before this command is issued. If
the sector is not pre-erased, Write Multiple command
operation will occur.
MITSUBISHI
ELECTRIC
19
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Identify Drive Information
Word Address
Data
Description
848Ah
General configuration bit-significant information
15
14
13
12
11
10
9
1
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
Non-rotating disk drive
Format speed tolerance gap not required
Track offset option not available
Data strobe offset option not available
Rotational speed tolerance is < 0.5%
Disk transfer rate > 10Mbs
10Mbs <= Disk transfer rate > 5Mbs
Disk transfer rate <= 5Mbs
Removable cartridge drive
Not a fixed drive
Spindle motor control option not implemented
Head switch time > 15us
Not MFM encoded
Not soft sectored
Hard sectored
8
7
6
5
4
3
2
1
0
Reserved
1
2
3
4
xxxxh
0000h
000xh
0000h
Number of Cylinder(32MB:01E9, 64MB:03D2, 96MB:02DD, 128MB:03D2)
Reserved
Number of Heads(32MB:4, 64MB:4, 96MB:8, 128MB:8)
Number of unformatted bytes per track
5
6
0200h
0020h
Number of unformatted bytes per sector
Number of sectors per track
7-8
xxxxh, xxxxh
Number of sectors per card (word 7 = MSW, word 8 = LSW)
(32MB:0000F480, 64MB:0001E900, 96MB:0002DD00, 128MB:0003D200)
Reserved
9
0000h
2020h
0001h
10-19
20
Reserved
Buffer type: Single ported, single-sector, w/o read cache
21
22
0001h
0004h
xxxxh
xxxxh
0001h
0000h
0200h
0000h
0200h
0000h
0001h
xxxxh
xxxxh
xxxxh
xxxxh
xxxxh
010xh
xxxxh
xxxxh
0000h
Buffer size, in 512 byte increments
ECC length used on Read and Write Long command
Firmware revision, 8 ASCII characters
Model number, 40 ASCII characters.
Maximum Block Count=1 for Read/write Multiple commands
Cannot perform doubleword I/O
Capabilities: LBA supported, DMA not supported
Reserved
PIO timing cycle timing mode 2
DMA transfer not supported
Words 54-58 are valid
23-26
27-46
47
(Rev1.0)
(MF0032M-05AA)
48
49
50
51
52
53
54
Number of Current Cylinders
Number of Current Heads
55
56
Number of Current Sectors per Track
LSW of the Current Capacity in Sectors
MSW of the Current Capacity in Sectors
Current Setting for Block Count for R/W Multiple commands
LSW of the total number of user addressable LBA mode
MSW of the total number of user addressable LBA mode
Reserved
57
58
59
60
61
62-255
MITSUBISHI
ELECTRIC
20
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Vi
Vo
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
-0.3~6.2
-0.3~VCC+0.3
-0.3~VCC+0.3
0~70
V
V
V
°C
°C
With respect to GND
-10~80
RECOMMENDED OPERATING CONDITIONS
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
VCC(5V)
VCC(3.3V)
GND
VCC Supply voltage
VCC Supply voltage
System ground
High input voltage
Low input voltage
4.5
3.135
5.0
3.3
0
5.5
3.465
V
V
V
V
V
VIH
VIL
0.7VCC
0
VCC
0.8
DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VCC=5V±10% or VCC=3.3V±5%, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
V
Min.
Typ.
Max.
3.135V 4.5V 3.3V 5.0V 3.465V 5.5V
READY,
IOH=3mA (3.135V)
4mA (4.5V)
INPACK#,
BVD1,
VOH
High output
voltage
0.8VCC
-
BVD2
IOH=6mA (3.135V)
8mA (4.5V)
the other
outputs
READY,
IOL=-3mA (3.135V) INPACK#,
-4mA (4.5V)
BVD1,
BVD2
VOL
Low output voltage
-
-
0.4
V
IOL=-6mA (3.135V) the other
-8mA (4.5V)
outputs
Output current in
off state
IOZ
±10
µA
CE1#=CE2#= VIH
D15-D0
Active supply
current (Read)
Active supply
current (Write)
ICCR
ICCW
30
35
Output open
75
100
4.0
mA
50
60
55
65
32MB
64/96/128MB
REG# = CE1# = CE2# = Vcc
OE# = IORD# = Vcc
Standby current
(Auto power down) WE# = IOWR# = Vcc
A0-A10 = GND
ICCS
0.15 0.20
3.0
mA
MITSUBISHI
ELECTRIC
21
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
DC ELECTRICAL CHARACTERISTICS(Continued)
Limits
Symbol
Parameter
Test Condition
Unit
Min.
3.135V
Typ.
Max.
3.465V 5.5V
4.5V
CE1#,
CE2#,
OE#,
WE#,
IORD#,
IOWR#,
REG#,
CSEL,
A10-A0,
RESET,
IIH
High input current VIN=VCC
-10
+10
µA
BVD1,BVD2,
D15-D0
CE1#,CE2#,
OE#,WE#,
REG#,
IORD#,IOWR#
RESET
-10
-10
-30
-10
-40
-20
-100
-50
VIN=GND
PC card mode
CSEL
A10-A0,
D15-D0
-10
-10
+10
+10
CE1#,
CE2#,
IORD#,
IOWR#,
A10-A0
RESET
D15-D0
OE#,
IIL
Low input current
µA
VIN=GND
True IDE
mode
WE#,
REG#,
BVD1,
BVD2
-10
-10
-30
-10
-40
-20
-100
-50
CSEL
CAPACITANCE
Limits
Typ.
Symbol
Parameter
Test Condition
Unit
pF
Min.
Max.
CI
CO
Input capacitance
Output capacitance
VI=GND, Vi=25mVrms, f=1 MHZ, Ta=25°C
VO=GND, Vo=25mVrms, f=1 MHZ, Ta=25°C
45
45
Note : These parameters are not 100% tested.
MITSUBISHI
ELECTRIC
22
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
AC ELECTRICAL CHARACTERISTICS
MEMORY TIMING
Read Cycle[Attribute] (Ta=0~70°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Symbol
tcR
Parameter
Unit
Min.
300
Max.
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
Address access time
Card enable access time
300
300
150
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Output enable access time
Output disable time (from CE)
Output disable time (from OE)
Output enable time (from CE)
Output enable time (from OE)
Data valid time (after address change)
5
5
0
MITSUBISHI
ELECTRIC
23
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Read Cycle[Common] (Ta=0~70°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
250
Max.
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcR
ta(A)
Address access time
Card enable access time
250
250
125
100
100
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Output enable access time
Output disable time (from CE)
Output disable time (from OE)
Output enable time (from CE)
Output enable time (from OE)
Data valid time after address change
5
5
0
Write Cycle[Common] (Ta=0~70°C, VCC=5V±10% or VCC=3.3V±5% unless otherwise noted)
Limits
Typ.
Symbol
tcW
Parameter
Unit
Min.
Max.
Write cycle time
Write pulse width
Address setup time
250
150
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(WE)
tsu(A)
tsu(A-WEH)
Address setup time with respect to WE high
180
180
80
tsu(CE-WEH) Card enable setup time with respect to WE high
tsu(D-WEH)
th(D)
Data setup time with respect to WE high
Data hold time
30
trec(WE)
tdis(WE)
tdis(OE)
Write recovery time
30
Output disable time (from WE)
Output disable time (from OE)
Output enable time (from WE)
Output enable time (from OE)
OE set up time with respect to WE low
OE hold time with respect to WE high
100
100
ten(WE)
5
5
ten(OE)
tsu(OE-WE)
th(OE-WE)
10
10
MITSUBISHI
ELECTRIC
24
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
MEMORY TIMING DIAGRAM
Read Cycle
tcR
VIH
An, REG#
VIL
ta(A)
ta(CE)
tV(A)
VIH
CE#
VIL
ten(CE)
tdis(CE)
VIH
ta(OE)
OE#
VIL
tdis(OE)
ten(OE)
VOH
VOL
Hi-Z
Dm
(DOUT)
OUTPUT VALID
WE# =”H” level
Note:
Indicates the don’t care input
Write Cycle
tcW
VIH
An, REG#
VIL
tSU(CE-WEH)
tSU(A-WEH)
VIH
CE#
VIL
VIH
OE#
WE#
VIL
trec(WE)
tW(WE)
tSU(A)
VIH
VIL
th(OE-WE)
tSU(OE-WE)
th(D)
tSU(D-WEH)
VIH
VIL
Dm
(DIN)
Hi-Z
DATA INPUT STABLE
tdis(WE)
ten(OE)
ten(WE)
tdis(OE)
VOH
VOL
Dm
(DOUT)
Hi-Z
MITSUBISHI
ELECTRIC
25
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
I/O READ (INPUT) TIMING
Limit
Unit
Symbol
Parameter
Min
Max
100
td(IORD)
Data Delay after IORD#
Data Hold following IORD#
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IORD)
0
165
70
20
5
tw(IORD)
IORD# Width Time
tsuA(IORD)
Address Setup before IORD#
Address Hold following IORD#
CE# Setup before IORD#
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IORD)
tdrINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
CE# Hold following IORD#
20
5
REG# Setup before IORD#
REG# Hold following IORD#
INPACK# Delay Falling from IORD#
INPACK# Delay Rising from IORD#
IOIS16# Delay Falling from Address
IOIS16# Delay Rising from Address
0
0
45
45
35
35
The maximum load on INPACK# and IOIS16# are 1 LSTTL with 50 pF total load.
I/O WRITE (OUTPUT) TIMING
Symbol
Limit
Parameter
Unit
Min
Max
tsu(IOWR)
Data Setup before IOWR#
60
30
165
70
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IOWR)
Data Hold following IOWR#
IOWR# Width Time
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
Address Setup before IOWR#
Address Hold following IOWR#
CE# Setup before IOWR#
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
CE# Hold following IOWR#
REG# Setup before IOWR#
REG# Hold following IOWR#
IOIS16# Delay Falling from Address
IOIS16# Delay Rising from Address
20
5
0
35
35
The maximum load on INPACK# and IOIS16# are 1 LSTTL with 50 pF total load.
MITSUBISHI
ELECTRIC
26
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
I/O READ (INPUT) TIMING DIAGRAM
An
thA(IORD)
tsuREG(IORD)
thREG(IORD)
REG#
thCE(IORD)
tsuCE(IORD)
CE#
tw(IORD)
IORD#
tsuA(IORD)
tdrINPACK(ADR)
tdrIOIS16(ADR)
INPACK#
IOIS16#
tdf INPACK(IORD)
td(IORD)
th(IORD)
tdfIOIS16(ADR)
D[15::0]
MITSUBISHI
ELECTRIC
27
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
I/O WRITE (OUTPUT) TIMING DIAGRAM
An
thA(IOWR)
tsuREG(IOWR)
thREG(IOWR)
thCE(IOWR)
REG#
CE#
tsuCE(IOWR)
tw(IOWR)
IOWR#
tsu A(IOWR)
tdrIOIS16(ADR)
IOIS16#
tdfIOIS16(ADR)
th(IOWR)
tsu(IOWR)
D[15::0]
MITSUBISHI
ELECTRIC
28
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
True IDE TIMING(Mode 2)
True IDE I/O READ (INPUT) TIMING
Limit
Unit
Symbol
Parameter
Min
Max
60
td(IORD)
Data Delay after IORD#
Data Hold following IORD#
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IORD)
5
tw(IORD)
IORD# Width Time
80
30
10
5
tsuA(IORD)
thA(IORD)
Address Setup before IORD#
Address Hold following IORD#
CS# Setup before IORD#
tsuCS(IORD)
thCS(IORD)
tdfIOCS16(ADR)
tdrIOCS16(ADR)
CS# Hold following IORD#
IOCS16# Delay Falling from Address
IOCS16# Delay Rising from Address
10
35
35
The maximum load on IOCS16# are 1 LSTTL with 50 pF total load.
True IDE I/O WRITE (OUTPUT) TIMING
Limit
Symbol
Parameter
Unit
Min
Max
tsu(IOWR)
Data Setup before IOWR#
30
10
80
30
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(IOWR)
Data Hold following IOWR#
IOWR# Width Time
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
Address Setup before IOWR#
Address Hold following IOWR#
CS# Setup before IOWR#
tsuCS(IOWR)
thCS(IOWR)
tdfIOCS16(ADR)
tdrIOCS16(ADR)
CS# Hold following IOWR#
IOCS16# Delay Falling from Address
IOCS16# Delay Rising from Address
10
35
35
The maximum load on IOCS16# are 1 LSTTL with 50 pF total load.
MITSUBISHI
ELECTRIC
29
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
True IDE I/O READ (INPUT) TIMING DIAGRAM
An
thA(IORD)
tsuCS(IORD)
thCS(IORD)
CS#
tw(IORD)
IORD#
tsuA(IORD)
tdrIOCS16(ADR)
IOCS16#
td(IORD)
th(IORD)
tdfIOCS16(ADR)
D[15::0]
True IDE I/O WRITE (OUTPUT) TIMING DIAGRAM
An
thA(IOWR)
tsuCS(IOWR)
thCS(IOWR)
CS#
tw(IOWR)
IOWR#
tsuA(IOWR)
tdrIOCS16(ADR)
IOCS16#
tsu(IOWR) th (IOWR)
tdf IOCS16(ADR)
D[15::0]
MITSUBISHI
ELECTRIC
30
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
RECOMMENDED POWER UP/DOWN CONDITIONS (Ta=0~70°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Conditions
Unit
Min.
Max.
VCC
VCC+0.1
VCC+0.1
0
V
V
V
0V£ VCC <2V
2V£ VCC <VIH
IH £ VCC
Vi(CE)
CE input voltage
VCC-0.1
VCC
VIH
20
20
1
0.1
3
10
1
0
V
tsu(Vcc)
CE setup time
RESET setup time
CE recover time
Vcc rising time
VCC falling time
RESET width
ms
ms
µs
ms
ms
µs
ms
ms
tsu(RESET)
trec(Vcc)
tpr
10%à90% of Vcc
90% of Vccà10%
100
300
tpf
tw(RESET)
th(Hi-zRESET)
ts(Hi-zRESET)
POWER UP/DOWN TIMING DIAGRAM
tsu(VCC)
tpr
VCC
tsu(RESET)
VCC @ 90%
tsu (RESET)
VIH
2V
VCC @ 10%
CE1#, CE2#
RESET
th(Hi-z RESET)
tw(RESET)
Hi-z
tw(RESET)
tpf
VCC
VCC @ 90%
trec(VCC)
VIH
2V
VCC @ 10%
CE1#, CE2#
ts(Hi-z RESET)
RESET
Hi-z
MITSUBISHI
ELECTRIC
31
June.2001. Rev. 1.3
MITSUBISHI STORAGE CARD
Preliminary
MF0XXXX-05AAXX series
CompactFlash CARDS
Keep safty first in your circuit designs!
· Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always
the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
·These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the
customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi
Electric Corporation or a third party.
·Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of
any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
·All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on
products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to
product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi
Semiconductor home page (http://www.mitsubishichips.com/).
·When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms,
please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained
herein.
·Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
·The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
·If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese
government and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
·Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these
materials or the products contained therein.
MITSUBISHI
ELECTRIC
32
June.2001. Rev. 1.3
相关型号：
MF02-10-5P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
MF02-10-5S
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Receptacle
AMPHENOL
MF02-10-98P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
MF02-12-10P
MIL Series Connector, 10 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
MF02-12-10S
MIL Series Connector, 10 Contact(s), Aluminum Alloy, Female, Crimp Terminal, Receptacle
AMPHENOL
MF02-12-4P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
MF02-12-8P
MIL Series Connector, 8 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
©2020 ICPDF网 联系我们和版权申明