MH16V7245BWJ-5 [MITSUBISHI]
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM; HYPER页模式1207959552 - BIT （ 16777216 - WORD 72 - BIT）动态RAM
| 型号： | MH16V7245BWJ-5 |
| 厂家： | 
Mitsubishi Group |
| 描述： | HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM |
| 文件： | 总22页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
PIN CONFIGURATION
The MH16V7245BWJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard
16M x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
85pin
1pin
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
94pin
95pin
10pin
11pin
FEATURES
/RAS
access access access access
time time time time
/CAS Address /OE
Cycle
Power
Type name
time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
(typ.W)
MH16V7245BWJ-5
MH16V7245BWJ-6
50
60
84
13
15
25
30
13
15
7.02
5.85
104
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
124pin
125pin
40pin
41pin
FRONT SIDE
BACK SIDE
Low stand-by power dissipation
32.4mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V7245BWJ -5 . . . . . . . . . . . . . . . . . . 8.43W(Max)
MH16V7245BWJ -6 . . . . . . . . . . . . . . . . . . 7.78W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 18) decoupling capacitors
4096 refresh cycle every 64ms
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address
A0 ~ A11
Column Address A0 ~ A11
168pin
84pin
APPLICATION
Main memory unit for computers , Microcomputer memory
MITSUBISHI
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ELECTRIC
( 1 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
PIN CONFIGURATION
Pin No.
Pin Name
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
85
86
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DU
NC
1
2
3
87
/CAS6
88
4
89
5
/CAS7
DU
6
90
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
91
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
Vcc
7
NC
92
NC
8
NC
9
93
NC
CB2
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB6
CB7
Vss
95
CB3
Vss
96
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ48
DQ49
DQ50
DQ51
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
DQ52
NC
DQ14
DQ15
CB0
CB1
Vss
DQ46
DQ47
CB4
DU
DU
NC
NC
Vss
CB5
Vss
Vss
DQ21
DQ22
DQ23
Vss
DQ53
DQ54
DQ55
Vss
NC
NC
NC
NC
Vcc
Vcc
/WE0
/CAS0
/CAS1
/RAS0
/OE0
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DU
/CAS4
DQ56
DQ57
DQ58
DQ59
Vcc
/CAS5
NC
DU
Vss
A1
DQ60
DQ61
DQ62
DQ63
Vss
DQ28
DQ29
DQ30
DQ31
Vss
A0
A2
A3
A4
A5
A6
A7
A8
A9
NC
NC
A10
A11
NC
Vcc
DU
DU
NC
NC
NC
SA0
NC
Vcc
SDA
SCL
SA1
Vcc
SA2
Vcc
DU
Vcc
NC: No Connect
DU: Don't Use
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ELECTRIC
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
BLOCK DIAGRAM
/RAS0
/WE0
/OE0
/RAS2
/WE2
/OE2
DQ32
DQ33
DQ34
DQ35
DQ0
DQ1
DQ2
DQ3
/OE
/W
/RAS
/RAS
/RAS
/OE
/OE
/OE
/W
/RAS
/RAS
/RAS
M5M465405BJ
D1
/CAS4
M5M465405BJ
D10
/CAS0
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
/OE
/W
/W
M5M465405BJ
D2
M5M465405BJ
D11
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
/OE
/W
/W
M5M465405BJ
D3
M5M465405BJ
D12
/CAS1
/CAS5
DQ44
DQ45
DQ46
DQ47
DQ12
DQ13
DQ14
DQ15
/OE
/OE
/W
/RAS
/RAS
/RAS
/RAS
/OE
/OE
/OE
/OE
/W
/RAS
/RAS
/RAS
/RAS
M5M465405BJ
D4
M5M465405BJ
D13
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
/W
/W
M5M465405BJ
D5
M5M465405BJ
D14
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
/OE
/W
/W
/CAS2
/CAS6
M5M465405BJ
D6
M5M465405BJ
D15
DQ52
DQ53
DQ54
DQ55
DQ20
DQ21
DQ22
DQ23
/OE
/W
/W
M5M465405BJ
M5M465405BJ
D16
D7
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
/OE
/W
/RAS
/RAS
/OE
/OE
/W
/RAS
/RAS
/CAS3
/CAS7
M5M465405BJ
D8
M5M465405BJ
D17
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
/OE
/W
/W
M5M465405BJ
D9
M5M465405BJ
D18
A0 ~ A11
Vcc
D1 ~ D18
D1 ~ D18
EEPROM
SCL
SDA
A0 A1 A2
C1 ~ C18
. . .
SA0 SA1 SA2
Vss
MITSUBISHI
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ELECTRIC
( 3 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
FUNCTION
The MH16V7245BWJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode,
/CAS before /RAS refresh, and delayed-write. The
input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Refresh
Operation
Remark
Column
address
Row
Input
/RAS
/CAS
/W
/OE
Output
address
Read
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
ACT
ACT
DNC
NAC
ACT
ACT
ACT
DNC
NAC
DNC
ACT
DNC
DNC
ACT
ACT
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
OPN
VLD
VLD
VLD
OPN
DNC
DNC
VLD
OPN
IVD
VLD
VLD
OPN
OPN
YES
YES
YES
YES
YES
YES
NO
Hyper page
mode
identical
Write (Early write)
Write (Delayed write)
Read-modify-write
Hidden refresh
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MITSUBISHI
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ELECTRIC
( 4 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
-0.5~ 4.6
-0.5~ 4.6
-0.5~ 4.6
Unit
V
Vcc
Supply voltage
VI
Input voltage
V
With respect to Vss
VO
IO
Output voltage
V
Output current
50
18
mA
W
Pd
Power dissipation
Operating temperature
Storage temperature
Ta=25°C
Topr
Tstg
0~70
°C
°C
-40~125
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Unit
Min
3.0
0
Nom Max
Vcc
Vss
VIH
Supply voltage
V
V
V
3.3
0
3.6
0
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
2.0
-0.3
Vcc+0.3
0.8
VIL
V
Note 1 : All voltage values are with respect to Vss
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test conditions
Unit
Max
Min
2.4
0
Typ
VOH
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /CAS)
IOH=-2.0mA
Vcc
0.4
10
V
VOL
IOZ
IOL=2.0mA
V
Q floating 0V £VOUT£ Vcc
0V£VIN£Vcc+0.3, Other input pins=0V
0V£VIN£Vcc+0.3, Other input pins=0V
-10
-180
-30
uA
uA
uA
I I
180
30
Input current (/CAS)
I I (CAS)
Average supply
current
from Vcc operating
/RAS, /CAS cycling
tRC=tWC=min.
output open
- 5
- 6
2340
2160
mA
ICC1 (AV)
(Note 3,4,5)
/RAS=/CAS =VIH, output open
18
9
Supply current from Vcc , stand-by
Average supply current
ICC2
mA
mA
/RAS=/CAS=WE³ Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
- 5
1800
1620
from Vcc
ICC4(AV)
Hyper-Page-Mode
- 6
(Note 3,4,5)
Average supply current from
Vcc
/CAS before /RAS refresh cycling
tRC=min.
output open
- 5
- 6
2340
2160
mA
/CAS before /RAS refresh
ICC6(AV)
(Note 3,5)
mode
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VIH
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Limits
Typ
Symbol
Parameter
Unit
Test conditions
Min
Max
20
CI (/CAS) Input capacitance, /CAS input
pF
pF
pF
CI
Input capacitance, except /CAS input
Input/Output capacitance,DATA
Input capacitance, SPD clock
140
15
VI=Vss
f=1MHZ
C(DQ)
C(SCL)
C(SDA)
9
Vi=25mVrms
pF
pF
pF
Input/Output capacitance,SPD DATA
9
7
C(SA0~3) Input capacitance, SPD address
MITSUBISHI
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ELECTRIC
( 5 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
SWITCHING CHARACTERISTICS
Limits
Symbol
Parameter
Unit
- 5
- 6
Min
Max
15
Min
Max
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCAC
tRAC
tAA
Access time from /CAS
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
60
Access time from /RAS
50
30
Column address access time
Access time from /CAS precharge
Access time from /OE
25
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
33
28
15
13
5
5
5
Output hold time from /CAS
Output hold time from /RAS
Output low impedance time /CAS low
Output disable time after /OE high
Output disable time after /WE high
Output disable time after /CAS high
Output disable time after /RAS high
5
5
5
(Note 13)
(Note 7)
13
13
13
13
15
15
15
15
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD ³ tRCD(max), tASC ³ tASC(max) and tCP ³ tCP(max).
9: Assumes that tRCD £ tRCD(max) and tRAD £ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ³ tRAD(max) and tASC £ tASC(max).
11: Assumes that tCP £ tCP(max) and tASC ³ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT £ I ± 10uA I )
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
-5
-6
Symbol
Parameter
Unit
Min
Max
64
Min
Max
64
tREF
tRP
Refresh cycle time
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RAS high pulse width
30
14
5
40
14
5
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
(Note16)
(Note17)
37
45
0
0
8
10
12
0
Column address delay time from /RAS low
Row address setup time before /RAS low
10
0
25
10
30
13
Column address setup time before /CAS low
0
(Note18)
0
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
8
10
10
0
8
0
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
0
0
13
13
13
1
15
15
15
1
50
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
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ELECTRIC
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MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Limits
Parameter
-5
-6
Unit
Min
84
50
8
Max
Min
104
60
10
48
15
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read cycle time
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
tORH
tOCH
10000
10000
/RAS low pulse width
10000
10000
/CAS low pulse width
35
13
0
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
Column address to /CAS hold time
/RAS hold time after /OE low
/CAS hold time after /OE low
0
0
(Note 22)
(Note 22)
0
0
25
13
13
13
30
18
15
15
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
Unit
-5
-6
Min
84
50
8
Max
Min
104
60
10
40
15
0
Max
tWC
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10000
10000
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
/RAS low pulse width
10000
10000
/CAS low pulse width
35
13
0
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
(Note 24)
8
10
10
10
10
0
8
8
8
tDS
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
0
tDH
8
10
Read-Write and Read-Modify-Write Cycles
Limits
Unit
Symbol
Parameter
-5
-6
Min
109
75
38
70
38
0
Max
Min
133
89
44
82
44
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
/RAS low pulse width
(Note23)
10000
10000
10000
10000
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/OE hold time after /W low
(Note24)
(Note24)
(Note24)
28
65
40
13
32
77
47
15
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min) and tCPWD ³ tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 7 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25)
Limits
Symbol
tHPC
Parameter
Unit
-6
-5
Max
Max
Min
25
66
5
Min
Hyper page mode read/write cycle time
ns
ns
ns
ns
ns
ns
ns
20
55
5
tHPRWC Hyper page mode read write/read modify write cycle time
Output hold time from /CAS low
/RAS low pulse width for read write cycle
/CAS high pulse width
tDOH
tRAS
tCP
77
10
33
50
100000
16
100000
13
(Note26)
(Note27)
65
8
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
28
43
7
tCPRH
tCPWD
(Note24)
Hold time to maintain the data Hi-Z until /CAS access
ns
ns
ns
7
7
tCHOL
tOEPE
tWPE
7
/OE Pulse width (Hi-Z control)
/W Pulse width (Hi-Z control)
7
7
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
32
47
50
ns
ns
ns
tHCWD
tHAWD
tHPWD
28
40
43
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS precharge to /OE high after read
15
30
33
ns
ns
ns
tHCOD
tHAOD
tHPOD
13
25
28
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
26: tRAS(min) is specified as two cycles of /CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP ³ tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 28)
Limits
Symbol
Parameter
Unit
-5
-6
Max
Max
Min
5
Min
5
ns
ns
ns
ns
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
10
10
10
10
10
10
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 8 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Timing Diagrams (Note 29)
Read Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
/CAS
tRAL
tCAL
tRAD
tASR
tASR
tRAH
tASC
tCAH
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
Address
tRRH
tRCH
tRCS
VIH
VIL
/W
tCDD
tDZC
tRDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tREZ
tOHR
tWEZ
tOFF
tOHC
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA VALID
Hi-Z
Hi-Z
tRAC
tOEA
tDZO
tOEZ
tODD
tOCH
VIH
VIL
/OE
tORH
Indicates the don't care input.
VIH(min) VIN VIH(max) or VIL(min)
Note 29
VIN
VIL(max)
Indicates the invalid output.
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 9 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Early Write Cycle
tWC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tASR
tRCD
tRSH
tCAS
VIH
/CAS
VIL
tASR
tRAH
tCAH
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
Address
VIL
tWCS
tWCH
VIH
/W
VIL
tDH
tDS
VIH
DQ
DATA VALID
(INPUTS)
VIL
VOH
DQ
Hi-Z
(OUTPUTS)
VOL
VIH
/OE
VIL
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 10 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Delayed Write Cycle
tWC
tRP
tRAS
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tASR
tRSH
tCAS
tRCD
VIH
/CAS
VIL
tRAH
tCAH
tASC
tASR
VIH
Address
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
VIL
tCWL
tRWL
tWP
tRCS
VIH
/W
VIL
tWCH
tDZC
tDS
tDH
VIH
DQ
DATA
VALID
Hi-Z
tCLZ
(INPUTS)
VIL
VOH
DQ
Hi-Z
Hi-Z
(OUTPUTS)
VOL
tOEH
tOEZ
tODD
tDZO
VIH
/OE
VIL
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 11 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tRSH
tCAS
tCRP
VIH
/CAS
VIL
tRAD
tASR
tRAH
ROW
tCAH
tASR
tASC
VIH
Address
COLUMN
ADDRESS
tAWD
ROW
ADDRESS
ADDRESS
VIL
tCWD
tRWD
tCWL
tRWL
tWP
tRCS
VIH
/W
VIL
tDH
tDS
tDZC
VIH
DQ
(INPUTS)
Hi-Z
DATA VALID
VIL
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
(12 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS
tRP
VIH
VIL
/RAS
/CAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tASR
tCAS
tRCD
tCP
tCP
VIH
VIL
tRAD
tRAH
tCPRH
tCAH
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tCAL
COLUMN-1
tRCS
Address
tRRH
tCAL
tCAL
tRCH
VIH
VIL
/W
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tDOH
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
(13 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCRP
tCP
tCP
VIH
VIL
/CAS
tCAL
tCAH
tCAL
tCAH
tASC
tASC
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
COLUMN-1
Address
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
/W
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIL
VIH
/OE
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 14 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRWL
tCRP
tCRP
tASR
tHPRWC
tCAS
tRCD
tCAS
tCP
VIH
VIL
/CAS
tRAD
tRAH
tCWL
tCAH
tASC
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
Address
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
/W
tRWD
tCPWD
tDZC
tDH
tDZC
tDH
tDS
tDS
VIH
VIL
DQ
(INPUTS)
DATA
VALID-1
DATA
VALID-2
Hi-Z
tCAC
Hi-Z
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tCPA
tDZO
tODD
tODD
tOEH
tDZO tOEA
tOEZ
tOEZ
tOEA
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 15 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRP
tRAS
tRWL
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tHPC
tCAS
tHPRWC
tCAS
tCRP
tASR
tCAS
tCP
tCP
VIH
tCWL
/CAS
VIL
tRAD
tRAH
tASR
tASC
tCAH
tASC tCAH
COLUMN-3
tCAH
tASC
VIH
Address
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-1
tRCS
VIL
tCPWD
tAWD
tCWD
tWCH
tCAL
tWCS
tCAL
tWP
VIH
/W
VIL
tDH
tDZ
C
tDZC
tDH
tDS
tDS
VIH
DATA
VALID-2
DATA
VALID-3
DQ
(INPUTS)
tCAC
tAA
VIL
tAA
tCAC
tWEZ
tCLZ
tCLZ
VOH
DQ
DATA
VALID-3
DATA
VALID-1
Hi-Z
(OUTPUTS)
VOL
tRAC
tDZO
tCPA
tOEA
tOEA
tOEH
tDZO
tOEZ
tOEZ
VIL
tOCH
/OE
VIH
tODD
tODD
Note 30: /OE=L; /W= Hi-Z control
/OE=H;/OE= Hi-Z control
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
(16 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH
VIL
/RAS
tHPC
VIH
VIL
/CAS
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tCAH
tASC
tASC
VIH
VIL
Address
COLUMN-1
COLUMN-2
COLUMN-3
tCAL
tRCH
tCAL
tWCH
tWCS
tDS
VIH
VIL
/W
tHCWD
tHAWD
tDH
tDZC
tHPWD
VIH
VIL
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tCAC
tAA
tCPA
tAA
tWEZ
tCPA
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tHCOD
tHAOD
tHPOD
tOEA
tDZC
tOEZ
tODD
VIL
VIH
/OE
Note 30: /OE=L; /W= Hi-Z control
/OE=H;/OE= Hi-Z control
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 17 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tASR
tCAS
tCRP
tRCD
tCP
tCP
VIH
VIL
/CAS
tRAD
tRAH
tCPRH
tCAH
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRAL
Address
tRRH
tRCS
tRCH
VIH
VIL
/W
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tDOH
tCLZ
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-1
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tCHOL
tOCH
tOEA
tOEZ
tOEZ
VIL
VIH
/OE
tODD
tOEPE
tOEPE
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 18 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS
tRP
VIH
VIL
/RAS
/CAS
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCP
tCP
tCRP
VIH
VIL
tCPRH
tCAH
tRAD
tRAH
tASR
tASC
tASC
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tRAL
COLUMN-1
Address
tRRH
tRCS
tRCH
tRCH
tRCS
VIH
VIL
/W
tDZC
tWPE
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tCLZ
tREZ
tOHR
tOFF
tOHC
tDOH
tCLZ
tWEZ
VOH
VOL
DATA
VALID-2
DQ
(OUTPUTS)
DATA
VALID-1
DATA
VALID-3
Hi-Z
tCPA
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MITSUBISHI
ELECTRIC
MIT-DS-0241-0.0
28/Jul/`98
19
(
/ 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
/CAS before /RAS Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
/RAS
/CAS
VIH
VIL
tCRP
tCSR
tRPC
tCHR
tCSR
tCHR
tRPC
tRPC
VIH
VIL
tCPN
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
Address
/W
tRRH
tRCH
tRCS
VIH
VIL
VIH
VIL
DQ
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
tOEZ
VIH
VIL
/OE
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 20 / 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
/RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
/CAS
Address
/W
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
COLUMN
ADDRESS
ROW
ADDRESS
ROW
ADDRESS
tRCS
tDZC
tRRH
tRAL
tRCH
VIH
VIL
tCDD
tRDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tREZ
tCAC
tAA
tOHR
tOFF
tOHC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
/OE
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
21
(
/ 22 )
MITSUBISHI LSIs
Preliminary Spec.
Specifications subject to
change without notice.
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Unit:mm
Package outline
133.35
8.6MAX
3.0
127.35
2-R2.0
2.0
2.0
1.27
2-ø3.0
1.27
6.35
29x1.27=36.83
9x1.27=11.43
6.35
43x1.27=54.61
8.89
42.18
24.495
MITSUBISHI
MIT-DS-0241-0.0
28/Jul/`98
ELECTRIC
( 22 / 22 )
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