MH2S72CMD-15B [MITSUBISHI]
Synchronous DRAM Module, 2MX72, 9ns, CMOS, DIMM-168;
| 型号： | MH2S72CMD-15B |
| 厂家： | 
Mitsubishi Group |
| 描述： | Synchronous DRAM Module, 2MX72, 9ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总47页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
DESCRIPTION
The MH2S72CMD is 2097152-word by 72-bit
Synchronous DRAM module. This consists of nine
industry standard 2Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
85pin
1pin
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
94pin
95pin
10pin
11pin
FEATURES
CLK Access Time
Frequency
(Component SDRAM)
-10
-12
8ns(CL=3)
8ns(CL=3)
100MHz
83MHz
9ns(CL=3)
67MHz
-15
124pin
125pin
40pin
41pin
Utilizes industry standard 2M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz/83MHz/67MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA(Bank Address)
/CAS latency- 1/2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
84pin
168pin
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
Module item "-10","-12" , and "-15" show mounted SDRAM devices Cycle time(min.).
MITSUBISHI
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MIT-DS-0105-2.0
28.Mar.1997
( 1 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
PIN NO.
PIN NAME
VSS
PIN NO.
PIN NAME
VSS
PIN NO.
PIN NAME
PIN NO.
PIN NAME
VSS
85
86
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
2
DQ0
NC
CKE0
NC
87
3
DQ1
/S2
88
4
DQ2
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
89
5
DQ3
90
6
VDD
DQ4
91
7
VDD
NC
VDD
NC
92
8
DQ5
93
9
DQ6
NC
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ7
CB2
CB6
95
DQ8
CB3
CB7
VSS
96
VSS
VSS
97
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NC
NC
NC
NC
CB1
VSS
CB5
VSS
VSS
DQ21
DQ22
DQ23
VSS
VSS
NC
DQ53
DQ54
DQ55
VSS
NC
NC
NC
VDD
/WE0
VDD
/CAS
DQMB4
DQMB5
NC
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
DQMB0
DQMB1
/S0
NC
/RAS
VSS
A1
VSS
A0
A2
A3
A4
A5
A6
A7
A8
A9
CK2
NC
CK3
NC
A10
NC
BA
NC
SA0
SA1
SA2
VDD
NC
VDD
VDD
CK0
SDA
SCL
VDD
VDD
CK1
NC
NC = No Connection
MIT-DS-0105-2.0
MITSUBISHI
ELECTRIC
28.Mar.1997
( 2 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
Block Diagram
/S0
DQMB0
DQMB4
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
DQ0
DQ1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ2
DQ3
DQ4
D0
D5
D6
DQ5
DQ6
DQ7
DQMB1
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D2
DQM /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0
CK1
CK2
CK3
/S2
DQMB2
DQMB6
DQM
DQM
/CS
/CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D4
D7
DQM
DQM
/CS
/CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D0 - D17
D0 - D17
D0 - D17
D0 - D17
D0 - D17
/RAS
/CAS
/WE
D0 - D8
CKE0
SCL
BA,A<10:0>
Vcc
SERIAL PD
A0 A1 A2
SA0 SA1 SA2
SDA
CK,DQ,CB=10W
others = 0W
Vss
D0 - D17
MITSUBISHI
ELECTRIC
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28.Mar.1997
(
/ 47 )
3
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
SPD enrty data
SPD DATA(hex)
0
128
80
08
04
0B
09
01
48
00
01
A0
C0
F0
80
80
90
02
80
08
08
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
1
256 Bytes
2
SDRAM
3
# Row Addresses on this assembly
A0-A10
4
# Column Addresses on this assembly
# Module Banks on this assembly
A0-A8
5
1BANK
6
Data Width of this assembly...
x72
7
... Data Width continuation
0
8
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -10
LVTTL
9
10ns
Cycle time for CL=3
-12
-15
-10
-12
-15
12ns
15ns
10
SDRAM Access from Clock
tAC for CL=3
8ns
8ns
9ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
ECC
self refresh(15.625uS)
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
x8
x8
1
1/2/4/8
# Banks on Each SDRAM device
CAS# Latency
2bank
CL=1/2/3
CS# Latency
0
Write Latency
0
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
-10
-12
-15
15ns
15ns
20ns
9ns
24
25
26
27
28
SDRAM Access form Clock(2nd highest CAS latency) -10
tAC for CL=2
-12
-15
-10
-12
-15
9.5ns
12ns
30ns
30ns
30ns
27ns
27ns
30ns
30ns
30ns
40ns
20ns
24ns
30ns
SDRAM Cycle time(3rd highest CAS latency)
Cycle time for CL=1
SDRAM Access form Clock(3rd highest CAS latency) -10
tAC for CL=1
-12
-15
-10
-12
-15
-10
-12
-15
Precharge to Active Minimum
Row Active to Row Active Min.
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
Serial Presence Detect Table
29
RAS to CAS Delay Min
-10
-12
-15
-10
-12
-15
30ns
30ns
1E
1E
30ns
1E
30
Active to Precharge Min
60ns
3C
70ns
46
80ns
50
31
32-61
62
Density of each bank on module
Superset Information (may be used in future)
SPD Revision
16MByte
04
option
00
rev 1
01
63
Checksum for bytes 0-62
Check sum for -10
Check sum for -12
Check sum for -15
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
B1
E4
84
64-71
72
Manufactures Jedec ID code per JEP-108E
Manufacturing location
1CFFFFFFFFFFFFFF
01
02
03
Germany
04
4D4832533732434D442D3130202020202020
4D4832533732434D442D3132202020202020
4D4832533732434D442D3135202020202020
4D4832533732434D442D3130422020202020
4D4832533732434D442D3132422020202020
4D4832533732434D442D3135422020202020
73-90
Manufactures Part Number
MH2S72CMD-10
MH2S72CMD-12
MH2S72CMD-15
MH2S72CMD-10B
MH2S72CMD-12B
MH2S72CMD-15B
PCB revision
year/week code
serial number
option
91-92
93-94
95-98
99-125
126
Revision Code
Manufacturing date
rrrr
yyww
ssssssss
00
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
66MHz
66
127
CL=3: 04H, CL=2/3: 06H
open
06
128+
00
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
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( 5 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CK
Input
(CK0 ~ CK3)
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE0
Input
Chip Select: When /S is high,any command means
No Operation.
/S
Input
Input
(/S0 ,/S2)
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-10 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-10.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
A0-10
Input
Bank Address:BA is not simply BA.BA specifies the bank
to which a command is applied.BA must be set with
ACT,PRE,READ,WRITE commands
BA
Input
Data In and Data out are referenced to the rising edge of
Input/Output
Input/Output
DQ0-63
CK
DQ
Check bit data In and Check bit data out are referenced
CB0-7
to the rising edge of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is high
in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss
Input
Power Supply Power Supply for the memory mounted module.
Input
Serial clock for serial PD
SCL
SDA
Output
Input
Serial data for serial PD
SA0-3
Address input for serial PD
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 6 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH2S72CMD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
Command
Command
define basic commands
/WE
CKE
A10
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks are
deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MITSUBISHI
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
CK
n-1
CK
n
/CAS
BA
COMMAND
MNEMONIC
/RAS
/WE
A10 A0-9
/S
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
V
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
WRITEA
READ
H
H
H
H
X
X
X
X
L
L
L
L
LH
H
L
L
L
L
V
V
V
V
L
V
V
V
V
Column Address Entry
& Write with Auto-
Precharge
H
L
H
L
Column Address Entry
& Read
H
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
HL
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
LX
H
REFSX
H
H
X
X
X
H
H
L
X
L
X
Burst Terminate
TERM
MRS
H
H
H
X
V*1
Mode Register Set
L
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MITSUBISHI
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Command
DESEL
NOP
Current State
IDLE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
L
BA
TBST
ILLEGAL*2
L
X
H
L
BA,CA,A10
BA,RA
READ/WRITE ILLEGAL*2
L
H
H
L
ACT
Bank Active,Latch RA
NOP*4
L
L
BA,A10
X
PRE/PREA
REFA
L
L
H
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
Precharge/Precharge All
ILLEGAL
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
PRE/PREA
REFA
BA,A10
H
X
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
X
TBST
BA
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
BA
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
READ/READA
L
L
H
H
L
L
H
L
BA,CA,A10
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
PRE/PREA
REFA
Bank Active/ILLEGAL*2
Terminate Burst,Precharge
ILLEGAL
H
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
BA
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
Bank Active/ILLEGAL*2
ILLEGAL*2
BA,A10
PRE/PREA
REFA
H
X
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
WRITE with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
TBST
BA
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
BA,RA
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2
ILLEGAL*2
BA,A10
X
PRE/PREA
REFA
H
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING
L
BA
TBST
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
L
L
NOP*4(Idle after tRP)
ILLEGAL
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL*2
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
L
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
L
L
H
Op-Code,
Mode-Add
X
L
L
L
L
MRS
ILLEGAL
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10
BA,RA
BA,A10
X
READ/WRITE ILLEGAL
H
H
L
ACT
PRE/PREA
REFA
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CK
n-1
CK
n
Action
Current State
/RAS /CAS /WE Add
/S
INVALID
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
REFRESH*1
L
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
Enter Power Down
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
ILLEGAL
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
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/ 47 )
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
REFA
AUTO
REFRESH
IDLE
ACT
CKEL
CKEH
CLK
SUSPEND
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
READ
READA
READ
WRITEA
WRITE
CKEL
CKEL
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
PRE
CKEL
CKEH
CKEL
CKEH
WRITEA
SUSPEND
READA
SUSPEND
PRE
WRITEA
READA
PRE
POWER
APPLIED
POWER
ON
PRE
CHARGE
PRE
Automatic Sequence
Command Sequence
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500É s.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
CK
/S
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/RAS
/CAS
0
0
0
0
0
BL
LTMODE
BT
/WE
V
BA, A10 -A0
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
1
2
2
CL
/CAS LATENCY
4
4
BURST
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
1
8
8
LENGTH
R
R
R
R
R
R
R
R
2
LATENCY
MODE
3
4
R
R
R
0
1
SEQUENTIAL
INTERLEAVED
BURST
TYPE
R:Reserved for Future Use
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
CK
Command
Address
DQ
Read
Y
Write
Y
Q0
Q1
Q2
Q3
D0
D1
D3
D2
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with
the bank address(BA). A row is indicated by the row address A10-0. The minimum activation
interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command
A0-9
A10
ACT
Xa
Xa
0
ACT READ
PRE
ACT
Xb
Xb
1
tRRD
tRAS
tRP
Xb
Xb
1
Y
0
0
tRCD
1
BA
DQ
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A8-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start
timing depends on /CAD Latency. The next ACT command can be issued after tRP from the
internal precharge timing.
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
Dual Bank Interleaving READ (BL=4, CL=3)
CK
Command
A0-9
ACT
Xa
Xa
0
READ ACT
READ PRE
Y
tRCD
Y
0
0
Xb
Xb
1
A10
0
1
0
0
BA
DQ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
/CAS latency
READ with Auto-Precharge (BL=4, CL=3)
CK
Command
A0-9
ACT
Xa
Xa
0
READ
ACT
Xa
Xa
0
tRCD
tRP
Y
1
0
A10
BA
DQ
Qa0 Qa1 Qa2 Qa3
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CK
Command
CL=4 DQ
CL=3 DQ
CL=2 DQ
ACT
READ
Qa0 Qa1 Qa2
Qa3
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A8-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by
interleaving the dual banks. From the last input data to the PRE command, the write recovery
time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA)
is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CK
Command
A0-9
A10
ACT
Xa
Xa
0
Write ACT
Write PRE
tRCD
tRCD
Y
0
0
Y
Xb
Xb
1
tWR
0
1
0
0
BA
DQ
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Burst Length
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Xa
Xa
0
Write
ACT
Xa
Xa
0
tRCD
Y
tRP
A0-9
A10
1
0
BA
tWR
DQ
Da0 Da1 Da2 Da3
Internal precharge begins
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank.
MH2S72CMD allows random column access. READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9
A10
READ READ
READ
READ
Yi
0
Yj
0
Yk
0
Yl
0
BA
0
0
1
0
DQ
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CK
Command
READ
Write
A0-9
Yi
0
Yj
0
A10
BA
0
0
DQMB0-7
Q
D
Qai0
Daj0 Daj1 Daj2 Daj3
DQM control
Write control
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank. Read
to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on
the /CAS Latency. The figure below shows examples, when the dataout is terminated.
Read Interrupted by Precharge (BL=4)
CK
Command
DQ
READ
READ
PRE
Q0
Q1
Q1
Q2
Q3
CL=4
CL=3
CL=2
Command
DQ
PRE
Q0
Command
DQ
READ
READ
PRE
Q1
Q0
Q0
Q2
Q3
Command
DQ
PRE
Q1
Command
DQ
PRE
Q2
READ
READ
Q0
Q1
Q1
Q3
Command
DQ
PRE
Q0
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Preliminary Spec.
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation and
disable the data output. READ to TERM interval is minimum 1 CK. The figure below shows
examples, when the dataout is terminated.
Read Interrupted by Burst Terminate (BL=4)
CK
Command
DQ
READ
TERM
Q1
Q0
Q2
Q2
Q3
Command
DQ
READ
TERM
Q0
CL=3
Q1
Command
DQ
READ TERM
Q0
Command
DQ
TERM
Q2
READ
READ
Q0
Q0
Q0
Q1
Q3
Command
DQ
TERM
Q1
CL=2
Q2
Command
DQ
READ
TERM
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Preliminary Spec.
MITSUBISHI LSIs
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MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9
A10
Write Write
Write
Yk
0
Write
Yi
0
Yj
0
Yl
0
BA
0
0
1
0
DQ
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CK
Command
A0-9
Write READ
Write
Yk
0
READ
Yi
0
Yj
0
Yl
0
A10
BA
0
0
0
1
DQMB0-7
DQ
Dai0
Qaj0 Qaj1
Dak0 Dak1
Qbl0
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required between
the last input data and the next PRE, 3rd data should be masked with DQMB0-7
shown as below.
Write Interrupted by Precharge (BL=4)
CK
Command
A0-9
Write
PRE
ACT
Xb
Xb
0
tWR
tRP
Yi
0
A10
0
0
BA
0
DQMB0-7
DQ
Dai0 Dai1
This data should be masked to satisfy tWR requirement.
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the write
recovery time is not required and the bank remains active. The figure below shows
the case 3 words of data are written. Random column access is allowed. WRITE to
TERM interval is minimum 1 CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
A0-9
Write
TERM
Yi
0
A10
BA
0
DQMB0-7
DQ
Dai0 Dai1 Dai2
MITSUBISHI
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MIT-DS-0105-2.0
28.Mar.1997
( 24 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 16Mbit memory cells. The auto-refresh is performed on
each bank alternately(ping-pong refresh). Before performing an auto-refresh, both
banks must be in the idle state. Additional commands must not be supplied to the
device before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-10
BA
Auto Refresh on Bank 0
Auto Refresh on Bank 1
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 25 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input (but asynchronous), all other inputs including CK0 are disabled and ignored, and
power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new
command can be issued after tRC, but DESEL or NOP commands must be asserted
till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-10
BA
X
0
minimum tRC
for recovery
Self Refresh Entry
Self Refresh Exit
MITSUBISHI
ELECTRIC
26
MIT-DS-0105-2.0
28.Mar.1997
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/ 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, but a command at the following cycle is ignored.
CK
(ext.CLK)
CKE
int.CLK
Power Down by CKE
CK
Standby Power Down
CKE
Command
PRE
NOP NOP NOP NOP NOP NOP NOP
Active Power Down
CKE
Command
NOP NOP NOP NOP NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
27
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the output
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7
to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQMB0-7
READ
Write
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
28
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Supply Voltage
Input Voltage
Condition
Ratings
-0.5 ~ 4.6
-0.5 ~ 4.6
Unit
V
with respect to Vss
VI
with respect to Vss
with respect to Vss
V
VO
IO
Output Voltage
Output Current
V
mA
W
-0.5 ~ 4.6
50
9
Pd
Power Dissipation
Operating Temperature
Ta=25°C
Topr
0 ~ 70
°C
Tstg
Storage Temperature
-40 ~ 100
°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Vdd
Vss
VIH
VIL
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Parameter Test Condition Limits(max.)
Unit
pF
Symbol
CI(A) Input Capacitance, address pin
CI(C) Input Capacitance, control pin
62
62
28
17
VI = Vss
f=1MHz
pF
pF
CI(K)
CI/O
Input Capacitance, CK pin
Input Capacitance, I/O pin
Vi=25mVrms
pF
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28.Mar.1997
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29
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits(max)
Test Condition
Symbol
Parameter
Unit
-10
720
1080
180
18
-12
-15
operating current, single bank
(discrete)
tRC=min.tCLK=min, BL=1, CL=3
tRC=min.tCLK=min, BL=1, CL=3
mA
mA
mA
mA
mA
mA
mA
mA
Icc1s
Icc1d
630 495
900 720
162 144
operating current, dual bank
(discrete)
Icc2h standby current, CKE=H
both banks idle, tCLK=min, CKE=H
both banks idle, tCLK=min, CKE=L
both banks active, tCLK=min, CKE=H
Icc2l
Icc3
Icc4
Icc5
Icc6
standby current, CKE=L
active standby current
burst current
18
18
360
675
585
9
315 270
585 495
540 450
tCLK=min, BL=4, CL=3, both banks active(discerte)
auto-refresh current
self-refresh current
tRC=min, tCLK=min
CKE <0.2V
9
9
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA
Low-Level Output Voltage(DC)
Parameter
Test Condition
Unit
Min. Max.
2.4
V
V
VOL(DC)
IOZOff-stareOutputCurrentQfloatingVO=0 ~ Vdd
IOL=2mA
0.4
-1010 uA
-90
Input Current
IiVIH=0~Vdd+0.3V
90uA
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-12
Symbol Parameter
-10
-15
Unit
Min. Max. Min. Max. Min. Max.
CL=1
CL=2
CL=3
ns
ns
ns
30
15
10
4
30
15
12
4
30
20
15
4
tCLK CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle time
ns
4
1
3
1
4
1
3
1
4
1
3
ns
10 ns
ns
10
10
1.5
120
30
ns
ns
ns
90
30
60 10000
100
30
70 10000
tRCD Row to Column Delay
tRAS Row Active time
80 10000 ns
tRP
Row Precharge time
30
12
20
20
30
12
24
24
40
15
30
30
15
ns
ns
ns
ns
ns
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
tPDE Power Down Exit time
tREF Refresh Interval time
10
12
65.6
65.6
65.6 ms
1.4V
Any AC timing is
CK
referenced to the input
signal crossing through
1.4V.
1.4V
Signal
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 31 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
-12
Min. Max. Min. Max. Min. Max.
Symbol Parameter
-10
-15
Unit
CL=1
CL=2
CL=3
27
9
8
27
9.5
8
30
12
9
ns
ns
ns
tAC Access time from CK
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
tOH
3
0
3
3
0
3
3
0
3
ns
ns
ns
tOLZ
tOHZ
8
8
10
Output Load
Condition
VTT=1.4V
CK
1.4V
50W
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Reference Point
1.4V
1.4V
CK
DQ
tOHZ
tAC
tOH
MITSUBISHI
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MIT-DS-0105-2.0
28.Mar.1997
( 32 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
WRITE CYCLE (single bank)
BL=4
CK
tRC
/S
tRAS
tRP
/RAS
/CAS
/WE
CKE
tRCD
DQMB
0-7
X
X
Y
X
X
A0-9
A10
BA
tWR
D
D
D
D
DQ
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
33
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/ 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BL=4
WRITE CYCLE (dual bank)
CK
tRC
/S
tRAS
tRRD
tRP
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQMB
0-7
Xb
Xb
Xa
Xa
Y
Y
A0-9
A10
BA
tWR
tWR
Db
Da
Da
Da
Da
Db
Db
Db
DQ
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 34 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
READ CYCLE (single bank)
BL=4, CL=3
CK
tRC
/S
tRAS
tRP
/RAS
/CAS
/WE
tRCD
CKE
DQMB
0-7
X
X
Y
X
X
A0-9
A10
BA
Q
Q
Q
Q
DQ
tCAC
tRAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
35
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
READ CYCLE (dual bank)
BL=4, CL=3
CK
tRC
/S
tRAS
tRP
tRRD
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQMB
0-7
Xa
Xa
Y
Xb
Xb
Y
Xa
Xa
A0-9
A10
BA
Qa Qa
tRAC
Qa
Qa
Qb Qb
Qb
Qb
DQ
tCAC
tCAC
tRAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
36
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BL=4, CL=3
WRITE to READ (single bank)
CK
/S
tRAS
/RAS
/CAS
/WE
CKE
tRCD
DQMB
0-7
X
X
Y
Y
A0-9
A10
BA
D
D
D
D
Q
Q
Q
Q
DQ
tCAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 37 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
WRITE to READ (dual bank)
BL=4, CL=3
CK
tRC
/S
tRAS
tRP
tRRD
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQMB
0-7
Xa
Xa
Y
Y
Xa
Xa
Xb
A0-9
A10
BA
Xb
tWR
Da
Qb Qb
Qb
Da
Da
Da
Qb
DQ
tCAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 38 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BL=4, CL=3
READ to WRITE (single bank)
CK
/S
tRAS
/RAS
/CAS
/WE
CKE
tRCD
for output diable
DQMB
0-7
X
X
Y
Y
A0-9
A10
BA
tWR
Q
Q
D
D
D
D
DQ
tCAC
tRAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 39 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
BL=4, CL=3
READ to WRITE (dual bank)
CK
tRC
/S
tRAS
tRRD
tRP
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
for output disable
DQMB
0-7
Xa
Xa
Y
Y
Xb
Xb
Xa
Xa
A0-9
A1
0
BA
DQ
tWR
Qa
Qa
Db
Db
Db
Db
tCAC
tRAC
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 40 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
WRITE with AUTO-PRECHARGE
BL=4
CK
tRC
/S
tWR + tRP
/RAS
/CAS
/WE
CKE
tRCD
DQMB
0-7
X
X
Y
X
X
A0-9
A10
BA
D
D
D
D
DQ
internal precharge starts
this timing depends on
BL
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 41 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
READ with AUTO-PRECHARGE
BL=4, CL=3
CK
tRC
/S
tRP
/RAS
/CAS
/WE
CKE
tRCD
DQMB
0-7
X
X
Y
X
X
A0-9
A10
BA
Q
Q
Q
Q
DQ
tCAC
tRAC
internal precharge starts @CL=3, BL=4
this timing depends on CL and BL
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 42 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
AUTO-REFRESH
CK
tRC
/S
tRP
/RAS
/CAS
/WE
CKE
DQMB
0-7
A0-9
A10
BA
DQ
if any bank is active, it must be precharged
MITSUBISHI
ELECTRIC
43
MIT-DS-0105-2.0
28.Mar.1997
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/ 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
SELF-REFRESH ENTRY
CK
/S
tRP
/RAS
/CAS
/WE
CKE
DQMB
0-7
A0-9
A10
BA
DQ
if any bank is active, it must be precharged
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 44 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
SELF-REFRESH EXIT
CK
/S
NOP or DESEL
/RAS
/CAS
/WE
CKE
tRC
DQMB
0-7
X
X
A0-9
A10
BA
DQ
internal CLK re-start
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 45 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
MODE REGISTER SET
BL=4, CL=3
CK
/S
tRSC
tRCD
tRP
/RAS
/CAS
/WE
CKE
DQMB
0-7
X
X
Y
mode
A0-9
A10
BA
Q
Q
Q
DQ
tCAC
tRAC
if any bank is active, it must be precharged
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 46 / 47 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH2S72CMD-10,-12,-15,-10B,-12B,-15B
150994944-BIT (2097152-WORD BY 72-BIT)SynchronousDRAM
OUTLINE
± 0 . 1 3 1 7 . 7 8
± 0 2 . 1 3
± 0 3 . 1 3
± 0 . 1 3 1 7 . 7 8
± 0 . 1 3 3 1 . 7 5
MITSUBISHI
ELECTRIC
MIT-DS-0105-2.0
28.Mar.1997
( 47 / 47 )
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