MH2V645CZJJ-5 [MITSUBISHI]
EDO DRAM Module, 2MX64, 50ns, CMOS, DIMM-144;
| 型号： | MH2V645CZJJ-5 |
| 厂家： | 
Mitsubishi Group |
| 描述： | EDO DRAM Module, 2MX64, 50ns, CMOS, DIMM-144 动态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
DESCRIPTION
APPLICATION
The MH2V645CZJJ is 2097152 - word by 64 - bit dynamic
RAM module. This consists of eight industry standard 2Mx8
dynamic RAMs in TSOP and one industry EEPROM in TSSOP.
The mounting of TSOP on a card edge dual in line package
provides any application where high densities and large of
quantities memory are required.
Main memory unit for computer,Microcomputer
memory,Refresh memory for CRT.
This is a socket-type memory module,suitable for easy
interchange of addition of modules.
FEATURES
RAS
CAS
Address
access
time
OE
access
time
Cycle
time
(min.ns)
Power
access access
dissipation
time
time
(typ.mW)
(max.ns)
(max.ns) (max.ns) (max.ns)
50
60
70
13
15
20
25
30
35
13
15
20
90
110
130
MH2V645CZJJ-5,5S
MH2V645CZJJ-6,6S
MH2V645CZJJ-7,7S
3480
2880
2520
single 3.3V ± 0.3V supply
Low stand-by power dissipation
14.4mW- - - - - - - - - CMOS input level
5.76mW- - - - - - - - - CMOS input level*
operating power dissipation
MH2V645CZJJ-5,5S - - - - 4200 mW(max.)
MH2V645CZJJ-6,6S - - - - 3480 mW(max.)
MH2V645CZJJ-7,7S - - - - 3040 mW(max.)
Self refresh capability*
Self refresh current - - - - 1600 uA(max.)
All input, output TTL compatible and low capacitance
2048 refresh cycle every 32.0ms(A0~A10)
Utilizes industry standard 2Mx8 RAMs in TSOP and
industry standard EEPROM in TSSOP.
Includes decoupling capacitor(0.22uFx8)
Hyper page mode , Read-modify-write,RAS-only
refresh,CAS before RAS refresh,Hidden refresh
capabilities.
Early-write mode,OE and W to control output buffer
impedance.
*:Applicable to self refresh version(MH2V645CZJJ-5S,-6S,-7S)
only
SPD Table
Byte No.
0
1
2
3
4
5
6
7
8
9
10 11 12
00 00
13 14 27 28 29
30 31
80 08 02 0B 0A 01 40 00 01
80 08 02 0B 0A 01 40 00 01
00
00
00
00
00
00
00
00
00
00
00
00
MH2V645CZJJ-5
MH2V645CZJJ-5S
MH2V645CZJJ-6
MH2V645CZJJ-6S
MH2V645CZJJ-7
MH2V645CZJJ-7S
32 0D
32 0D
12
12
14
14
14
08
08
1E
1E
28
28
32
32
04
04
04
04
04
04
32
32
3C
3C
46
00
80
80 08 02 0B 0A 01 40 00 01 3C
80 08 02 0B 0A 01 40 00 01
00 00
0F
08
00
80
3C 0F
46 14
08
80 08 02 0B 0A 01 40 00 01
00
00
08
80 08 02 0B 0A 01 40 00 01 46 14 00
80 08
14 46
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
1
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/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
PIN CONFIGURATION
Front side
Pin Name
Back side
Pin Name
Front side
Pin Name
Back side
Pin Name
PIN
Number
PIN
Number
PIN
Number
PIN
Number
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
2
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
73
75
/OE
Vss
74
RFU
Vss
3
4
76
5
6
Reserved
Reserved
Vcc
78
Reserved
Reserved
Vcc
77
7
8
79
80
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
81
82
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
83
DQ16
DQ17
DQ18
DQ19
Vss
84
DQ48
DQ49
DQ50
DQ51
Vss
DQ4
DQ5
DQ6
DQ7
Vss
DQ36
DQ37
DQ38
DQ39
Vss
86
85
88
87
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
Vcc
94
DQ52
DQ53
DQ54
DQ55
Vcc
/CAS0
/CAS1
Vcc
/CAS4
/CAS5
Vcc
96
95
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A0
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A6
A7
A2
A5
A8
NC
Vss
Vss
Vss
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ40
DQ41
DQ42
DQ43
Vcc
A9
NC
A10
NC
Vcc
Vcc
/CAS2
/CAS3
Vss
/CAS6
/CAS7
Vss
DQ12
DQ13
DQ14
DQ15
Vss
DQ44
DQ45
DQ46
DQ47
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
Reserved
Reserved
RFU
Vcc
Reserved
Reserved
FRU
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
Vcc
RFU
/WE
RFU
RFU
/RAS0
NC
RFU
SDA
SCL
RFU
Vcc
Vcc
NC,RFU,Reserved: NO CONNECTION
RFU:Reserved Future Use
MIT-DS-0034-1.0
Jan/23/1997
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ELECTRIC
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/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Block Diagram
A0~A10
/OE
/WE
/RAS0
/CAS0
/CAS4
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ0
I/O0
I/O1
I/O2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O3
D4
D0
I/O4
I/O5
I/O6
I/O7
/CAS1
/CAS5
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O0
I/O1
I/O2
I/O0
I/O1
I/O2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O3
I/O3
D1
D5
I/O4
I/O5
I/O6
I/O7
I/O4
I/O5
I/O6
I/O7
/CAS2
/CAS6
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O0
I/O1
I/O2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O0
I/O1
I/O2
I/O3
I/O3
D6
I/O4
I/O5
I/O6
I/O7
I/O4
D2
I/O5
I/O6
I/O7
/CAS3
/CAS7
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
I/O0
I/O1
I/O2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O0
I/O1
I/O2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O3
I/O3
D7
D3
I/O4
I/O4
I/O5
I/O6
I/O7
I/O5
I/O6
I/O7
SERIAL PD
Vcc
D0 to D7
D0 to D7
SDA
SCL
A0 A1 A2
Vss
C1~C8
Vss
MIT-DS-0034-1.0
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MITSUBISHI
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/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
FUNCTION
The MH2V645CZJJ provide, in addition to normal
read, write, and read-modify-write operations,
a number of other functions, e.g., Hyper page mode,
/RAS-only refresh, and delayed-write. The input
conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Input/Output
Column
Input Output
address address
Operation
Refresh
Remark
Hyper
page mode
identical
Row
/RAS
/CAS
/W
/OE
Read
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
DNC
ACT
NAC
ACT
ACT
ACT
DNC
NAC
NAC
DNC
NAC
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
DNC
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
YES
YES
YES
YES
YES
YES
YES
NO
Write (Early write)
Write (Delayed write)
Read-modify-write
/RAS-only refresh
Hidden refresh
/CAS before /RAS refresh ACT
Standby
Self refresh
NAC
ACT
YES
*
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
*MH2V645CZJJ-5S,-6S,-7S only
MIT-DS-0034-1.0
Jan/23/1997
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ELECTRIC
( 4 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Vcc Supply voltage
Conditions
Ratings
-0.5~4.6
-0.5~4.6
Unit
V
V
VI
Input voltage
With respect to Vss
VO
IO
Pd
Topr
Tstg
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature (SOJ)
-0.5~4.6
50
V
mA
W
°C
°C
Ta=25°C
8
0~ 70
-40~ 100
(Ta=0~ 70°C, unless otherwise noted) (Note 1)
RECOMMENDED OPERATING CONDITIONS
Limits
Unit
Symbol
Parameter
Min
3.0
0
2.0
**-0.3
Nom
3.3
0
Max
3.6
Vcc
Vss
VIH
VIL
V
V
V
V
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
0
Vcc+0.3
0.8
Note 1 : All voltage values are with respect to Vss
** : VIL(Min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
ELECTRICAL CHARACTERISTICS
Limits
Min Typ
Symbol
Parameter
Test conditions
IOH=-2.0mA
IOL=2.0mA
Q floating 0V£VOUT£3.6V
0V£VIN£3.6V, Other input pins=0V -80
/RAS, /CAS cycling
tRC=tWC=min.
Unit
Max
Vcc
0.4
10
80
1160
960
840
16
4
1160
960
840
1120
920
720
VOH
VOL
IOZ
I I
High-level output voltage
Low-level output voltage
Off-state output current
Input current
2.4
0
-10
V
V
uA
uA
-5,-5S
-6,-6S
-7,-7S
Average supply
mA
ICC1 (AV)
ICC2
current
(Note 3,4,5)
from Vcc operating
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS³ Vcc -0.2, output open
/RAS cycling, /CAS= VIH
tRC=min.
Supply current from Vcc , stand-by
mA
mA
-5,-5S
-6,-6S
Average supply
current
ICC3 (AV)
(Note 3,5)
from Vcc refreshing
-7,-7S output open
Average supply current
from Vcc
Hyper-Page-Mode (Note 3,4,5)
-5,-5S
-6,-6S
/RAS=VIL,/CAS cycling
tPC=min.
-7,-7S output open
mA
ICC4(AV)
Average supply current
-5,-5S
1160
960
840
/CAS before /RAS refresh cycling
tRC=min.
output open
from Vcc
-6,-6S
(Note 3,5)
-7,-7S
mA
uA
ICC6(AV)
ICC9(AV)*
/CAS before /RAS refresh
mode
Average supply current
/RAS=/CAS£0.2V
output open
1600
from Vcc Self-Refresh mode
(Note 6)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VOH
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
CAPACITANCE
Limits
Typ Max
Symbol
Parameter
Unit
Test conditions
Min
CI (A)
CI
Input capacitance, address inputs
Input capacitance, clock inputs except CAS
VI=Vss
f=1MHZ
Vi=25mVrms
55
65
25
25
pF
pF
pF
pF
C(CAS) Input capacitance, CAS
C(DQ) Input/Output capacitance,DATA
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
( 5 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
SWITCHING CHARACTERISTICS
-5,-5S
-6,-6S
-7,-7S
Symbol
Parameter
Unit
Min Max Min Max Min Max
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
Access time from /CAS
Access time from /RAS
Column address access time
Access time from /CAS precharge
Access time from /OE
Output hold time /CAS high
Output hold time /RAS high
13
50
25
30
13
tCAC
tRAC
tAA
15
60
30
35
15
20
70
35
40
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
tDOH
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
5
5
5
5
5
5
5
5
5
Output low impedance time from /CAS low
Output disable time after /OE high
Output disable time after /WE high
13
13
13
13
15
15
15
15
20
20
20
20
(Note 12,13)
(Note 12,13)
Output disable time after /CAS high
Output disable time after /RAS high
Output hold time from /CAS low
5
5
5
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 32 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 100pF. The reference levels for measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD³ tRCD(max), tASC³ tASC(max) and tCP³ tCP(max).
9: Assumes that tRCD£tRCD(max) and tRAD£tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD³ tRAD(max) and tASC£tASC(max).
11: Assumes that tCP£tCP(max) and tASC³ tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state
(IOUT£ | ±10uA|) and is not reference to VOH(min) or VOL(max).
13: Output is disable after both /RAS and /CAS go to high
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits
-6,-6S
-5,-5S
-7,-7S
Symbol
Parameter
Unit
Min Max Min Max Min Max
tREF
tRP
Refresh cycle time
/RAS high pulse width
32
32
32
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
18
5
0
8
13
0
0
8
8
0
0
13
13
13
1
40
20
5
50
20
5
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low (Note17)
Row address setup time before /RAS low
Column address setup time before /CAS low (Note18)
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
(Note16)
32
38
42
0
0
10
15
0
13
15
0
25
10
30
13
35
13
0
0
10
10
0
10
10
0
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
0
0
15
15
15
1
20
20
20
1
50
50
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD³ tRAD(max) and tASC£tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD³ tRCD(max) and tASC³ tASC(max), access time is controlled exclusively by
tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
6
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/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Read and Refresh Cycles
Limits
Symbol
Parameter
-5,-5S
-6,-6S
-7,-7S
Unit
Min Max Min Max Min Max
tRC
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
Column address to /CAS hold time
90
50
8
40
13
0
0
0
25
13
13
13
110
60
10
48
15
0
0
0
30
18
15
15
130
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
tCAL
10000
10000
10000
10000
10000 13 10000
55
20
0
0
0
35
23
20
20
(Note 22)
(Note 22)
tORH
tOCH
/RAS hold time after /OE low
/CAS hold time after /OE low
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits
-6,-6S
Min Max Min Max Min Max
90 110 130
50 10000 60 10000 70 10000
Symbol
Parameter
-5,-5S
-7,-7S
Unit
tWC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
/RAS low pulse width
/CAS low pulse width
8
40
13
0
10000 10 10000
10000
13
55
20
0
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after W low
Write pulse width
48
15
0
(Note 24)
8
8
8
8
10
10
10
10
0
13
13
13
13
0
tDS
tDH
Data setup time before /CAS low or W low
Data hold time after /CAS low or W low
0
8
10
13
Read-Write and Read-Modify-Write Cycles
Limits
-5,-5S
-6,-6S
-7,-7S
Unit
Symbol
Parameter
Min Max Min Max
Min Max
161
(Note21)
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
Read write/read modify write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
Delay time, /RAS low to /W low
Delay time, address to /W low
/OE hold time after /W low
109
133
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75 10000 89 10000 107 10000
38
70
38
0
44
82
44
0
10000
10000
57 10000
99
57
0
(Note24)
(Note24)
(Note24)
28
65
40
13
32
77
47
15
42
92
57
20
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS³ tWCS(min) the cycle is an early write cycle
and the DQ pins will remain high impedance throughout the entire cycle. If tCWD³ tCWD(min), tRWD³ tRWD (min), tAWD³ tAWD(min)
and tCPWD³ tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the
data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE
goes back to VIH) is indeterminate.
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
7
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /WE) (Note 25)
Limits
Symbol
Parameter
-5,-5S
-6,-6S
-7,-7S
Unit
Min Max Min Max Min Max
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
(Note26)
tHPC
tHPRWC
tRAS
20
57
65
8
28
43
7
25
66
77
10
33
50
7
30
79
92
13
38
60
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100000
100000
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
Hold time to maintain the data Hi-Z until /CAS access
/OE Pulse Width (Hi-Z control)
/W Pulse Width (Hi-Z control)
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS prechargeto /OE high after read
(Note27)
(Note28)
100000
tCP
13
16
16
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
(Note24)
7
7
7
7
7
7
28
40
43
13
25
28
32
47
50
15
30
33
42
57
60
20
35
38
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
29: tHPC(min) is specified in the case of read-only and early write only in Hyper Page Mode.
27: tRAS(min) is specified as two cycles of CAS input are performed.
28: tCP(max) is specified as a reference point only.
/CAS before /RAS Refresh Cycle (Note 29)
Limits
-7,-7S
Symbol
Parameter
-5,-5S
-6,-6S
Unit
Min Max Min Max Min Max
tCSR
tCHR
tCAS
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
/CAS low pulse width
Read setup time before /RAS low
Read hold time after /RAS low
5
10
17
5
5
10
17
5
5
15
22
5
ns
ns
ns
ns
ns
10
10
15
Note 29: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS
refresh mode.
Hidden Refresh Cycle (note 31)
Limits
Symbol
Parameter
-5,-5S
-6,-6S
-7,-7S
Unit
Min
Max Min
Max Min Max
ns
ns
tRSR
tRHR
Read set up time before /RAS low
Read hold time after /RAS low
5
10
5
10
5
15
Note 31: Read, early write, delayed write, read write or read-modify-write cycle is applicable to hidden refresh cycle. In all cases tRSR and
tRHR should be satisfied.
MIT-DS-0034-1.0
Jan/23/1997
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ELECTRIC
8
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Self Refresh Cycle* (notes 32)
Limits
Symbol
tRASS
Parameter
-5S
Max
-6S
Max
-7S
Unit
Min
100
90
Min
100
110
Min
100
130
Max
CBR Self Refresh RAS low pulse width
CBR Self Refresh RAS high precharge time
CBR Self Refresh RAS hold time
Read setup time before RAS low
us
ns
ns
ns
ns
tRPS
tCHS
tRSR
tRHR
- 50
5
- 50
5
- 50
5
10
10
15
Read hold time after RAS low
Note 32:
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of distributed refresh
The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh ,
on the condition of tNS£32 ms and tSN £ 32 ms.
tSN
tNS
DISTRIBUTED REFRESH
< 2K / 32 ms >
(2) In case of burst refresh
The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh ,
on the condition of tNS + tSN £ 32 ms.
tSN
tNS
BURST REFRESH
< 2K / 32ms >
BURST REFRESH
< 2K / 32 ms >
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
9
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Timing Diagrams (Note 30)
Read Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH
VIL
/CAS
tRAL
tCAL
tRAD
tASR
tASR
tRAH
tASC
tCAH
VIH
VIL
ROW
ADDRESS
A0~A10
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCH
tRCS
VIH
VIL
/W
tCDD
tDZC
tRDD
tREZ
VIH
VIL
DQ
(INPUTS)
Hi-Z
tWEZ
tOFF
tOHC
tCAC
tAA
tCLZ
tOHR
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
DATA VALID
Hi-Z
tRAC
tDZO
tOEA
tOEZ
tODD
tOCH
VIH
VIL
/OE
tORH
Indicates the don't care input.
VIH(min)£VIN£VIH(max) or VIL(min)£VIN£VIL(max)
Note 30
Indicates the invalid output.
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Jan/23/1997
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Early Write Cycle
tWC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tCRP
tASR
tRCD
tRSH
tCAS
VIH
/CAS
VIL
tASR
tRAH
tCAH
tASC
VIH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
A0~A10
VIL
tWCS
tWCH
VIH
/W
VIL
tDH
tDS
VIH
DQ
DATA VALID
(INPUTS)
VIL
VOH
DQ
(OUTPUTS)
VOL
Hi-Z
VIH
/OE
VIL
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
( 11 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Delayed Write Cycle
tWC
tRP
tRAS
VIH
/RAS
VIL
tCRP
tCSH
tCRP
tASR
tRSH
tCAS
tRCD
VIH
/CAS
VIL
tRAH
tCAH
tASC
tASR
VIH
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
A0~A10
VIL
tCWL
tRWL
tWP
tRCS
VIH
/W
VIL
tWCH
tDZC
tDS
tDH
VIH
DQ
(INPUTS)
VIL
DATA
VALID
Hi-Z
tCLZ
VOH
DQ
(OUTPUTS)
VOL
Hi-Z
Hi-Z
tOEH
tOEZ
tODD
tDZO
VIH
/OE
VIL
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12
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tRSH
tCAS
tCRP
VIH
/CAS
VIL
tRAD
tASR
tRAH
tCAH
tASR
tASC
VIH
VIL
COLUMN
ADDRESS
tAWD
ROW
ADDRESS
ROW
ADDRESS
A0~A10
tCWL
tRWL
tWP
tCWD
tRWD
tRCS
VIH
VIL
/W
tDH
tDS
tDZC
VIH
VIL
DQ
(INPUTS)
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID
Hi-Z
Hi-Z
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
VIL
/OE
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13
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tCAS
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tCAL
COLUMN-1
tRCS
tRRH
tCAL
tCAL
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tDOH
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
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14
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS
tRP
VIH
/RAS
VIL
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCRP
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tCAL
tCAH
tCAL
tCAH
tASC
tASC
tASR
tRAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
COLUMN-1
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
VIH
VIL
tDS
tDH
tDS
tDH
tDS
tDH
VIH
VIL
DATA
VALID-2
DATA
VALID-3
DATA
VALID-1
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIL
VIH
/OE
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15
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRWL
tCRP
tCRP
tASR
tHPRWC
tCAS
tRCD
tCAS
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCWL
tCAH
tASC
tCAH
tASC
tASR
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
tAWD
tCWD
tAWD
tCWD
tCWL
tWP
tRCS
tRCS
tWP
VIH
VIL
tRWD
tCPWD
tDZC
tDH
tDZC
tDH
tDS
tDS
VIH
VIL
DATA
VALID-1
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
tCAC
Hi-Z
tCAC
tAA
tAA
tCLZ
tRAC
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DQ
(OUTPUTS)
Hi-Z
Hi-Z
Hi-Z
tCPA
tDZO
tODD
tODD
tOEH
tDZO tOEA
tOEZ
tOEZ
tOEA
VIH
VIL
/OE
MIT-DS-0034-1.0
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MITSUBISHI
ELECTRIC
16
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRP
tRAS
tRWL
VIH
/RAS
VIL
tCRP
tCSH
tRCD
tHPC
tCAS
tHPRWC
tCAS
tCRP
tASR
tCAS
tCP
tCP
VIH
VIL
tCWL
/CAS
A0~A10
/W
tRAD
tRAH
tASR
tASC
tCAH
tASC tCAH
COLUMN-3
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-1
tRCS
tCPWD
tAWD
tCWD
tWCH
tCAL
tWCS
tCAL
tWP
VIH
VIL
tDH
tDZ
C
tDZC
tDH
tDS
tDS
VIH
VIL
DQ
(INPUTS)
DATA
VALID-2
DATA
VALID-3
tCAC
tAA
tAA
tCAC
tWEZ
tCLZ
tCLZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-3
DATA
VALID-1
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOEA
tOEH
tDZO
tOEZ
tOEZ
VIL
VIH
tOCH
/OE
tODD
tODD
MIT-DS-0034-1.0
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MITSUBISHI
ELECTRIC
17
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH
/RAS
VIL
tHPC
VIH
VIL
/CAS
A0~A10
/W
tCP
tASC
tCAS
tCAH
tCAS
tCAH
tASC
tASC
tCAH
VIH
VIL
COLUMN-1
tCAL
COLUMN-2
COLUMN-3
tRCH
tCAL
tWCH
tWCS
tDS
VIH
VIL
tHCWD
tHAWD
tDH
tDZC
tHPWD
VIH
VIL
DATA
VALID-2
DQ
(INPUTS)
Hi-Z
Hi-Z
tCAC
tAA
tCAC
tAA
tCPA
tWEZ
tCPA
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-3
DQ
(OUTPUTS)
Hi-Z
tHCOD
tHAOD
tHPOD
tOEA
tDZC
tOEZ
tODD
VIL
VIH
/OE
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
18
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tASR
tCAS
tCRP
tRCD
tCP
tCP
VIH
VIL
/CAS
A0~A10
/W
tRAD
tRAH
tCPRH
tCAH
tASR
tASC
tCAH
tASC
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRAL
tRRH
tRCS
tRCH
VIH
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tREZ
tOHR
tOFF
tOHC
tCLZ
tDOH
tCLZ
VOH
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-1
DQ
(OUTPUTS)
DATA
VALID-3
Hi-Z
Hi-Z
tRAC
tDZO
tCPA
tCPA
tOEZ
tOEA
tCHOL
tOCH
tOEA
tOEZ
tOEZ
VIL
VIH
/OE
tODD
tOEPE
tOEPE
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
19
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS
tRP
VIH
VIL
/RAS
tCSH
tRSH
tCAS
tHPC
tCAS
tCRP
tASR
tCAS
tRCD
tCP
tCP
tCRP
VIH
VIL
/CAS
A0~A10
/W
tCPRH
tCAH
tRAD
tRAH
tASR
tASC
tASC
tCAH
tCAH
tASC
VIH
VIL
ROW
ADDRESS
ROW
ADDRESS
COLUMN-2
COLUMN-3
tRAL
COLUMN-1
tRRH
tRCS
tRCH
tRCH
tRCS
VIH
VIL
tDZC
tWPE
tRDD
tCDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tCAC
tAA
tCAC
tAA
tCAC
tAA
tCLZ
tREZ
tOHR
tOFF
tOHC
tDOH
tCLZ
tWEZ
VOH
VOL
DQ
(OUTPUTS)
DATA
VALID-2
DATA
VALID-1
DATA
VALID-3
Hi-Z
tCPA
Hi-Z
tRAC
tDZO
tCPA
tOEA
tOCH
tOEZ
VIL
VIH
/OE
tODD
MIT-DS-0034-1.0
Jan/23/1997
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ELECTRIC
20
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MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tRPC
tCRP
tCRP
VIH
/CAS
VIL
tASR
tRAH
tASR
VIH
ROW
ROW
A0~A10
ADDRESS
ADDRESS
VIL
VIH
VIL
/W
VIH
VIL
DQ
(INPUTS)
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
VIH
VIL
/OE
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
( 21 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
*
/CAS before /RAS Refresh Cycle, Extended Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH
VIL
/RAS
tCRP
tCSR
tRPC
tCHR
tRPC tCSR
tCHR
tRPC
VIH
VIL
/CAS
A0~A10
/W
tCPN
tASR
VIH
VIL
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCH
tRCS
VIH
VIL
VIH
VIL
DQ
(INPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
tOEZ
VIH
VIL
/OE
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
22
(
/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
/RAS
tCRP
tRCD
tRSH
tCHR
VIH
VIL
/CAS
A0~A10
/W
tRAD
tASR
tRAH tASC
tCAH
tASR
VIH
VIL
COLUMN
ROW
ADDRESS
ROW
ADDRESS
ADDRESS
tRCS
tDZC
tRRH
tRAL
tRCH
VIH
VIL
tCDD
tRDD
VIH
VIL
DQ
(INPUTS)
Hi-Z
tREZ
tCAC
tAA
tOHR
tOFF
tOHC
tCLZ
VOH
VOL
DQ
(OUTPUTS)
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tORH
VIH
VIL
/OE
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
23
(
/ 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
Self Refresh Cycle
tRASS
tRP
tRPS
VIH
VIL
/RAS
/CAS
tRPC
tRPC
tCRP
tASR
tCSR
tCHS
VIH
VIL
tCPN
VIH
VIL
ROW
ADDRESS
A0~A10
tRRH
tRCH
tRCS
VIH
VIL
/W
tRDD
tCDD
Hi-Z
DQ
(INPUTS)
VIH
VIL
tREZ
tOHR
tOFF
tOHC
Hi-Z
VOH
VOL
DQ
(OUTPUTS)
tOEZ
tODD
VIH
VIL
/OE
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
( 24 / 25 )
MITSUBISHI LSIs
Preliminary
Preliminary
Some of contents are subject
to change without notice.
MH2V645CZJJ-5,-6,-7,-5S,-6S,-7S
HYPER PAGE MODE 134217728-BIT (2097152-WORD BY 64-BIT)DYNAMIC RAM
4.00
3.20
25.4
20.00
6.00
4.00
MIT-DS-0034-1.0
Jan/23/1997
MITSUBISHI
ELECTRIC
25
(
/ 25 )
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