MH32S64PFJ-6L [MITSUBISHI]
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM; 2147483648位（ 33554432 - WORD 64位） SynchronousDRAM
| 型号： | MH32S64PFJ-6L |
| 厂家： | 
Mitsubishi Group |
| 描述： | 2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM |
| 文件： | 总55页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
Utilizes industry standard 16M x 16 Synchronous
DRAMs TSOP and industry standard EEPROM in
TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
The MH32S64PFJ is 33554432 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
Fully synchronous operation referenced to clock rising
edge
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
FEATURES
CLK Access Time
Frequency
(Component SDRAM)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
5.4ns(CL=3)
6.0ns(CL=2)
-6,-6L
-7,-7L
133MHz
100MHz
8192 refresh cycle /64ms
LVTTL Interface
PC133/100 Compliant
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
143
144
MITSUBISHI
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26.Apr.2001
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
PIN CONFIGURATION
Front side
Pin Name
Back side
Pin Name
Front side
Pin Name
Back side
Pin Name
PIN
Number
PIN
Number
PIN
Number
PIN
Number
2
Vss
1
Vss
73
75
74
76
CLK1
Vss
Reserved
Vss
Reserved
3
5
DQ0
DQ1
DQ2
4
6
DQ32
DQ33
DQ34
Reserved
77
78
Reserved
Reserved
79
80
7
9
8
DQ3
10
DQ35
81
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
82
Vcc
83
11
13
Vcc
12
14
Vcc
84
DQ48
DQ49
DQ50
DQ51
DQ4
DQ36
85
86
15
17
DQ5
DQ6
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DQ37
DQ38
87
88
89
90
91
19
21
23
DQ7
Vss
DQ39
Vss
92
Vss
93
DQ20
DQ21
DQ22
DQ23
Vcc
94
DQ52
DQ53
DQMB4
DQMB0
95
96
DQMB5
Vcc
DQ54
DQ55
Vcc
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DQMB1
Vcc
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A0
101
103
105
107
109
111
113
115
117
119
121
123
A3
A1
A6
A4
A7
A2
A8
A5
BA0
Vss
Vss
Vss
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
A9
DQ40
DQ41
DQ42
DQ43
Vcc
BA1
A10
A11
Vcc
Vcc
DQMB2
DQMB3
Vss
DQMB6
DQMB7
Vss
DQ12
DQ13
DQ14
DQ44
DQ45
DQ46
DQ24
DQ25
DQ56
DQ57
DQ58
DQ59
Vcc
DQ15
Vss
125
127
129
131
133
DQ26
DQ27
Vcc
DQ47
Vss
Reserved
Reserved
CLK0
Reserved
Reserved
DQ28
DQ29
DQ60
DQ61
DQ62
DQ63
Vss
CKE0
Vcc
Vcc
/RAS
/WE
/S0
135
137
139
141
143
DQ30
DQ31
Vss
/CAS
CKE1
A12
SDA
Vcc
SCL
/S1
Vcc
A13
NC = No Connection
MITSUBISHI
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MIT-DS-0337-0.2
26.Apr.2001
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
/S1
DQMB4
DQML
DQML
DQML
DQML
DQMB0
DQ0
/CS
/CS
/CS
/CS
I/O 0
I/O 0
I/O 0
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 1
I/O 1
I/O 1
D0
D4
D2
D6
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 6
I/O 7
I/O 7
DQMB1
DQMU
DQMU
DQMU
DQMU
DQMB5
I/O 8
I/O 8
I/O 8
I/O 8
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 9
I/O 9
I/O 9
I/O 9
DQ9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB6
DQMB2
DQML
DQML
DQML
DQML
/CS
/CS
/CS
/CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 1
I/O 1
I/O 1
D1
D5
D3
D7
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DQMB3
DQMU
DQMU
DQMU
DQMU
DQMB7
I/O 8
I/O 8
I/O 8
I/O 8
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 9
I/O 9
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
10W
CLK0
CLK1
CKE0
CKE1
/RAS
/CAS
/WE
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
SERIAL PD
A0 A2
SCL
SDA
A1
BA0,BA1,A<12:0>
Vcc
D0 - D7
D0 - D7
Vss
D0 - D7
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
3
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
SPD enrty data
128
SPD DATA(hex)
Byte
0
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
80
08
04
0D
09
02
40
00
256 Bytes
SDRAM
A0-A12
A0-A8
1
2
3
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
4
2BANK
x64
5
6
... Data Width continuation
7
0
8
Voltage interface standard of this assembly
LVTTL
7.5ns
01
75
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-6
-7
9
10ns
5.4ns
6ns
A0
54
60
-6
-7
10
SDRAM Access from Clock
tAC for CL=3
Non-PARITY
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
11
12
13
14
15
00
82
10
00
01
self refresh(7.8125uS)
x16
SDRAM width,Primary DRAM
Error Checking SDRAM data width
N/A
Minimum Clock Delay,Back to Back Random Column Addresses
1
1/2/4/8/Full page
Burst Lengths Supported
16
17
18
19
8F
04
4bank
# Banks on Each SDRAM device
CAS# Latency
06
2/3
CS# Latency
Write Latency
0
01
01
00
0E
20
21
22
0
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Module Attributes
SDRAM Device Attributes:General
-6
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
10ns
10ns
6ns
A0
A0
60
-7
-6
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
24
-7
6ns
60
00
SDRAM Cycle time(3rd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
Precharge to Active Minimum
25
26
27
N/A
N/A
00
14
0F
20ns
15ns
-6
-7
28
29
Row Active to Row Active Min.
RAS to CAS Delay Min
20ns
20ns
14
14
2D
32
-6
-7
45ns
50ns
30
Active to Precharge Min
MITSUBISHI
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MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
4
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
128MByte
1.5ns
20
15
31
32
Density of each bank on module
-6
Command and Address signal input setup time
-7
-6
2ns
0.8ns
1ns
20
08
10
33
Command and Address signal input hold time
-7
-6
1.5ns
2ns
15
34
35
Data signal input setup time
Data signal input hold time
-7
-6
20
08
10
0.8ns
1ns
-7
Superset Information (may be used in future)
SPD Revision
36-61
62
option
00
12
rev 1.2B
63
Checksum for bytes 0-62
Check sum for -6
Check sum for -7
BA
21
Manufactures Jedec ID code per JEP-108E
Manufacturing location
64-71
72
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
1CFFFFFFFFFFFFFF
01
02
03
Germany
04
4D48333253363450464A2D36202020202020
73-90
Manufactures Part Number
MH32S64PFJ-6
MH32S64PFJ-6L
MH32S64PFJ-7
MH32S64PFJ-7L
4D48333253363450464A2D364C2020202020
4D48333253363450464A2D37202020202020
4D48333253363450464A2D374C2020202020
PCB revision
year/week code
serial number
option
Revision Code
rrrr
yyww
91-92
93-94
95-98
99-125
126
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
ssssssss
00
Intetl specification frequency
100MHz
64
127
Intel specification CAS# Latency support
Unused storage locations
-6,-7
CL=2/3,AP,CK0,1
open
CF
00
128+
The -6, -7 indicate also -6L, -7L.
MITSUBISHI
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MIT-DS-0337-0.2
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CLK0, CLK1
Input
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE0
CKE1
Chip Select: When /S is high,any command means
No Operation.
Input
Input
/S0, /S1
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-12 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-12.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
A0-12
Input
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
BA0,1
Input
Data In and Data out are referenced to the rising edge
of CLK
Input/Output
DQ0-63
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss
Input
Power Supply Power Supply for the memory mounted module.
Input
Serial clock for serial PD
Serial data for serial PD
SCL
SDA
Output
MITSUBISHI
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MIT-DS-0337-0.2
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( 6 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH32S64PFJ provides basic functions,bank(row)activate,burst read / write,
bank(row) precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CLK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
Chip Select : L=select, H=deselect
/S
Command
/RAS
Command
Command
define basic commands
/CAS
/WE
CKE
A10
Ref resh Option @ref resh
command
Precharge Option @precharge or read/write
command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MITSUBISHI
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MIT-DS-0337-0.2
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
A0-9,
11-12
CKE CKE
/CAS
A10
/WE BA0,1
note
COMMAND
MNEMONIC
/RAS
/S
n-1
n
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
WRITEA
READ
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
L
V
V
V
V
L
V
V
V
V
Column Address Entry
& Write with Auto-
Precharge
L
H
L
Column Address Entry
& Read
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
L
L
REFSX
H
H
X
X
X
H
H
L
X
H
H
L
L
Burst Terminate
TERM
MRS
H
H
1
Mode Register Set
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number
NOTE:
1.A7-8,11-12 = L, A0-6,A9 = Mode Address
MITSUBISHI
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MIT-DS-0337-0.2
26.Apr.2001
( 8 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE
Command
DESEL
NOP
Current State
IDLE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
L
X
TBST
ILLEGAL*2
L
X
H
L
BA,CA,A10
BA,RA
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
PRE/PREA NOP*4
L
H
H
L
L
L
BA,A10
X
L
L
H
REFA
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP
NOP
TBST
NOP
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
BA,A10
PRE/PREA Precharge/Precharge All
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
TBST
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MITSUBISHI
ELECTRIC
( 9 / 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
X
H
H
X
H
L
X
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
READ/READA
L
L
H
H
L
L
H
L
BA,CA,A10
BA,CA,A10
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
WRITE/
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
PRECHARGE
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
Bank Active/ILLEGAL*2
BA,A10
PRE/PREA ILLEGAL*2
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
WRITE with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
PRECHARGE
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
BA,RA
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2
BA,A10
X
PRE/PREA ILLEGAL*2
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
MITSUBISHI
ELECTRIC
( 10 / 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
CHARGING
L
TBST
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
L
H
H
L
BA,RA
ACT
ILLEGAL*2
L
L
BA,A10
PRE/PREA NOP*4(Idle after tRP)
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
DESEL
NOP
NOP
NOP
TBST
ILLEGAL*2
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MITSUBISHI
ELECTRIC
( 11/ 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
L
H
H
L
BA,RA
ACT
ILLEGAL
L
L
BA,A10
PRE/PREA ILLEGAL
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL
L
PRE/PREA ILLEGAL
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 12/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CK
n-1
CK
n
Action
Current State
/RAS /CAS /WE Add
/S
INVALID
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
REFRESH*1
L
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
Enter Power Down
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
ILLEGAL
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
13
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
REFA
CKEL
CKEH
ACT
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
WRITE
READ
READA
READ
WRITEA
WRITE
CKEL
CKEL
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
CKEH
CKEH
WRITEA
READA
WRITEA
READA
CKEL
CKEH
CKEL
CKEH
PRE
READA
PRE
PRE
POWER
APPLIED
POWER
ON
PRE
CHARGE
PRE
Automatic Sequence
Command Sequence
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 14/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
/CAS
A12 BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
WM
0
0
0
0
0
0
0
LTMODE
BT
BL
/WE
BA0,1 A12-0
V
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
LENGTH
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
8
8
R
R
R
FP
R
R
R
R
LATENCY
MODE
3
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
BURST
SINGLE BIT
0
1
WRITE
MODE
MITSUBISHI
ELECTRIC
( 15/ 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK
frequency,i.e.,the speed of CLK determines which CL should be used.First output data is
available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CK
ACT
X
READ
Y
Command
Address
tRCD
CL=2
CL=2
CL=3
Q0
Q1
Q0
Q2
Q1
Q3
Q2
DQ
DQ
CL=3
Q3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page
the output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
READ
ACT
X
Command
Y
Address
Q0
DQ
DQ
BL=1
BL=2
BL=4
BL=8
BL=FP
Q0 Q1
DQ
DQ
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q8
Qm Q0 Q1
Full Page counter rolls over
and continues to count.
m=511
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 16/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CK
Read
Write
Y
Command
Y
Address
Q0
Q1
Q2
Q3
D0
D1
D3
D2
DQ
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 17/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
OPERATION DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open
banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command ACT
ACT
Xb
READ
Yb
0
PRE
ACT
Xa
tRCD
tRRD
tRP
A0-9,11-12
A10
Xa
Xa
Xb
1
Xa
BA0,1 00
DQ
01
01
00
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
defined by the Burst Type. Minimum delay time of a READ command after an ACT command
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 18/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command
ACT
READ
ACT
READ PRE
Yb
ACT
tRCD
tRCD
tRCD
Xa
Xa
Ya
0
Xb
Xb
Xa
Xa
A0-9, 11-12
A10
0
0
BA0,1
DQ
00
01
00
00
00
01
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
READ with Auto-Precharge (BL=4, CL=2)
CK
Command ACT
READ
ACT
tRCD
tRP
BL
Xa
Xa
Xa
Ya
1
A0-9, 11-12
A10
Xa
00
BA0,1
DQ
00
00
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
READ Auto-Precharge Timing (BL=4)
CK
Command
ACT
READ
ACT
tRCD
BL
CL=3 DQ
CL=2 DQ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
19
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRCD
BL
tRP
Ya
0
Xa
Xa
Xa
Xa
A0-9, 11-12
A10
0
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRP
tRCD
Xa
Xa
Xa
Xa
Ya
1
A0-9, 11-12
A10
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
Internal precharge begins
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 20 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read option can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
A0-9,11-12
A10
READ
Ya
0
READ READ
Yb
0
Yc
0
BA0,1
00
00
10
DQ
Qa0 Qa1 Qa2 Qb0 Qc0 Qc1
Qc2 Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of the same or the other bank. Random
column access is allowed. In this case, the DQ should be controlled adequately by using the
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after
WRITE assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command ACT
READ
Ya
0
Write
Ya
0
Xa
A0-9,11-12
A10
Xa
00
00
00
BA0,1
DQMB0-7
DQ
Qa0
Da0 Da1 Da2 Da3
Output disableby DQM by WRITE
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 21/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same or the other bank.
Read to PRE interval is minimum 1 CK. A PRE command output disable latency is
equivalent to the /CAS Latency.As a result, READ to PRE interval determines valid data
length to be output.The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
READ
PRE
Q0
DQ
Q1
Q1
Q2
CL=3
Command
PRE
DQ
Q0
Q0
Command
READ PRE
DQ
Command
DQ
PRE
Q1
READ
Q0
Q2
CL=2
Command
READ
PRE
Q0
DQ
Q1
Command
READ PRE
DQ
Q0
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 22 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST
is mainly used to interrupt FP bursts.The figure below show examples, of how the output
data is terminated with TBST.
Read Interrupted by Terminate (BL=4)
CK
Command
DQ
READ
TBST
Q0
Q1
Q1
Q2
Command
DQ
READ
TBST
CL=3
Q0
Q0
Command
DQ
READ TBST
Command
DQ
TBST
Q1
READ
READ
Q0
Q2
Command
DQ
TBST
Q0
CL=2
Q1
Command
DQ
TBST
READ
Q0
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
23
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of the same or the other bank.
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11-12
A10
Write
Ya
Write Write
Yb
0
Yc
0
0
BA0,1
00
00
10
DQ
Da0 Da1 Da2 Db0 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank.
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The
input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command
ACT
Write
READ
A0-9,11-12
A10
Xa
Xa
Ya
0
Yb
0
00
BA0,1
DQ
00
00
Da0 Da1
Qb0 Qb1
Qb2 Qb3
don't care
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
(24 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random
column access is allowed. Because the write recovery time(tWR) is required from
the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRP
Xa
0
Ya
0
Xa
0
A0-9,11-12
A10
0
00
00
00
00
BA0,1
DQMB0-7
DQ
tWR
Da0 Da1
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can terminate burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the
waveforms below).The WRITE to TBST minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
ACT
Xa
0
Write
Ya
0
TBST
Write
Yb
0
A0-9,11-12
A10
BA0,1
DQ
00
00
00
Da0 Da1
Db0 Db1 Db2 Db3
MITSUBISHI
ELECTRIC
( 25 / 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on
4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks
must be in the idle state. Additional commands must not be supplied to the device
before tRC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRC
A0-12
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 26 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle
state and a new command can be issued after tRC, but DESEL or NOP commands
must be asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
BA0,1
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
MITSUBISHI
ELECTRIC
27
MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle, but a command at the following cycle is ignored.
CK
(ext.CLK)
tIH tIS
tIH tIS
CKE
int.CLK
Power Down by CKE
CK
CKE
Standby Power Down
Activ e Power Down
Command
PRE NOP NOP NOP
CKE
Command
NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
28
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to write mask latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQMB0-7
READ
Write
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
29
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Condition
Ratings
Unit
V
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
VI
VO
IO
Input Voltage
Output Voltage
with respect to Vss -0.5 ~ Vdd+0.5
with respect to Vss -0.5 ~ VddQ+0.5
50
V
V
Output Current
mA
W
Ta=25°C
Pd
Power Dissipation
Operating Temperature
8
Topr
0 ~ 70
°C
°C
Storage Temperature
Tstg
-40 ~ 100
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Typ.
3.3
0
Min.
3.0
0
Max.
3.6
Vdd
Vss
VIH
VIL
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
Note:* VIH (max) = 5.5V for pulse width less than 10ns.
VIL (min) = -1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition Limits(max.) Unit
pF
pF
pF
pF
CI(A) Input Capacitance, address pin
CI(C) Input Capacitance, control pin
58
50
40
22
VI = Vss
f=1MHz
CI(K)
CI/O
Input Capacitance, CK pin
Input Capacitance, I/O pin
Vi=25mVrms
MITSUBISHI
ELECTRIC
/ 55 )
MIT-DS-0337-0.2
26.Apr.2001
(
30
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, Output Open, unless otherwise noted)
Limits
(max)
Symbol
Icc1
Parameter
Test Condition
Unit Note
-6,-6L -7,-7L
Operating current
one bank active (discrete)
tRC=min.tCLK=min, BL=1, CL=3
mA
mA
*1
500
440
Idle Standby Current in
Normal Mode
tCLK=min, CKE>VIHmin
tCLK=L, CKE>VIHmin
Icc2N
Icc2NS
Icc2P
200
48
12
8
160
48
8
*2,3
mA *2,4
Idle Standby Current in
Power Down Mode
mA
*2
tCLK=min, CKE<VILmax
mA
8
Icc2PS CLK= L, CKE<VILmax
Active Standby Current
in Normal Mode
Icc3N
Icc3NS
Icc4
tCLK=min, CKE>VIHmin
CLK=L, CKE=>VIHmin
mA
mA
*3,5
*4,5
240
120
580
200
120
480
Burst Operating Current
Auto-Refresh Current
Self-Refresh Current
tCLK=min, BL=4, gapless data
mA
*5
mA
mA
mA
1440 1360
Icc5
tRFC=min, tCLK=min
CKE <VILmax
6,7
24
16
24
16
Icc6
6L,7L
Notes
1. addresses are charged 3 times during tRC, only 1 bank is active & all other banks are idle
2. all banks are idle
3. input signals are charged one time during 3xtCLK
4. input signals are stable
5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
Unit
Min. Max.
2.4
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA
V
V
Low-Level Output Voltage(DC)
VOL(DC)
IOZOff-stareOutputCurrentQfloatingVO=0~ Vdd
IOL=2mA
0.4
-20
20
80
uA
Input Current
IiVIH=0~Vdd+0.3V
-80
uA
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 31 / 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
-6,-6L
Unit
-7,-7L
Symbol Parameter
Min.
Max.
Min. Max.
CL=2
CL=3
10
10
10
3
3
1
2
1
ns
ns
tCLK
CK cycle time
7.5
tCH CK High pulse width
tCL CK Low pilse width
tT
tIS
tIH
2.5
2.5
1
1.5
0.8
ns
ns
ns
ns
ns
10
10
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
tRC Row cycle time
67.5
75
20
45
20
15
15
15
70
80
20
50
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
us
tRFC Refresh Cycle time
tRCD Row to Column Delay
tRAS Row Active time
tRP Row Precharge time
tWR Write Recovery time
tRRD Act to Act Deley time
tRSC Mode Register Set Cycle time
120K
7.8
120K
7.8
20
tREF Refresh Interval time
Any AC timing is
1.4V
1.4V
CLK
referenced to the input
signal crossing through
1.4V.
Signal
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
32
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
-6,-6L
-7,-7L
Symbol Parameter
Unit
ns
Min. Max. Min. Max.
tAC
Access time from CK
CL=2
CL=3
6
6
6
ns
ns
5.4
Output Hold time
from CK
3
0
3
3
0
3
tOH
Delay time, output low
ns
ns
tOLZ
tOHZ
impedance from CK
Delay time, output high
impedance from CK
6
6
Output Load
Condition
CK
1.4V
DQ
1.4V
VOUT
50pF
Output Timing
Measurement
Reference Point
1.4V
1.4V
CK
DQ
tAC
tOH
tOHZ
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 33/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
X
X
X
0
Y
A12
0
0
0
BA0,1
DQ
D0
D0 D0
D0
D0 D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
( 34/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
tRCD
tRCD
/WE
tWR
tWR
CKE
DQM
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
A0-9,11
X
X
1
A10
A12
0
1
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0
D0
D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
( 35 / 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A0-9,11
A10
A12
0
0
0
BA0,1
DQ
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³ BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
( 36 / 55 )
MIT-DS-0337-0.2
26.Apr.2001
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRAS
tRP
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQM
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
0
X
Y
A0-9,11
X
X
1
X
X
A10
A12
0
1
0
1
2
0
BA0,1
DQ
CL=3
CL=3
Q0
Q0
Q0
Q0
Q1 Q1
Q1
Q1
Q0
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
37
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
CKE
DQM
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
A0-9,11
X
X
1
A10
A12
0
1
0
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0 D0
D0
D0 D1
ACT#0
ACT#1
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
ACT#1
WRITE#1 with
AutoPrecharge
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
38
MIT-DS-0337-0.2
26.Apr.2001
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
CKE
DQM
A0-9,11
A10
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
Y
X
X
X
Y
X
X
1
A12
0
1
0
0
1
1
BA0,1
DQ
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#1 with
Auto-Precharge
READ#0
ACT#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
/ 55 )
MIT-DS-0337-0.2
26.Apr.2001
(
39
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
tRCD
/WE
CKE
DQM
X
X
X
0
X
Y
Y
Y
Y
A0-9,11
X
X
1
A10
A12
0
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D0 D0
D0
D0 D1
D1
D1 D1
D0
D0 D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
26.Apr.2001
40
(
/ 55 )
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
DQM read latency=2
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A12
0
0
1
0
BA0,1
DQ
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
tRCD
tCCD
DQM
X
X
X
0
X
Y
Y
Y
Y
Y
A0-9,11
X
X
1
A10
A12
0
0
0
1
0
BA0,1
CL=3
D0
D0 D0
D0
D0 D0
D1
D1
Q0
Q0
Q0 Q0
DQ
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
DQM read latency=2
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A12
0
0
0
1
0
0
BA0,1
DQ
Q0
Q0 Q0
Q0
Q0 Q0
Q1
Q1 Q0
D0 D0
WRITE#0
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
X
X
X
0
X
Y
Y
X
X
X
1
Y
A0-9,11
A10
X
X
1
A12
0
1
0
1
1
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1 D1
ACT#0
WRITE#0
PRE#0
ACT#1
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted
by Precharge of the other bank.
Burst Write is interrupted by
Precharge of the same bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-9,11
A10
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A12
0
1
0
1
1
BA0,1
DQ
Q0
Q0 Q0
Q0
Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is not interrupted
by Precharge of the other bank.
Burst Read is interrupted
by Precharge of the same bank.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
M
X
X
X
0
Y
A12
0
0
BA0,1
DQ
D0
D0
D0 D0
Auto-Ref (last of 8 cycles)
ACT#0
WRITE#0
Mode
Register
Setting
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
tRCD
/WE
CKE
DQM
X
X
X
0
Y
A0-9,11
A10
A12
BA0,1
DQ
0
D0
D0 D0
D0
Auto-Refresh
Before Auto-Refresh,
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
all banks must be idle state.
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
CLK can be stopped
tRC
/RAS
/CAS
/WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM
A0-9,11
A10
X
X
X
0
A12
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
After tRC from Self-Refresh Exit,
all banks are idle state.
Before Self-Refresh Entry,
all banks must be idle state.
Italic parameter indicates minimum case
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ELECTRIC
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48
Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-9,11
A10
X
X
X
0
Y
Y
Y
A12
0
0
0
BA0,1
DQ
masked
masked
D0
D0 D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
tRCD
/WE
CKE
DQM read latency=2
DQM
X
X
X
0
Y
Y
Y
A0-9,11
A10
A12
0
0
0
BA0,1
masked
masked
Q0
Q0 Q0
Q0
Q0
Q0
Q0
DQ
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
CKE latency=1
DQM
X
X
X
0
A0-9,11
A10
A12
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
CKE latency=1
CKE latency=1
DQM
A0-9,11
A10
X
X
X
0
Y
Y
A12
0
0
BA0,1
DQ
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0
READ#0
CLK suspended
CLK suspended
Italic parameter indicates minimum case
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
OUTLINE
31.75
20.00
4.00
6.00
MITSUBISHI
ELECTRIC
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
EEPROM Components A.C. and D.C. Characteristics
Limits
Typ.
Symbol
Parameter
Units
Min.
Max.
3.6
0
VCC
Supply Voltage
Supply Voltage
3.3
0
3.0
0
Vddx0.7
V
V
V
V
VSS
VIH
Input High Voltage
Input Low Voltage
-0.3
Vccx0.3
0.4
VIL
VOL
Output Low Voltage
V
EEPROM A.C.Timing Parameters(Ta=0 to 70C)
Limits
Symbol
fSCL
Parameter
SCL Clock Frequency
Units
Min.
Max.
80
KHz
100
7.0
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New
Transmission Can Start
TI
TAA
ns
us
0.3
6.7
TBUF
us
THD:STA
TLOW
4.5
6.7
4.5
6.7
0
Start Condition Hold Time
Clock Low Time
us
us
THIGH
Clock High Time
us
us
TSU:STA
Start Condition Setup Time
THD:DAT
TSU:DAT
TR
Data In Hold Time
us
ns
us
ns
500
Data In Setup Time
1
1
SDA and SCL Rise Time
SDA and SCL Fall Time
TF
300
TSU:STO
TDH
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
6.7
us
ns
ms
300
TWR
15
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TR
TF
THIGH
TLOW
54
SCL
TSU:STO
TSU:STA
THD:DAT
THD:STA
TSU:DAT
SDA
IN
TAA
TDH
TBUF
SDA
OUT
MITSUBISHI
ELECTRIC
MIT-DS-0337-0.2
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Preliminary Spec.
Some contents are subject to change without
notice.
MITSUBISHI LSIs
MH32S64PFJ -6, -6L -7,-7L
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
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due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
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The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
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Please also pay attention to information published by Mitsubishi Electric Corporation by
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4.When using any or all of the information contained in these materials, including product
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Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
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6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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