PM100CSE120 [MITSUBISHI]
FLAT-BASE TYPE INSULATED PACKAGE; FLAT -BASE型绝缘包装
| 型号： | PM100CSE120 |
| 厂家： | 
Mitsubishi Group |
| 描述： | FLAT-BASE TYPE INSULATED PACKAGE |
| 文件： | 总6页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI<INTELLIGENTPOWER MODULES>
PM100CSE120
FLAT-BASETYPE
INSULATEDPACKAGE
PM100CSE120
FEATURE
a) Adopting new 4th generation planar IGBT chip, which per-
formance is improved by 1µm fine rule process.
b) Using new Diode which is designed to get soft reverse
recovery characteristics.
• 3φ 100A, 1200V Current-sense IGBT for 15kHz switching
• Monolithic gate drive & protection logic
• Detection, protection & status indication circuits for over-
current, short-circuit, over-temperature & under-voltage
• Acoustic noise-less 18.5/22kW class inverter application
APPLICATION
General purpose inverter, servo drives and other motor controls
PACKAGE OUTLINES
Dimensions in mm
135
1
120.5 0.5
4- φ5.5
MOUNTING
HOLES
24.1
Terminal code
1. VUPC
2. U
39.7
LABEL
0.5 0.3
11. VN1
12. NC
P
11 13 15
10 12 14 16
1
2 3
4
5 6
7 8 9
3. VUP1
4. VVPC
13. U
14. V
15. W
16. F
N
N
3.22
10.16
10.16
10.16
5. V
P
N
2-2.54 2-2.54 2-2.54 6-2.54
67.4
6. VVP1
7. VWPC
O
74.4
8. W
P
9. VWP1
10. VNC
10.5
φ2.54
U
V
W
2-2.54
3.22
0.64
4-R6
51.5
A
26
26
16- 0.64
Screwing depth
Min9.0
6-M5 NUTS
2-φ2.54
A : DETAIL
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM100CSE120
FLAT-BASE TYPE
INSULATED PACKAGE
INTERNAL FUNCTIONS BLOCK DIAGRAM
Rfo=1.5kΩ
W
P
V
WP1
V
P
V
VP1
U
P
VUP1
NC Fo
V
NC
W
N
V
N1
V
N
UN
V
WPC
V
VPC
VUPC
Rfo
Gnd In Fo Vcc Gnd In Fo Vcc
TEMP
Gnd In Fo Vcc Gnd In
Vcc Gnd In
Gnd
Vcc Gnd In
Gnd
Si Out
Vcc
Gnd
Gnd
Gnd
Gnd
Si Out
Si Out
Si Out
Si Out
Si Out
Th
NC
N
W
V
U
P
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
VCES
IC
Parameter
Collector-Emitter Voltage
Collector Current
Condition
Ratings
Unit
V
A
VD = 15V, VCIN = 15V
TC = 25°C
TC = 25°C
1200
100
200
595
ICP
Collector Current (Peak)
Collector Dissipation
Junction Temperature
A
W
°C
PC
TC = 25°C
Tj
–20 ~ +150
CONTROL PART
Symbol
Parameter
Condition
Applied between : VUP1-VUPC
VVP1-VVPC, VWP1-VWPC, VN1-VNC
Applied between : UP-VUPC, VP-VVPC
WP-VWPC, UN • VN • WN-VNC
Applied between : FO-VNC
Sink current at FO terminal
Ratings
20
Unit
V
VD
Supply Voltage
VCIN
20
V
Input Voltage
VFO
IFO
Fault Output Supply Voltage
Fault Output Current
20
20
V
mA
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM100CSE120
FLAT-BASE TYPE
INSULATED PACKAGE
TOTAL SYSTEM
Ratings
Unit
Symbol
Parameter
Condition
Supply Voltage Protected by
OC & SC
VD = 13.5 ~ 16.5V, Inverter Part,
Tj = 125°C Start
VCC(PROT)
800
1000
V
V
VCC(surge) Supply Voltage (Surge)
Applied between : P-N, Surge value or without switching
Module Case Operating
Temperature
TC
(Note-1)
–20 ~ +100
°C
Storage Temperature
Isolation Voltage
Tstg
Viso
–40 ~ +125
°C
Vrms
60Hz, Sinusoidal, Charged part to Base, AC 1 min.
2500
(Note-1) TC measurement point is as shown below. (Base plate depth 3mm)
Tc
63mm
U
V
W
THERMAL RESISTANCES
Limits
Typ.
—
Symbol
Parameter
Unit
Test Condition
Min.
—
—
Max.
0.21
0.35
0.13
0.21
0.018
Rth(j-c)Q
Rth(j-c)F
Rth(j-c’)Q
Inverter IGBT part (per 1 element), (Note-1)
Inverter FWDi part (per 1 element), (Note-1)
Inverter IGBT part (per 1 element), (Note-2)
Inverter FWDi part (per 1 element), (Note-2)
Case to fin, Thermal grease applied (per 1 module)
—
Junction to case Thermal
Resistances
°C/W
—
—
—
—
Rth(j-c’)F
Rth(c-f)
—
—
Contact Thermal Resistance
(Note-2) TC measurement point is just under the chips.
If you use this value, Rth(f-a) should be measured just under the chips.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Limits
Typ.
2.4
2.1
2.5
1.0
0.15
0.4
2.5
0.7
—
Symbol
VCE(sat)
Parameter
Collector-Emitter
Unit
Test Condition
Min.
—
Max.
3.2
2.8
3.5
2.5
0.3
1.0
3.5
1.2
1
VD = 15V, IC = 100A
VCIN = 0V, Pulsed
Tj = 25°C
(Fig. 1) Tj = 125°C
–IC = 100A, VD = 15V, VCIN = 15V
V
V
Saturation Voltage
—
—
(Fig. 2)
VEC
ton
FWDi Forward Voltage
0.5
—
VD = 15V, VCIN = 15V↔0V
VCC = 600V, IC = 100A
Tj = 125°C
trr
µs
—
—
tc(on)
toff
Switching Time
Inductive Load (upper and lower arm)
(Fig. 3)
—
—
tc(off)
Collector-Emitter
Cutoff Current
Tj = 25°C
Tj = 125°C
ICES
V
CE = VCES, VCIN = 15V
(Fig. 4)
mA
—
—
10
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM100CSE120
FLAT-BASE TYPE
INSULATED PACKAGE
CONTROL PART
Limits
Unit
Symbol
Parameter
Circuit Current
Test Condition
VD = 15V, VCIN = 15V
Min.
—
Typ.
45
Max.
62
VN1-VNC
ID
mA
V
—
VXP1-VXPC
15
20
Input ON Threshold Voltage
Input OFF Threshold Voltage
Vth(on)
Vth(off)
Applied between : UP-VUPC, VP-VVPC, WP-VWPC
1.2
1.7
228
145
—
1.5
2.0
1.8
2.3
—
UN • VN • WN-VNC
Tj = 25°C
345
—
OC
Over Current Trip Level
VD = 15V
(Fig. 5,6)
A
—
Tj = 125°C
(Fig. 5,6)
(Fig. 5,6)
Trip level
—
SC
Short Circuit Trip Level
–20≤ Tj ≤ 125°C, VD = 15V
VD = 15V
Base-plate
340
10
A
µs
—
—
toff(OC)
OT
Over Current Delay Time
111
—
118
100
12.0
12.5
—
125
—
Over Temperature Protection
°C
V
Temperature detection, VD = 15V
OTr
Reset level
Trip level
UV
Supply Circuit Under-Voltage
Protection
11.5
—
12.5
—
–20 ≤ Tj ≤ 125°C
UVr
Reset level
—
IFO(H)
IFO(L)
0.01
15
VD = 15V, VFO = 15V
VD = 15V
(Note-3)
Fault Output Current
mA
ms
—
10
Minimum Fault Output Pulse
Width
—
(Note-3)
tFO
1.0
1.8
(Note-3) Fault output is given only when the internal OC, SC, OT & UV protection.
Fault output of OT protection operate by lower arm.
Fault output of OC, SC protection given pulse.
Fault output of OT, UV protection given pulse while over level.
MECHANICAL RATINGS AND CHARACTERISTICS
Limits
Typ.
3.0
Test Condition
Unit
Parameter
Mounting torque
Symbol
Min.
2.5
2.5
—
Max.
3.5
3.5
—
—
—
—
Main terminal
Mounting part
screw : M5
screw : M5
N • m
3.0
Mounting torque
Weight
N • m
g
920
—
RECOMMENDED CONDITIONS FOR USE
Symbol Parameter
Supply Voltage
Test Condition
Recommended value
Unit
V
VCC
Applied across P-N terminals
≤ 800
Applied between : VUP1-VUPC, VVP1-VVPC
VWP1-VWPC, VN1-VNC
VD
Control Supply Voltage
15 1.5
V
V
(Note-4)
Input ON Voltage
Input OFF Voltage
VCIN(on)
VCIN(off)
Applied between : UP-VUPC, VP-VVPC, WP-VWPC
UN • VN • WN-VNC
≤ 0.8
≥ 4.0
Using Application Circuit input signal of IPM, 3φ
sinusoidal PWM VVVF inverter
kHz
µs
PWM Input Frequency
fPWM
tdead
≤ 20
(Fig. 8)
(Fig. 7)
Arm Shoot-through
Blocking Time
For IPM’s each input signals
≥ 3.0
(Note-4) Allowable Ripple rating of Control Voltage : dv/dt ≤ 5V/µs, 2Vp-p
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM100CSE120
FLAT-BASE TYPE
INSULATED PACKAGE
PRECAUTIONS FOR TESTING
1. Before appling any control supply voltage (VD), the input terminals should be pulled up by resistores, etc. to their corre-
sponding supply voltage and each input signal should be kept off state.
After this, the specified ON and OFF level setting for each input signal should be done.
2. When performing “OC” and “SC” tests, the turn-off surge voltage spike at the corresponding protection operation should not
be allowed to rise above VCES rating of the device.
(These test should not be done by using a curve tracer or its equivalent.)
P, (U,V,W)
P, (U,V,W)
IN
IN
(Fo)
(Fo)
Ic
–Ic
V
V
V
CIN
(15V)
V
CIN
(0V)
U,V,W, (N)
U,V,W, (N)
VD
(all)
VD (all)
Fig. 1 VCE(sat) Test
Fig. 2 VEC Test
a) Lower Arm Switching
P
trr
Irr
VCE
Signal input
(Upper Arm)
V
(15V)
CIN
Ic
U,V,W
Vcc
C
S
90%
Fo
90%
Signal input
(Lower Arm)
V
CIN
N
P
10%
V
D (all)
Ic
10%
b) Upper Arm Switching
10%
10%
tc (on)
tc (off)
V
CIN
Signal input
(Upper Arm)
VCIN
U,V,W
Vcc
C
S
td (on)
tr
td (off)
tf
Fo
V
(15V)
CIN
Signal input
(Lower Arm)
(ton= td (on) + tr)
(toff= td (off) + tf)
N
Ic
VD (all)
Fig. 3 Switching time Test circuit and waveform
P, (U,V,W)
A
VCIN
IN
(Fo)
Pulse
VCE
V
(15V)
CIN
Over Current
OC
U,V,W, (N)
IC
VD (all)
toff (OC)
Constant Current
Fig. 4 ICES Test
P, (U,V,W)
Short Circuit Current
IN
(Fo)
V
CC
Constant Current
SC
V
CIN
IC
U,V,W, (N)
V
D
(all)
IC
Fig. 5 OC and SC Test
Fig. 6 OC and SC Test waveform
P
VD
VCINP
U,V,W
Vcc
VD
V
CINN
CINP
N
Ic
V
0V
0V
t
t
VCINN
tdead
t
dead
t
dead
Fig. 7 Dead time measurement point example
Sep. 2001
MITSUBISHI <INTELLIGENT POWER MODULES>
PM100CSE120
FLAT-BASE TYPE
INSULATED PACKAGE
P
≥10µ
20k
V
UP1
Vcc
In
¡
OUT
Si
+
VD
I
F
U
P
–
U
V
UPC
GND GND
≥0.1µ
V
VP1
Vcc
OUT
Si
V
D
D
V
V
P
In
V
VPC
GND GND
M
V
WP1
Vcc
OUT
Si
V
W
P
In
W
V
WPC
GND GND
20k
Vcc
Fo
In
OUT
Si
¡
≥10µ
I
F
U
N
GND GND
≥0.1µ
N
Th
20k
TEMP
Vcc
¡
OUT
≥10µ
≥10µ
Fo
I
F
Si
V
V
N
In
GND GND
≥0.1µ
20k
N1
Vcc
¡
OUT
Fo
I
F
VD
Si
In
W
N
GND GND
NC
≥0.1µ
V
NC
NC
Fo
1k
5V
Rfo
: Interface which is the same as the U-phase
Fig. 8 Application Example Circuit
NOTES FOR STABLE AND SAFE OPERATION ;
Design the PCB pattern to minimize wiring length between opto-coupler and IPM’s input terminal, and also to minimize the
stray capacity between the input and output wirings of opto-coupler.
•
•
Quick opto-couplers : TPLH, TPLH ≤ 0.8µs. Use High CMR type. The line between opto-coupler and intelligent module
should be shortened as much as possible to minimize the floating capacitance.
Slow switching opto-coupler : recommend to use at CTR = 100 ~ 200%, Input current = 8 ~ 10mA, to work in active.
Use 4 isolated control power supplies (VD). Also, care should be taken to minimize the instantaneous voltage charge of the
power supply.
•
•
Make inductance of DC bus line as small as possible, and minimize surge voltage using snubber capacitor between P and N
terminal.
•
•
Use line noise filter capacitor (ex. 4.7nF) between each input AC line and ground to reject common-mode noise from AC line
and improve noise immunity of the system.
Sep. 2001
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