MSM8128SXLI-025 [MOSAIC]
Standard SRAM, 128KX8, 25ns, CMOS, CDXA32, VIL-32;
| 型号： | MSM8128SXLI-025 |
| 厂家： | 
MOSAIC |
| 描述： | Standard SRAM, 128KX8, 25ns, CMOS, CDXA32, VIL-32 CD 静态存储器 |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 8 SRAM
MSM8128X - 020/25/35
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : November 1998
131,072 x 8 CMOS High Speed Static RAM
Description
Features
The MSM8128X is a 1Mbit monolithic SRAM
organised as 128K X 8 with access times of
20ns to 35ns. This part is available in the high
density VIL package. It has completely static
operation and and is directly TTL compatible.
The device features a low power standby and
has 3.0V battery backup capability.
• Fast Access Times of 20/25/35 ns.
• Operating Power 935 mW (max)
• Standby Power 55 mW (max) - L Version
• Low Voltage Data Retention.
• Completely Static Operation.
• Directly TTL compatible.
The device may be screened in accordance
with MIL-STD-883 requirements.
• Single Chip Select Pinout.
• May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
A4
A5
A6
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
NC
WE
A13
A8
MEMORY ARRAY
512 ROWS
256 X 8 COLUMNS
A7
A12
A13
A14
A15
A16
A9
TOP VIEW 25
A11
OE
A10
CS
D7
D6
D5
D4
D3
VX
24
23
22
21
20
19
18
17
D0
COLUMN I/O
I/O
BUFFER
COLUMN DECODE
D7
Y ADDRESS BUFFER
WE
OE
CS
Pin Functions
A0-A16
D0-7
CS
Address Inputs
Data Input/Output
Chip Select
Package Details
OE
WE
NC
VCC
Output Enable
Write Enable
No Connect
Power (+5V)
Ground
Pin Count
Description
0.1" Vertical-in-Line (VILTM)
Package Type
32
V X
GND
ISSUE 4.3 : November 1998
MSM8128X - 020/25/35
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
(2)
Voltage on any pin relative to VSS
Power Dissipation
VT
PT
-0.5V to +7.0
1
V
W
oC
Storage Temperature
TSTG -65 to +150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) Pulse width:- 3.0V for less than 10ns.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
5.5
Supply Voltage
VCC
VIH
VIL
4.5
2.2
-0.5
0
5.0
V
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
-
Vcc+0.5 V
0.8
70
V
C
C
C
o
o
o
TA
TAI
TAM
-40
-55
85
(I suffix)
125
(M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol
Test Condition
min
typ
max Unit
Input Leakage Current
Output Leakage Current
ILI
VIN=0V to VCC
-2
-2
-
-
2
2
µA
µA
ILO
CS=VIH, VI/O=0V to VCC, OE=VIH
Average Operating Current
Standby Supply Current
-L Version
ICC
CS=VIL, II/O=0mA, I/P's Static
CS=VIH, VIN = VIHor VIL
CS≥VCC-0.2V, 0.2V≥VIN≥VCC-0.2V
IOL=8.0mA
-
-
-
-
-
-
170 mA
ISB
-
-
40
10
0.4
-
mA
mA
V
ISB1
VOL
VOH
Output Voltage
-
IOH=-4.0mA
2.4
V
Typical values are at VCC=5.0V,TA=25oC and specified loading.
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol
Test Condition
typ
max
Unit
Input Capacitance:
I/O Capacitance:
CIN
VIN = 0V
VI/O= 0V
-
-
6
8
pF
pF
CI/O
Note: This parameter is sampled and not 100% tested.
2
MSM8128X - 020/25/35
ISSUE 4.3 : November 1998
Operating Modes
The table below shows the logic inputs required to control the MSM8128X SRAM.
Mode
CS OE
WE
VCC Current
I/O Pin Reference Cycle
Not Selected
Output Disable
Read
1
0
0
0
X
1
X
1
1
0
ISB,ISB1
ICC
High Z
High Z
DOUT
Power Down
0
ICC
Read Cycle
Write Cycle
Write
X
ICC
DIN
1 = VIH,
0 = VIL,
X = Don't Care
Low Vcc Data Retention Characteristics - L Version Only (TA=-55OC to +125OC)
Parameter
Symbol
Test Condition
min
2
typ
-
max Unit
VCC for Data Retention
Data Retention Current
VDR
ICCDR
CS≥VCC-0.2V
-
V
VCC=3.0V, CS≥VCC-0.2V,
0.2V≥VIN≥VCC-0.2V
See Retention Waveform
-
-
-
-
-
-
5
-
mA
ns
Chip Deselect to Data Retentiont
Operation Recovery Time
tCDR
tR
See Retention Waveform
-
ms
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
I/O Pin
Ω
166
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
1.76V
30pF
3
ISSUE 4.3 : November 1998
MSM8128X - 020/25/35
AC OPERATING CONDITIONS
Read Cycle
-020
-025
min max
-35
min max Unit
Parameter
Symbol min max
Read Cycle Time
tRC
20
-
-
20
20
8
25
-
-
25
25
8
35
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
35
35
12
-
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Enable to Output in Low Z
Chip Selection to Output in Low Z
Output Disable to Output in High Z(3)
Chip Deselection to Output in High Z(3)
Output Hold from Address Change
-
-
-
tOLZ
tCLZ
tOHZ
tCHZ
tOH
0
5
0
0
5
-
0
5
0
0
5
-
0
5
0
0
5
-
-
-
15
15
-
15
15
-
15
15
-
Write Cycle
-020
min max
-025
min max
-035
min max
Unit
Parameter
Symbol
Write Cycle Time
tWC
tCW
tAS
20
16
0
-
-
25
16
0
-
-
35
20
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Setup Time
-
-
-
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
16
15
5
-
16
15
5
-
20
20
5
-
-
-
-
Write Recovery Time
-
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
10
-
0
10
-
0
10
-
10
0
10
0
15
0
-
-
-
tOW
3
-
3
-
3
-
Under Development
4
MSM8128X - 020/25/35
ISSUE 4.3 : November 1998
Read Cycle Timing Waveform(1,2)
t
RC
A0~A16
OE
t AA
t OE
t OH
t OLZ
t CLZ
CS
t ACS
t CHZ(3)
tOHZ(3)
High-Z
D0~7
Data Valid
Notes:
(1) During the Read Cycle, WE is high for the MSM8128X.
(2) Address valid prior to or coincident with CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
tWC
A0~A16
t AS(3)
OE
tAW
tWR
(2)
tCW(4)
(6)
CS
tWP(1)
WE
tOHZ(3,9)
tOW
High-Z
D0~7out
tDW
tDH
High-Z
D0~7in
5
ISSUE 4.3 : November 1998
MSM8128X - 020/25/35
Write Cycle No.2 Timing Waveform (5)
tWC
A0~A16
CS
(4)
tCW
(6)
tAW
tWP(1)
tWR(2)
WE
tAS(3)
tOH
tWHZ(3,9)
tOW
(8)
(7)
High-Z
D0~7out
tDW
tDH
High-Z
D0~7in
Low VCC Data Retention Timing Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS1~4 > Vcc-0.2V
CS1~4
0V
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
6
MSM8128X - 020/25/35
ISSUE 4.3 : November 1998
32 pin 0.1" Vertical-in-Line (VILTM) - 'VX' Package
3.18 (0.125)
2.67 (0.105)
41.02 (1.615)
40.26 (1.585)
4.00 (0.157)
3.00 (0.117)
1.54 (0.060)
1.02 (0.040)
2.67 (0.105)
2.41 (0.095)
0.51 (0.020)
0.41 (0.016)
2.54 (0.100)
Military Screening Procedure
Screening Flow for high reliability product in accordance with MIL-STD-883 method 5004 is shown below.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition E (Y, only) (30,000g)
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
100%
100%
100%
100%
100%
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Hermeticity
Calculated at post-burn-in at TA=+25°C
1014
5%
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
7
100%
ISSUE 4.3 : November 1998
MSM8128X - 020/25/35
Ordering Information
MSM8128SXLMB - 35
Speed
020 = 20 ns
025 = 25 ns
35
= 35 ns
Temp. range/screening
Blank = Commercial
I
M
= Industrial
= Military
MB = Screened in accordance
with MIL-STD-883
Power Consumption
Blank = Standard Power
L
= Low Power
Package
VX
= 32 pin 0.1" VIL
Memory Organisation
8128 = 128K x 8 SRAM
Although this data is beleived to be accurate, the information contained herein is not intended to and does not
create any warranty of merchantibility or fitness for a particular purpose.
Our products are subjected to a constant process of development. Data may be changed at any time without
notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
8
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