MSM8512JLMB-85 [MOSAIC]
Standard SRAM, 512KX8, 85ns, CMOS, CQCC32, JLCC-32;
| 型号： | MSM8512JLMB-85 |
| 厂家： | 
MOSAIC |
| 描述： | Standard SRAM, 512KX8, 85ns, CMOS, CQCC32, JLCC-32 静态存储器 |
| 文件： | 总8页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512K x 8 SRAM
MSM8512 - 70/85/10
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.3 : January 1999
524,288 x 8 CMOS Static RAM
Description
Features
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70nsto100nsavailable.Thedeviceisavailablein
three 32 pin ceramic packages, one being the
space saving VILTM. The device has a low power
standby version which supports data retention
mode and is directly TTL compatible.
Fast Access Times of 70/85/100 ns
JEDEC standard package.
Average Operating Power 385 mW (max)
Standby Power
550 µW (max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
All versions can be screened in accordance with
MIL-STD-883C.
May be processed in accordance with MIL-STD-883C
Block Diagram
Pin Definition
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A18
A16
A14
A12
A7
Vcc
A15
A17
WE
A13
A8
A18
A17
2
3
A16
A15
A14
A13
A12
A11
A10
A9
4,194,304
BIT
4
5
6
A6
A5
A4
MEMORY
ARRAY
S,V
Package
Top View
7
A9
8
A11
OE
A10
CS
D7
9
A3
A2
A1
10
11
12
13
14
15
16
A0
D0
D6
D5
D0
D7
D1
D2
GND
COLUMN I/O
I/O
BUFFER
D4
D3
COLUMN DECODE
Y ADDRESS BUFFER
WE
D1
D2
4
A12
A14
A16
A18
VCC
A15
CS2
14
15
16
17
18
19
20
OE
CS
3
2
TOP VIEW
J
GND
D3
1
D4
32
31
30
D5
D6
Pin Functions
Package Details
A0-A18
D0-7
CS
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
Power (+5V)
Ground
Pin Count
Descripion
Package Type
32
32
32
0.6" Dual-in-Line (DIP)
0.1" Vertical-in-line (VILTM)
Extended JLCC Package
S
V
J
OE
WE
VCC
GND
ISSUE4.3:January1999
MSM8512 -70/85/10
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
(2)
Voltage on any pin relative to VSS
Power Dissipation
VT
-0.5
-55
to
1
+7.0
V
PT
W
OC
Storage Temperature
TSTG
to
+150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) Pulse width:- 3.0V for less than 30ns.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
min
4.5
2.2
-0.3
0
typ
max
5.5
6.0
0.8
70
unit
V
Supply Voltage
5.0
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
-
V
VIL
V
o
TA
C
o
TAI
-40
-55
85
C
(I suffix)
o
TAM
125
C
(M, MB suffix)
DC Electrical Characteristics (VCC = 5.0V±10%, TA=-55°C to +125°C)
Parameter
Symbol Test Condition
min
typ
max Unit
Input Leakage Current
Output Leakage Current
ILI
VIN=0V to VCC
-1
-1
-
-
1
1
µA
µA
ILO
CS=VIH, VI/O=0V to VCC, OE=VIH or WE=VIL
Average Supply Current ICC1 CS=VIL, II/O=0mA, min cycle, duty=100%
-
-
-
-
-
-
70
3
mA
mA
µA
Standby Supply Current
-L version only
ISB
CS=VIH, VIN=VIH or VIL
ISB1 CS≥VCC-0.2V, VIN≥VCC -0.2V or 0.2V≥VIN
100
Output Voltage
VOL IOL=2.1mA
VOH IOH=-1.0mA
-
-
-
0.4
-
V
V
2.4
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol
Test Condition
typ
max
Unit
Input Capacitance:
I/O Capacitance:
CIN
VIN = 0V
VI/O= 0V
-
-
8
pF
pF
CI/O
10
Note : This parameter is sampled and not 100% tested.
AC Test Conditions
Output Load
* Input pulse levels: 0.8V to 2.2V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* Vcc=5V±10%
I/O Pin
645
Ω
1.76V
100pF
2
MSM8512 -70/85/10
ISSUE4.3 :January1999
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter
Symbol TestCondition
min
typ
max
Unit
VCC for Data Retention
DataRetentionCurrent
Chip Deselect to Data Retention tCDR
VDR
ICCDR
CS≥VCC-0.2V
2.0
-
0
-
-
-
5.5
250
-
V
µA
ns
VCC=3.0V,CS≥VCC-0.2V,
See Retention Waveform
OperationRecoveryTime
tR
See Retention Waveform
5
-
-
ms
AC OPERATING CONDITIONS
Read Cycle
70
min max
85
10
min max
Parameter
Symbol
min max
Units
Read Cycle Time
tRC
tAA
70
-
-
85
-
-
100
-
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
70
70
35
-
85
85
45
-
tACS
tOE
-
-
-
-
-
-
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z(3) tCHZ
Output Disable to Output in High Z(3) tOHZ
tOH
tCLZ
tOLZ
10
10
5
10
10
5
10
10
5
-
-
-
-
-
-
0
25
25
0
30
30
0
30
30
0
0
0
Write Cycle
70
min max
85
min max
10
min max
Parameter
Symbol
Unit
Write Cycle Time
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
70
60
60
0
50
0
0
30
0
-
-
-
-
-
-
30
-
-
-
85
75
75
0
55
5
0
35
0
-
-
-
-
-
-
30
-
-
-
100
80
80
0
60
5
0
40
0
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Output Disable to Output in High Z
tOW
tOHZ
5
0
5
0
5
0
25
30
30
3
ISSUE4.3:January1999
MSM8512 -70/85/10
Read Cycle Timing Waveform(1,2)
t
RC
Address
OE
t AA
tOE
t OH
t OLZ
tCLZ
CS
t ACS
t CHZ(3)
tOHZ(3)
High-Z
D0~7
Data Valid
Notes:
(1) During the Read Cycle, WE is high.
(2) Address valid prior to or coincident with CS transition Low.
(3) CHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
t
Write Cycle No.1 Timing Waveform
tWC
Address
OE
t AS(3)
tAW
tCW(4)
tWR
(2)
(6)
CS
tWP(1)
WE
tOHZ(3,9)
tOW
tDH
High-Z
D0~7 out
D0~7 in
tDW
High-Z
4
MSM8512 -70/85/10
ISSUE4.3 :January1999
Write Cycle No.2 Timing Waveform (5)
tWC
Address
CS
(4)
tCW
(6)
tAW
tWP(1)
tWR(2)
WE
tAS(3)
tOH
tWHZ(3,9)
tOW
(8)
(7)
High-Z
D0~7 out
tDW
tDH
High-Z
D0~7 in
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Low VCC Data Retention Timing Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS>Vcc-0.2V
CS
0V
5
ISSUE4.3:January1999
MSM8512 -70/85/10
Package Details
32 pin 0.6" Dual-in-Line (DIP) - 'S' Package
41.05 (1.616)
40.23 (1.584)
1.52 (0.060)
1.02 (0.040)
4.30 (0.170)
3.30 (0.130)
4.00 (0.157)
3.00 (0.117)
0.51 (0.020)
0.41 (0.016)
2.67 (0.105)
2.41 (0.095)
All dimensions in mm (inches).
32 pin 0.1" Vertical-in-Line (VILTM) - 'V' Package
41.05 (1.616)
40.23 (1.584)
3.18 (0.125)
2.67 (0.105)
4.00 (0.157)
3.00 (0.117)
1.40 (0.055)
0.51 (0.020)
0.41 (0.016)
2.54 (0.100)
1.14 (0.045)
2.54 (0.100)
38.23 (1.505)
37.97 (1.495)
All dimensions in mm (inches).
MSM8512 -70/85/10
ISSUE4.3 :January1999
32 pin J Leaded LCC (JLCC)
0.71 (0.028) typ
1.27 (0.050) typ
1.90 (0.075)
1.65 (0.065)
11.70 (0.460)
11.30 (0.445)
No. 1 Index
0.43 (0.017)
typ
4.07 (0.160)
3.56 (0.140)
7.87 (0.310)
7.37 (0.290)
All dimensions in mm (inches).
Military Screening Procedure
Screening Flow for high reliability product in accordance with MIL-STD-883 method 5004 is shown below.
MB COMPONENT SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
Internal visual
2010 Condition B or manufacturers equivalent
1010 Condition C (10 Cycles,-65°C to +150°C)
2001 Condition E (Y, only) (30,000g)
100%
100%
100%
100%
100%
Temperature cycle
Constant acceleration
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Hermeticity
Calculated at post-burn-in at TA=+25°C
5%
1014
Fine
Gross
Condition A
Condition C
100%
100%
External Visual
2009 Per vendor or customer specification
7
100%
ISSUE4.3:January1999
MSM8512 -70/85/10
Ordering Information
MSM8512SLMB - 70
Speed
70
85
10
=
=
=
70ns
85ns
100ns
Temp. Range/Screening Blank
=
=
=
=
Commercial
Industrial
Military
Screened in accordance with
MIL-STD-883
I
M
MB
Power Consumption
Package
Blank
L
=
=
Standard Power
Low Power
S
V
J
=
=
=
32 pin 0.6" DIP
32 pin 0.1" VILTM
32 pin JLCC Package
Memory Organisation
8512
=
5125K x 8 SRAM
Although this data is beleived to be accurate, the information contained herein, is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
8
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