PUMA2E1000LMB-12 [MOSAIC]
EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CPGA66, CERAMIC, PGA-66;
| 型号： | PUMA2E1000LMB-12 |
| 厂家： | 
MOSAIC |
| 描述： | EEPROM Module, 32KX32, 120ns, Parallel, CMOS, CPGA66, CERAMIC, PGA-66 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32K x 32 EEPROM MODULE
PUMA 2E1000-70/90/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
Description
1,048,576 bit CMOS High Speed EEPROM
The PUMA 2E1000 is a 1Mbit High Speed
EEPROM module user configurable as
32Kx32, 64Kx16 or 128Kx8. Available with
Features
Very Fast access times of 70/90/120 ns.
User Configurable as 8 / 16 / 32 bit wide.
Upgradeable footprint.
Operating Power
Standby Power
access times of 70, 90 & 120ns the device
has an industry standard ceramic 66 pin
P.G.A footprint.
1760 mW (max).
1320 mW (max).
Package Suitable for Thermal Ladder Applications.
Single byte and Page Write operation.
DATA Polling and Toggle Bit for End of Write Detection.
Hardware and Software Data Protection.
The device features byte and page write
facility, 10,000 Write Erase cycle capability
and data retention time of 10 years.
The device may be screened in accordance
with MIL-STD-883
May be screened in accordance with MIL-STD-883.
Pin Definition
Block Diagram
45
34
56
12
23
1
D8
2
WE2
13
D15
24
D24
35
VCC
46
D31
57
D9
3
CS2
14
D14
25
D25
36
CS4
47
D30
58
A0~A14
OE
D10
4
GND
15
D13
26
D26
37
WE4
48
D29
59
WE4
WE3
WE2
A13
5
D11
16
D12
27
A6
38
D27
49
D28
60
WE1
VIEW
FROM
ABOVE
A14
6
A10
17
OE
28
A7
39
A3
50
A0
61
32K x 8
EEPROM EEPROM EEPROM
32K x 8
32K x 8
32K x 8
EEPROM
NC
7
NC
29
A11
18
NC
40
A4
51
A1
62
CS1
CS2
NC
A12
19
WE1
30
A8
41
A5
52
A2
63
CS3
CS4
8
NC
9
VCC
20
D7
31
A9
42
WE3
53
D23
64
D0~7
D8~15
D16~23
D24~31
D0
10
CS1
21
D6
32
D16
43
CS3
54
D22
65
D1
11
NC
22
D5
33
D17
44
GND
55
D21
66
D2
D3
D4
D18
D19
D20
Pin Functions
A0-14
CS1-4
WE1-4
VCC
Address Inputs
D0-31
OE
Data Inputs/Outputs
Output Enable
No Connect
Chip Select
Write Enable
Power (+5V)
NC
GND
Ground
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Temperature Under Bias
Storage Temperature
All input voltages (including N.C. pins) with Respect to GND
All output voltages with respect to GND
Voltage on OE and A9 with Respect to GND
TBIAS
TSTG
VT
VOUT
VOEA
-55 to +125
°C
°C
V
V
V
-65 to +150
-0.6 to +6.25
-0.6 to VCC +0.6
-0.6 to +13.5
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated below is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
VCC
VIL
VIH
TA
TAI
TAM
4.5
-0.1
2.0
0
-40
-55
5.0
5.5
0.8
VCC+1
70
85
125
V
V
V
-
-
-
-
-
°
Operating Temp Range
C
°
C (2E1000I)
°C (2E1000M, MB)
DC Electrical Characteristics (VCC=5.0V±10%, TA=-55 to +125°C)
Parameter
Symbol Test Condition
min
typ max
Unit
µA
Input Leakage Current Address, OE
ILI1
0V ≤ VIN≤ VCC+1V
-
-
40
CS1~4, WE1~4 ILI2
As above.
CS1~4=VIH, VI/O=GND to VCC
-
-
-
-
10
40
µA
µA
Output Leakage Current
ILO
Operating Supply Current
Standby Supply Current
ICC32
ISB1
f=5MHz, II/O=0mA
2.0V≤CS1~4≤VCC+1V
-
-
-
-
320
240
mA
mA
-L Version (CMOS) -90, -12 ISB2
-3.0V≤CS1~4≤VCC+1V
-
-
1.2
mA
Output Low Voltage
Output High Voltage
VOL
VOH
IOL = 6.0mA
IOH = -4.0mA
-
-
-
0.45
-
V
V
2.4
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol
Test Condition
typ
26
max
Unit
Input Capacitance:
I/O Capacitance:
CIN
CI/O
VIN =0V
VI/O=0V, 8 bit mode
34
58
pF
pF
42
AC Test Conditions
Output Test Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
645
I/O Pin
Ω
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
1.76V
100pF
2
PUMA 2E1000-70/90/12
ISSUE 4.2 : November 1998
AC READ CHARACTERISTICS
Read Cycle
-70
-90
-12
Parameter
Symbol
min max
min max
min max
Unit
Read Cycle Time
tRC
tACC
tCS
tOE
tDF
-
-
-
0
0
0
70
70
70
40
40
-
-
-
-
0
0
0
90
90
90
45
45
-
-
-
-
0
0
0
120
120
120
50
50
-
ns
ns
ns
ns
ns
ns
Address to Output Delay
CS1~4 to Output Delay(1)
OE to Output Delay (2)
CS1~4 or OE to Output Float (3,4)
Output Hold from OE, CS1~4 or
Address, (whichever occured first)
tOH
Notes: (1) CS1~4 may be delayed up to tACC - tCS after the address transition without impact on tACC
(2) OE may be delayed up to tCS - tOE after the falling edge of CS1~4 without impact on tCS or by tACC - tOE after an
address change without impact on tACC
.
.
(3) tDF is specified from OE or CS1~4 whichever occurs first (CL = 5pF).
(4) This parameter is only sampled and is not 100% tested.
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Address, OE Set-up Time
Address Hold Time
Chip Select Set-up Time
Chip Select Hold Time
tAS, tOES
tAH
tCS
0
50
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tCH
0
Write Pulse Width (WE1~4 or CS1~4) tWP
100
50
0
NR(1)
Data Set-up Time
Data, OE Hold Time
Time to Data Valid
tDS
tDH, tOEH
tDV
Note: (1) NR = No Restriction
Page Mode Write Cycle
Parameter
Symbol
min
typ
max
Unit
Write Cycle Time
tWC
tAS
tAH
-
0
50
50
0
100
-
50
5
-
-
-
-
-
-
-
10
-
-
-
ms
ns
ns
ns
ns
ns
µs
ns
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
Write Pulse Width
tDS
tDH
tWP
tBLC
tWPH
-
-
150
-
Byte/Word Load Cycle Time
Write Pulse Width High
See notes on page 6, Mode Write Waveform.
DATA Polling Characteristics
Parameter
Symbol
min
typ
max
Unit
Data Hold Time
tDH
tOEH
tOE
0
0
-
-
-
-
ns
ns
ns
ns
OE Hold Time
OE to Output Delay(1)
Write Recovery Time
tWR
0
-
-
Note : (1) See AC Read Characteristics.
3
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
Toggle Bit Characteristics (1,2,3,4)
Parameter
Symbol
min
typ
max
Unit
Data Hold Time
tDH
10
10
-
-
-
-
ns
ns
ns
ns
ns
OE Hold Time
tOEH
tOE
tOEHP
tWR
OE to Output Delay (1)
OE High Pulse
150
0
-
-
-
-
Write Recovery Time
Note : (1) See AC Read Characteristics.
(2) Toggling either OE or CS1~4, or both OE and CS1~4 will operate toggle bit.
(3) Beginning and ending state of D6 will vary.
(4) Any address location may be used but the address should not vary.
Read Cycle Timing Waveform (1,2,3,4)
Address Valid
tRC
Address
CS1~4
tCS
tOE
tDF
OE
tOH
tACC
Output
Valid
HIGH Z
DATA OUT
AC Write Waveform - WE1~4 Controlled
tWC
Address
tAH
tAS
tWPH
tWP
WE1~4
tCS
tCH
CS1~4
tOES
OE
tOEH
tDV
High-Z
High-Z
DATA IN
Data Valid
tDS
tDH
4
PUMA 2E1000-70/90/12
ISSUE 4.2 : November 1998
AC Write Waveform - CS1~4 Controlled
tWC
Address
tAS
tCS
tAH
tCH
WE1~4
tWP
CS1~4
tWPH
tOES
OE
tOEH
tDV
High-Z
High-Z
Data Valid
tDS
DATA IN
tDH
(1,2)
Page Mode Write Waveform
OE
CS1~4
tWPH
tBLC
tWP
WE1~4
tAH
tDH
tAS
Valid
Add
A0-A5
Data
tDS
Valid
Data
Byte 0
Byte 1
Byte 2
Byte 3
Byte 62
Byte 63
tWC
Note: (1) A6 through A14 must specify the page address during each high to low transition of WE1~4 (or CS1~4).
(2) OE must be high only when WE1~4 and CS1~4 are both low.
5
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
DATA Polling Waveform (1)
WE1~4
CS1~4
tOEH
OE
tDH
tOE
tWR
High Z
D7,D15,
D23,D31
An
An
An
An
An
A0-A14
Toggle Bit Waveform (1,2,3,4)
WE1~4
CS1~4
tOEH
tOEHP
tOE
OE
tDH
tWR
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
D6,D14,
D22,D30
Software Protected Write Waveform (1,2)
OE
CS1~4
tWP
tBLC
WE1~4
tWPH
tAH
tAS
BYTE ADDRESS
A0~A5
05555
02AAA
05555
A6~A14
Data
PAGE ADDRESS
tDS tDH
tWC
AA
55
A0
Byte 0
Byte 62
Byte 63
Notes: (1) A6 through A14 must specify the page address during each high to low transition of WE1~4 (or CS1~4).
(2) OE must be high only when WE1~4 and CS1~4 are both low.
6
PUMA 2E1000-70/90/12
ISSUE 4.2 : November 1998
Chip Erase Waveform
VIH
CS1~4
VIL
VH
OE
VIL
VIH
t S
t H
t W
WE1~4
VIL
tS = tH = 5µs (min) tW = 10 ms (min) VH = 12V ± 0.5V
7
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
Device Operation
Where references are made to byte/word operations, the user will control the memory configuration of 8, 16, or
32 bits wide using CS1~4.
Read
The PUMA 2E1000 read operations are initiated by both Output Enable and Chip Select(s) LOW, while Write
Enable(s) is HIGH. The read operation is terminated by either Chip Select(s) or Output Enable returning HIGH.
Thisdual-linecontrolarchitectureeliminatesbuscontentioninasystemenvironment.Thedatabuswillbeinahigh
impendence state when either Output Enable or Chip Select is HIGH.
Write
Write operations are initiated when both Chip Select(s) and Write Enable(s) are LOW and Output Enable is HIGH.
ThePUMA2E1000supportsbothaChipSelect(s)andWriteEnable(s)controlledwritecycle. Thatis, theaddress
is latched by the falling edge of either Chip Select(s) or Write Enable(s), whichever occurs last. Similarly, the data
is latched internally by the rising edge of either Chip Select(s) or Write Enable(s), whichever occurs first. A byte/
word write operation, once initiated, will automatically continue to completion, within 10 ms max.
Page Mode Write
Thepagewritefeatureofthe PUMA2E1000allowstheentirememorytobewrittenintypically5.12seconds. Page
Write allows 1 to 64 bytes/words of data to be written into the device during a single programming cycle. The host
can fetch data from another location within the system during a page write operation (change the source address),
butthepageaddress(A6throughA14)foreachsubsequentvalidwritecycletothepart, duringthisoperationmust
be the same as the initial page address.
The page write mode can be initiated during any write operation. Following the initial byte/word write cycle, the
host can write up to 63 bytes/words in the same manner as the first byte/word written. Each successive byte/word
load cycle, started by the Write Enable(s) HIGH to LOW transition, must begin within 150 µs of the falling edge of
the preceding Write Enable(s). If a subsequent Write Enable(s) HIGH to LOW transition is not detected within 150
µs, the internal automatic programming cycle will commence.
The A0 to A5 inputs are used to specify which bytes/words within the page are to be written. The bytes/words may
be loaded in any order and altered within the same load period. Only bytes/words which are specified for writing
will be written; unnecessary cycling of other bytes/words within the page does not occur.
DATA Polling
The PUMA 2E1000 features DATA Polling to indicate if the write cycle is completed. During the internal
programming cycle, any attempt to read the last byte/word written will produce the complement of that data on D7.
Once the programming is complete, D7 will refect the true data. Note: If the the PUMA 2E1000 is in a protected
stateandanillegalwriteoperationis attemptedDATAPollingwillnotoperate. DATAPollingmaybeginatanytime
during the write cycle.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 toggling between 1 and 0. Once a write is complete,
thistogglingwillstopandvaliddatawillberead. Readingthetogglebitmaybeginatanytimeduringthewritecycle.
8
PUMA 2E1000-70/90/12
ISSUE 4.2 : November 1998
Hardware Data Protection
The PUMA 2E1000 provides hardware features to protect non-volatile data from inadvertent writes.
•
•
VCC Sense - If VCC is below 3.8V (typical) the write function is inhibited.
VCC Power-on-Delay - Once VCC has reached 3.8V the device will automatically time out 5ms (typical) before
allowing a write.
•
•
Write Inhibit - Holding any one of OE Low, CS High, WE High inhibits write cycles
Noise Filter - Pulses of less than 15ns (typical) on the WE or CS inputs will not initiate a write cycle.
Software Data Protection
ThePUMA2E1000canbeautomaticallyprotectedduringpower-upandpower-downwithouttheneedforexternal
circuitsbyemployingthesoftwaredataprotectfeature. Theinternalsoftwaredataprotectioncircuitisenabledafter
the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of
the device unless the reset command is issued.
Once the software protection is enabled, the PUMA 2E1000 is also protected against inadvertent and accidental
writes in that, the software algorithm must be issued prior to writing additional data to the device.
Operating Modes
The table below shows the logic inputs required to control the operation of the PUMA 2E1000.
CS1~4 OE
WE1~4
OUTPUTS
MODE
Read
Data Out
Data in
High-Z
0
0
1
X
X
0
1
1
0
X
1
X
X
0
Write
X
X
0
Standby/Write inhibit
Write Inhibit
High-Z
High-Z
Output Disable
Chip Erase(1)
1
1
X
0
0 = VIL : 1 = VIH : X = VIH or VIL
Notes : (1) OE must be 12.0V ± 0.5V
Device Indentification
An extra 64 bytes of EEPROM memory are avaliable to the user for device identification, accessed by placing
12V±0.5V on A9 and using locations 7FC0H to 7FFFH. These locations can be used during the initial programming
of each EEPROM to record data such as issue number and release date, and subsequent reprogramming can
change these locations to record the alterations performed.
Chip Erase
All of the memory locations on the PUMA 2E1000 can be erased in 10 ms by placing 12.0V±0.5V onto OE and
controlling WE1~4 and CS1~4 to follow the Chip Erase timing characteristics. This function will operate even if the
module is in Software Data Protection Mode as explained later.
9
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
Software Data Protection
Softwarecontrolleddataprotection,onceenabled by theuser,necessitatestheuseofasoftwarealgorithmbefore
any Write can be performed. To enable this feature a special sequence of 3 Writes to 3 specific addresses must
be performed, and must be reused for each subsequent Write cycle. Once set the data protection remains
operational until it is disabled by using a second algorithm; power transitions will not reset this feature.
Note that the PUMA 2E1000 is supplied with the Software data Protection feature disabled.
The algorithms to enable and disable the protection are shown below:
SDP Enable
SDP Disable
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 5555
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA A0
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
WRITES
ENABLED
(2)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS
(4)
LOAD DATA 55
TO
ADDRESS2AAA
LOAD LAST BYTE/
WORD TO
LAST ADDRESS
ENTER DATA
PROTECT
STATE
LOAD DATA 20
TO
ADDRESS 5555
Once initiated, the enable sequence of
write operations should not be interrupted
EXIT DATA
PROTECT
STATE
(3)
LOAD DATA XX
TO
ANY ADDRESS
(4)
Notes : (1) Data D7 - D0 (hex); Address A14 - A0 (hex).
(2) Write Protect Mode will be activated at end of
Write even if no other data is loaded.
LOAD LAST BYTE/
WORD TO
LAST ADDRESS
(3) Write protect state will be disabled at end of
write period even if no other data is loaded.
(4) 1 to 64 bytes/words of data can be loaded.
Note: Load Data above represents 8 bit mode. For 16 or 32 bit mode, place the load data in the 2 bytes or
all 4 bytes on the data lines, respectively. Eg/ 8 bit load data = 55HEX, 16 bit load data = 5555HEX
.
All software write commands must obey the Page Write timing specifications.
TheprocessofdisablingtheDataProtectionmodeisverysimilartothatdescribedforenable,except6bytes/words
must be loaded to specific locations in the EEPROM as shown.
Noteheretheuseoftheword'load'todescribeenablinganddisablingtheprotectionmodesinpreferenceto'write'.
Although it may seem that if the Write command sequence is performed to enable protection then the three bytes/
words at those addresses will be overwritten with AA,55,A0, this is not the case.
10
PUMA 2E1000-70/90/12
ISSUE 4.2 : November 1998
Package Details Dimensions in mm (inches).
27.69 (1.090) Sq. Max.
4.83 (0.190)
2.54 (0.100) typ.
15.24 (0.60) typ
4.32 (0.170)
0.53 (0.021)
0.38 (0.015)
1.40 (0.055)
1.14 (0.045)
2.54 (0.100) typ.
1.27 (0.050)
0.64 (0.025)
1.52 (0.060)
1.02 (0.040)
8.13 (0.320) max
Military Screening Procedure
Module Screening Flow for high reliability product is in accordance with MIL-STD-883 method 5004 Level B and
is detailed below:
MB MODULE SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
Visual and Mechanical
External visual
Temperature cycle
2017 Condition B (or manufacturers equivalent)
1010 Condition C (10 Cycles,-65°C to +150°C)
100%
100%
Burn-In
Pre Burn-in Electrical
Burn-In
Per Applicable device Specifications at TA = +25°C (optional) 100%
Method 1015, Condition D, TA = +125°C
100%
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective Allowable (PDA)
Quality Conformance
Calculated at Post Burn-in at TA=+25°C
Per applicable Device Specification
2009 Per HMP or customer specification
10%
Sample
External Visual
11
ISSUE 4.2 : November 1998
PUMA 2E1000-70/90/12
Ordering Information
PUMA 2E1000LMB-70
Speed
70
90
12
= 70 ns
= 90 ns
= 120 ns
Temp. range/screening
Blank = Commercial Temp.
I
= Industrial Temp.
= Military Temp.
= Screened in accordance with
MIL-STD-883
M
MB
Power Consumption
Memory Type
Blank = Standard Part
L
= Low Power Part (-90, -12 Only)
E1000 = EEPROM (Configurable as
32Kx32, 64Kx16 or 128Kx8)
Although this data is believed to be accurate the information contained herein is not intended to and does not create any
warranty of merchantability or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of a
company director.
12
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