PUMA68SV16000XL-015 [MOSAIC]
SRAM Module, 512KX32, 15ns, CMOS, PLASTIC, LCC-68;
| 型号： | PUMA68SV16000XL-015 |
| 厂家： | 
MOSAIC |
| 描述： | SRAM Module, 512KX32, 15ns, CMOS, PLASTIC, LCC-68 静态存储器 |
| 文件： | 总12页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
51Kx32SaticRAM
PUMA 68SV16000X - 012/015/017
Issue 5.1 December 1999
Description
Block Diagram
The PUMA68 range of devices provide a high
density surface mount industry standard memory
solution which may accommodate various memory
technologies including SRAM, EEPROM and
Flash. The devices are designed to offer a defined
upgrade path and may be user configured as 8, 16
or 32 bits wide.
A0~A18
/OE
/WE
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
512K x 8
SRAM
The PUMA68SV16000X is a 512Kx32 SRAM mod-
ulehousedina68Jleadedpackagewhichcomplies
withtheJEDEC68PLCCstandard.Accesstimesof
12, 15 or 17ns are available. The 3.3V low voltage
device is available to commercial and industrial
temperature grade.
/CS1
/CS2
/CS3
/CS4
D0~7
D8~15
D16~23
D24~31
64Kx32, 128Kx32 and 256Kx32 SRAM PUMA68
devices are available in the same footprint. The
upgrade part (1Mx32 SRAM) is planned.
Features
Pin Definition
See page 2.
• Access times of 12/15/17 ns.
• 3.3V + 10%.
• Comercial and Industrial temperature grades
• JEDEC standard 68 J Lead footprint.
• Industry standard pinout.
Pin Functions
• May be organised as 512K x 32, 1M x 16, 2M X 8
• Operating Power
(32 Bit) 2.95W (max)
Description
Signal
• Low power standby. (TTL) 0.72W (max)
(CMOS) 145mW (max)
Address Input
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power
A0~A18
D0~D31
/CS1~4
/WE
• Low voltage data retention mode.
• Completely Static Operation.
/OE
NC
Package Details
VCC
PUMA 68 - Plastic 68 ‘J’ Leaded Package
Max. Dimensions (mm) - 25.27 x 25.27 x 5.08
Ground
VSS
11403 West Bernardo Court, Suite 100, San Diego, CA92127.
TEL (858) 674 2233, Fax No. (858) 674 2230 E-mail: sales@mosaicsemi.com
Pin Definition - PUMA68SV16000X
Pin
1
Signal
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
VCC
A13
A12
A11
A10
A9
VCC
NC
2
3
/CS1
/CS2
/CS3
/CS4
A17
A18
D16
D17
D18
D19
VSS
4
5
6
7
A8
8
A7
9
D0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
D1
D2
D3
VSS
D4
D20
D21
D22
D23
VCC
D5
D6
D7
VCC
D8
D24
D25
D26
D27
VSS
D9
D10
D11
VSS
D12
D13
D14
D15
A14
A15
A16
/WE
/OE
NC
NC
D28
D29
D30
D31
A6
A5
A4
A3
A2
A1
A0
Issue 5.1 December 1999
PAGE 2
Absolute Maximum Ratings(1)
DOperagCdtions
Parameter
Symbol
VT
Min
-0.3
Max
+4.6
Unit
V
Voltage on any pin relative to VSS
Power Dissipation
to
4.0
to
PT
W
Storage Temperature
TSTG
-55
+125
OC
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
Recommended Operating Conditions
Parameter
Symbol
VCC
Min
3.0
2.0
-0.3
0
Typ
Max
3.6
Unit
V
Supply Voltage
3.3
Input High Voltage
Input Low Voltage
Operating Temperature
VIH
-
-
-
-
VCC+0.3
0.8
V
(1)
VIL
V
TA
70
OC
OC
TAI
-40
85
(I Suffix)
Notes : (1) Pulse Width : -2.0V for less than 10ns.
DC Electrical Characteristics
(VCC=3.3V+10%, TA=-40OC to +85OC)
Parameter
Symbol Test Condition
Min Typ Max
Unit
µ
Input Leakage Current
Output Leakage Current
ILI
VIN=0V to VCC
VI/O=0V to VCC
-8
-8
-
-
-
-
-
-
-
8
A
µ
A
ILO
8
Average Supply Current(2) 32 Bit ICC32 /CS(1)=VIL, II/O=0mA,f=fmax
820
510
355
200
mA
mA
mA
mA
16 Bit ICC16 As Above.
-
8 Bit
TTL
ICC8
ISB
As Above.
-
Standby Supply Current
/CS(1)=VIH ,Min Cycle
-
/CS>VCC-0.2V, 0.2V
>VIN>VCC-0.2V, f=0
CMOS ISB1
-
-
40
mA
Output Voltage Low
Output Voltage High
VOL
VOH
IOL=8.0mA, VCC=Min
IOH=-4.0mA, VCC=Min
-
-
-
0.4
-
V
V
2.4
Notes (1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
(2) At f=fMAX address and data inputs are cycling at max frequency.
Issue 5.1 December 1999
PAGE 3
Capacitance
(VCC = 3.3V, TA = 25OC, F=1MHz.)
Parameter
Symbol Test Condition Min
Typ Max Unit
Address, /OE, /WE
Input Capacitance,
CIN1
CI/O
VIN=0V
VI/O=0V
-
-
-
-
32
38
pF
pF
8 bit mode (worst case)
Output Capacitance,
Note : These Parameters are calculated not measured.
Test Conditions
Output Load
166Ω
• Input pulse levels : 0V to 3.0V
• Input rise and fall times : 3ns
I/O Pin
1.76V
• Input and Output timing reference levels : 1.5V
• Output Load : See Load Diagram.
• VCC = 3.3V+10%
30pF
• PUMA module tested in 32 bit mode.
Operation Truth Table
/CS1 /CS2 /CS3 /CS4
/OE
X
X
X
X
X
X
X
L
/WE Supply Current
Mode
L
H
H
H
L
H
L
H
H
L
H
H
H
L
L
L
ICC8
ICC8
Write D0~D7
Write D8~D15
Write D16~D23
Write D24~D31
Write D0~D15
Write D16~D31
Write D0~D31
Read D0~D7
H
H
L
L
ICC8
H
H
L
L
ICC8
H
L
L
ICC16
ICC16
ICC32
ICC8
H
L
H
L
L
L
L
L
L
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
X
H
H
H
L
L
ICC8
Read D8~D15
Read D16~D23
Read D24~D31
Read D0~D15
Read D16~D31
Read D0~D31
H
H
L
L
ICC8
H
H
L
L
ICC8
H
L
L
ICC16
ICC16
ICC32
H
L
H
L
L
L
L
L
X
H
X
H
X
H
X
H
H
X
ICC32 /ICC16/ICC8 D0~D31 High-Z
ISB, ISB1 D0~D31 Standby
Notes : H=VIH : L=VIL : X=VIH or VIL
Issue 5.1 December 1999
PAGE 4
AOperagCdtions
Read Cycle
12
15
17
Parameter
Symbol Min Max Min Max Min Max Units
Read Cycle Time
tRC
12
-
-
12
12
6
15
-
-
15
15
7
17
-
-
17
17
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold From Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
-
-
-
tOH
3
3
0
0
0
-
3
3
0
0
0
-
3
3
0
0
0
-
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
6
7
8
6
7
8
Write Cycle
12
15
17
Parameter
Symbol Min Max Min Max Min Max Units
Write Cycle Time
tWC
tCW
tAW
tAS
12
8
-
-
-
-
-
-
-
6
-
-
-
15
10
10
0
-
-
-
-
-
-
-
7
-
-
-
17
12
12
0
-
-
-
-
-
-
-
8
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
8
0
Write Pulse Width (/OE High)
Write Pulse Width (/OE Low)
Write Recovery Time
tWP1
tWP2
tWR
tWHZ
tDW
tDH
8
10
12
0
12
13
0
12
0
Write to Output in High Z
Data to Write Time Overlap
Data Hold time from Write Time
Output Active from End of Write
0
0
0
6
7
8
0
0
0
tOW
3
3
3
Issue 5.1 December 1999
PAGE 5
Read Cycle 1
TingWaveforms
(Address Controlled, /CS=/OE=VIL, /WE=VIH)
tRC
Address
tAA
tOH
Previous Data Valid
Data Valid
Data Out
Read Cycle 2
(/WE = VIH)
tRC
Address
tAA
tCHZ(3,4,5)
tACS
/CS
tOHZ
tOE
/OE
tOLZ
tOH
tCLZ(4,5)
Data Out
Valid Data
(READ CYCLE)
NOTES
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or
VOL levels.
4. At any given temperature and voltage condition, t CHZ(Max.) is less than t CLZ(Min.) both for a given device and from device to
device.
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
±
6. Device is continuously selected with /CS=V IL
.
7. Address valid prior to coincident with /CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. /CS=/CS1~4
Issue 5.1 December 1999
PAGE 6
Write Cycle 1
(/OE = Clock)
tWC
Address
/OE
tAW
tWR(5)
tCW(3)
/CS
tAS(4)
tWP(2)
/WE
Data In
tDW
tDH
High Z
Valid Data
tOHZ(6)
High Z(8)
Data Out
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11./CS=/CS1~4
Issue 5.1 December 1999
PAGE 7
Write Cycle 2
(/OE = Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
/CS
/WE
tAS(4)
tWP(2)
tDW
tDH
High Z
Data In
Data Out
Valid Data
tWHZ(6)
tOW
(10)
(9)
High Z(8)
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
6. If OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11./CS=/CS1~4
Issue 5.1 December 1999
PAGE 8
Write Cycle 3
(/CS = Controlled)
tWC
Address
/CS
tAW
tWR(5)
tCW(3)
tAS(4)
tWP(2)
/WE
Data In
tDW
tDH
High Z
High Z
High Z
Valid Data
tLZ
tWHZ(6)
High Z(8)
Data Out
(WRITE CYCLE)
NOTES
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and /WE. A write begins at the latest transition /CS going low and /WE going low ;
A write ends at the earliest transition /CS going high or /WE going high. t WP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. t WR applied in case a write ends as /CS or /WE going high.
6. If /OE, /CS and /WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If /CS goes low simultaneously with /WE going or after /WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When /CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
11/CS=/CS1~4
Data Retention
tSDR
tRDR
Data Retention Mode
/CS Controlled
VCC
3.0V
2.2V
VDR
/CS>VCC - 0.2V
/CS
GND
Note: /CS = /CS1~4
Issue 5.1 December 1999
PAGE 9
PckgDetails
PUMA 68 Pin JEDEC Surface Mount PLCC
25.27 (0.995) sq.
25.02 (0.985) sq.
Pin 1
Pin 68
Top View
5.08
0.90 (0.035) typ.
(0.200) max
0.10 (0.004)
0.46 typ.
(0.018)
1.27 typ.
(0.050)
24.13 (0.950)
23.11 (0.910)
PAGE 10
Issue 5.1 December 1999
Ordering Information
OdegIfrmation
PUMA 68SV16000XLI-015
Speed
012 = 12ns
015 = 15ns
017 = 17ns
Temp. Range/Screening Blank = Commercial
I = Industrial
Power Consumption
Blank = Standard
L = Low Power
Pinout Configuration
Memory Organisation
X = Industry Standard
Pinout
16000 = 512K x 32 configurable
as 1M x 16 and 2M x 8
Technology
Package
SV = SRAM 3.3V+10% VCC
PUMA 68 = 68 pin ‘J’ Leaded PLCC
Note :
Although this data is believed to be accurate the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed without notice.
Products are not authorised for use as critical components in life support devices without the express written
approval of a company director.
PAGE 11
http://www.mosaicsemi.com/
Issue 5.1 December 1999
CtomrGudlines
Co Planarity
Specified as +/- 2 thou max.
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive.
Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH).
After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or
equivalent processing (peak package body temp 220OC) must be :
A : Mounted within 72 Hours at factory conditions of <30OC/60% RH
OR
B : Stored at <20% RH
Iftheseconditionsarenotmetorindicatorcardis>20%whenreadat23OC +/-5% devicesrequirebaking
as specified below.
If baking is required, devices may be baked for :-
A : 24 hours at 125OC +/-5% for high temperature device containers
OR
B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020.
Packaged in trays as standard.
Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection - Ramp Rate
Temp. exceeding 183OC 150 secs. max.
Peak Temperature
225OC
Time within 5OC of peak 20 secs max.
6OC/sec max.
Ramp down
6OC/sec max.
Vapour Phase - Ramp up rate
6OC/sec max.
215 - 219OC
Peak Temperature
Time within 5OC of peak 60 secs max.
Ramp down
6OC/sec max.
The above conditions must not be exceeded
Note : The above recomendations are based on standard industry practice. Failure to comply with
the above recommendations invalidates product warranty.
PAGE 12
Issue 5.1 December 1999
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