SYS161000FKXLI-85 [MOSAIC]

SRAM Module, 1MX16, 85ns, CMOS, PDIP44, PLASTIC, DIP-44;


型号：	SYS161000FKXLI-85
厂家：	MOSAIC
描述：	SRAM Module, 1MX16, 85ns, CMOS, PDIP44, PLASTIC, DIP-44 静态存储器光电二极管内存集成电路
文件：	总7页 (文件大小：120K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

1M x 16 SRAM MODULE

SYS161000FKX - 70/85/10/12

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (619) 674 2233, Fax No: (619) 674 2230

Issue 1.4 : January 1999

Description

Features

•

Access Times of 70/85/100/120 ns.

44 pin DIL Package.

The SYS161000FKX is a plastic 16Mbit Static

RAM Module in a 44 pin DIP package. The module

utilises four 512Kx8 SRAMs housed in TSOPII

packages, surface mounted onto an FR4 epoxy

substrate. The RAMs are organised as two banks

of 512Kx16 each. The upper address line is used

to select one of the two banks, and using LB and

UB as two extra chip select functions for Lower

Byte and Upper Byte control, respectively.

5 Volt Supply ± 10%

Power Dissipation:

Operating

1.20 W (Max.)

Standby -L Version (CMOS) 2.64 mW (Max.)

Completely Static Operation.

•

Low Voltage V_CCData Retention.

On-board Supply Decoupling Capacitors.

Provides upgrade from JEDEC Standard 64Kx16

40 pin modules..

The module is completely asynchronous, static

design requiring no clocks or refreshing.

Block Diagram

Pin Definition

A0 - A18

D8-D15

A17

A16

A15

D15

D14

D13

D12

D11

D10

GND

A19

A18

Vcc

A14

A13

A12

A11

A10

GND

D0 - D7

512K X 8

SRAM

512K X 8 512K X 8 512K X 8

SRAM

11_{TOP VIEW}

A19

DECODER

Pin Functions

Address Inputs

A0 - A19

D0 - D15

Data Input/Output

Chip Select

Write Enable

Package Details

Lower Byte Enable

Upper Byte Enable

Output Enable

Power (+5V)

Plastic 44 Pin Dual-In-Line (DIP)

V_CC

Ground

GND

ISSUE 1.4 January 1999

SYS161000FKX - 70/85/10/12

DC OPERATING CONDITIONS

Absolute Maximum Ratings ⁽¹⁾

Parameter

Symbol

Min

Typ

Max

Unit

Voltage on any pin relative to V_SS

Power Dissipation

V_T⁽²⁾

P_T

-0.3

7.0

2.0

125

^oC

Storage Temperature

T_STG

-55

Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at those or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

(2) V_Tcan be -3.0V pulse of less than 30ns.

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

V_CC

V_IH

V_IL

T_A

4.5

2.2

-0.3

5.0

5.5

V_CC+0.3

0.8

Input High Voltage

Input Low Voltage

Operating Temperature (Commercial)

(Industrial)

^oC

T_AI

-40

DC Electrical Characteristics

(V_CC=5V±10%)

TA 0 to 70 ^oC

Parameter

Symbol Test Condition

Min Typ max Unit

I/P Leakage Current

Address,OE,WE I_LI

0V < V_IN< V_CC

CS = V_IH,V_I/O= GND to V_CC

-4

-2

µA

Output Leakage Current

I_LO

Operating Supply Current 16-bitmode I_CC1Min. Cycle, CS = V_IL,V_IL<V_IN<V_IH

215 mA

Standby Supply Current

TTLlevels I_SB1

CS = V_IH

CMOSlevels I_SB2

CS > V_CC-0.2V, 0.2<V_IN<V_CC-0.2V

-L Version (CMOS) I_SB3

480 mA

Output Voltage

V_OLI_OL= 8.0mA

V_OHI_OH= -4.0mA

0.4

2.4

Typical values are at V_CC=5.0V,T_A=25^oC and specified loading.

Capacitance (V_CC=5V±10%,T_A=25^oC)

Note: Capacitance calculated, not measured.

Parameter

Symbol Test Condition

max

Unit

Input Capacitance (Address,OE,WE)

I/P Capacitance (other)

I/O Capacitance

C_IN1V_IN= 0V

C_IN2V_IN= 0V

C_I/OV_I/O= 0V

SYS161000FKX - 70/85/10/12

ISSUE 1.4 January 1999

AC Test Conditions

Output Load

* Input pulse levels: 0V to 3.0V

* Input rise and fall times: 5ns

* Input and Output timing reference levels: 1.5V

* Output load: see diagram

I/O Pin

Ω

645

1.76V

100pF

* V_CC=5V±10%

Operation Truth Table

DATA PINS

SUPPLY CURRENT

MODE

High Impedance

D_0-15IN

I_SB1, I_SB2, I_SB3, I_SB4

ICC1 / 2

Standby

Write

D_0-15OUT

D_0-15IN

ICC1 / 2

Read

ICC1 / 2

Write

High-Impedance

D_0-7IN

ICC1

High-Z

ICC1 / 2

Write LB

Read LB

Write LB

High-Z

D_0-7OUT

ICC1 / 2

D_0-7IN

ICC1 / 2

High-Impedance

D_8-15IN

ICC1 / 2

Write UB

Read UB

Write UB

High-Z

D_8-15OUT

D_8-15IN

ICC1 / 2

High-Impedance

ICC1 / 2

Notes : H = V_IH: L =V_IL: X = V_IHor V_IL

Low V_ccData Retention Characteristics - L & P Version's Only.

Parameter

Symbol Test Condition

min typ⁽¹⁾max Unit

V_CCfor Data Retention

V_DR

I_CCDR1

t_CDR

t_R

CS>V_CC-0.2V

2.0

(2)

Data Retention Current -L Version

CS High to Data Retention Time

Operation Recovery Time

V_CC=3.0V, V_IN>0, CS>V_CC-0.2V

See Retention Waveform

280 mA

Notes (1) Typical figures are measured at 25°C.

(2) This parameter is guaranteed not tested.

ISSUE 1.4 January 1999

SYS161000FKX - 70/85/10/12

AC OPERATING CONDITIONS

Read Cycle

-70

-85

-10

-12

Parameter

Symbol min max min max min max min max Unit

Read Cycle Time

t_RC

100

120

Address Access Time

t_AA

CS, LB, UB Access Time

t_ACS

t_OE

Output Enable to Output Valid

Output Hold from Address Change

Chip Selection to Output in Low Z

Output Enable to Output in Low Z

Chip Deselection to O/P in High Z

Output Disable to Output in High Z

t_OH

t_CLZ

t_OLZ

t_CHZ

t_OHZ

Write Cycle

-70

-85

-10

-12

Parameter

Symbol min max min max min max min max Unit

Write Cycle Time

t_WC

t_CW

t_AW

t_AS

100

120

CS, LB, UB to End of Write

Address Valid to End of Write

Address Setup Time

Write Pulse Width

t_WP

t_WR

t_WHZ

t_DW

t_DH

Write Recovery Time

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output active from end of write

t_OW

SYS161000FKX - 70/85/10/12

ISSUE 1.4 January 1999

Read Cycle Timing Waveform ^(1,2)

t _RC

Address

t_AA

CS,LB,UB

Dout

t_OE

t_OLZ

t_OH

Don't

care.

t_ACS

t_{CLZ (4,5)}

t_{OHZ (3)}

Data Valid

t_{CHZ (3,4,5)}

AC Read Characteristics Notes

(1) WE is High for Read Cycle.

(2) All read cycle timing is referenced from the last valid address to the first transition address.

(3) t_CHZand t_OHZare defined as the time at which the outputs achieve open circuit conditions and are

not referenced to output voltage levels.

(4) At any given temperature and voltage condition, t_CHZ(max) is less than t_CLZ(min) both for a given module

and from module to module.

(5) These parameters are sampled and not 100% tested.

Write Cycle No.1 Timing Waveform^(1,4)

t_WC

Address

t_WR(7)

t_AS(6)

t_AW

t_CW

CS,LB,UB

Don't

Care

t_OHZ(3,9)

t_OW

t_WP(2)

(8)

High-Z

Dout

Din

t_DW

Data Valid

t_DH

High-Z

ISSUE 1.4 January 1999

SYS161000FKX - 70/85/10/12

Write Cycle No.2 Timing Waveform ^(1,5)

t_WC

Address

t_AS(6)

t_WR(7)

t_CW

CS,LB,UB

t_AW

t_WP(2)

t_OH

Don't

Care

t_WHZ(3,9)

t_OW

(4)

(8)

High-Z

Dout

t_DH

t_DW

High-Z

Din

Data Valid

AC Write Characteristics Notes

(1) All write cycle timing is referenced from the last valid address to the first transition address.

(2) All writes occur during the overlap of CS/LB/UB and WE low.

(3) If OE, CS/LB/UB, and WE are in the Read mode during this period, the I/O pins are low impedance

state. Inputs of opposite phase to the output must not be applied because bus contention can occur.

(4) Dout is the Read data of the new address.

(5) OE is continuously low.

(6) Address is valid prior to or coincident with CS/LB/UB and WE low, too avoid inadvertant writes.

(7) CS/LB/UB or WE must be high during address transitions.

(8) When CS/LB/UB is low : I/O pins are in the output state. Input signals of opposite phase leading to

the output should not be applied.

(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to

output voltage levels. These parameters are sampled and not 100% tested.

Data Retention Waveform

DATA RETENTION MODE

Vcc

4.5V

2.2V

t_CDR

t_R

2.2V

V_DR

CS > Vcc -0.2V

SYS161000FKX - 70/85/10/12

ISSUE 1.4 January 1999

Package Information

Dimensions in mm

Plastic 44 Pin 0.6" Dual-In-Line (DIP)

56.00 MAX

15.92 MAX

15.24 TYP.

2.54 TYP.

Ordering Information

SYS161000FKXLI - 70

Speed

70 = 70 ns

85 = 85 ns

10 = 100 ns

12 = 120 ns

Temperature range

Power Consumption

Blank = Commercial Temp.

I = Industrial Temp.

Blank = Standard Part

L = Low Power Part

Package

FKX = Plastic 44 Pin DIP

161000 = 1M x 16

Organisation

Memory Type

SYS = Static RAM

Note :

Although this data is believed to be accurate the information contained herein is not intended to and does not create

any warranty of merchantibility or fitness for a particular purpose.

Our products are subject to a constant process of development. Data may be changed at any time without notice.

Products are not authorised for use as critical components in life support devices without the express written approval

of a company director.

SYS161000FKXLI-85 [MOSAIC]

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