SYS32128ZKL-015 [MOSAIC]
SRAM Module, 128KX32, 15ns, CMOS, PZIP64, PLASTIC, ZIP-64;
| 型号： | SYS32128ZKL-015 |
| 厂家： | 
MOSAIC |
| 描述： | SRAM Module, 128KX32, 15ns, CMOS, PZIP64, PLASTIC, ZIP-64 静态存储器 内存集成电路 |
| 文件： | 总7页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128K x 32 SRAM MODULE
SYS32128ZK/LK - 010/012/015/017
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.3 : January 1999
Description
Features
TheSYS32128ZK/LKisaplastic4MbitStaticRAM
Module offered in 64 pin ZIP and 64 lead SIMM
packages, organised as 128K x 32. The module
utilises four fast 128kx8 SRAMs housed in SOJ
packages, surface mounted onto an FR4 epoxy
PCB.
•
Access Times of 10/12/15/17 ns.
64 Pin ZIP & SIMM standard pinouts.
5 Volt Supply ± 10%.
•
•
•
Power Dissipation :
Operating (10ns)
Standby (CMOS) -L
5.5 W (maximum).
44mW (maximum).
Fourchipselectsareusedtoindependentlyenable
the four bytes. Reading or Writing is executed on
individual or any combination of multiple bytes.
Two pins PD0 & PD1 are used to identify module
memory density where alternative versions of the
JEDEC standard modules can be interchanged.
•
•
•
•
Completely Static Operation.
Equal Access and Cycle Times.
On-board Supply Decoupling Capacitors.
Data Retention capability. (-L version only).
SIMM
Block Diagram
Pin Definition
1
2
3
4
Gnd
PD0
PD1
D0
ZIP
A0-A16
OE
WE
D8
D1
D9
D2
D10
D3
D11
Vcc
A0
A7
A1
A8
A2
A9
D12
D4
D13
D5
D14
D6
D15
D7
Gnd
WE
A15
A14
CS2
CS1
5
6
7
8
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
GND
PD1
D8
2
4
6
8
PD0
D0
D1
D2
D3
Vcc
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D9
D10
D11
A0
A1
A2
D12
D13
D14
D15
GND
A15
CS2
128kx8
D0-D7
SRAM
10
12
14
16
18
20
22
24
26
28
30
32
CS1
A8
A9
D4
D5
D6
D7
WE
A14
128kx8
D8-D15
SRAM
CS2
128kx8
SRAM
CS4
CS3
NC
A16
OE
Gnd
D24
D16
D25
D17
D26
D18
D27
D19
A3
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
D16-D23
CS1
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
CS4
NC
OE
D24
D25
D26
D27
A3
A4
A5
VCC
A6
D28
D29
D30
D31
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
CS3
A16
GND
D16
D17
D18
D19
A10
A11
A12
A13
D20
D21
D22
D23
GND
CS3
128kx8
D24-D31
SRAM
A10
A4
A11
A5
CS4
A12
Vcc
A13
A6
D20
D28
D21
D29
D22
D30
D23
D31
Gnd
Pin Functions
Address Inputs
Data Input/Output
Chip Selects
A0 - A16
D0 - D31
CS1~4
WE
Write Enable
Output Enable
No Connect
Package Details
OE
NC
Plastic 64 Pin JEDEC ZIP
Plastic 64 Pin JEDEC SIMM
Presence Detect
Power (+5V)
Ground
PD0~1
VCC
GND
1
ISSUE 1.3 January 1999
SYS32128ZK/LK - 010/012/015/017
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
VT
min
-0.5
-
typ
max
+7.0
4.0
unit
V
Voltage on any pin relative to VSS
Power Dissipation
-
-
-
PT
W
oC
Storage Temperature
TSTG
-55
+125
Notes :
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Recommended Operating Conditions
Parameter
Symbol
min
typ
max
unit
Supply Voltage
VCC
VIH
VIL
TA
4.5
2.2
-0.5(2)
5.0
5.5
VCC+0.5
0.8
V
Input High Voltage
Input Low Voltage
Operating Temperature
-
-
-
-
V
V
0
70
oC
oC (I)
TAI
-40
85
(2) VT can be -1.5 V pulse of less than 10 ns.
DC Electrical Characteristics (VCC=5V±10%)
TA 0 to 70OC
Parameter
Symbol Test Condition
min typ max Unit
I/P Leakage Current
ILI
VIN = GND to VCC
CS = VIH, VI/O = GND to VCC
-20
-
20
20
µA
µA
Output Leakage Current
Operating Supply Current
ILO
ICC
-20
-
CS = VIL, min cycle,
10ns
12ns
-
-
-
-
-
-
-
-
-
1000 mA
920 mA
780 mA
720 mA
280 mA
80 mA
V
-
100% duty, II/O=0mA , 15ns
-
17ns
-
Standby Supply Current TTL levels ISB1
-L (CMOS levels) ISB
CS = VIH
-
-
CS = VCC-0.2V, 0.2 > VIN > VCC-0.2V
Output Low Voltage
Output High Voltage
VOL
VOH
IOL = 8.0mA
IOH = -4.0mA
-
0.4
-
2.4
V
Typical values are at VCC=5.0V,TA=25°C and specified loading. All values specified for 32 bit operation.
CS above refers to CS1~4 on the module.
Capacitance (VCC=5V±10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Symbol
Test Condition
typ
max
Unit
Input Capacitance (CS1~4)
Input Capacitance (other)
I/O Capacitance
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
-
-
-
8
32
8
pF
pF
pF
2
SYS32128ZK/LK -010/012/015/017
ISSUE 1.3 January 1999
Operation Truth Table
CS
H
L
OE
X
WE
X
DATA PINS
High Impedance
Data Out
SUPPLY CURRENT
MODE
Standby
Read
ISB1 , ISB2
ICC
L
H
L
X
L
Data In
ICC
Write
L
H
H
High Impedance
ICC
OutputDisabled
Notes : H = VIH : L =VIL : X = VIH or VIL
AC Test Conditions
Output Load
* Input pulse levels: 0 V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
166 O H M S
I/O PIN
1.76V
30pF
* VCC = 5V± 10%
Low VCC Data Retention Characteristics - L Version Only
Parameter
Symbol
VDR
Test Condition
min
typ
max
Unit
VCC for Data Retention
CS>VCC-0.2V
2.0
-
-
-
-
3
V
Data Retention Current ICCDR1
ICCDR2
VCC=2.0V,CS>1.8V,TOP=TA
VCC=3.0V,CS>2.8V,TOP=TAI
-
-
mA
mA
3.5
Chip Deselect to
Data Retention Time
Operation Recovery
Time
tCDR
tR
See Retention Waveform
See Retention Waveform
0
-
-
-
-
ns
ns
(1)
tRC
Notes: (1) tRC=Read Cycle Time
3
ISSUE 1.3 January 1999
SYS32128ZK/LK - 010/012/015/017
AC OPERATING CONDITIONS
(1)
Read Cycle
-010
-012
-015
-017
Parameter
Symbol min max min max min max min max Unit
Read Cycle Time
tRC
10
-
-
10
10
6
12
-
-
12
12
6
15
-
-
15
15
8
17
-
-
17
17
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
Chip Select Access Time
tACS
tOE
-
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
-
-
-
-
tOH
2
0
0
0
0
-
3
0
0
0
0
-
3
0
0
0
0
-
3
0
0
0
0
-
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
-
-
(2)
Chip Deselection to O/P in High Z
6
6
7
8
(2)
Output Disable to Output in High Z
6
6
6
7
Write Cycle
-010
-12
-15
-17
Parameter
Symbol min max min max min max min max Unit
Write Cycle Time
tWC
tCW
tAS
10
9
0
9
7
0
0
6
0
0
-
-
-
-
-
-
6
-
-
-
12
10
0
-
-
-
-
-
-
7
-
-
-
15
12
0
-
-
-
-
-
-
8
-
-
-
17
13
0
-
-
-
-
-
-
9
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
tWHZ
tDW
tDH
10
9
12
12
0
13
13
0
Write Recovery Time
0
(3)
Write to Output in High Z
0
0
0
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
7
8
9
0
0
0
tOW
0
0
0
4
SYS32128ZK/LK -010/012/015/017
ISSUE 1.3 January 1999
(1,2)
Read Cycle Timing Waveform
t RC
Address
OE
tAA
tOE
tOLZ
tOH
CS1~4
Dout
Don't
care.
tACS
tCLZ
tOHZ
Data Valid
tCHZ
(1) WE is High for Read Cycle.
(2) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform (1-10)
tWC
Address
tWR
tAS
OE
tAW
t CW
CS1~4
Don't
Care
WE
tOHZ
tWP
tOW
High-Z
Dout
Din
tDH
tDW
High-Z
5
ISSUE 1.3 January 1999
SYS32128ZK/LK - 010/012/015/017
(1-10)
Write Cycle No.2 Timing Waveform
tWC
Address
tAS
tCW
tWR
CS1~4
tAW
tWP
WE
tOH
Don't
Care
tWHZ
tOW
High-Z
Dout
tDH
tDW
High-Z
Din
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS1~4 and a low WE.
(2) All write cycle timing is referenced from the last valid address to the first transition address.
(3) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output
voltage levels. These parameters are sampled and not 100% tested.
(4) At any given temperature and voltage condition, tWHZ (max) is less than tOW (min) both for a given
module and from module to module.
(5) Module is continuously selected with CS1~4 = VIL.
(6) CS1~4 or WE must be high during address transition.
(7) WE is High for Read Cycle.
(8) All read cycle timing is referenced from the last valid address to the first transition address.
(9) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given
module
and from module to module.
(10) Address is valid prior to or coincident with CS1~4 transition low.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
VDR
tCDR
tR
VIH
VIL
Don't
care
VDR
CS1~4
6
SYS32128ZK/LK -010/012/015/017
ISSUE 1.3 January 1999
Package Information
Dimensions in mm
Plastic 64 Pin Zig-Zag-In-line Package (ZIP)
88.26 Max.
5.85 MAX.
1
4.00
3.20
2.54 Typ.
2.54 Typ.
6.35 Typ.
Plastic 64 Pin Single In-line Memory Module (SIMM)
97.92 Max.
91.03 Typ.
5.59
48.90 Typ.
Ordering Information
SYS32128 ZK/LK LI-010
Speed
010 = 10ns
012 = 12 ns
015 = 15 ns
017 = 17 ns
Temperature range
Blank = Commercial Temp.
I
= Industrial Temp.
Power Consumption
Package
Blank = Standard Part
= Low Power Part
L
ZK = Plastic 64 Pin ZIP
LK = Plastic 64 Pin SIMM
Organisation
Memory Type
32128 = 128K X 32
SYS = Static RAM
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval
of a company director.
7
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