SYS8256RKXLI-70 [MOSAIC]
SRAM Module, 256KX8, 70ns, CMOS, PLASTIC, SIP-32;型号: | SYS8256RKXLI-70 |
厂家: | MOSAIC |
描述: | SRAM Module, 256KX8, 70ns, CMOS, PLASTIC, SIP-32 静态存储器 内存集成电路 |
文件: | 总8页 (文件大小:93K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
256K x 8 SRAM MODULE
SYS8256RKX - 55/70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 2.0 : February 1999
Features
• Access Times of 55/70/85/100/120 ns.
Description
The SYS8256RKX is a plastic 2M Static RAM Module
housed in a standard 32 pin Single In-Line package • 32 Pin Single-In-Line package.
organised as 256K x 8. This offers a very high PCB
packing density, with the possibility of placing the
modules on a 5mm pitch.
• 5 Volt Supply ± 10%.
• Low Power Dissipation:
Average (min cycle) 566 mW (max).
Fast access times of 55 to 85 ns are available as well
Standby (CMOS)
61 mW (max).
as standard times of 100 to 120 ns, with the faster • Completely Static Operation.
modules operating at a slightly higher power
consumption.
• Low Voltage VCC Data Retention.
• Directly TTL Compatible.
The SYS8256RKX is offered as standard and low
power versions, with the -L module having a low
voltage data retention mode.
• On-board Supply Decoupling Capacitors.
Block Diagram
Pin Definition
A0 - A16
D0 - D17
WE
1
2
3
4
5
6
7
8
Vcc
A0
A1
A2
A3
D0
D1
A4
A5
OE
128K X 8
SRAM
128K X 8
SRAM
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A6
A7
A8
A13
D2
CS
CS
CS
A15
A16
A17
A9
GND
OE
A14
D3
CS
A17
DECODER
Pin Functions
D4
D5
Address Inputs
A0 ~ A17
D0 ~ D7
CS
Data Input/Output
Chip Select Input
Read/Write Input
Output Enable Input
Power (+5V)
WE
A10
A11
A12
D6
WE
OE
D7
GND
VCC
Ground
GND
ISSUE 2.0 February 1999
SYS8256RKX - 55/70/85/10/12
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Parameter
Symbol
VT
min typ max
unit
V
Voltage on any pin relative to GND
Power Dissipation
-0.5V
-
-
1.0
-
+7.0
-
PT
W
oC
Storage Temperature
TSTG
-55
+150
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
(2) VT can be -3.5V pulse of less than 20ns.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
min typ max
4.5 5.0 5.5
Unit
V
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
2.2
-0.3
0
-
-
-
-
6.0
0.8
70
V
VIL
V
TA
0C
0C
TAI
-40
85
DC Electrical Characteristics (VCC=5V±10%)
TA 0 to 70OC
Parameter
Symbol Test Condition
min typ max Unit
I/P Leakage Current
O/P Leakage Current
ILI1
ILo
0V - VIN - VCC
CS = VIH, VI/O = GND to Vcc
-
-
-
-
±4
±4
µA
µA
D0~D7
-
Average Supply Current 55/70/85
ICC1 tCYC = 55ns, CS = VIL,
VIN = VIL/VCC-2.1V
55
103 mA
Average Supply Current 10/12/15
ICC2 tCYC = 100ns, CS= VIL,
VIN =VIL/VCC-2.1V
-
45
7
70
11
mA
Standby Supply Current TTL levels ISB
CS = VCC-2.1V, VIL > VIN > VCC-2.1V
-
mA
mA
CMOS levels
ISB1 CS = VCC-0.2V, 0.2 > VIN > VCC-0.2V
ISB2 As above
-
0.05 5
-L part, CMOS levels
-
10
-
300 µA
Output Low Voltage
VOL IOL = 2.1mA
-
0.4
-
V
V
Output High Voltage
VOH IOH = -1.0mA
2.4
-
Typical values are at VCC=5.0V,TA=25°C and specified loading.
2
SYS8256RKX - 55/70/85/10/12
ISSUE 2.0 February 1999
Capacitance (VCC=5V±10%,TA=25°C)
Parameter
Symbol Test Condition
max
8
Unit
pF
Input Capacitance (CS, A17)
Input Capacitance (other)
I/O Capacitance
CIN1
CIN2
CI/O
VIN = 0V
VIN = 0V
VI/O = 0V
12
16
pF
pF
Data Retention Characteristics - L Version Only
Parameter
Symbol
VDR
Test Condition
CS > VCC-0.2V
min typ(1) max
Unit
V
VCC for Data Retention
Data Retention Current
2.0
-
-
VCC = 3.0V, CS > VCC-0.2V
TOP = 0°C to 40°C
TOP = TA
(2)
ICCDR1
-
5
5
-
100
150(3)
TBA
-
µA
µA
µA
ns
ICCDR2
ICCDR3
tCDR
-
TOP = TAI
-
Chip Deselect to
See Retention Waveform
0
-
Data Retention Time
Operation Recovery Time
tR
See Retention Waveform
5
-
-
ms
Notes
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
(3) Maximum figure at 70OC
AC Test Conditions
Output Load
I/O Pin
645Ω
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
1.76V
100pF
* VCC=5V±10%
3
ISSUE 2.0 February 1999
SYS8256RKX - 55/70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
-55
-70
-85
Parameter
Symbol min max min max min max Unit
Read Cycle Time
tRC
55
-
-
70
-
-
85
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
55
55
30
-
70
70
35
-
85
85
55
-
Chip Select Access Time
tACS
tOE
-
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z (2)
Output Enable to Output in Low Z (2)
Chip Deselection to O/P in High Z (2)
Output Disable to Output in High Z (2)
-
-
-
tOH
5
5
5
0
0
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
-
-
20
20
0
25
25
0
30
30
0
0
Read Cycle
-10
-12
Parameter
Symbol min max min max Unit
Read Cycle Time
tRC
100
-
-
100
100
60
-
120
-
-
ns
Address Access Time
tAA
120 ns
120 ns
Chip Select Access Time
tACS
tOE
-
-
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z (2)
Output Enable to Output in Low Z (2)
Chip Deselection to O/P in High Z (2)
Output Disable to Output in High Z (2)
-
-
70
-
ns
ns
ns
ns
ns
ns
tOH
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
-
-
-
-
0
35
35
0
45
45
0
0
4
SYS8256RKX - 55/70/85/10/12
ISSUE 2.0 February 1999
Write Cycle
-55
-70
-85
Parameter
Symbol min max min max min max Unit
Write Cycle Time
tWC
tCW
tAW
tAS
55
50
50
0
-
-
-
-
-
-
0
-
-
-
70
60
60
0
-
-
85
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
40
0
50
0
-
65
5
-
Write Recovery Time
-
-
Write to Output in High Z (11)
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write (10)
02
30
0
0
25
-
0
30
-
35
0
35
0
-
-
tOW
5
5
-
5
-
Write Cycle
-10
-12
Parameter
Symbol min max min max Unit
Write Cycle Time
tWC
tCW
tAW
tAS
100
90
90
0
-
-
120
100
100
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
-
-
-
-
Write Pulse Width
tWP
tWR
tWHZ
tDW
tDH
75
5
-
85
10
0
-
Write Recovery Time
-
-
Write to Output in High Z (11)
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write (10)
0
35
-
40
-
40
0
45
0
-
-
tOW
5
-
5
-
5
ISSUE 2.0 February 1999
SYS8256RKX - 55/70/85/10/12
Read Cycle Timing Waveform
t RC
Address
OE
tAA
tOE
tOLZ
tOH
CS
Don't
care.
tACS
tCLZ
tOHZ
Dout
Data Valid
tCHZ
Notes (1) WE is High for Read Cycle.
(2) tHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
tWC
Address
tWR(4)
tAS(3)
OE
tAW
t CW(2)
(6)
CS
Don't
Care
WE
tOHZ(5)
tWP(1)
tOW
High-Z
Dout
Din
tDH
tDW
High-Z
6
SYS8256RKX - 55/70/85/10/12
ISSUE 2.0 February 1999
Write Cycle No.2 Timing Waveform
tW C
Address
t A S (3)
t C W
(2)
tW R (4)
C S
tA W
tW P (1)
W E
D out
D in
tO H
D on't
C are
(8)
t W H Z (5)
t O W
(7)
H igh-Z
tD H
tD W
H igh-Z
(9)
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tCW is measured from the earlier of CS or WE going high to the end of write cycle.
(3) tAS is measured from the address valid to the beginning of write.
(4) tWR is measured from the earliest of CS or WE going high to the end of write.
(5) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(6) If CS goes low simultaneously with WE going low or after WE going low , outputs remain in a high
impedance state.
(7) DOUT is in the same phase as written data of this write cycle.
(8) DOUT is the read data of next address.
(9) If CS is low during this period, I/O pins are in the output state, and inputs out of phase must not be
applied to I/O pins.
(10) This parameter is sampled and not 100% tested.
(11) tWHZ isdefinedasthetimeatwhichtheoutputsachieveopencircuitconditionsandisnotreferencedtooutput
voltage levels. This parameter is sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
2.2V
tCDR
tR
2.2V
VDR
CS > Vcc -0.2V
CS
0V
7
ISSUE 2.0 February 1999
SYS8256RKX - 55/70/85/10/12
Package Information
32 Pin SIP
5.50 MAX
82.63 MAX
U1
M1
C1
M2
C2
3.50 +/- 0.50
2.54 TYP.
0.50 TYP.
Dimensions in mm
Ordering Information
SYS8256RKXLI - 10
Speed
55 = 55 ns (Commercial only)
70 = 70 ns
85 = 85 ns
10 = 100 ns
12 = 120 ns
Temperature Range
Power Consumption
Blank = Commercial Temperature
I = Industrial Temperature
Blank = Standard Part
L = Low Power Part
Package
RKX = Plastic 32 pin SIL
8256 = 256K x 8
Organization
Memory Type
SYS = Static RAM
I-55 parts are not available at present
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create
any warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at an time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
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