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SYS8512FK-20 [MOSAIC]

SRAM Module, 512KX8, 20ns, CMOS, PDIP32, PLASTIC, DIP-32;
SYS8512FK-20
型号： SYS8512FK-20
厂家： MOSAIC    MOSAIC
描述：

SRAM Module, 512KX8, 20ns, CMOS, PDIP32, PLASTIC, DIP-32

静态存储器 光电二极管 内存集成电路
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中文：  中文翻译
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512K x 8 SRAM MODULE  
SYS8512FK-20/25/35/45  
11403 West Bernado Court, Suite 100, San Diego, CA 92127.  
Tel No: (619) 674 2233, Fax No: (619) 674 2230  
Issue 5.0 : November 1999  
Description  
Features  
•
•
Access Times of 20/25/35/45 ns.  
The SYS8512FK is plastic 4M Static RAM Module  
housed in a standard 32 pin Dual-In-Line package  
organised as 512K x 8. The module utilises fast  
256Kx4 SRAMs housed in SOJ packages, and  
uses double sided surface mount techniques to  
achieve a very high density module.  
32 Pin 0.6" Dual-In-Line package with  
JEDEC compatible pinout.  
•
•
5 Volt Supply ± 10%.  
Low Power Dissipation:  
Average (min cycle)  
Standby -L (CMOS)  
2.42W (maximum).  
44mW (maximum).  
The module has Chip Select, Write Enable and  
Output Enable control inputs; the Output Enable  
pinallowsfasteraccesstimesthanaddressaccess  
during a Read Cycle.  
•
•
•
•
Completely Static Operation.  
Equal Access and Cycle Times.  
All Inputs and Outputs Directly TTL Compatible  
On-board Supply Decoupling Capacitors.  
A0 - A17  
D0 - D7  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A18  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
D0  
D1  
D2  
VCC  
A15  
A17  
WE  
A13  
A8  
WE  
OE  
256K X 4  
SRAM  
256K X 4  
SRAM  
256K X 4  
SRAM  
256K X 4  
SRAM  
A9  
A11  
OE  
A10  
CS  
D7  
D6  
D5  
D4  
D3  
CS  
CS  
CS  
CS  
9
10  
11  
12  
13  
14  
15  
16  
CS  
DECODER  
A18  
Pin Functions  
GND  
Address Inputs  
Data Input/Output  
Chip Select  
A0 - A18  
D0 - D7  
CS  
Package Details  
Write Enable  
Output Enable  
Power (+5V)  
Ground  
WE  
OE  
Plastic 32 pin 0.6" Jedec DIP  
VCC  
GND  
ISSUE 5.0 November 1999  
SYS8512FK-20/25/35/45  
DC OPERATING CONDITIONS  
Absolute Maximum Ratings (1)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Voltage on any pin relative to VSS  
Power Dissipation  
VT(2)  
PT  
-0.3  
-
-
2.5  
-
7.0  
-
V
W
oC  
Storage Temperature  
TSTG  
-55  
125  
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at those or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
(2) VT can be -2.0V pulse of less than 10ns.  
Recommended Operating Conditions  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Supply Voltage  
VCC  
VIH  
VIL  
TA  
4.5  
2.2  
-0.3  
0
5.0  
5.5  
VCC+0.3  
0.8  
V
V
Input High Voltage  
Input Low Voltage  
Operating Temperature  
-
-
-
-
V
(Commercial)  
(Industrial)  
70  
oC  
oC  
TAI  
-40  
85  
DC Electrical Characteristics (VCC=5V±10%)  
TA 0 to 70 oC  
Parameter  
Symbol Test Condition  
Min Typ max Unit  
I/P Leakage Current Address,OE,WE ILI  
0V < VIN < VCC  
CS = VIH, VI/O = GND to VCC  
ICC1 Min. Cycle, CS = VIL,VIL<VIN<VIH  
-8  
-
-
-
-
-
-
-
-
8
µA  
µA  
Output Leakage Current  
Operating Supply Current  
Standby Supply Current  
ILO  
-40  
40  
-
440 mA  
246 mA  
TTL levels ISB1  
CMOS levels ISB2  
-L Version (CMOS) ISB3  
CS = VIH  
-
-
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V  
CS > VCC-0.2V, 0.2<VIN<VCC-0.2V  
60  
8
mA  
mA  
V
-
Output Voltage  
VOL IOL = 8.0mA  
VOH IOH = -4.0mA  
-
0.4  
-
2.4  
V
Typical values are at VCC=5.0V,TA=25oC and specified loading.  
Capacitance (VCC=5V±10%,TA=25oC)  
Note: Capacitance calculated, not measured.  
Parameter  
Symbol Test Condition  
max  
Unit  
Input Capacitance (Address,OE,WE)  
I/P Capacitance (other)  
I/O Capacitance  
CIN1 VIN = 0V  
CIN2 VIN = 0V  
CI/O VI/O = 0V  
32  
8
pF  
pF  
pF  
32  
2
SYS8512FK-20/25/35/45  
ISSUE 5.0 November 1999  
AC Test Conditions  
Output Load  
* Input pulse levels: 0V to 3.0V  
* Input rise and fall times: 5ns  
* Input and Output timing reference levels: 1.5V  
* Output load: see diagram  
I/O Pin  
Ω
645  
1.76V  
100pF  
* VCC=5V±10%  
Operation Truth Table  
CS  
H
L
OE  
X
WE  
X
DATA PINS  
High Impedance  
Data Out  
SUPPLY CURRENT  
MODE  
Standby  
Read  
ISB1 , ISB2 , ISB3  
ICC1  
L
H
L
H
L
L
Data In  
ICC1  
Write  
L
L
Data In  
ICC1  
Write  
L
H
H
High-Impedance  
ISB1 , ISB2 , ISB3  
High-Z  
Notes : H = VIH : L =VIL : X = VIH or VIL  
Low Vcc Data Retention Characteristics - L Version Only  
Parameter  
Symbol  
VDR  
Test Condition  
CS > VCC-0.2V  
min  
2.0  
typ(1) max  
Unit  
V
VCC for Data Retention  
Data Retention Current  
-
-
VCC = 3.0V, CS > VCC-0.2V  
TOP = 0 to 70OC  
ICCDR2  
tCDR  
tR  
-
-
-
-
2
-
mA  
ns  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
See Retention Waveform  
See Retention Waveform  
0
5
-
ms  
Notes (1) Typical figures are measured at 25°C.  
(2) This parameter is guaranteed not tested.  
3
ISSUE 5.0 November 1999  
SYS8512FK-20/25/35/45  
AC OPERATING CONDITIONS  
Read Cycle  
-20  
-25  
-35  
-45  
Parameter  
Symbol min max min max min max min max Unit  
Read Cycle Time  
tRC  
20  
-
-
25  
-
-
35  
-
-
45  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
tAA  
20  
20  
10  
-
25  
25  
13  
-
35  
35  
15  
-
45  
45  
20  
-
Chip Select Access Time  
tACS  
tOE  
-
-
-
-
Output Enable to Output Valid  
Output Hold from Address Change  
Chip Selection to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to O/P in High Z  
Output Disable to Output in High Z  
-
-
-
-
tOH  
3
0
0
0
0
3
0
0
0
0
3
0
0
0
0
3
0
0
0
0
tCLZ  
tOLZ  
tCHZ  
tOHZ  
-
-
-
-
-
-
-
-
12  
10  
15  
12  
15  
20  
20  
20  
Write Cycle  
-20  
-25  
-35  
-45  
Parameter  
Symbol min max min max min max min max Unit  
Write Cycle Time  
tWC  
tCW  
tAW  
tAS  
20  
17  
17  
0
-
-
25  
20  
20  
0
-
-
35  
30  
30  
0
-
-
45  
40  
40  
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Setup Time  
-
-
-
-
-
-
-
-
Write Pulse Width  
tWP  
tWR  
tWHZ  
tDW  
tDH  
15  
3
-
20  
3
-
30  
3
-
30  
3
-
Write Recovery Time  
-
-
-
-
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output active from end of write  
0
12  
-
0
15  
-
0
15  
-
0
15  
-
12  
0
15  
0
20  
0
25  
0
-
-
-
-
tOW  
0
-
0
-
0
-
0
-
4
SYS8512FK-20/25/35/45  
ISSUE 5.0 November 1999  
Read Cycle Timing Waveform(1,2)  
t RC  
Address  
OE  
tAA  
tOE  
tOLZ  
tOH  
CS  
Don't  
care.  
tACS  
tOHZ (3)  
tCLZ (4,5)  
Dout  
Data Valid  
tCHZ (3,4,5)  
AC Read Characteristics Notes  
(1) WE is High for Read Cycle.  
(2) All read cycle timing is referenced from the last valid address to the first transition address.  
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not  
referenced to output voltage levels.  
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module  
and from module to module.  
(5) These parameters are sampled and not 100% tested.  
Write Cycle No.1 Timing Waveform(1,4)  
tWC  
Address  
tWR(7)  
tAS(6)  
OE  
tAW  
tCW  
CS  
Don't  
Care  
WE  
tOHZ(3,9)  
tOW  
tWP(2)  
(8)  
High-Z  
Dout  
Din  
tDW  
Data Valid  
tDH  
High-Z  
5
ISSUE 5.0 November 1999  
SYS8512FK-20/25/35/45  
Write Cycle No.2 Timing Waveform (1,5)  
tWC  
Address  
tAS(6)  
tWR(7)  
tCW  
CS  
tAW  
tWP(2)  
WE  
tOH  
Don't  
Care  
tWHZ(3,9)  
tOW  
(4)  
(8)  
High-Z  
tDW  
Data Valid  
Dout  
tDH  
High-Z  
Din  
AC Write Characteristics Notes  
(1) All write cycle timing is referenced from the last valid address to the first transition address.  
(2) All writes occur during the overlap of CS and WE low.  
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.  
Inputs of opposite phase to the output must not be applied because bus contention can occur.  
(4) Dout is the Read data of the new address.  
(5) OE is continuously low.  
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.  
(7) CS or WE must be high during address transitions.  
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the  
output should not be applied.  
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to  
output voltage levels. These parameters are sampled and not 100% tested.  
Data Retention Waveform  
DATA RETENTION MODE  
Vcc  
4.5V  
4.5V  
2.2V  
tCDR  
tR  
2.2V  
VDR  
CS > Vcc -0.2V  
CS  
0V  
6
SYS8512FK-20/25/35/45  
ISSUE 5.0 November 1999  
Package Information  
(Dimensions in Millimetres)  
Plastic 32 Pin 0.6" Dual-in-Line  
41.28 MAX  
15.92 MAX  
2.54 TYP.  
15.24 TYP.  
Ordering Information  
SYS8512FKLI-20  
Speed  
20 = 20 ns  
25 = 25 ns  
35 = 35 ns  
45 = 45 ns  
Temperature Range  
Power Consumption  
Blank = Commercial Temperature  
I = Industrial Temperature  
Blank = Standard Part  
L = Low Power Part  
Package  
FK = Plastic 32 Pin 0.6" DIP  
8512 = 512K x 8  
Organization  
Memory Type  
SYS = Static RAM  
Note :  
Although this data is believed to be accurate the information contained herein is not intended to and does not create  
any warranty of merchantibility or fitness for a particular purpose.  
Our products are subject to a constant process of development. Data may be changed without notice.  
Products are not authorised for use as critical components in life support devices without the express written  
approval of a company director.  

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