V53C317405A60 [MOSEL]
4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM; 4M X 4 EDO页模式的CMOS动态RAM
| 型号： | V53C317405A60 |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM |
| 文件： | 总24页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
V53C317405A
MO SEL VITELIC
4M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C317405A
50
60
Max. RAS Access Time, (t
)
50 ns
25 ns
20 ns
84 ns
60 ns
30 ns
25 ns
104 ns
RAC
Max. Column Address Access Time, (t
)
CAA
Min. Extended Data Out Page Mode Cycle Time, (t
)
PC
Min. Read/Write Cycle Time, (t
)
RC
Features
Description
■ 4M x 4-bit organization
The V53C317405A is a 4,194,304 x 4 bit high-
performance CMOS dynamic random access
memory. The V53C317405A offers Page mode
operation with Extended Data Output. The
V53C317405A has a symmetric address, 11-bit row
and 11-bit column.
■ EDO Page Mode for a sustained data rate
of 50 MHz
■ RAS access time: 50, 60, 70 ns
■ Low power dissipation
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
■ Refresh Interval: 2048 cycles/32 ms
■ Available in 24/26-pin 300 mil SOJ,
and 24/26-pin 300 mil TSOP-II
■ Single +3.3 V ±10% Power Supply
■ TTL Interface
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 2048 x 4 bits,
within a page, with cycle times as short as 20ns.
These features make the V53C317405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
50
60
Std.
0°C to 70°C
•
•
•
•
•
Blank
V53C317405A Rev. 0.2 September 1998
1
MO SEL VITELIC
V53C317405A
Pin Names
24/26 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
A –A
Row, Column Address Inputs
0
10
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Write Enable
VCC
I/O1
I/O2
WE
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O4
I/O3
CAS
OE
OE
Output Enable
Data Input, Output
+3.3V Supply
I/O –I/O
1
4
RAS
NC
V
A9
CC
V
0V Supply
SS
A10
A0
A1
A2
A3
A8
A7
A6
A5
A4
VSS
8
19
18
17
16
15
14
NC
No Connect
9
10
11
12
13
Description Pkg.
Pin Count
24/26
VCC
SOJ
K
T
511740502-02
TSOP-II
24/26
V53C317405A Rev. 0.2 September 1998
2
MO SEL VITELIC
V53C317405A
Absolute Maximum Ratings*
Capacitance*
Operating temperature range ..................0 to 70 °C
Storage temperature range ............... -55 to 150 °C
T = 25°C, V = 3.3 V ± 10%, V = 0 V, f = 1 MHz
A
CC
SS
Min.
—
Symbol Parameter
Max. Unit
Input/output voltage.... -0.5 to min (V +0.5, 4.6) V
CC
C
C
C
Address Input
5
7
7
pF
pF
pF
Power supply voltage .........................-1.0V to 4.6V
Power dissipation .......................................... 0.5 W
Data out current (short circuit)...................... 50 mA
IN1
RAS, CAS, WE, OE
Data Input/Output
—
IN2
—
OUT
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
4096 x 4
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
Data Out
Buffer
OE
4
WE
4
CAS
No. 2 Clock
Generator
11
Column
Address
Buffers (11)
11
Column
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Refresh
Controller
4
Sense Amplifier
I/O Gating
Refresh
Counter (11)
2048
x4
11
11
Row
11
Row
Decoder
Memory Array
2048 x 2048 x 4
Address
2048
Buffers (11)
No. 1 Clock
Generator
RAS
VCC
VCC (internal)
Voltage Down
Generator
511740500-03
V53C317405A Rev. 0.2 September 1998
3
MO SEL VITELIC
V53C317405A
DC and Operating Characteristics (1-2)
T = 0°C to 70°C, V = 3.3 V ± 10%, V = 0 V, t = 2ns, unless otherwise specified.
A
CC
SS
T
V53C317405A
Access
Symbol
Parameter
Time
Min.
Typ.
Max.
Unit
Test Conditions
Notes
I
Input Leakage Current
(any input pin)
–10
10
mA
V
V
£ V £ V + 0.5V
1
LI
SS
SS
IN
CC
I
Output Leakage Current
(for High-Z State)
–10
10
mA
£ V
£ V + 0.5V
1
LO
OUT
CC
RAS, CAS at V
IH
other input ³ V
SS
I
V
Supply Current,
50
60
120
110
2
mA
t
= t (min.)
2, 3, 4
CC1
CC
RC
RC
Operating
I
I
V
Supply Current,
mA
mA
RAS, CAS at V
IH
CC2
CC
TTL Standby
other inputs ³ V
SS
V
Supply Current,
50
60
50
60
120
110
70
t
= t (min.)
2, 4
CC3
CC
RC
RC
RAS-Only Refresh
I
I
I
V
Supply Current,
mA
mA
mA
Minimum Cycle
2, 3, 4
CC4
CC5
CC6
CC
EDO Page Mode
Operation
55
V
Supply Current,
50
60
120
110
2, 4
1
CC
during CAS-before-RAS
Refresh
V
Supply Current,
1.0
RAS ³ V – 0.2 V,
CC
CC
CMOS Standby
CAS ³ V – 0.2 V
CC
other input ³ V
SS
V
V
V
V
V
Power Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
3.0
–0.5
2.0
3.3
3.6
0.8
V
V
V
V
V
CC
1
1
1
1
IL
V
+0.5
CC
IH
0.4
—
I
I
= 2 mA
OL
OH
OL
2.4
= –2 mA
OH
V53C317405A Rev. 0.2 September 1998
4
MO SEL VITELIC
V53C317405A
(5, 6)
AC Characteristics
T = 0 to 70 ˚C,V = 3.3 V ± 10 %, t = 2 ns
A
CC
T
-50
-60
#
Symbol
Parameter
min.
max.
min.
max. Unit Note
Common Parameters
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read or write cycle time
RAS precharge time
84
30
50
8
–
–
104
40
60
10
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
RC
RP
3
RAS pulse width
10k
10k
–
10k
10k
–
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
T
4
CAS pulse width
5
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
0
6
8
–
10
0
–
7
0
–
–
8
8
–
10
14
12
15
50
5
–
9
12
10
13
40
5
37
25
45
30
–
10
11
12
13
14
15
CAS hold time
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
1
50
32
1
50
32
7
–
–
REF
Read Cycle
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Access time from RAS
–
–
50
13
25
13
–
–
–
60
15
30
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8, 9
8, 9
8,10
RAC
CAC
CAA
OEA
RAL
RCS
RCH
RRH
CLZ
Access time from CAS
Access time from column address
OE access time
–
–
–
–
Column address to RAS lead time
Read command setup time
Read command hold time
Read command hold time referenced to RAS
CAS to output in low-Z
25
0
30
0
–
–
0
–
0
–
11
11
8
0
–
0
–
0
–
0
–
Output buffer turn-off delay
Output turn-off delay from OE
Data to CAS low delay
0
13
13
–
0
15
15
–
12
12
13
13
14
14
OFF
OEZ
DZC
DZO
CDD
ODD
0
0
0
0
Data to OE low delay
0
–
0
–
CAS high to data delay
10
10
–
13
13
–
OE high to data delay
–
–
V53C317405A Rev. 0.2 September 1998
5
MO SEL VITELIC
V53C317405A
(5, 6)
AC Characteristics
T = 0 to 70 ˚C,V = 3.3 V ± 10 %, t = 2 ns
A
CC
T
-50
-60
#
Symbol
Parameter
min.
max.
min.
max. Unit Note
Write Cycle
31
32
33
34
35
36
37
t
t
t
t
t
t
t
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
8
8
0
8
8
0
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
WCH
WP
15
WCS
RWL
CWL
DS
10
10
0
16
16
Data hold time
10
DH
Read-modify-Write Cycle
38
39
40
41
42
t
t
t
t
t
Read-write cycle time
113
64
27
39
10
–
–
–
–
–
138
77
32
47
13
–
–
–
–
–
ns
ns
ns
ns
ns
RWC
RWD
CWD
AWD
OEH
RAS to WE delay time
15
15
15
CAS to WE delay time
Column address to WE delay time
OE command hold time
EDO Page Mode Cycle
43
44
45
46
47
48
49
t
t
t
t
t
t
t
EDO page mode cycle time
CAS precharge time
20
8
–
–
25
10
–
–
–
ns
ns
ns
ns
ns
ns
ns
PC
CP
Access time from CAS precharge
Output data hold time
–
27
–
32
–
7
CPA
COH
RASP
RHPC
OES
5
5
RAS pulse width in EDO mode
CAS precharge to RAS Delay
OE setup time prior to CAS
50
27
5
200k
–
60
32
5
200k
–
–
EDO Page Mode Read-modify-Write Cycle
50
51
t
t
EDO page mode read-write cycle time
CAS precharge to WE
58
41
–
–
68
49
–
–
ns
ns
PRWC
CPWD
CAS-before-RAS Refresh Cycle
52
53
54
55
56
t
t
t
t
t
CAS setup time
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CSR
CHR
RPC
WRP
WRH
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
V53C317405A Rev. 0.2 September 1998
6
MO SEL VITELIC
V53C317405A
(5, 6)
AC Characteristics
T = 0 to 70 ˚C,V = 3.3 V ± 10 %, t = 2 ns
A
CC
T
-50
-60
#
Symbol
Parameter
min.
max.
min.
max. Unit Note
CAS-before-RAS Counter Test Cycle
57
t
CAS precharge time
35
–
40
–
ns
CPT
Test Mode
61
62
63
64
t
t
t
t
Write command setup time
Write command hold time
CAS hold time
10
10
30
30
–
–
–
–
10
10
30
30
–
–
–
–
ns
ns
ns
ns
WTS
WTH
CHRT
RAHT
RAS hold time in test mode
V53C317405A Rev. 0.2 September 1998
7
MO SEL VITELIC
V53C317405A
Notes:
1) All voltages are referenced to V
.
SS
2)
3)
I
I
, I
, I
and I
depend on cycle rate.
CC1 CC3 CC4
CC5
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
4) Address can be changed once or less while RAS = V . In case of I
it can be changed once or less during a EDO
IL
CC4
page mode cycle
5) An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum
of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume t = 2 ns.
T
7)
V
and V
are reference levels for measuring timing of input signals. Transition times are also measured
IH (min.)
IL (max.)
between V and V .
IH
IL
8) Measured with the specified current load and 100 pF at V = 0.8 V and V = 2.0 V. Access time is determined
OL
OH
by the latter of t
, t
, t
,t
, t
. t
is measured from tristate.
RAC CAC CAA CPA OEA CAC
9) Operation within the t
limit ensures that t
can be met. t
is specified as a reference point
RCD (max.)
RAC (max.)
RCD (max.)
only. If t
is greater than the specified t
limit, then access time is controlled by t
.
RCD
RCD (max.)
CAC
10) Operation within the t
limit ensures that t
can be met. t
is specified as a reference point
RAD (max.)
RAC (max.)
RAD (max.)
only. If t
is greater than the specified t
limit, then access time is controlled by t
.
RAD
RAD (max.)
CAA
11) Either t
12)
or t
must be satisfied for a read cycle.
RCH
RRH
t
, t
define the time at which the output achieves the open-circuit conditions and are not referenced
OFF (max.) OEZ (max.)
to output voltage levels. t
is referenced from the rising edge of RAS or CAS, whichever occurs last.
OFF
13) Either t
14) Either t
or t
must be satisfied.
must be satisfied.
DZC
CDD
DZO
or t
ODD
15)
t
, t
, t
and t
are not restrictive operating parameters. They are included in the data sheet as electri-
AWD
WCS RWD CWD
cal characteristics only. If t
> t
, the cycle is an early write cycle and data out pin will remain open-circuit
WCS
WCS (min.)
(high impedance) through the entire cycle; if t
> t
, t
> t
and t
> t
, the cycle
AWD (min.)
RWD
RWD (min.) CWD
CWD (min.)
AWD
is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions
is satisfied, the condition of I/O (at access time) is indeterminate.
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
V53C317405A Rev. 0.2 September 1998
8
MO SEL VITELIC
V53C317405A
Waveforms of Read Cycle
t
RC
t
t
RAS
RP
V
IH
RAS
V
IL
t
CSH
t
CRP
t
t
t
RCD
RSH
CAS
V
IH
CAS
V
IL
t
RAD
t
RAL
t
t
CAH
ASR
t
t
ASR
ASC
V
IH
Column
Row
Row
Address
V
IL
t
RCH
t
t
RAH
RCS
t
RRH
V
IH
WE
OE
V
IL
t
CAA
t
OEA
V
IH
V
IL
t
t
DZC
CDD
t
ODD
t
DZO
V
IH
I/O
(Inputs)
V
IL
t
CAC
t
OFF
t
OEZ
t
CLZ
V
OH
I/O
Hi Z
Valid Data Out
Hi Z
(Outputs)
V
OL
t
RAC
“H” or “L”
WL1
V53C317405A Rev. 0.2 September 1998
9
MO SEL VITELIC
V53C317405A
Waveforms of Write Cycle (Early Write)
t
RC
t
t
RP
RAS
V
IH
RAS
CAS
V
IL
t
CSH
t
t
t
RCD
CRP
RSH
V
IH
t
CAS
V
IL
t
t
RAL
RAD
t
t
CAH
ASR
t
ASR
t
ASC
.
V
IH
Column
Row
Row
Address
V
IL
t
CWL
t
RAH
t
WCS
t
V
WP
IH
WE
OE
V
IL
t
WCH
t
RWL
V
IH
V
IL
t
DH
t
DS
V
IH
I/O
Valid Data In
(Inputs)
V
IL
V
OH
I/O
Hi Z
(Outputs)
V
OL
“H” or “L”
WL2
V53C317405A Rev. 0.2 September 1998
10
MO SEL VITELIC
V53C317405A
Waveforms of Write Cycle (OE Controlled Write)
t
RC
t
t
RP
RAS
V
IH
RAS
V
IL
t
CSH
t
t
t
CRP
RCD
RSH
V
IH
t
CAS
CAS
V
IL
tRAD
tASC
tRAL
tCAH
tASR
tASR
V
IH
Row
Column
Row
Address
V
IL
tCWL
tRWL
tRAH
tWP
V
IH
WE
OE
V
IL
t
OEH
V
IH
t
ODD
V
IL
t
DH
t
DZO
t
DS
t
DZC
t
OEZ
V
IH
I/O
Valid Data
(Inputs)
V
IL
t
CLZ
t
OEA
V
OH
Hi-Z
I/O
Hi-Z
V
(Outputs)
OL
WL3
“H” or “L”
V53C317405A Rev. 0.2 September 1998
11
MO SEL VITELIC
V53C317405A
Waveforms of Read-Write (Read-Modify-Write) Cycle
t
RWC
t
t
RAS
RP
V
IH
V
IL
RAS
t
CSH
t
t
RCD
RSH
t
CRP
t
CAS
V
IH
V
CAS
IL
t
t
CAH
RAH
t
ASR
t
t
ASC
ASR
V
IH
Address
Row
Column
Row
V
IL
t
CWL
t
AWD
t
RAD
t
CWD
t
RWL
t
RWD
t
WP
V
IH
WE
OE
V
IL
t
CAA
t
t
OEA
t
t
RCS
OEH
DS
V
IH
V
IL
t
DZO
t
DZC
t
DH
V
IH
Valid
Data in
I/O
(Inputs)
V
IL
t
t
CLZ
t
ODD
CAC
t
OEZ
V
V
OH
OL
I/O
(Outputs)
Data
Out
tRAC
“H” or “L”
WL4
V53C317405A Rev. 0.2 September 1998
12
MO SEL VITELIC
V53C317405A
Waveforms of EDO Page Mode Read Cycle
tRP
t
RASP
VIH
t
t
RHPC
RCD
RAS
VIL
t
RSH
t
t
CRP
PC
t
CRP
t
t
CAS
t
t
CP
CAS
CAS
VIH
VIL
CAS
t
CRH
t
RAL
t
t
t
t
CAH
t
t
CAH
RAH ASC
ASC
t
CAH
ASC
t
ASR
VIH
VIL
Address
Row
Column 2
Column N
Column 1
t
RAD
t
RRH
t
RCS
t
RCH
VIH
VIL
WE
t
t
CAC
CAC
t
t
CAA
CPA
CAA
t
CPA
t
t
t
OES
OFF
t
OEA
VOH
VOL
OE
t
RAC
t
t
OEZ
CAA
t
t
t
COH
CAC
COH
t
CLZ
VIH
VIL
I/O
(Output)
Data Out
1
Data Out
2
Data Out
N
WL5
“H” or “L”
V53C317405A Rev. 0.2 September 1998
13
MO SEL VITELIC
V53C317405A
Waveforms of EDO Page Mode Early Write Cycle
t
RP
t
RASP
VIH
VIL
t
t
RCD
RHPC
RAS
t
t
CRP
RSH
t
PC
t
CRP
t
t
t
t
CAS
CAS
CAS
CP
VIH
VIL
CAS
t
t
RAL
CSH
t
t
t
RAH
t
t
t
CAH
ASC
CAH
t
ASC
ASC
t
CAH
ASR
VIH
VIL
Row
Addr
Address
Column 1
t
Column 2
t
Column N
t
t
RAD
RWL
CWL
CWL
t
CWL
t
WCS
t
t
WCS
WCS
t
WCH
t
t
t
WCH
WP
WCH
t
t
WP
WP
VIH
VIL
WE
VOH
VOL
OE
t
t
DH
t
DS
t
DS
t
DH
t
DS
DH
VIH
VIL
Data In 1
Data In 2
Data In N
I/O (Input)
“H” or “L”
WL8
V53C317405A Rev. 0.2 September 1998
14
MO SEL VITELIC
V53C317405A
Waveforms of EDO Page Mode Late Write and Read-Modify-Write Cycle
DO
t
WL17
V53C317405A Rev. 0.2 September 1998
15
MO SEL VITELIC
V53C317405A
Waveforms of RAS Only Refresh Cycle
t
RC
t
t
RP
RAS
VIH
RAS
VIL
t
t
CRP
t
RPC
VIH
VIL
CAS
t
RAH
ASR
t
ASR
VIH
VIL
Address
Row
Row
VOH
VOL
I/O
(Outputs)
HI-Z
“H” or “L”
WL9
V53C317405A Rev. 0.2 September 1998
16
MO SEL VITELIC
V53C317405A
Waveforms of CAS-before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
VIH
VIL
RAS
CAS
t
RPC
t
CRP
t
CSR
t
t
RPC
CP
t
CHR
VIH
VIL
t
WRP
t
WRH
VIH
VIL
WE
OE
t
OEZ
CDD
ODD
VIH
VIL
t
VIH
VIL
I/O
(Inputs)
t
VOH
VOL
I/O
(Outputs)
HI-Z
t
OFF
“H” or “L”
WL10
V53C317405A Rev. 0.2 September 1998
17
MO SEL VITELIC
V53C317405A
Waveforms of Hidden Refresh Read Cycle
t
t
RC
RC
t
t
RP
RP
t
RAS
t
RAS
VIH
VIL
RAS
t
RSH
t
RCD
t
t
CHR
CRP
VIH
VIL
CAS
t
RAD
t
WRP
t
ASC
t
RAH
t
t
ASR
t
WRH
CAH
t
ASR
VIH
VIL
Column
Address
Row
Row
t
RRH
t
RCS
VIH
VIL
WE
OE
t
CAA
t
OEA
VIH
VIL
t
DZC
t
CDD
t
DZO
t
t
ODD
OFF
VIH
VIL
I/O
(Inputs)
t
CAC
t
CLZ
t
OEZ
t
RAC
VOH
VOL
I/O
(Outputs)
HI-Z
Valid Data Out
WL11
“H” or “L”
V53C317405A Rev. 0.2 September 1998
18
MO SEL VITELIC
V53C317405A
Waveforms of Hidden Refresh Early Write Cycle
t
t
RC
RC
t
RP
t
RP
t
t
RAS
VIH
VIL
RAS
RAS
t
t
RSH
RCD
t
t
CHR
CRP
VIH
VIL
CAS
t
RAD
t
RAH
t
ASC
t
ASR
t
t
ASR
CAH
VIH
VIL
Address
Row
Column
t
Row
t
WCS
t
t
WRH
WRP
WCH
t
VIH
VIL
WP
WE
t
DS
t
DH
VIH
VIL
I/O
(Input)
Valid Data
VOH
VOL
I/O
(Output)
HI-Z
“H” or “L”
WL12
V53C317405A Rev. 0.2 September 1998
19
MO SEL VITELIC
V53C317405A
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t
t
RAS
RP
Read Cycle:
RAS
VIH
VIL
t
RSH
t
t
t
CP
CSB
CHR
t
CAS
VIH
VIL
CAS
t
RAL
t
ASR
t
t
ASC
CAH
VIH
VIL
Address
WE
Column
Row
t
WRP
t
t
RRH
CAA
t
RCH
VIH
VIL
t
CAC
t
WRH
t
t
RCS
OEA
VIH
VIL
OE
t
DZC
t
CDD
t
I/O
(Inputs)
VIH
VIL
ODD
t
t
DZO
OFF
t
t
CLZ
OEZ
VOH
VOL
I/O
(Outputs)
Data
Out
t
WCS
t
WRP
t
RWL
Write Cycle:
WE
t
CWL
WCH
VIH
VIL
t
t
WRH
VIH
VIL
OE
t
t
DS
DH
I/O
(Inputs)
VIH
VIL
Data In
I/O
(Outputs)
VIH
VIL
HI-Z
V53C317405A Rev. 0.2 September 1998
20
MO SEL VITELIC
V53C317405A
Waveforms of Test Mode Entry
t
RC
t
RP
t
t
RAS
RP
VIH
RAS
VIL
t
RPC
t
t
t
t
t
CRP
CSR
t
CHRT
CP
RPC
VIH
VIL
CAS
t
ASR
RAHT
VIH
VIL
Address
Row
t
t
WTH
WTS
VIH
VIL
WE
VIH
VIL
OE
t
ODD
HI-Z
VIH
VIL
I/O
(Inputs)
t
CDD
t
OEZ
VOH
VOL
I/O
(Outputs)
HI-Z
t
OFF
“H” or “L”
WL15
V53C317405A Rev. 0.2 September 1998
21
MO SEL VITELIC
V53C317405A
If they were not equal, the I/O would indicate a “0”.
The WCBR cycle (WE, CAS before RAS) puts the
device into test mode. To exit from test mode, a
“CAS before RAS refresh”, “RAS only refresh” or
“Hidden refresh” can be used.Refresh during test
mode operation can be performed by normal read
cycles or by WCBR refresh cycles.
Row addresses A0 through A9 have to kept high
to perform a testmode entry cycle. All other address-
es are don’t care.
Test Mode
As the V53C317405A is organized internally as
1M x 16-bits, a test mode cycle using 4:1 compres-
sion can be used to improve test time. Note that in
the 4M x 4 version the test time is reduced by 1/4 for
a N test pattern.
In a test mode “write” the data from each I/O pin is
written into four 1M blocks simultaneously (all “1” s
or all “0” s). In test mode “read” each I/O output is
used for indicating the test mode result. If the inter-
nal four bits are equal, the I/O would indicate a “1”.
Block Diagram in Test Mode
A0C,A1C
A0C,A1C
1 M Block
Vcc
Normal
1 M Block
Normal
I/O 1
I/O 1
1 M Block
Test
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
Normal
1 M Block
I/O 2
I/O 2
1 M Block
Test
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
1 M Block
Normal
I/O 3
1 M Block
Test
I/O 3
Test
1 M Block
Vss
Vcc
A0C,A1C
A0C,A1C
1 M Block
Normal
1 M Block
Normal
I/O 4
I/O 4
Vss
1 M Block
Test
Test
1 M Block
V53C317405A Rev. 0.2 September 1998
22
MO SEL VITELIC
V53C317405A
Package Diagrams
24/26-pin 300 mil SOJ
0.104 ± 0.003
[2.64 ± 0.1]
1
0.008 +0.003
[0.2 +0.1]
0.305 -0.009
[7.75 -0.25]
0.315 min
[0.8] min
0.148 -0.020
[3.75 -0.5]
0.020 [0.5]
B
30¡
0.268 ±0.008
[6.8 ±0.2]
0.009 [0.25]
0.007 [0.18]
B
M
0.335 [0.85] Max
.05 [1.27]
[0.003] 0.1
0.009 [0.25]
B
0.340 -0.009
[8.63 -0.25]
0.020 -0.003
[0.51 -0.1]
0.007 [0.18] M 24x
0.6 [15.24]
A
26
21
19
14
1
6
8
13
1
A
0.680 -0.009
[17.27 -0.25]
Units in inches [mm]
Index Marking
1
Does not include plastic or metal protrusion of 0.15 max. per side
24/26-pin 300 mil TSOP-II
0.039 ± 0.002
[1.0 ± 0.05]
+0.003
–0.004
+0.08
–0.09
0.006
0.3 ± 0.005
[7.62 ± 0.13]
0.006 ±0.002
[0.15±0.05]
0.15
0.050 max
[1.27 max]
5¡ max.
0.024 -0.008
[0.6 -0.2]
0.05 [1.27]
0.004 [0.1]
+0.005
–0.004
+0.12
0.4
–0.1
M
0.016
0.008 [0.2]
24x
0.363 ± 0.008
[9.22 ± 0.2]
26
14
1
13
Unit in inches [mm]
1
0.680±0.005
[17.27±0.13]
1
Does not include plastic or metal protrusion of 0.15 max. per side
V53C317405A Rev. 0.2 September 1998
23
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Printed in U.S.A.
© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
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100% product quality assurance and does not assume any liabil-
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