V53C8129H40
更新时间：2024-09-18 12:50:29
品牌：MOSEL
描述：ULTRA-HIGH PERFORMANCE, 128K X 8EDO PAGE MODE CMOS DYNAMIC RAM
概述
数据手册V53C8129H40 概述
ULTRA-HIGH PERFORMANCE, 128K X 8EDO PAGE MODE CMOS DYNAMIC RAM 超高性能， 128K X 8EDO页模式的CMOS动态RAM
V53C8129H40 数据手册
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PRELIMINARY
MOSEL VITELIC
ULTRA-HIGH PERFORMANCE,
128K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (tRAC
)
35 ns
18 ns
14 ns
70 ns
40 ns
20 ns
15 ns
75 ns
45 ns
22 ns
17 ns
80 ns
50 ns
24 ns
19 ns
90 ns
Max. Column Address Access Time, (tCAA
)
Min. Fast Page Mode With EDO Cycle Time, (tPC
)
Min. Read/Write Cycle Time, (tRC
)
Features
Description
■ 128K x 8-bit organization
The V53C8129H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8129H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
■ RAS access time: 35, 40, 45, 50 ns
■ EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
■ Low power dissipation
• V53C8129H-50
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random ac-
cess of up to 256 columns (x8) bits within a row with
cycle times as short as 14 ns. Because of static cir-
cuitry, the CAS clock is not in the critical timing path.
The flow-through column address latches allow ad-
dress pipelining while relaxing many critical system
timing requirements for fast usable speed. These
features make the V53C8129H ideally suited for
graphics, digital signal processing and high perfor-
mance peripherals.
— Operating Current: 135 mA max
— TTL Standby Current: 2.0 mA max
■ Low CMOS Standby Current: 1.0 mA max
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
■ Refresh Interval: 512 cycles/8 ms
■ Available in 26/24 pin 300 mil SOJ package
Device Usage Chart
Operating
Temperature
Range
Package Outline
K
Access Time (ns)
Power
Std.
Temperature
Mark
35
40
45
50
0°C to 70 °C
•
•
•
•
•
•
Blank
V53C8129H Rev. 1.3 July 1997
1
MOSEL VITELIC
V53C8129H
V
5
3
C
8
1
2
9
H
FAMILY
DEVICE
PKG SPEED
( t
TEMP.
PWR.
.
)
RAC
BLANK (0°C to 70°C)
K
(SOJ)
BLANK (NORMAL)
Description Pkg. Pin Count
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
SOJ
K
26/24
8129H-01
26/24 Lead SOJ
Pin Names
PIN CONFIGURATION
Top View
A0–A8
RAS
CAS
WE
Address Inputs (A8: Column Address only)
Row Address Strobe
Column Address Strobe
Write Enable
1
2
3
4
5
6
26
25
24
23
22
21
VSS
I/O1
I/O2
I/O3
I/O4
WE
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
Output Enable
I/O1–I/O8
VCC
Data Input, Output
+5V Supply
8
19
18
17
16
15
14
RAS
A0
OE
9
A8 (Column Add. only)
VSS
0V Supply
10
11
12
13
A1
A7
A6
A5
A4
A2
A3
VCC
8129H-02
Absolute Maximum Ratings*
Ambient Temperature
Capacitance*
T = 25°C, V = 5 V ± 10%, V = 0 V
A
CC
SS
Under Bias .............................. –10°C to +80°C
Storage Temperature (plastic)..... –55°C to +125°C
Symbol
Parameter
Typ.
Max.
Unit
pF
Voltage Relative to V .................–1.0 V to +7.0 V
SS
C
C
C
Address Input
3
4
5
4
5
7
IN1
Data Output Current ..................................... 50 mA
Power Dissipation.......................................... 1.0 W
RAS, CAS, WE, OE
Data Input/Output
pF
IN2
pF
OUT
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
* Note: Capacitance is sampled and not 100% tested
V53C8129H Rev. 1.3 July 1997
2
MOSEL VITELIC
V53C8129H
Block Diagram
128K x 8
OE
WE
CAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
V
V
CC
SS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O
BUFFER
4
5
Y –Y
0
8
6
7
8
REFRESH
COUNTER
512 x 8
9
A
0
A
1
X –X
0 7
256
MEMORY
ARRAY
•
•
•
A
A
7
8
8129H-03
V53C8129H Rev. 1.3 July 1997
3
MOSEL VITELIC
V53C8129H
DC and Operating Characteristics (1-2)
T = 0°C to 70°C, V = 5 V ± 10%, V = 0 V, unless otherwise specified.
A
CC
SS
V53C8129H
Typ.
Access
Time
Symbol
Parameter
Min.
Max..
Unit
Test Conditions
Notes
I
I
I
Input Leakage Current
(any input pin)
–10
10
µA
V
V
≤ V ≤ V
IN CC
LI
SS
Output Leakage Current
(for High-Z State)
–10
10
µA
≤ V
≤ V
OUT
LO
CC1
SS
CC
IH
RAS, CAS at V
V
Supply Current,
35
40
45
50
160
150
145
135
4
mA
t
= t (min.)
1, 2
CC
RC
RC
Operating
I
I
V
Supply Current,
mA
mA
RAS, CAS at V
IH
CC2
CC3
CC
TTL Standby
other inputs ≥ V
SS
V
Supply Current,
35
40
45
50
35
40
45
50
160
150
145
135
95
t
= t (min.)
2
1, 2
1
CC
RC
RC
RAS-Only Refresh
I
V
Supply Current,
CC
mA
Minimum cycle
CC4
EDO Page Mode Operation
90
85
80
I
I
V
Supply Current,
2
mA
mA
RAS = V , CAS = V
IH IL
CC5
CC
Standby, Output Enabled
other inputs ≥ V
SS
V
Supply Current,
1
RAS ≥ V – 0.2 V,
CC
CC6
CC
CMOS Standby
CAS ≥ V – 0.2 V,
CC
All other inputs ≥ V
SS
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–1
0.8
V
V
V
V
3
3
IL
2.4
V
+ 1
CC
IH
0.4
I
I
= 4.2 mA
= –5 mA
OL
OH
OL
2.4
OH
V53C8129H Rev. 1.3 July 1997
4
MOSEL VITELIC
V53C8129H
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
35
40
45
50
JEDEC
#
1
2
3
4
5
6
7
8
9
Symbol
tRL1RH1
tRL2RL2
tRH2RL2
tRL1CH1
tCL1CH1
tRL1CL1
tWH2CL2
tAVRL2
Symbol Parameter
tRAS RAS Pulse Width
tRC
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
35 75K 40 75K 45 75K 50 75K ns
Read or Write Cycle Time
RAS Precharge Time
CAS Hold Time
70
25
35
7
75
25
40
8
80
25
45
9
90
30
50
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRP
tCSH
tCAS
tRCD
tRCS
tASR
tRAH
tASC
tCAH
CAS Pulse Width
RAS to CAS Delay
16
0
23
17
0
28
18
0
32
19
0
36
Read Command Setup Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
4
0
0
0
0
tRL1AX
6
7
8
9
10 tAVCL2
11 tCL1AX
0
0
0
0
4
5
6
7
12 tCL1RH1(R) tRSH (R) RAS Hold Time (Read Cycle)
14
5
14
5
15
5
15
5
13 tCH2RL2
14 tCH2WX
tCRP
tRCH
CAS to RAS Precharge Time
Read Command Hold Time Referenced
to CAS
0
0
0
0
5
5
15 tRH2WX
tRRH
Read Command Hold Time Referenced
to RAS
0
8
0
9
0
0
ns
16 tOEL1RH2
17 tGL1QV
18 tCL1QV
19 tRL1QV
20 tAVQV
21 tCL1QX
22 tCH2QZ
23 tRL1AX
24 tRL1AV
tROH
tOAC
tCAC
tRAC
tCAA
tLZ
RAS Hold Time Referenced to OE
Access Time from OE
10
10
ns
ns
ns
12
12
35
18
12
12
40
20
13
13
45
22
14
14
50
24
Access Time from CAS (EDO)
Access Time from RAS
6, 7
ns 6, 8, 9
ns 6, 7, 10
Access Time from Column Address
CAS to Low-Z Output
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
16
16
tHZ
Output buffer turn-off delay time
Column Address Hold Time from RAS
RAS to Column Address Delay Time
6
6
7
8
tAR
28
11
12
12
0
30
12
12
12
0
35
13
13
13
0
40
14
14
14
0
tRAD
17
20
23
26
11
25 tCL1RH1(W) tRSH (W) RAS or CAS Hold Time in Write Cycle
26 tWL1CH1
27 tWL1CL2
28 tCL1WH1
29 tWL1WH1
30 tRL1WH1
31 tWL1RH1
tCWL
tWCS
tWCH
tWP
Write Command to CAS Lead Time
Write Command Setup Time
Write Command Hold Time
ns 12, 13
5
5
6
7
ns
ns
ns
ns
Write Pulse Width
5
5
6
7
tWCR
tRWL
Write Command Hold Time from RAS
Write Command to RAS Lead Time
28
12
30
12
35
13
40
14
V53C8129H Rev. 1.3 July 1997
5
MOSEL VITELIC
V53C8129H
AC Characteristics (Cont’d)
35
40
45
50
JEDEC
#
Symbol
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
32 tDVWL2
33 tWL1DX
34 tWL1GL2
35 tGH2DX
tDS
Data in Setup Time
0
4
0
5
0
6
0
7
ns
ns
ns
ns
ns
14
14
14
14
tDH
Data in Hold Time
tWOH
tOED
tRWC
Write to OE Hold Time
OE to Data Delay Time
Read-Modify-Write Cycle Time
5
6
7
8
5
6
7
8
36 tRL2RL2
(RMW)
105
110
115
130
37 tRL1RH1
(RMW)
tRRW
Read-Modify-Write Cycle RAS Pulse
Width
70
75
80
87
ns
38 tCL1WL2
39 tRL1WL2
tCWD
tRWD
CAS to WE Delay
28
54
30
58
32
62
34
68
ns
ns
12
12
RAS to WE Delay in Read-Modify-Write
Cycle
40 tCL1CH1
41 tAVWL2
42 tCL2CL2
tCRW
tAWD
tPC
CAS Pulse Width (RMW)
Col. Address to WE Delay
46
35
14
48
38
15
50
41
17
52
42
19
ns
ns
ns
12
EDO Page Mode Read or Write Cycle
Time
43 tCH2CL2
44 tAVRH1
45 tCH2QV
46 tRL1DX
47 tCL1RL2
tCP
CAS Precharge Time
4
5
6
7
ns
ns
ns
ns
ns
tCAR
tCAP
tDHR
tCSR
Column Address to RAS Setup Time
Access Time from Column Precharge
Data in Hold Time Referenced to RAS
18
20
22
24
21
23
25
27
7
28
10
30
10
35
10
40
10
CAS Setup Time CAS-before-RAS
Refresh
48 tRH2CL2
49 tRL1CH1
tRPC
tCHR
tPCM
RAS to CAS Precharge Time
0
8
0
8
0
0
ns
ns
ns
CAS Hold Time CAS-before-RAS Refresh
10
65
12
70
50 tCL2CL2
(RMW)
EDO Page Mode Read-Modify-Write
Cycle Time
58
60
51 tT
52
tT
Transition Time (Rise and Fall)
Refresh Interval (512 Cycles)
Output Hold After CAS Low
3
5
50
8
3
5
50
8
3
5
50
8
3
5
50
8
ns
ms
ns
15
tREF
tCOH
53
V53C8129H Rev. 1.3 July 1997
6
MOSEL VITELIC
V53C8129H
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2.
ICC is dependent upon the number of address transitions. Specified IDD (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VDD
.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC
.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to two TTL inputs and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP
.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD ex-
ceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC
.
12.
13.
14.
t
t
t
WCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
WCS (min.) must be satisfied in an Early Write Cycle.
DS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8129H Rev. 1.3 July 1997
7
MOSEL VITELIC
V53C8129H
Waveforms of Read Cycle
t
RC (2)
t
t
RP (3)
RAS (1)
t
AR (23)
V
IH
RAS
V
IL
t
CSH (4)
t
t
t
t
t
CRP (13)
RCD (6)
RSH (R)(12)
CAS (5)
CRP (13)
V
IH
CAS
V
t
IL
RAD (24)
t
t
RAH (9)
CAH (11)
t
t
ASR (8)
ASC (10)
V
IH
ADDRESS
ROW ADDRESS
COLUMN ADDRESS
V
IL
t
t
RCH (14)
CAR (44)
t
t
RCS (7)
RRH (15)
V
IH
WE
OE
V
IL
t
ROH (16)
t
t
HZ (22)
CAA (20)
t
V
OAC (17)
IH
V
IL
t
CAC (18)
t
HZ (22)
t
t
RAC (19)
HZ (22)
V
OH
I/O
VALID DATA-OUT
V
OL
8129H-04
t
LZ (21)
Waveforms of Early Write Cycle
t
RC (2)
t
t
RP (3)
RAS (1)
t
AR (23)
V
IH
RAS
V
IL
t
CSH (4)
t
t
t
t
t
CRP (13)
RCD (6)
RSH (W)(25)
CAS (5)
CRP (13)
V
V
IH
IL
CAS
t
CAR (44)
t
t
RAH (9)
CAH (11)
t
t
ASC (10)
ASR (8)
V
V
IH
IL
ADDRESS
ROW ADDRESS
t
COLUMN ADDRESS
t
RAD (24)
WCH (28)
t
CWL (26)
t
t
t
t
WP (29)
WSR
RWH
WCS (27)
V
V
IH
IL
WE
OE
I/O
t
WCR (30)
t
RWL (31)
V
V
IH
IL
t
DHR (46)
t
t
DH (33)
DS (32)
V
V
IH
IL
VALID DATA-IN
HIGH-Z
8129H-05
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
8
MOSEL VITELIC
V53C8129H
Waveforms of OE-Controlled Write Cycle
t
RC (2)
t
t
RP (3)
RAS (1)
t
AR (23)
V
V
IH
IL
RAS
CAS
t
CSH (4)
t
t
t
t
t
CRP (13)
RCD (6)
RSH (W)(12)
CAS (5)
CRP (13)
V
V
IH
IL
t
t
RAD (24)
t
CAR (44)
t
CAH (11)
RAH (9)
t
t
ASR (8)
ASC (10)
V
V
IH
IL
ADDRESS
ROW ADDRESS
COLUMN ADDRESS
t
t
CWL (26)
RWL (31)
WP (29)
t
V
V
IH
IL
WE
OE
t
WOH (34)
V
V
IH
IL
t
t
OED (35)
DH (33)
DS (32)
t
V
V
IH
IL
I/O
VALID DATA-IN
8129H-06
Waveforms of Read-Modify-Write Cycle
t
RWC (36)
t
t
RRW (37)
RP (3)
t
AR (23)
V
IH
RAS
CAS
V
IL
t
CSH (4)
t
t
t
t
t
CRP (13)
RCD (6)
RSH (W)(25)
CRP (13)
CRW (40)
V
IH
V
IL
t
t
t
RAH (9)
CAH (11)
t
t
ASC (10)
ASR (8)
V
IH
ROW
ADDRESS
COLUMN
ADDRESS
ADDRESS
V
IL
t
AWD (41)
t
CWL (26)
t
t
RWL (31)
t
RAD (24)
CWD (38)
t
RWD (39)
t
WP (29)
RCS (17)
V
IH
WE
OE
V
IL
t
CAA (20)
t
OAC (17)
V
IH
V
IL
t
t
OED (35)
DH (33)
t
t
HZ (22)
CAC (18)
t
t
DS (32)
RAC (19)
V
V
OH
IH
VALID
DATA-OUT
VALID
DATA-IN
I/O
V
V
OL
IL
8129H-07
t
LZ (21)
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
9
MOSEL VITELIC
V53C8129H
Waveforms of EDO Page Mode Read Cycle
t
t
RAS (1)
RP (3)
t
AR (23)
V
V
IH
IL
t
RAS
CAS
RCD (6)
t
t
PC (42)
t
RSH (R)(12)
t
t
CRP (13)
CP (43)
CRP (13)
t
CAS (5)
t
t
CAS (5)
CAS (5)
V
V
IH
IL
t
t
CSH (4)
CAR (44)
t
t
RAH (9)
t
ASC (10)
ASC (10)
t
t
t
ASR (8)
CAH (11)
CAH (11)
V
V
IH
IL
ROW
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ADDRESS
t
t
t
RCH (14)
RCH (14)
RCS (7)
t
RCS (7)
t
t
RCS (7)
CAH (11)
V
V
IH
IL
WE
OE
t
t
CAA (20)
CAA (20)
t
t
RRH (15)
CAP (45)
t
t
OAC (17)
OAC (17)
V
V
IH
IL
t
t
t
RAC (19)
CAC (18)
CAC (18)
t
t
t
t
CAC (18)
HZ (22)
t
LZ (21)
HZ (22)
t
t
HZ (22)
COH
HZ (22)
V
V
OH
OL
VALID
DATA OUT
VALID
DATA OUT
VALID
DATA OUT
I/O
t
LZ
8129H-08
Waveforms of EDO Page Mode Write Cycle
t
t
RP (3)
AR (23)
t
RAS (1)
V
V
IH
IL
RAS
CAS
t
t
t
RSH (W)(25)
CRP (13)
t
PC (42)
t
t
CRP (13)
RCD (6)
CP (43)
t
t
CAS (5)
t
CAS (5)
V
V
CAS (5)
IH
IL
t
CSH (4)
t
t
RAH (9)
CAR (44)
t
t
t
t
ASC (10)
t
CAH (11)
ASC (10)
t
ASR (8)
CAH (11)
CAH (11)
V
V
IH
IL
ROW
ADD
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ADDRESS
t
t
t
t
RAD (24)
CWL (26)
CWL (26)
CWL (26)
t
t
WCS (27)
WCS (27)
t
t
t
t
WCS (27)
WCH (28)
WCH (28)
RWL (31)
t
WCH (28)
WP (29)
t
t
t
WP (29)
WP (29)
V
V
IH
IL
WE
OE
V
V
IH
IL
t
t
t
t
t
DS (32)
DH (33)
DH (33)
DH (33)
DS (32)
t
DS (32)
V
V
IH
IL
VALID
DATA IN
VALID
DATA IN
VALID
DATA IN
I/O
OPEN
OPEN
8129H-09
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
10
MOSEL VITELIC
V53C8129H
Waveforms of EDO Page Mode Read-Write Cycle
t
RAS (1)
V
IH
RAS
V
IL
t
t
CSH (4)
RP (3)
t
RCD (6)
t
t
PCM (50)
RSH (W)(25)
t
t
CP (43)
CRP (13)
t
t
V
t
CAS (5)
CAS (5)
CAS (5)
IH
CAS
t
RAD (24)
V
IL
t
t
RAH (9)
CAR (44)
t
t
t
t
ASC (10)
ASC (10)
CAH (11)
ASC (10)
t
CAH (11)
t
t
CAH (11)
ASR (8)
V
IH
ROW
ADD
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
ADDRESS
V
IL
t
t
t
RWD (39)
t
CWD (38)
CWD (38)
t
t
t
RWL (31)
RCS (7)
CWL (26)
t
t
CWL (26)
CWD (38)
CWL (26)
V
IH
WE
OE
V
IL
t
AWD (41)
WP (29)
OAC (17)
t
t
AWD (41)
AWD (41)
WP (29)
t
OAC (17)
t
t
t
t
CAA (20)
WP (29)
t
t
t
WSR
OAC (17)
V
IH
V
IL
t
t
t
CAP (43)
t
CAP (43)
t
CAA (20)
EMH
t
t
CAA (20)
t
EMS
t
t
OED (35)
OED (35)
OED (35)
t
t
t
CAC (18)
CAC (18)
RAC (19)
CAC (18)
t
t
t
HZ (22)
HZ (22)
t
HZ (22)
t
t
t
t
DH (33)
DH (33)
DH (33)
DS (32)
t
DS (32)
DS (32)
V
I/O
I/OH
I/OL
OUT
OUT
OUT
IN
IN
IN
V
8129H-10
t
LZ (21)
t
t
LZ
LZ
Waveforms of RAS-Only Refresh Cycle
t
RC (2)
t
RP (3)
t
RAS (1)
V
V
IH
IL
RAS
CAS
t
CRP (13)
V
V
IH
IL
t
t
RAH (9)
ASR (8)
V
V
IH
IL
ADDRESS
ROW ADD
8129H-11
NOTE: WE, OE = Don’t care
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
11
MOSEL VITELIC
V53C8129H
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t
t
RAS (1)
RP (3)
V
V
IH
IL
RAS
t
RSH (W)(25)
t
t
CP (43)
CHR (49)
t
t
CSR (47)
CAS (5)
V
V
IH
IL
CAS
V
V
IH
IL
ADDRESS
t
t
RRH (15)
RCH (14)
READ CYCLE
t
RCS (7)
V
V
IH
IL
WE
OE
I/O
t
ROH (16)
t
OAC (17)
V
V
IH
IL
t
t
HZ (22)
HZ (22)
t
LZ (21)
V
V
IH
IL
D
OUT
t
t
t
RWL (31)
CWL (26)
HZ (22)
WRITE CYCLE
t
t
WCS (27)
WCH (28)
V
V
IH
IL
WE
OE
I/O
V
V
IH
IL
t
t
DH (33)
DS (32)
V
V
IH
IL
D
IN
8129H-12
Waveforms of CAS-before-RAS Refresh Cycle
t
RC (2)
t
t
t
RP (3)
RP (3)
RAS (1)
V
V
IH
IL
RAS
t
RPC (48)
t
t
t
CHR (49)
CP (43)
HZ (22)
t
CSR (47)
V
V
IH
IL
CAS
I/O
V
V
OH
OL
8129H-13
WE, OE, A –A = Don’t care
NOTE:
8
0
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
12
MOSEL VITELIC
V53C8129H
Waveforms of Hidden Refresh Cycle (Read)
t
t
RC (2)
RC (2)
t
t
RP (3)
t
t
t
RAS (1)
RAS (1)
RP (3)
AR (23)
V
V
IH
IL
RAS
CAS
t
t
RSH (R)(12)
t
t
CRP (13)
RCD (6)
CRP (13)
CHR (49)
t
V
V
IH
IL
t
RAD (24)
t
t
ASR (8)
t
ASC (10)
t
RAH (9)
CAH (11)
V
V
IH
IL
COLUMN
ADDRESS
ROW
ADD
ADDRESS
WE
t
t
RCS (7)
RRH (15)
V
V
IH
IL
t
CAA (20)
t
t
HZ (22)
OAC (17)
V
V
IH
IL
OE
I/O
t
t
HZ (22)
CAC (18)
t
t
HZ (22)
LZ (21)
t
RAC (19)
V
OH
OL
VALID DATA
V
8129H-14
Waveforms of Hidden Refresh Cycle (Write)
t
t
RC (2)
RC (2)
t
t
RP (3)
t
t
RAS (1)
RAS (1)
RP (3)
t
AR (23)
V
V
IH
IL
RAS
CAS
t
t
RSH (12)
t
t
CRP (13)
RCD (6)
CRP (13)
CHR (49)
t
V
V
IH
IL
t
RAD (24)
t
t
ASR (8)
t
ASC (10)
t
RAH (9)
CAH (11)
V
V
IH
IL
ROW
COLUMN
ADDRESS
ADDRESS
WE
ADD
t
t
WCS (27)
WCH (28)
V
V
IH
IL
V
V
IH
IL
OE
t
t
DS (32)
DH (33)
V
IH
IL
VALID DATA-IN
I/O
V
8129H-15
t
DHR (46)
Undefined
Don’t Care
V53C8129H Rev. 1.3 July 1997
13
MOSEL VITELIC
V53C8129H
Functional Description
Refresh Cycle
The V53C8129H is a CMOS dynamic RAM opti-
mized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C8129H reads and writes
data by multiplexing an 17-bit address into a 8-bit
row and an 9-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address “flows through” an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
To retain data, 512 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A
0
through A ) with RAS at least once every 8 ms.
8
Any Read, Write, Read-Modify-Write or RAS-
only cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CAS-
before-RAS
refresh
is
activated.
The
V53C8129H uses the output of an internal 9-bit
counter as the source of row addresses and ig-
nore external address inputs.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be end-
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cy-
cle. A CAS-before-RAS counter test mode is provid-
ed to ensure reliable operation of the internal
refresh counter.
ed or aborted before the minimum t
time has ex-
RAS
pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t /t has elapsed.
RP CP
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
Extended Data Out Page Mode
The V53C8129H offers fast access within a row.
Unlike ordinary fast page mode DRAM, the
V53C8129H output remains active and valid even
after CAS goes high and it will stay valid for 5ns af-
ter CAS changes low. The feature allows the
V53C8129H to CAS cycle faster than ordinary page
mode DRAM since the cycle time be short as data
access time.
mum specified by t . Data Out becomes valid only
AR
when t
, t
, t
and t
are all satisifed. As
OAC RAC CAA
CAC
a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by t
when t
,
CAA
RAC
t
and t
are all satisfied.
CAC
OAC
The outputs are disabled at the tHZ time after
RAS and CAS are high. The tHZ time is referenced
from rising edge of RAS or CAS whichever occurs
last. In addition, high on OE input and activation of
the write-cycle will also disable the outputs.
The following equation can be used to calculate
the maximum data rate:
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
256
Data Rate = ----------------------------------------
t
+ 255 × t
RC
PC
the high state and t
must be satisfied.
OED
V53C8129H Rev. 1.3 July 1997
14
MOSEL VITELIC
V53C8129H
Data Output Operation
Table 1. V53C8129H Data Output
Operation for Various Cycle Types
The V53C8129H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
Cycle Type
I/O State
Read Cycles
Data from Addressed Memory
Cell
CAS-Controlled Write Cycle
(Early Write)
High-Z
WE-Controlled Write Cycle
(Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
Data from Addressed Memory
Cell
EDO Page Mode Read
Data from Addressed Memory
Cell
EDO Page Mode Write Cycle High-Z
(Early Write)
EDO Page Mode Read-
Modify-Write Cycle
Data from Addressed Memory
Cell
RAS-only Refresh
High-Z
(t ) to be satisfied.
DS
CAS-before-RAS Refresh
Cycle
Data remains as in previous
cycle
Power-On
CAS-only Cycles
High-Z
After application of the V
supply, an initial
CC
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the V current requirement of
CC
the V53C8129H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and I will exhibit
CC
current transients. It is recommended that RAS and
CAS track with V or be held at a valid V during
CC
IH
Power-On to avoid current surges.
V53C8129H Rev. 1.3 July 1997
15
MOSEL VITELIC
V53C8129H
Package Outlines
24-pin 300 mil PDIP
0.300 – 0.330
[7.62 – 8.38]
Unit in inches [mm]
0.250 – 0.300
[6.35 – 7.62]
.180 Max.
[4.57 Max.]
1.310 Max.
[33.27 Max.]
0.005 – 0.050
[0.127 – 1.27]
0.110 – 0.140
[2.79 – 3.56]
.008 – .013
[.203 – .330]
.100 Typ.
0.018 – 0.024
[0.457 – 0.610]
[2.54 Typ.]
0.320 – 0.390
[8.13 – 9.91]
0.048 – 0.065
[1.22 – 1.65]
26/24-pin 300 mil SOJ
Unit in inches [mm]
0.332 – 0.342
[8.43 – 8.69]
0.296 – 0.304
[7.52 – 7.72]
0.665 – 0.698
[16.89 – 17.73]
0.125 – 0.135
[3.175 – 3.429]
0.082 – 0.093
[2.08 – 2.36]
0.025 Min.
[0.635 Min.]
0.028 Typ.
[0.711 Typ.]
0.255 – 0.275
[6.477 – 6.985]
0.05 Typ.
[1.27 Typ.]
0.018 Typ.
[0.457 Typ.]
V53C8129H Rev. 1.3 July 1997
16
MOSEL VITELIC
V53C8129H
V53C8129H Rev. 1.3 July 1997
17
MOSEL VITELIC WORLDWIDE OFFICES
V53C8129H
U.S.A.
TAIWAN
JAPAN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
7F, NO. 102
RM.302 ANNEX-G
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 011-886-2-545-1213
FAX: 011-886-2-545-1209
HIGASHI-NAKANO
NAKANO-KU, TOKYO 164
PHONE: 011-81-03-3365-2851
FAX: 011-81-03-3365-2836
HONG KONG
19 DAI FU STREET
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 011-886-35-783344
FAX: 011-886-35-792838
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 011-852-665-4883
FAX: 011-852-664-7535
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0185
SOUTHWESTERN
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 310-498-3314
FAX: 310-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 972-690-1402
FAX: 972-690-0341
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
7/97
Printed in U.S.A.
© Copyright 1997, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
V53C8129H40 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| V53C8129H45 | MOSEL | ULTRA-HIGH PERFORMANCE, 128K X 8EDO PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
|
| V53C8129H50 | MOSEL | ULTRA-HIGH PERFORMANCE, 128K X 8EDO PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
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| V53C816H40 | MOSEL | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
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| V53C816H45 | MOSEL | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
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| V53C816H50 | MOSEL | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
|
| V53C816H60 | MOSEL | 512K X 16 FAST PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
|
| V53C818H | MOSEL | HIGH PERFORMANCE 512K X 16 EDO PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
|
| V53C818H30 | MOSEL | HIGH PERFORMANCE 512K X 16 EDO PAGE MODE CMOS DYNAMIC RAM | 获取价格 |
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